CN105575825A - Chip packaging method and packaging assembly - Google Patents
Chip packaging method and packaging assembly Download PDFInfo
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- CN105575825A CN105575825A CN201511007942.3A CN201511007942A CN105575825A CN 105575825 A CN105575825 A CN 105575825A CN 201511007942 A CN201511007942 A CN 201511007942A CN 105575825 A CN105575825 A CN 105575825A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
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- H01L2924/3512—Cracking
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a chip packaging method and a packaging assembly. The chip packaging method comprises the steps of forming a first packaging layer on multiple chips, wherein the multiple chips comprise opposite first surfaces and second surfaces respectively, and multiple first conductive convex blocks formed on the first surfaces; forming a re-wiring layer on the surface of the first packaging layer; forming multiple second conductive convex blocks on the re-wiring layer so as to form the packaging structure; and separating the packaging structure into multiple packaging assemblies, wherein the re-wiring layer enables the multiple first conductive convex blocks to be connected to the multiple second conductive convex blocks so as to provide a conductive path from the multiple chips to an external circuit. According to the chip packaging method, a lead frame and a bonding wire can be saved, so that flexible pin layout is allowed, and the electrical performance of the packaging assemblies is improved.
Description
Technical field
The present invention relates to ground semiconductor technology, more specifically, relate to the wafer level chip method for packing without the need to lead frame and package assembling.
Background technology
Chip package is wrapped in encapsulating compound by chip, thus semi-conducting material and external environment separated and provide the technique with the electrical connection of external circuit.The package assembling formed after chip package process namely can at the chip product of market sale.
Existing chip package process comprises wafer is cut into one single chip, is placed on the lead frames by one single chip, multiple steps such as plastic packaging and cutting lead framework.The chip package process of further improvement is included in whole wafer and places lead frame and carry out plastic packaging, then wafer, plastic packaging material is cut into single package assembly together with lead frame.The chip package process of this improvement is called wafer-class encapsulation (Wafer-LevelChipScalePackaging, be abbreviated as WL-CSP), not only can reduce the size of package assembling, and owing to not needing chip one by one to carry out plastic packaging, thus can enhance productivity.
Above-mentioned existing chip package process all uses lead frame, chip must be placed on the correct position of lead frame and be electrically connected before plastic packaging.Electrical connection between chip with lead frame mainly contains two kinds of modes: wire bonding and conductive projection weld.In lead key closing process, the non-active face of chip is relative with lead frame, by the lead frames bonding for the non-active face of chip, then adopts bonding line, is connected on lead frame by the pad on the active face of chip.In conductive projection pad technique, the non-active face lead frame dorsad of chip, the active face of chip forms conductive projection, and by conductive projection welding on the lead frames, realizes chip machinery on the lead frames simultaneously and fix and be electrically connected.
Connection between chip and lead frame causes process complexity and yield to reduce.Preformed lead frame to the number of pins of encapsulation chip thereon and pin layout restricted, be not easy to the agile kernel model encapsulated like this.In lead key closing process, metal lead wire must increase packaged resistance and parasitic capacitance.In conductive projection welding procedure, conductive projection makes the spacing between conductive projection be restricted with welding of lead frame.Correspondingly, chip bonding pad also needs to be greater than certain spacing, thus can not be used for the encapsulation of close solder pad space length chip.
Expect to improve wafer grade chip packaging process further to improve the electrical property of package assembling, improve reliability and the pin density of package assembling.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of layer that reroutes that utilizes to replace lead frame and bonding line, thus the problem that solution bonding line causes electrical property deterioration and lead frame to cause pin layout to limit.
According to an aspect of the present invention, a kind of chip packaging method is provided, comprises; Multiple chip is formed the first encapsulated layer, and described multiple chip comprises relative first surface and second surface respectively, and at multiple first conductive projections that described first surface is formed; The surface of described first encapsulated layer forms the layer that reroutes; The described layer that reroutes forms multiple second conductive projection, thus forms encapsulating structure; And described encapsulating structure is separated into multiple package assembling, wherein, described in the layer that reroutes described multiple first conductive projection is connected to described multiple second conductive projection, thus provide described multiple chip to the conductive path of external circuit.
Preferably, between the step forming multiple second conductive projection and the step described encapsulating structure being separated into multiple package assembling, also comprise: form solder on the surface of described multiple second conductive projection.
Preferably, described solder comprises welding block or soldered ball.
Preferably, before the step of formation first encapsulated layer, also comprise and described multiple chip is fixed on supporting layer.
Preferably, the step that described multiple chip is fixed on supporting layer is comprised: form the first supporting layer at the back side of the wafer comprising described multiple chip; Described wafer is separated into multiple chip together with described first supporting layer; And described multiple chip is fixed on the second supporting layer.
Preferably, described multiple chip is fixed on described second supporting layer comprises: viscous layer is set on described second supporting layer; And described multiple chip is placed on described viscous layer, make described first supporting layer contact described viscous layer.
Preferably, between the step forming described multiple second conductive projection and the step described encapsulating structure being separated into multiple package assembling, also comprise: heat, make described viscous layer lose viscosity, thus described second supporting layer is separated with described first supporting layer.
Preferably, described multiple chip is fixed on described second supporting layer comprises: adopt bonding agent to be bonded on described second supporting layer by described first supporting layer.
Preferably, between the step forming described multiple second conductive projection and the step described encapsulating structure being separated into multiple package assembling, also comprise: use bonding agent described in removal of solvents, described second supporting layer is separated with described first supporting layer.
Preferably, described first supporting layer is insulation glue-line or insulating resin layer, and in described package assembling, described first supporting layer is as a part for the packaging body of described package assembling.
Preferably, described first supporting layer is metal level, and in described package assembling, and described first supporting layer provides additional conductive channel or heat dissipation channel for described multiple chip.
Preferably, before multiple chip is formed the step of the first encapsulated layer, also comprise: place described multiple chip according to preset space length, described preset space length corresponds to the size of described multiple package assembling.
Preferably, described first encapsulated layer covers the first surface of described multiple chip and the space of filling between adjacent chips, and described multiple chip is connected into entirety.
Preferably, the step forming the layer that reroutes comprises: the seed layer forming patterning on the surface of described first encapsulated layer; And the layer that reroutes described in described seed layer thickened into.
Preferably, the step forming the seed layer of patterning comprises: form seed layer, the surface contacting described multiple first conductive projection at least partially of described seed layer; On the surface of described seed layer, photoresist oxidant layer is adopted to form the patterned layer comprising opening; Etchant is adopted optionally to remove the expose portion of described seed layer; Remove described patterned layer, wherein, the remainder of described seed layer forms wiring pattern.
Preferably, chemical plating or vacuum evaporation is adopted to form seed layer.
Preferably, plating or chemical plating is adopted to thicken described seed layer.
Preferably, before the seed layer forming patterning, also comprise: at described first encapsulated layer split shed, to expose the surface of described multiple first conductive projection.
Preferably, before the seed layer forming patterning, also comprise: the surface of smooth described first encapsulated layer, to expose the surface of described multiple first conductive projection.
Preferably, before the step forming the layer that reroutes, also comprise: surface coarsening process is carried out to described multiple first conductive projection.
Preferably, soda acid chemical treatment is adopted to obtain the surface of alligatoring.
Preferably, between the step forming described multiple second conductive projection and the step described encapsulating structure being separated into multiple package assembling, also comprise: on described first encapsulated layer, form the second encapsulated layer, reroute described in described second encapsulated layer covers layer and described multiple second conductive projection; And the surface of smooth described second encapsulated layer, to expose the surface of described multiple second conductive projection.
According to a further aspect in the invention, provide a kind of package assembling, comprising: chip, described chip has relative first surface and second surface; Multiple first conductive projection, is positioned on the first surface of described chip; Supporting layer, is attached on the second surface of described chip; First encapsulated layer, covers first surface and the side of described chip; Reroute layer, is positioned on the surface of described first encapsulated layer, and with described multiple first conductive projection electrical contact; Multiple second conductive projection, reroutes described in being positioned on layer, wherein, described in the layer that reroutes described multiple first conductive projection is connected to described multiple second conductive projection, thus provide described multiple chip to the conductive path of external circuit.
Preferably, also comprise: the solder formed on the surface of described multiple second conductive projection.
Preferably, described solder comprises welding block or soldered ball.
Preferably, described supporting layer is insulation glue-line or insulating resin layer, and a part for packaging body as described package assembling.
Preferably, described supporting layer is metal level, and provides additional conductive channel or heat dissipation channel for described chip.
Preferably, also comprise: the second encapsulated layer, be positioned on described first encapsulated layer, and expose the surface of described multiple second conductive projection.
According to the chip packaging method of the embodiment of the present invention, not only can realize wafer-class encapsulation, and lead frame and bonding line can be saved further.In the method, utilize the layer that reroutes to replace lead frame and bonding line, be arranged on reroute layer and the conductive path between the practical chip of conductive projection and external circuit in multiple encapsulated layer, and can directly utilize conductive projection directly as pin.
Relative to prior art, due to without the need to using preformed lead frame, the pin of packaged chip is formed in the process of encapsulation, and be conducive to the flexible design encapsulated, without the need to bonding wire, packaged resistance is low.In addition, by the layer that reroutes again arrange electrode position after, then carry out extraction electrode by conductive projection, the encapsulation of the chip of high pad density can be adapted to.
In a preferred embodiment, this packaging technology step major part all completes on the second supporting layer, is conducive to realizing automation encapsulation, enhances productivity.
Accompanying drawing explanation
By referring to the description of accompanying drawing to the embodiment of the present invention, above-mentioned and other objects of the present invention, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1 illustrates the vertical view of the wafer comprising multiple chip; And
Fig. 2 a to 2j illustrates the sectional view in each stage of the chip packaging method according to the first embodiment of the present invention.
Embodiment
In more detail the present invention is described hereinafter with reference to accompanying drawing.In various figures, identical element adopts similar Reference numeral to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.In addition, may some known part not shown.For brevity, in a width figure, the semiconductor structure obtained after several step can be described.
Be to be understood that, when the structure of outlines device, when one deck, region are called be positioned at another layer, another region " above " or " top " time, can refer to be located immediately at another layer, another over, or itself and another layer, also comprise other layer or region between another region.Further, if overturn by device, this one deck, a region will be positioned at another layer, another region " below " or " below ".
If the form of presentation of " A is directly on B " or " A also adjoins with it on B " in order to describe the situation being located immediately at another layer, another over, will be adopted herein.In this application, " A is located immediately in B " represents that A is arranged in B, and A and B directly adjoins, but not A is arranged in the doped region that B is formed.
In this application, term " semiconductor structure " refers to, in the general designation manufacturing the whole semiconductor structure formed in each step of semiconductor device, comprise all layers or region that have been formed.Term " horizontal expansion " refers to that the direction along being approximately perpendicular to gash depth direction extends.
Describe hereinafter many specific details of the present invention, the structure of such as device, material, size, treatment process and technology, more clearly to understand the present invention.But just as the skilled person will understand like that, the present invention can be realized not in accordance with these specific details.
The present invention can present in a variety of manners, below will describe some of them example.
Fig. 1 illustrates the vertical view of the wafer comprising multiple chip, and wherein, line AA illustrates the interception position of sectional view subsequently.
After the multiple steps completing wafer process, wafer 100 comprises multiple chip 110 and multiple conductive projection 120.Multiple chip 110 is provided as array and adjacent to each other in wafer 100.The neighboring area of wafer 100 comprises the recess (notch) for indicating crystal orientation and is convenient to the edge of wafer operations.In this application, chip 110 can be the tube core of discrete component or the bare chip of integrated circuit.
Fig. 2 a to 2j illustrates the sectional view in each stage of the chip packaging method according to the first embodiment of the present invention.
The method starts from the wafer 100 completing wafer process.Three chips 111 to 113 adjacent one another are in wafer 100 are shown in fig. 2 a, and for the sake of clarity, the dicing lane 116 between chip 111 to 113 are amplified and illustrates.
Chip 111 to 113 comprises Semiconductor substrate, multiple semiconductor layer, multiple conductor layer and multiple insulating barrier respectively, for limiting the active area of multiple semiconductor device.Such as, Semiconductor substrate is silicon substrate, semiconductor device is mos field effect transistor (MOSFET), MOSFET source region and drain region etc. are limited in Semiconductor substrate and semiconductor layer, in conductor layer, form source contact, drain contact, conductive channel, grid conductor etc., insulating barrier is used for providing gate-dielectric or zone isolation.
Chip 111 to 113 comprises relative first surface and second surface respectively, wherein, first surface is formed described multiple conductive projection 120, for providing electrical connection.First surface can be called the active face of chip, and second surface can be called the non-active face of chip.Conductive projection 120 can be any one in copper post, solder projection and soldered ball.When semiconductor device is MOSFET, conductive projection 120 is connected to source contact, drain contact and the grid conductor of described MOSFET via conductive channel.
Then, the first supporting layer 130 is formed at the second surface of chip 111 to 113, as shown in Figure 2 b.First supporting layer 130 can be any one in insulation glue-line, metal level or insulating resin layer.Such as, form insulation glue-line by coating, form metal level by deposition, form insulating resin layer by plastic package process.
First supporting layer 130 not only in follow-up technique for chip provides support and protective effect, an and part for package assembling as final products.Preferably, the first supporting layer 130 is metal level, for providing additional conductive channel or heat dissipation channel for chip.Alternatively, the first supporting layer 130 adopts plastic package process to be formed, thus compatible with follow-up packaging technology, and as the part of packaging body.Such as, the first supporting layer 130 can adopt epoxy resin as encapsulating compound.Plastic package process comprise epoxy resin is heated to molten condition after cover or multiple steps of parcel chip, then curing molding.Or the first supporting layer 130 can be plastic sheet, and is bonded on the second surface of chip.
Then, along dicing lane 116 cut crystal, chip 111 to 113 is adhered to together with its second surface.First supporting layer 130 is separated from one another, as shown in Figure 2 c.In cutting step, such as, use the instrument cut crystal such as diamond blade or emery wheel and the first supporting layer, obtain three chips 111 to 113 separated from one another.First supporting layer 130 provides additional protection for chip, thus can avoid chip cracks.
Then, adhesive film 151 is sticked on the surface of the second supporting layer 152.Adhesive film 151 has temperature sensitive viscosity, thus can at normal temperatures for adhering to the parts of package assembling, lose viscosity when heating, easily and the isolation of components of package assembling.The shape of the second supporting layer 152 is such as circular or square.Second supporting layer 152 can be flexible resin sheet preferably, as POLYCARBONATE SHEET etc., or sheet metal, as copper strips etc.Preferably, the second supporting layer 152 is made up of sheet metal, to obtain good mechanical strength and pliability.
Chip 111 to 113 is placed on adhesive film 151, thus utilize adhesive film 151 to be bonded on the second supporting layer 152, the placement location of chip 111 to 113 determines spacing each other as shown in Figure 2 d, and this spacing equals the package dimension of predetermined Chip scale packaging components.In this step, the surface of the first supporting layer 130 is bonded in and utilizes adhesive film 151 to be bonded on the surface of the second supporting layer 152, thus fixed chip 111 to 113.Second supporting layer 152 is as the supporting layer of subsequent technique.
In an alternative embodiment, copper carrier band can be adopted and replace the second above-mentioned supporting layer 152.Copper carrier band is conducive at follow-up packaging technology supporting chip, and can realize follow-up automation encapsulation, enhances productivity.
In the embodiment that another substitutes, bonding agent can be adopted to replace above-mentioned adhesive film.In subsequent technique, use removal of solvents bonding agent and the second supporting layer 152.
Then, above chip 111 to 113, the first encapsulated layer 132 is formed, as shown in Figure 2 e.First encapsulated layer 132 fills the space between chip, and covers the first surface of chip.Chip 111 to 113 is connected into entirety by the first encapsulated layer 132, forms encapsulating structure.This step can adopt any one in gluing or pressing mold or plastic packaging.Preferably, adopt conventional plastic package process to form the first encapsulated layer 132, epoxy resin wherein can be adopted as encapsulating compound.First encapsulated layer 132 also covers the surface of conductive projection 120.After encapsulating compound solidification, exposure perforate can be carried out further or laser beam drilling forms opening in the first encapsulated layer 132, expose the surface of conductive projection 120.
In an alternative embodiment, replace the step of perforate in the first encapsulated layer 132, adopt the surface of smooth first encapsulated layer 132 of grinding, expose the surface of conductive projection 120 simultaneously.
Then, reroute layer 133 and conductive projection 134 is formed on the surface at the first encapsulated layer 132, as shown in figure 2f.The layer 133 that reroutes is included in the wiring of the first encapsulated layer 132 horizontal expansion on the surface, and lower surface contacts with conductive projection 120, and upper surface contacts with conductive projection 134, thus realizes the electrical connection between conductive projection 120 and 134.The layer 133 that reroutes makes the conductive projection 134 connected for outside, compared with the conductive projection 132 connected for inside, can layout again, thus the spacing between increase conductive projection 134.
Because the first encapsulated layer 132 is the insulators such as formed by epoxy resin, therefore usually Direct Electroplating metal level can not be formed.In order to form the layer 133 that reroutes, can adopt chemical plating or vacuum evaporation etc. in patterned layer, form metal seed layer.Such as, this metal seed layer is made up of titanium or copper.Adopt photoresist oxidant layer, form the patterned layer comprising opening on the surface of metal seed layer, the part surface of described opening exposing metal seed layer.Then, adopt etchant optionally to remove the expose portion of metal seed layer, make the remainder of metal seed layer form the pattern of the layer that reroutes.Further, adopt plating or chemical plating that metal seed layer is thickened, thus form the layer 133 that reroutes.Such as, the thickness of this layer 133 that reroutes can be greater than 10 microns.
See Fig. 2 f, the layer 133 that reroutes fills the opening in the first encapsulated layer 132, forms the conductive path arriving conductive projection 134.In order to improve reroute layer 133 and the electrical contact of conductive projection 134, before forming above-mentioned metal seed layer, additional surface treatment step can also be comprised.This surface treatment step is such as the surface coarsening process of conductive projection 134.Soda acid chemical treatment can be adopted to obtain the surface of alligatoring.
Adopt similar technique, conductive projection 134 can be formed rerouting on layer 133.Conductive projection 134 such as adopts the formation such as copper post.
Then, form the second encapsulated layer 135 on the surface at the first encapsulated layer 132, cover reroute layer 133 and conductive projection 134, as shown in Figure 2 g.This step can adopt conventional plastic package process, and epoxy resin wherein can be adopted as encapsulating compound.Second encapsulated layer 135 also covers the surface of conductive projection 134.After encapsulating compound solidification, adopt the surface of smooth second encapsulated layer 135 of grinding further, expose the surface of conductive projection 134 simultaneously.Conductive projection 134 is direct as external pin, for external electrical connections.As can be seen here, the conductive path that chip bonding pad forms via conductive projection 120, the layer 133 that reroutes, conductive projection 134 is successively drawn.
In a preferred embodiment, solder 135 is set on the surface of conductive projection 134.Such as, this solder 135 is come to the surface block tin or the soldered ball implanted by steel mesh.In use, this solder 135 is for being fixed to outside printed circuit board (PCB) (PCB) by final package assembling.
Then, adhesive film 151 is separated with the first supporting layer 130 together with the first supporting layer 152, as shown in fig. 2h.Due to the temperature sensitivity of adhesive film 151, just can realize being separated by heating.If adopt bonding agent to replace adhesive film in aforesaid technique, then can use removal of solvents bonding agent and the second supporting layer 152 in this separating step.
Then, encapsulating structure is separated into the multiple package assemblings comprising chip 111 to 113 respectively, as shown in fig. 2i.In cutting step, such as, use the instrument such as diamond blade or emery wheel, along the region between chip, cut the second encapsulated layer 135, first encapsulated layer 132 and the second supporting layer 152 from top to bottom successively.Due to further diced chip itself can be avoided, the damage that the difficulty of aligning and chip cutting cause thus can be avoided.
Then, the second supporting layer 152 is separated with package assembling, thus obtains single package assembly 200, as shown in figure 2j.
The packaging body that package assembling 200 comprises chip 113, first supporting layer 130 and is made up of the first encapsulated layer 132 and the second encapsulated layer 135.Described chip 113 comprises relative first surface and second surface.First supporting layer 130 covers the second surface of chip 113, and the first encapsulated layer 132 covers side and the first surface of chip 113, and the second encapsulated layer 135 covers the first encapsulated layer 132.The layer 133 that reroutes is formed on the surface of the first encapsulated layer 132, and forms conductive path with the conductive projection 120 in the first encapsulated layer 132 and the conductive projection 134 in the second encapsulated layer 135.
In an example, the first supporting layer 130 can be insulation glue-line or insulating resin layer, thus forms packaging body with the first encapsulated layer 132 together with the second encapsulated layer 135.In another example, the first supporting layer 130 can be metal level.Due to the first supporting layer 130 directly contact chip 113, therefore, the first supporting layer 130 can provide additional conductive channel or heat dissipation channel for chip 113.
Chip packaging method according to this embodiment not only can realize wafer-class encapsulation, and can save lead frame and bonding line further.In the method, utilize the layer that reroutes to replace lead frame and bonding line, be arranged on reroute layer and the conductive path between the practical chip of conductive projection and external circuit in multiple encapsulated layer, and can directly utilize conductive projection directly as pin.
In a preferred embodiment, between the step shown in Fig. 2 h and 2i, namely before separate package assembly, the test of chip-scale can also be carried out, effectively improve production efficiency.
Should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
According to embodiments of the invention as described above, these embodiments do not have all details of detailed descriptionthe, do not limit the specific embodiment that this invention is only described yet.Obviously, according to above description, can make many modifications and variations.This specification is chosen and is specifically described these embodiments, is to explain principle of the present invention and practical application better, thus makes art technical staff that the present invention and the amendment on basis of the present invention can be utilized well to use.The present invention is only subject to the restriction of claims and four corner and equivalent.
Claims (28)
1. a chip packaging method, comprises;
Multiple chip is formed the first encapsulated layer, and described multiple chip comprises relative first surface and second surface respectively, and at multiple first conductive projections that described first surface is formed;
The surface of described first encapsulated layer forms the layer that reroutes;
The described layer that reroutes forms multiple second conductive projection, thus forms encapsulating structure; And
Described encapsulating structure is separated into multiple package assembling,
Wherein, described in the layer that reroutes described multiple first conductive projection is connected to described multiple second conductive projection, thus provide described multiple chip to the conductive path of external circuit.
2. method according to claim 1, between the step forming multiple second conductive projection and the step described encapsulating structure being separated into multiple package assembling, also comprises: form solder on the surface of described multiple second conductive projection.
3. method according to claim 2, wherein, described solder comprises welding block or soldered ball.
4. method according to claim 1, before the step of formation first encapsulated layer, also comprises and being fixed on supporting layer by described multiple chip.
5. method according to claim 4, comprises the step that described multiple chip is fixed on supporting layer:
The first supporting layer is formed at the back side of the wafer comprising described multiple chip;
Described wafer is separated into multiple chip together with described first supporting layer; And
Described multiple chip is fixed on the second supporting layer.
6. method according to claim 5, wherein, is fixed on described multiple chip on described second supporting layer and comprises:
Described second supporting layer arranges viscous layer; And
Described multiple chip is placed on described viscous layer, makes described first supporting layer contact described viscous layer.
7. method according to claim 6, between the step forming described multiple second conductive projection and the step described encapsulating structure being separated into multiple package assembling, also comprises:
Heat, make described viscous layer lose viscosity, thus described second supporting layer is separated with described first supporting layer.
8. method according to claim 5, wherein, is fixed on described multiple chip on described second supporting layer and comprises:
Bonding agent is adopted to be bonded on described second supporting layer by described first supporting layer.
9. method according to claim 8, between the step forming described multiple second conductive projection and the step described encapsulating structure being separated into multiple package assembling, also comprises:
Use bonding agent described in removal of solvents, described second supporting layer is separated with described first supporting layer.
10. method according to claim 5, wherein, described first supporting layer is insulation glue-line or insulating resin layer, and in described package assembling, described first supporting layer is as a part for the packaging body of described package assembling.
11. methods according to claim 5, wherein, described first supporting layer is metal level, and in described package assembling, and described first supporting layer provides additional conductive channel or heat dissipation channel for described multiple chip.
12. methods according to claim 1, wherein, before multiple chip is formed the step of the first encapsulated layer, also comprise:
Place described multiple chip according to preset space length, described preset space length corresponds to the size of described multiple package assembling.
13. methods according to claim 1, wherein, described first encapsulated layer covers the first surface of described multiple chip and the space of filling between adjacent chips, and described multiple chip is connected into entirety.
14. methods according to claim 1, wherein, the step forming the layer that reroutes comprises:
The seed layer of patterning is formed on the surface of described first encapsulated layer; And
Reroute described in described seed layer being thickened into layer.
15. methods according to claim 14, wherein, the step forming the seed layer of patterning comprises:
Form seed layer, the surface contacting described multiple first conductive projection at least partially of described seed layer;
On the surface of described seed layer, photoresist oxidant layer is adopted to form the patterned layer comprising opening;
Etchant is adopted optionally to remove the expose portion of described seed layer;
Remove described patterned layer,
Wherein, the remainder of described seed layer forms wiring pattern.
16. methods according to claim 15, wherein, adopt chemical plating or vacuum evaporation to form seed layer.
17. methods according to claim 14, wherein, adopt plating or chemical plating to thicken described seed layer.
18. methods according to claim 14, before the seed layer forming patterning, also comprise:
At described first encapsulated layer split shed, to expose the surface of described multiple first conductive projection.
19. methods according to claim 14, before the seed layer forming patterning, also comprise:
The surface of smooth described first encapsulated layer, to expose the surface of described multiple first conductive projection.
20. methods according to claim 1, before the step forming the layer that reroutes, also comprise: carry out surface coarsening process to described multiple first conductive projection.
21. methods according to claim 20, wherein adopt soda acid chemical treatment to obtain the surface of alligatoring.
22. methods according to claim 1, between the step forming described multiple second conductive projection and the step described encapsulating structure being separated into multiple package assembling, also comprise:
Described first encapsulated layer forms the second encapsulated layer, and reroute described in described second encapsulated layer covers layer and described multiple second conductive projection; And
The surface of smooth described second encapsulated layer, to expose the surface of described multiple second conductive projection.
23. 1 kinds of package assemblings, comprising:
Chip, described chip has relative first surface and second surface;
Multiple first conductive projection, is positioned on the first surface of described chip;
Supporting layer, is attached on the second surface of described chip;
First encapsulated layer, covers first surface and the side of described chip;
Reroute layer, is positioned on the surface of described first encapsulated layer, and with described multiple first conductive projection electrical contact;
Multiple second conductive projection, reroutes described in being positioned on layer,
Wherein, described in the layer that reroutes described multiple first conductive projection is connected to described multiple second conductive projection, thus provide described multiple chip to the conductive path of external circuit.
24. package assemblings according to claim 23, also comprise: the solder formed on the surface of described multiple second conductive projection.
25. package assemblings according to claim 24, described solder comprises welding block or soldered ball.
26. package assemblings according to claim 23, wherein, described supporting layer is insulation glue-line or insulating resin layer, and a part for packaging body as described package assembling.
27. package assemblings according to claim 23, wherein, described supporting layer is metal level, and provides additional conductive channel or heat dissipation channel for described chip.
28. package assemblings according to claim 23, also comprise:
Second encapsulated layer, is positioned on described first encapsulated layer, and exposes the surface of described multiple second conductive projection.
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