CN101202259A - Chip stack encapsulation structure, inner embedded type chip packaging structure and method of manufacture - Google Patents
Chip stack encapsulation structure, inner embedded type chip packaging structure and method of manufacture Download PDFInfo
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- CN101202259A CN101202259A CNA2006101693012A CN200610169301A CN101202259A CN 101202259 A CN101202259 A CN 101202259A CN A2006101693012 A CNA2006101693012 A CN A2006101693012A CN 200610169301 A CN200610169301 A CN 200610169301A CN 101202259 A CN101202259 A CN 101202259A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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Abstract
An interior-type chip packaging structure comprises a base plate, a semiconductor structure, a sealing material layer and a plurality of through holes; wherein, the base plate comprises at least a dielectric layer and at least a patterned line layer which is arranged on the dielectric layer; the semiconductor structure which is positioned on the base plate is provided with a plurality of electric gaskets which are in contact with the dielectric layer; the sealing material layer is arranged on the base plate around the semiconductor structure; additionally, a plurality of through holes are arranged in the base plate, thus the patterned line layer can be electrically connected with the electric gaskets.
Description
Technical field
The present invention relates to a kind of chip-packaging structure and manufacture method thereof, and be particularly related to a kind of chip stack package structure, buried chip encapsulation structure and manufacture method thereof.
Background technology
In semiconductor industry, the purpose of Chip Packaging is to prevent that bare chip is subjected to moisture, heat and The noise, and the medium that electrically connects between bare chip and the external circuit is provided.In recent years, along with making rapid progress and the continuous integration and the innovation of high-tech electronic product of electronic technology, the conventional semiconductor package technology can't satisfy product function and cost demand.At present, semiconductor packaging strides forward towards the trend that chip is integrated in the circuit substrate, so that whole package area/volume dwindles significantly, reaches the demand of compactization of electronic product, multifunction, high speed and densification.
The main making flow process of existing chip buried-in encapsulation technology is, earlier chip is loaded on the substrate, utilizes dielectric material that chip is buried in wherein afterwards again.Generally speaking, dielectric material can utilize modes such as rotary coating, printing or pressing and be formed on the chip, but this mode causes the air spots of dielectric material smooth easily, and influences subsequent technique.Particularly,, tend to thickness difference, cause the uniformity of dielectric material surface not good, and influence process yield because of chip and substrate at the thicker chip of thickness.Therefore, need utilize lapping mode with the chip thinning usually after, carry out the chip buried-in packaging technology again, or need use more multi-dielectric material, to improve the uniformity.But grinding steps can make manufacturing cost improve, and causes the chip damage easily, and is coated with more that the mode of multi-dielectric material can increase manufacturing cost equally.
About the chip buried-in encapsulation technology, industry also proposes different ways.For example, (Freescale Semiconductor, Inc.) company just proposes the related semiconductor encapsulation technology about the chip buried-in packaged type to the Freescale semiconductor.In addition, the publication number 6759270 of U.S. patent application case (US 6759270) exercise question is " Semiconductor chip module and method of manufacture of same ", its content discloses, earlier in substrate, make groove (cavity) as chip buried district, afterwards chip is placed in the groove, then carry out technologies such as dielectric material coating, metallic circuit shaping and pad making more in regular turn, to finish the chip buried-in encapsulation.Yet the mode of this piece patent needs extra packing material filling up the gap of chip and substrate, and has the substrate uppity problem of main package thickness and depth of groove that still can account for.
In addition, the publication number 6469374 of U.S. patent application case (US 6469374) exercise question is " Superposed printed substrates and insulating substrates having semiconductorelements inside ", it is to utilize the mode of a plurality of hollow substrates of superposition to form the groove that buries chip in order to interior, to carry out the chip buried-in packaging technology.The mode of this piece patent still exist substrate account for main package thickness, need extra packing material filling up the gap of chip and substrate, and problems such as contraposition between substrate.
Therefore, how with chip buried-in in circuit substrate and the variety of problems that can avoid existing chip encapsulation technology to be produced, become current key technology.
Summary of the invention
The invention provides a kind of chip stack package structure, buried chip encapsulation structure and manufacture method thereof, can avoid the variety of problems of existing encapsulation, and can and save the technology cost with existing process compatible, simplification technology.
The present invention proposes a kind of buried chip encapsulation structure, and this structure comprises substrate, semiconductor structure, involution material layer and a plurality of via.Wherein, substrate comprises at least one dielectric layer and at least one patterned line layer that is arranged on the dielectric layer.Semiconductor structure is arranged on the substrate, has a plurality of first electric connection pad on this semiconductor structure, and these first electric connection pads contact with dielectric layer.The involution material layer is arranged on the semiconductor structure substrate on every side.In addition, above-mentioned a plurality of vias are arranged in the substrate, so that patterned line layer electrically connects these first electric connection pads.
Hold above-mentionedly, the material of involution material layer for example is mould envelope compound or perfusion compound.Semiconductor structure is the semiconductor chip with first electric connection pad.In addition, semiconductor structure can also be for being made of semiconductor chip and metal level, and the first electric connection pad is positioned on the semiconductor chip.In addition, semiconductor structure can also be made up of first semiconductor chip, articulamentum and second semiconductor chip.Wherein, has the first electric connection pad on first semiconductor chip.Articulamentum is arranged on first semiconductor chip, and it can be adhesion layer or metal level.Second semiconductor chip is arranged on the articulamentum, and the second semiconductor chip upper surface has a plurality of second electric connection pad, and its lower surface contacts with articulamentum.
The present invention proposes a kind of buried chip encapsulation structure in addition, and this structure comprises first substrate, semiconductor structure, involution material layer, a plurality of first via, second substrate and a plurality of second via.Wherein, first substrate comprises at least one first dielectric layer and at least one first patterned line layer that is arranged on first dielectric layer.Semiconductor structure is arranged on first substrate, and has a plurality of first electric connection pad on the semiconductor structure, and these first electric connection pads contact with first dielectric layer.The involution material layer is arranged on semiconductor structure first substrate on every side.A plurality of first vias are arranged in first substrate, make first patterned line layer electrically connect the first electric connection pad.Second substrate comprises at least one second dielectric layer and at least one the second patterned circuit figure that is arranged on second dielectric layer, and second substrate is arranged on semiconductor structure and the involution material layer, and second dielectric layer contacts with semiconductor structure.A plurality of second vias are arranged in first substrate, involution material layer and second substrate, make first patterned line layer electrically connect second patterned line layer.
Hold above-mentionedly, the material of involution material layer for example is mould envelope compound or perfusion compound.And the involution material layer further comprises and being arranged on the semiconductor structure.Above-mentioned semiconductor structure is the semiconductor chip with first electric connection pad.In addition, semiconductor structure can also be for being made of semiconductor chip and metal level, and the first electric connection pad is positioned on the semiconductor chip.In addition, semiconductor structure can also be made up of first semiconductor chip, articulamentum and second semiconductor chip.Wherein, have these first electric connection pads on first semiconductor chip.Articulamentum is arranged on first semiconductor chip, and it can be adhesion layer or metal level.Second semiconductor chip is arranged on the articulamentum, and the upper surface of second semiconductor chip has a plurality of second electric connection pad, and its lower surface contacts with articulamentum.
According to the described buried chip encapsulation structure of embodiments of the invention, further comprise a plurality of the 3rd vias, so that second patterned line layer electrically connects the second electric connection pad.
The present invention reintroduces a kind of chip stack package structure.This chip stack package structure comprises bearing assembly and at least one chip-packaging structure.Wherein, bearing assembly is one of them of buried chip encapsulation structure of above-mentioned double-sided substrate.Above-mentioned chip-packaging structure is arranged on the bearing assembly, and electrically connects with bearing assembly, and this chip-packaging structure is the buried chip encapsulation structure that is selected from above-mentioned single face substrate.And bearing assembly and chip-packaging structure can utilize solder taul or the metal coupling mode electrically connects.
The present invention proposes a kind of manufacture method of buried chip encapsulation structure again.The method wherein has been formed with a plurality of first electric connection pad for to form semiconductor structure on support plate on the semiconductor structure, and the first electric connection pad contacts with support plate.Then, on the support plate around the semiconductor structure, form the involution material layer.Afterwards, remove support plate, then on involution material layer and semiconductor structure, form first substrate.Wherein, first substrate comprises at least one first dielectric layer and at least one first patterned line layer that is formed on first dielectric layer, and first dielectric layer contacts with semiconductor structure.Subsequently, in first substrate, form a plurality of first vias, so that first patterned line layer electrically connects the first electric connection pad.
On to be set forth in the method that forms the involution material layer on the support plate around the semiconductor structure for example be to carry out pressing mold step or perfusion filling step.Hold above-mentionedly, the material of involution material layer for example is mould envelope compound or perfusion compound.Semiconductor structure is the semiconductor chip with first electric connection pad.In addition, semiconductor structure can also be for being made of semiconductor chip and metal level, and the first electric connection pad is positioned on the semiconductor chip.In addition, semiconductor structure can also be made up of first semiconductor chip, articulamentum and second semiconductor chip.Wherein, have these first electric connection pads on first semiconductor chip.Articulamentum is formed on first semiconductor chip, and it can be adhesion layer or metal level.Second semiconductor chip is formed on the articulamentum, and the upper surface of second semiconductor chip has a plurality of second electric connection pad, and its lower surface contacts with articulamentum.
In addition, in first substrate, form before first via, further be included in and form second substrate on involution material layer and the semiconductor structure.Wherein, second substrate comprises at least one second dielectric layer and at least one second patterned line layer that is formed on second dielectric layer, and second dielectric layer contacts with semiconductor structure.In addition, further be included in and form a plurality of second vias in first substrate, second substrate and the involution material layer, so that first patterned line layer electrically connects second patterned line layer.And the involution material layer further comprises and being formed between the semiconductor chip and second substrate.Hold above-mentionedly, semiconductor structure is the semiconductor chip with first electric connection pad.Semiconductor structure can also be to be made of semiconductor chip and metal level, and the first electric connection pad is positioned on the semiconductor chip.In addition, semiconductor structure can also be to comprise first semiconductor chip, articulamentum and second semiconductor chip.Wherein, have the first electric connection pad on first semiconductor chip, articulamentum is formed on first semiconductor chip, and it can be adhesion layer or metal level.Second semiconductor chip is formed on the articulamentum, and the second semiconductor chip upper surface has a plurality of second electric connection pad, and its lower surface contacts with articulamentum.In the above-described embodiments, further be included in and form a plurality of the 3rd vias in second substrate, so that second patterned line layer electrically connects the second electric connection pad.
The present invention proposes a kind of manufacture method of buried chip encapsulation structure again.The method is to form first substrate on support plate, and wherein first substrate comprises at least one first dielectric layer and at least one first patterned line layer that is formed on first dielectric layer, and this first patterned line layer contacts with this support plate.Then, on first substrate, form semiconductor structure, wherein be formed with a plurality of first electric connection pad on the semiconductor structure, and these first electric connection pad and first substrate contacts.Then, on first substrate around the semiconductor structure, form the involution material layer.Subsequently, remove support plate, in first substrate, form a plurality of first vias then, so that first patterned line layer electrically connects these first electric connection pads.
On to be set forth in the method that forms the involution material layer on first substrate around the semiconductor structure for example be to carry out pressing mold step or perfusion filling step.The material of involution material layer for example is mould envelope compound or perfusion compound.Semiconductor structure is the semiconductor chip with first electric connection pad.Semiconductor structure can also be to be made of semiconductor chip and metal level, and the first electric connection pad is positioned on the semiconductor chip.In addition, semiconductor structure comprises first semiconductor chip, articulamentum and second semiconductor chip.Wherein, have these first electric connection pads on first semiconductor chip.Articulamentum is formed on first semiconductor chip, and it can be adhesion layer or metal level.Second semiconductor chip is formed on the articulamentum, and the upper surface of second semiconductor chip has a plurality of second electric connection pad, and its lower surface contacts with articulamentum.
In addition, in first substrate, form before first via, further be included in and form second substrate on involution material layer and the semiconductor structure.Wherein, second substrate comprises at least one second dielectric layer and at least one second patterned line layer that is formed on second dielectric layer, and second dielectric layer contacts with semiconductor structure.In addition, further be included in and form a plurality of second vias in first substrate, second substrate and the involution material layer, so that first patterned line layer electrically connects second patterned line layer.And the involution material layer further comprises and being formed between the semiconductor chip and second substrate.Hold above-mentionedly, semiconductor structure is the semiconductor chip with first electric connection pad.Semiconductor structure can also be to be made of semiconductor chip and metal level, and the first electric connection pad is positioned on the semiconductor chip.In addition, semiconductor structure can also be to comprise first semiconductor chip, articulamentum and second semiconductor chip.Wherein, have the first electric connection pad on first semiconductor chip, articulamentum is formed on first semiconductor chip, and it can be adhesion layer or metal level.Second semiconductor chip is formed on the articulamentum, and the second semiconductor chip upper surface has a plurality of second electric connection pad, and its lower surface contacts with articulamentum.In the above-described embodiments, further be included in and form a plurality of the 3rd vias in second substrate, so that second patterned line layer electrically connects the second electric connection pad.
Structure of the present invention is the strong layer of core (core layer) that replaces substrate in the existing encapsulating structure with the involution material layer, therefore can avoid existing variety of problems.This involution material layer can be used to support semiconductor chip and packaging body conductor layer, and can reach the purpose of protection semiconductor chip and packaging body.And involution material layer of the present invention can be selected for use closely with the thermal coefficient of expansion of semiconductor chip, or possesses the material of stress buffer, reduces the stress that produces because of thermal dilation difference between the two.Therefore in addition, structure of the present invention also includes metal level, can help whole encapsulating structure heat radiation, and can reduce the external world or in bury electromagnetic interference between stack chip.And, to compare with existing, structure of the present invention can increase the number of chips in the buried chip encapsulation structure, and can improve components performance.On the other hand, structure of the present invention can make buried chip encapsulation structure have two-sided contact, and this structure can be used as the required supporting body of storehouse encapsulation.Method of the present invention can replace existing recess process, and method of the present invention can with existing process compatible, and can make work simplification, therefore can save the technology cost.
For above and other objects of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1, Fig. 2 (a)～2 (c), Fig. 3 (a)～3 (b), Fig. 4, Fig. 5 (a)～5 (b), Fig. 6 (a)～6 (b), Fig. 7, Fig. 8 (a)～8 (b) and Fig. 9 (a)～9 (b) are respectively the generalized section of the buried chip encapsulation structure that is illustrated according to embodiments of the invention 1～9.
Figure 10 A to Figure 10 D is the generalized section according to the chip stack package structure that the embodiment of the invention illustrated.
Figure 11 A to Figure 11 D is the flow process profile of a kind of manufacture method of the buried chip encapsulation structure that illustrated according to embodiments of the invention 1-3.
Figure 12 A to Figure 12 D is the flow process profile of a kind of manufacture method of the buried chip encapsulation structure that illustrated according to embodiments of the invention 4-6.
Figure 13 A to Figure 13 D is the flow process profile of a kind of manufacture method of the buried chip encapsulation structure that illustrated according to embodiments of the invention 7-9.
Figure 14 A to Figure 14 D is the flow process profile of the another kind of manufacture method of the buried chip encapsulation structure that illustrated according to embodiments of the invention 1-3.
Figure 15 A to Figure 15 D is the flow process profile of the another kind of manufacture method of the buried chip encapsulation structure that illustrated according to embodiments of the invention 4-6.
Figure 16 A to Figure 16 D is the flow process profile of the another kind of manufacture method of the buried chip encapsulation structure that illustrated according to embodiments of the invention 7-9.
Description of reference numerals
102,202,302,412,422: dielectric layer
103,203,303,414,424: patterned line layer
104,204,304,410,420: substrate
106,106a, 408,408a: involution material layer
108,107,109,416,426: via
110,120,130,140,150,160,170,180,190: buried chip encapsulation structure
200,402: semiconductor structure
202,210,406: electric connection pad
204,208,404: semiconductor chip
206a, 206b, 206c: metal level
207: articulamentum
400: support plate
Embodiment
Below, especially exemplified by embodiment 1 to embodiment 9 to explain buried chip encapsulation structure of the present invention.Identical member gives identical label in embodiment 1 to embodiment 9, and omits the explanation that may repeat.
Fig. 1, Fig. 2 (a)～2 (c) and Fig. 3 (a)～3 (b) are respectively the structural representation that illustrates embodiment 1～3, and it all is to illustrate the buried chip encapsulation structure with single face substrate.
Please refer to Fig. 1, it is the generalized section of the buried chip encapsulation structure that illustrated according to embodiments of the invention 1.The buried chip encapsulation structure 110 of present embodiment mainly is made of substrate 104, semiconductor structure 200, involution material layer 106 and a plurality of via 108.
Wherein, substrate 104 is made of dielectric layer 102 and the patterned line layer 103 that is arranged on the dielectric layer 102.The material of dielectric layer 102 for example is polyimides (polyimide, PI), glass epoxide base resin (FR-4, FR-5), bismaleimide (bismaleimide-triazine, BT), epoxy resin (epoxy resin) or other suitable dielectric material.The material of patterned line layer 103 for example is an electric conducting material, and it can for example be a Copper Foil.Semiconductor structure 200 is arranged on the substrate 104.Have a plurality of electric connection pads (electricity pad) 202 on the semiconductor structure 200, and these electric connection pads 202 contact with dielectric layer 102.The material of electric connection pad 202 can for example be aluminium, copper, nickel/gold or other electric conducting material.In this embodiment, semiconductor structure 200 is to constitute by on semiconductor chip (semiconductorchip) 204 electric connection pad 202 being set, and wherein semiconductor chip 204 for example is a silicon.In addition, a plurality of vias 108 are arranged in the substrate 104, so that patterned line layer 103 electrically connects with electric connection pad 202.The material of via 108 for example is an electric conducting material, and it for example is copper, silver, leypewter or other suitable material.
In addition, buried chip encapsulation structure 110 also comprises involution material layer 106, and it is arranged on semiconductor structure 200 substrate 104 on every side.The material of involution material layer 106 for example is mould envelope compound (molding compound) or perfusion compound, and it for example is macromolecular material or other suitable mould envelope compound of epoxy resin, flinty soil (silica).Be noted that especially acting as of involution material layer 106 can support and protect semiconductor chip.On the other hand, because thermal coefficient of expansion (the coefficient of thermal expansion of the material of involution material layer 106 and semiconductor chip 204, CTE) close, therefore can reduce the stress that produces because of thermal dilation difference between involution material layer 106 and the semiconductor chip 204.Hold above-mentionedly, involution material layer 106 can only be arranged on around the semiconductor structure 200, and need not must cover whole assembly as existing encapsulating material.Particularly, make for the higher semiconductor chip of reduced thickness or thickness for not grinding, when carrying out encapsulation step, structure of the present invention need not utilized existing recess process, therefore can save the technology cost, and can simplify technology.
Please refer to Fig. 2 (a)～2 (c), it is the generalized section of the buried chip encapsulation structure that illustrated according to embodiments of the invention 2.The buried chip encapsulation structure 120 of present embodiment is similar with the buried chip encapsulation structure 110 of the foregoing description, only the main difference of the two is: the semiconductor structure 200 of buried chip encapsulation structure 120 can further comprise metal level 206a, 206b, 206c, and it is arranged on the semiconductor chip 204.Shown in the subgraph (a) of Fig. 2, metal level 206a only is positioned on the semiconductor chip 204; Shown in the subgraph (b) of Fig. 2, metal level 206b is positioned on the semiconductor chip 204, and is arranged on the part involution material layer 106; Shown in the subgraph (c) of Fig. 2, metal level 206c is positioned on the semiconductor chip 204, and is arranged on the involution material layer 106.The material of metal level 206a, 206b, 206c for example is copper, aluminium or other suitable metal material.This metal level 206a, 206b, 206c can be in order to helping the heat radiation of whole encapsulating structure, and can reduce the external world or in bury electromagnetic interference between stack chip (electron magnetic interfering, EMI).
Please refer to Fig. 3 (a)～3 (b), it is the generalized section of the buried chip encapsulation structure that illustrated according to embodiments of the invention 3.The buried chip encapsulation structure 130 of present embodiment is similar with buried chip encapsulation structure 110, and only main difference is: the semiconductor structure 200 of buried chip encapsulation structure 130 also can further comprise semiconductor chip 208 and articulamentum 207.Wherein, semiconductor chip 208 is arranged at semiconductor chip 204 tops, and the upper surface of semiconductor chip 208 has a plurality of electric connection pads 210, and lower surface contacts with articulamentum 207.The material of electric connection pad 210 can for example be aluminium, copper, nickel/gold or other electric conducting material.In addition, articulamentum 207 is arranged between semiconductor chip 204 and the semiconductor chip 208, and it is adhesion layer or metal level.If articulamentum 207 is for connecting the adhesion layer of semiconductor chip 204,208, its structure can be shown in the subgraph (a) of Fig. 3.If the metal level of articulamentum 207 for helping whole encapsulating structure to dispel the heat, its structure can be as the subgraph (a) of Fig. 3 with shown in the subgraph (b).In this embodiment, semiconductor structure 200 comprises semiconductor chip 204 and semiconductor chip 208, that is be to be embedded with two chips in buried chip encapsulation structure 130, therefore can increase the number of chips in the buried chip encapsulation structure, and can improve components performance.
The present invention still has other enforcement kenel except the foregoing description.Fig. 4, Fig. 5 (a)～5 (b), Fig. 6 (a)～6 (b), Fig. 7, Fig. 8 (a)～8 (b) are respectively the structural representation that illustrates embodiment 4～9 with Fig. 9 (a)～9 (b), and it all is to illustrate the buried chip encapsulation structure with double-sided substrate.
Please refer to Fig. 4, Fig. 5 (a)～5 (b) and Fig. 6 (a)～6 (b), the buried chip encapsulation structure 140,150,160 of present embodiment is similar with buried chip encapsulation structure 110,120,130 respectively, and only main difference is: buried chip encapsulation structure 140,150,160 can further comprise substrate 304.Wherein, substrate 304 is made of dielectric layer 302 and the patterned line layer 303 that is arranged on the dielectric layer 302.Substrate 304 is arranged on semiconductor structure 200 and the involution material layer 106, and dielectric layer 302 contacts with semiconductor structure 200.Above-mentioned, the material of dielectric layer 302 for example is polyimides, glass epoxide base resin, bismaleimide, epoxy resin or other suitable dielectric material.The material of patterned line layer 303 for example is an electric conducting material, and it can for example be a Copper Foil.In addition, can comprise via 109 in buried chip encapsulation structure 140,150,160, it is arranged in substrate 304, involution material layer 106 and the substrate 104, so that patterned line layer 303 electrically connects patterned line layer 103.Above-mentioned, the material of via 109 for example is an electric conducting material, and it for example is copper, silver, leypewter or other suitable material.In addition, please referring again to Fig. 6 (a)～6 (b), also can comprise via 107 in buried chip encapsulation structure 160, it is arranged in the substrate 204, so that patterned line layer 303 electrically connects electric connection pad 210.The material of via 107 for example is an electric conducting material, and it for example is copper, silver, leypewter or other suitable material.
In addition, please refer to Fig. 7,8 (a)～8 (b) and Fig. 9 (a)～9 (b), the buried chip encapsulation structure 170,180,190 of present embodiment is similar with buried chip encapsulation structure 140,150,160 respectively, only main difference is: the involution material layer 106a of buried chip encapsulation structure 170,180,190 is arranged at around the semiconductor structure 200, and covers semiconductor structure 200.
Structure of the present invention is, utilizes the involution material layer to replace existing recess process, makes buried chip encapsulation structure, therefore can save manufacturing cost.And, the present invention includes, with two back-to-back joints of chip and in be embedded in the encapsulating structure, therefore can increase the number of chips in the buried chip encapsulation structure, to improve components performance.In addition, structure of the present invention also can be provided with metal level, with help the encapsulating structure heat radiation and reduce extraneous or in bury electromagnetic interference between stack chip.In addition, structure of the present invention includes double-sided substrate, therefore can make buried chip encapsulation structure have two-sided contact, and this structure can be used as the required supporting body of storehouse encapsulation.
Next, chip stack package structure of the present invention is described.Chip stack package structure comprises bearing assembly and at least one chip-packaging structure.Wherein, chip-packaging structure is arranged on the bearing assembly, and electrically connects with bearing assembly.The quantity of chip-packaging structure can be single or multiple, and the present invention does not do special qualification to its quantity, all is with single chip-packaging structure to be the example explanation in following examples.
Please refer to Figure 10 A, it is the generalized section according to the chip stack package structure that one embodiment of the invention illustrated.In this embodiment, bearing assembly can be buried chip encapsulation structure 140, and chip-packaging structure can be buried chip encapsulation structure 110.Particularly, buried chip encapsulation structure 110 is not limited to the mode that Figure 10 A is illustrated with the relation that is provided with of buried chip encapsulation structure 140.The relation that is provided with of buried chip encapsulation structure 110,140 can for example be that the substrate 104 with buried chip encapsulation structure 110 is arranged on (shown in Figure 10 B) on the buried chip encapsulation structure 140 down.In addition, the relation that is provided with of buried chip encapsulation structure 110,140 also can for example be shown in Figure 10 C and Figure 10 D.Hold above-mentionedly, in Figure 10 A and Figure 10 C, buried chip encapsulation structure 110,140 for example is to electrically connect in solder taul (wire bonding) mode.In Figure 10 B and Figure 10 D, buried chip encapsulation structure 110,140 for example is to utilize the metal coupling mode to electrically connect, and just can for example utilize the mode that forms soldered ball to electrically connect.
In other embodiments, the bearing assembly of chip stack package structure of the present invention also can be one of them of buried chip encapsulation structure 140,150,160,170,180,190, and chip-packaging structure also can be buried chip encapsulation structure 110,120,130 one of them.Hold above-mentioned, the embodiment of other chip stack package structure of the present invention for those skilled in the art can comply with for embodiment can finish easily, so just do not illustrate and repeat no more in this.
In addition, be noted that especially the structure that is illustrated among Figure 10 A to Figure 10 D only is a schematic diagram, the present invention does not do special qualification to the bearing assembly of chip stack package structure and the size of chip-packaging structure.
Then, especially exemplified by a plurality of manufactures to explain the manufacture method of buried chip encapsulation structure of the present invention.Following graphic in, identical member gives identical label, and omits the explanation that may repeat.
Figure 11 A to Figure 11 D is the flow process profile of a kind of manufacture method of the buried chip encapsulation structure that illustrated according to embodiments of the invention 1-3.
Please refer to Figure 11 A, support plate 400 is provided, support plate 400 can for example be metallic plate, insulation board or other the suitable support plate with supportive.Then, semiconductor structure 402 is placed on the support plate 400.Above-mentioned, the method that forms semiconductor structure 402 on support plate 400 can for example be to utilize adhesive agent that semiconductor structure 402 is engaged with support plate 400.Structure with embodiment 1 is an example, and semiconductor structure 402 is to be provided with electric connection pad 406 and to be constituted by semiconductor chip 404.And the electric connection pad 406 on the semiconductor structure 402 contacts with support plate 400.The material of electric connection pad 406 can for example be aluminium, copper, nickel/gold or other electric conducting material.
In addition, be example with the structure of embodiment 2, semiconductor structure 402 can further comprise metal level (not illustrating), it can be formed on the semiconductor chip 404.The material of metal level for example is copper, aluminium or other suitable metal material.Metal level can be in order to helping the heat radiation of encapsulating structure, and can reduce electromagnetic interference, makes the chip can normal operation.Hold above-mentioned, structure with embodiment 3 is an example, semiconductor structure 402 also can further comprise another semiconductor chip (not illustrating) and the articulamentum that is formed on the semiconductor chip 404, wherein articulamentum is formed between two semiconductor chips, and is formed with electric connection pad (not illustrating) on this semiconductor chip equally.
Then, please refer to Figure 11 B, carry out pressing mold or perfusion filling step, on the support plate 400 around the semiconductor structure 402, form involution material layer 408.The material of involution material layer 408 for example is mould envelope compound or perfusion compound, and it for example is macromolecular material or other suitable mould envelope compound of epoxy resin, flinty soil.More specifically, the formation method of involution material layer 408 for example is, by on semiconductor structure, covering mould, and in wherein injecting mould envelope compound-material layer, and directly on the support plate 400 around the semiconductor structure 402, form involution material layer 408.In addition, the formation method of involution material layer 408 also can for example be, carry out the pressing mold step, on support plate 400, form mould envelope compound-material layer, and cover semiconductor structure 402, and then remove the mould envelope compound-material layer of part, to exposing semiconductor structure 402, to form involution material layer 408.In addition, in said method, also can remove part mould envelope compound-material layer and part semiconductor structure 402, to required chip thickness according to different process requirements.
Subsequently, please refer to Figure 11 C, after involution material layer 408 forms, then remove support plate 400.Then, on involution material layer 408 and semiconductor structure 402, form substrate 410.Substrate 410 is made of dielectric layer 412 and the patterned line layer 414 that is formed on the dielectric layer 412.Wherein, the material of dielectric layer 412 for example is polyimides, glass epoxide base resin, bismaleimide, epoxy resin or other suitable dielectric material.The material of patterned line layer 414 for example is an electric conducting material, and it can for example be a Copper Foil.Above-mentioned, the method that involution material layer 408 and semiconductor structure 402 are formed on the substrate 410 for example is, form dielectric layer 412 and patterned line layer 414 earlier with after constituting substrate 410, re-use adhesive agent involution material layer 408 and semiconductor structure 402 are attached on the substrate 410.In addition, the formation method that forms substrate 410 on involution material layer 408 and semiconductor structure 402 also can for example be to form one dielectric layer 412 on involution material layer 408 and semiconductor structure 402, and then form patterned line layer 414 on dielectric layer 412.
Then, please refer to Figure 11 D, 410 form a plurality of vias 416 in substrate, so that patterned line layer 414 electrically connects electric connection pad 406.The material of via 416 for example is an electric conducting material, and it for example is copper, silver, leypewter or other suitable material.The formation method of via 416 for example is to utilize the laser drill technology, forms a plurality of through holes (not illustrating) in 410 in substrate, and then insert electric conducting material in these through holes, can form.Then, after via 416 forms, can further remove part substrate 410, and cut according to different assembly required sizes.
Figure 12 A to Figure 12 D is the flow process profile of a kind of manufacture method of the buried chip encapsulation structure that illustrated according to embodiments of the invention 4-6.
Please refer to Figure 12 A～12B, its step is identical with Figure 11 A～11B, so the member identical with Figure 11 A～11B and its relativeness then repeat no more.Similarly, be example with the structure of embodiment 4, semiconductor structure 402 is to be provided with electric connection pad 406 and to be constituted by semiconductor chip 404.Structure with embodiment 5 is an example, and semiconductor structure 402 can further comprise metal level (not illustrating), and it is formed on the semiconductor chip 404.Structure with embodiment 6 is an example, semiconductor structure 402 also can further comprise another semiconductor chip (not illustrating) and the articulamentum that is formed on the semiconductor chip 404, wherein articulamentum is formed between two semiconductor chips, and is formed with electric connection pad (not illustrating) on this semiconductor chip.
Then, please refer to Figure 12 C, remove support plate 400.Then, on involution material layer 408 and semiconductor structure 402, form substrate 410 and substrate 420.Wherein, substrate 410 is made of dielectric layer 412 and patterned line layer 414.Substrate 420 is made of dielectric layer 422 and patterned line layer 424.
Then, please refer to Figure 12 D, form via 416,426, electrically connect to make patterned line layer 414 and electric connection pad 406 respectively, and patterned line layer 414 and patterned line layer 424 are electrically connected.In addition, be example with the structure of embodiment 6, in the step of Figure 12 D, also comprise forming via (not illustrating), to electrically connect patterned line layer 424 and semiconductor structure 402.Then, after forming via 416,426, can further remove part substrate 410,420, and cut according to different assembly required sizes.
Figure 13 A to Figure 13 D is the flow process profile of a kind of manufacture method of the buried chip encapsulation structure that illustrated according to embodiments of the invention 7-9.The step of the step of Figure 13 A to Figure 13 D and Figure 12 A to Figure 12 D is similar, and only main difference is: involution material layer 408a is formed at around the semiconductor structure 402, and covers semiconductor structure 402.The formation method of involution material layer 408a for example is, carries out the pressing mold step, forms mould envelope compound-material layer on support plate 400, and covers semiconductor structure 402, and then according to different process requirements, remove the mould envelope compound-material layer of part, can form.Similarly, be example with the structure of embodiment 7, semiconductor structure 402 is to be provided with electric connection pad 406 and to be constituted by semiconductor chip 404.Structure with embodiment 8 is an example, and semiconductor structure 402 can further comprise metal level (not illustrating), and it is formed on the semiconductor chip 404.Structure with embodiment 9 is an example, semiconductor structure 402 also can further comprise second half conductor chip (not illustrating) and the articulamentum (not illustrating) that is formed on the semiconductor chip 404, wherein articulamentum is formed between two semiconductor chips, and is formed with electric connection pad (not illustrating) on this semiconductor chip.
Figure 14 A to Figure 14 D is the flow process profile of the another kind of manufacture method of the buried chip encapsulation structure that illustrated according to embodiments of the invention 1-3.
Please refer to Figure 14 A, support plate 400 is provided.Then, form substrate 410 on support plate 400, substrate 410 is made of dielectric layer 412 and the patterned line layer 414 that is formed on the dielectric layer 412, and patterned line layer 414 contacts with support plate 400.
Then, please refer to Figure 14 B, on substrate 410, form semiconductor structure 402.Structure with embodiment 1 is an example, and semiconductor structure 402 is to be provided with electric connection pad 406 and to be constituted by semiconductor chip 404.Structure with embodiment 2 is an example, and semiconductor structure 402 can further comprise metal level (not illustrating), and it is formed on the semiconductor chip 404.Structure with embodiment 3 is an example, semiconductor structure 402 also can further comprise second half conductor chip (not illustrating) and the articulamentum that is formed on the semiconductor chip 404, wherein articulamentum is formed between two semiconductor chips, and is formed with electric connection pad (not illustrating) on this semiconductor chip.
Afterwards, please refer to Figure 14 C, on the support plate 400 around the semiconductor structure 402, form involution material layer 408.
Subsequently, please refer to Figure 14 D, after involution material layer 408 forms, then remove support plate 400.Then, 410 form a plurality of vias 416 in substrate, so that patterned line layer 414 electrically connects electric connection pad 406.Then, after forming via 416, can further remove part substrate 410, and cut according to different assembly required sizes.
Figure 15 A to Figure 15 D is the flow process profile of the another kind of manufacture method of the buried chip encapsulation structure that illustrated according to embodiments of the invention 4-6.
Please refer to Figure 15 A～15C, its step is identical with Figure 14 A～14C, so the member identical with Figure 14 A～14C and its relativeness then repeat no more.Structure with embodiment 4 is an example, and semiconductor structure 402 is to be provided with electric connection pad 406 and to be constituted by semiconductor chip 404.Structure with embodiment 5 is an example, and semiconductor structure 402 can further comprise metal level (not illustrating), and it is formed on the semiconductor chip 404.Structure with embodiment 6 is an example, semiconductor structure 402 also can further comprise second half conductor chip (not illustrating) and the articulamentum that is formed on the semiconductor chip 404, wherein articulamentum is formed between two semiconductor chips, and is formed with electric connection pad (not illustrating) on this semiconductor chip.
Then, please refer to Figure 15 D.Form substrate 420 on involution material layer 408 and semiconductor structure 402, wherein substrate 420 is made of dielectric layer 422 and patterned line layer 424.Afterwards, remove support plate 400, then form via 416,426, electrically connect to make patterned line layer 414 and electric connection pad 406 respectively, and patterned line layer 414 and patterned line layer 424 are electrically connected.In addition, be example with the structure of embodiment 6, in the step of Figure 15 D, also comprise forming via (not illustrating), to electrically connect patterned line layer 424 and semiconductor structure 402.Then, after forming via 416,426, can further remove part substrate 410,420, and cut according to different assembly required sizes.
Figure 16 A to Figure 16 D is the flow process profile of the another kind of manufacture method of the buried chip encapsulation structure that illustrated according to embodiments of the invention 7-9.
The step of the step of Figure 16 A to Figure 16 D and Figure 15 A to Figure 15 D is similar, and only main difference is: involution material layer 408a is formed at around the semiconductor structure 402, and covers semiconductor structure 402.Similarly, be example with the structure of embodiment 7, semiconductor structure 402 is to be provided with electric connection pad 406 and to be constituted by semiconductor chip 404.Structure with embodiment 8 is an example, and semiconductor structure 402 can further comprise metal level (not illustrating), and it is formed on the semiconductor chip 404.Structure with embodiment 9 is an example, semiconductor structure 402 also can further comprise second half conductor chip (not illustrating) and the articulamentum that is formed on the semiconductor chip 404, wherein articulamentum is formed between two semiconductor chips, and is formed with electric connection pad (not illustrating) on this semiconductor chip.In addition, be example with the structure of embodiment 6, in the step of Figure 16 D, also comprise forming via (not illustrating), to electrically connect patterned line layer 424 and semiconductor structure 402.
From the above, method of the present invention is to utilize pressing mold or perfusion filling mode to form the involution material layer, to replace existing recess process, carries out the encapsulation of built-in type chip.Compare with existing, method of the present invention can with existing process compatible, and can make work simplification, therefore can save the technology cost.
In sum, the present invention can have following advantage:
1. structure of the present invention is the strong layer of core (core layer) that replaces substrate in the existing encapsulating structure with the involution material layer, therefore can avoid existing variety of problems.This involution material layer can be used to support semiconductor chip and packaging body conductor layer, and can reach the purpose of protection semiconductor chip and packaging body.And involution material of the present invention can be selected for use closely with the thermal coefficient of expansion of semiconductor chip, or possesses the material of stress buffer, reduces the stress that produces because of thermal dilation difference between the two.
2. structure of the present invention can help the heat radiation of whole encapsulating structure, and can reduce the external world or in bury electromagnetic interference between stack chip.In addition, compare with existing, structure of the present invention can increase the number of chips in the buried chip encapsulation structure, and can improve components performance.
3. structure of the present invention can make buried chip encapsulation structure have two-sided contact, and this structure can be used as the required supporting body of storehouse encapsulation.
4. method of the present invention can replace existing recess process, and method of the present invention can with existing process compatible, and can make work simplification, therefore can save the technology cost.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art without departing from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is by being as the criterion that claim defined.
Claims (46)
1. buried chip encapsulation structure comprises:
Substrate, this substrate comprise at least one dielectric layer and at least one patterned line layer that is arranged on this dielectric layer;
Semiconductor structure is arranged on this substrate, has a plurality of first electric connection pad on this semiconductor structure, and this first electric connection pad contacts with this dielectric layer;
The involution material layer is arranged on this semiconductor structure this substrate on every side; And
A plurality of vias are arranged in this substrate, make this patterned line layer electrically connect this first electric connection pad.
2. buried chip encapsulation structure as claimed in claim 1, wherein the material of this involution material layer comprises mould envelope compound or perfusion compound.
3. buried chip encapsulation structure as claimed in claim 1, wherein this semiconductor structure is the semiconductor chip with this first electric connection pad.
4. buried chip encapsulation structure as claimed in claim 1, wherein this semiconductor structure is for to be made of semiconductor chip and metal level, and this first electric connection pad is positioned on this semiconductor chip.
5. buried chip encapsulation structure as claimed in claim 1, wherein this semiconductor structure comprises:
First semiconductor chip has this first electric connection pad on this first semiconductor chip;
Articulamentum is arranged on this first semiconductor chip; And
Second semiconductor chip is arranged on this articulamentum, and this second semiconductor chip upper surface has a plurality of second electric connection pad, and its lower surface contacts with this articulamentum.
6. buried chip encapsulation structure as claimed in claim 5, wherein this articulamentum is adhesion layer or metal level.
7. buried chip encapsulation structure comprises:
First substrate, this first substrate comprise at least one first dielectric layer and at least one first patterned line layer that is arranged on this first dielectric layer;
Semiconductor structure is arranged on this first substrate, has a plurality of first electric connection pad on this semiconductor structure, and this first electric connection pad contacts with this first dielectric layer;
The involution material layer is arranged on this semiconductor structure this first substrate on every side;
A plurality of first vias are arranged in this first substrate, make this first patterned line layer electrically connect this first electric connection pad;
Second substrate comprises at least one second dielectric layer and at least one the second patterned circuit figure that is arranged on this second dielectric layer, and this second substrate is arranged on this semiconductor structure and this involution material layer, and this second dielectric layer contacts with this semiconductor structure; And
A plurality of second vias are arranged in this first substrate, this involution material layer and this second substrate, make this first patterned line layer electrically connect this second patterned line layer.
8. buried chip encapsulation structure as claimed in claim 7, wherein the material of this involution material layer comprises mould envelope compound or perfusion compound.
9. buried chip encapsulation structure as claimed in claim 7, wherein this involution material layer further comprises and being arranged on this semiconductor structure.
10. buried chip encapsulation structure as claimed in claim 7, wherein this semiconductor structure is the semiconductor chip with this first electric connection pad.
11. buried chip encapsulation structure as claimed in claim 7, wherein this semiconductor structure is for to be made of semiconductor chip and metal level, and this first electric connection pad is positioned on this semiconductor chip.
12. buried chip encapsulation structure as claimed in claim 7, wherein this semiconductor structure comprises:
First semiconductor chip has this first electric connection pad on this first semiconductor chip;
Articulamentum is arranged on this first semiconductor chip; And
Second semiconductor chip is arranged on this articulamentum, and the upper surface of this second semiconductor chip has a plurality of second electric connection pad, and its lower surface contacts with this articulamentum.
13. buried chip encapsulation structure as claimed in claim 12, wherein this articulamentum is adhesion layer or metal level.
14. buried chip encapsulation structure as claimed in claim 12 further comprises a plurality of the 3rd vias, so that this second patterned line layer electrically connects this second electric connection pad.
15. a chip stack package structure comprises:
Bearing assembly, this bearing assembly be as claim 7 to the 14th described buried chip encapsulation structure one of them; And
At least one chip-packaging structure is arranged on this bearing assembly, and electrically connects with this bearing assembly, and wherein this chip-packaging structure is for being selected from as claim 1 to the 6th described buried chip encapsulation structure.
16. chip stack package structure as claimed in claim 15, wherein this bearing assembly and this chip-packaging structure can utilize solder taul or the metal coupling mode electrically connects.
17. the manufacture method of a buried chip encapsulation structure comprises:
On support plate, form semiconductor structure, wherein be formed with a plurality of first electric connection pad on this semiconductor structure, and this first electric connection pad contacts with this support plate;
On this support plate around this semiconductor structure, form the involution material layer;
Remove this support plate;
On this involution material layer and this semiconductor structure, form first substrate, wherein this first substrate comprises at least one first dielectric layer and at least one first patterned line layer that is formed on this first dielectric layer, and this first dielectric layer contacts with this semiconductor structure; And
In this first substrate, form a plurality of first vias, so that this first patterned line layer electrically connects this first electric connection pad.
18. the manufacture method of buried chip encapsulation structure as claimed in claim 17, the method that wherein forms this involution material layer on this support plate around this semiconductor structure comprise, carry out pressing mold step or perfusion filling step.
19. the manufacture method of buried chip encapsulation structure as claimed in claim 17, wherein the material of this involution material layer comprises mould envelope compound or perfusion compound.
20. the manufacture method of buried chip encapsulation structure as claimed in claim 17, wherein this semiconductor structure is the semiconductor chip with this first electric connection pad.
21. the manufacture method of buried chip encapsulation structure as claimed in claim 17, wherein this semiconductor structure is for to be made of semiconductor chip and metal level, and this first electric connection pad is positioned on this semiconductor chip.
22. the manufacture method of buried chip encapsulation structure as claimed in claim 17, wherein this semiconductor structure comprises:
First semiconductor chip has this first electric connection pad on this first semiconductor chip;
Articulamentum is formed on this first semiconductor chip; And
Second semiconductor chip is formed on this articulamentum, and this second semiconductor chip upper surface has a plurality of second electric connection pad, and its lower surface contacts with this articulamentum.
23. the manufacture method of buried chip encapsulation structure as claimed in claim 22, wherein this articulamentum is adhesion layer or metal level.
24. the manufacture method of buried chip encapsulation structure as claimed in claim 17, wherein in this first substrate, form before those first vias, further comprise: on this involution material layer and this semiconductor structure, form second substrate, wherein this second substrate comprises at least one second dielectric layer and at least one second patterned line layer that is formed on this second dielectric layer, and this second dielectric layer contacts with this semiconductor structure.
25. the manufacture method of buried chip encapsulation structure as claimed in claim 24, further be included in and form a plurality of second vias in this substrate, this second substrate and this involution material layer, so that this first patterned line layer electrically connects this second patterned line layer.
26. the manufacture method of buried chip encapsulation structure as claimed in claim 24, wherein this involution material layer further comprises and being formed between this semiconductor chip and this second substrate.
27. the manufacture method of buried chip encapsulation structure as claimed in claim 24, wherein this semiconductor structure is the semiconductor chip with this first electric connection pad.
28. the manufacture method of buried chip encapsulation structure as claimed in claim 24, wherein this semiconductor structure is for to be made of semiconductor chip and metal level, and this first electric connection pad is positioned on this semiconductor chip.
29. the manufacture method of buried chip encapsulation structure as claimed in claim 24, wherein this semiconductor structure comprises:
First semiconductor chip has this first electric connection pad on this first semiconductor chip;
Articulamentum is formed on this first semiconductor chip; And
Second semiconductor chip is formed on this articulamentum, and this second semiconductor chip upper surface has a plurality of second electric connection pad, and its lower surface contacts with this articulamentum.
30. the manufacture method of buried chip encapsulation structure as claimed in claim 29, wherein this articulamentum is adhesion layer or metal level.
31. the manufacture method of buried chip encapsulation structure as claimed in claim 29 is selected a step to be included in and is formed a plurality of the 3rd vias in this second substrate, so that this second patterned line layer electrically connects this second electric connection pad.
32. the manufacture method of a buried chip encapsulation structure comprises:
Form first substrate on support plate, wherein this first substrate comprises at least one first dielectric layer and at least one first patterned line layer that is formed on this first dielectric layer, and this first patterned line layer contacts with this support plate;
On this first substrate, form semiconductor structure, wherein be formed with a plurality of first electric connection pad on this semiconductor structure, and this first electric connection pad and this first substrate contacts;
On this first substrate around this semiconductor structure, form the involution material layer;
Remove this support plate; And
In this first substrate, form a plurality of first vias, so that this first patterned line layer electrically connects this first electric connection pad.
33. the manufacture method of buried chip encapsulation structure as claimed in claim 32, the method that wherein forms this involution material layer on this first substrate around this semiconductor structure comprise, carry out pressing mold step or perfusion filling step.
34. the manufacture method of buried chip encapsulation structure as claimed in claim 32, wherein the material of this involution material layer comprises mould envelope compound or perfusion compound.
35. the manufacture method of buried chip encapsulation structure as claimed in claim 32, wherein this semiconductor structure is the semiconductor chip with this first electric connection pad.
36. the manufacture method of buried chip encapsulation structure as claimed in claim 32, wherein this semiconductor structure is for to be made of semiconductor chip and metal level, and this first electric connection pad is positioned on this semiconductor chip.
37. the manufacture method of buried chip encapsulation structure as claimed in claim 32, wherein this semiconductor structure comprises:
First semiconductor chip has this first electric connection pad on this first semiconductor chip;
Articulamentum is formed on this first semiconductor chip; And
Second semiconductor chip is formed on this articulamentum, and this second semiconductor chip upper surface has a plurality of second electric connection pad, and its lower surface contacts with this articulamentum.
38. the manufacture method of buried chip encapsulation structure as claimed in claim 37, wherein this articulamentum is adhesion layer or metal level.
39. the manufacture method of buried chip encapsulation structure as claimed in claim 32, wherein in this first substrate, form before this first via, further comprise: on this involution material layer and this semiconductor structure, form second substrate, wherein this second substrate comprises at least one second dielectric layer and at least one second patterned line layer that is formed on this second dielectric layer, and this second dielectric layer contacts with this semiconductor structure.
40. the manufacture method of buried chip encapsulation structure as claimed in claim 39, further be included in and form a plurality of second vias in this first substrate, this second substrate and this involution material layer, so that this first patterned line layer electrically connects this second patterned line layer.
41. the manufacture method of buried chip encapsulation structure as claimed in claim 39, wherein this involution material layer further comprises and being formed between this first semiconductor chip and this second substrate.
42. the manufacture method of buried chip encapsulation structure as claimed in claim 39, wherein this semiconductor structure is the semiconductor chip with this first electric connection pad.
43. the manufacture method of buried chip encapsulation structure as claimed in claim 39, wherein this semiconductor structure is for to be made of semiconductor chip and metal level, and this first electric connection pad is positioned on this semiconductor chip.
44. the manufacture method of buried chip encapsulation structure as claimed in claim 39, wherein this semiconductor structure comprises:
First semiconductor chip has this first electric connection pad on this first semiconductor chip;
Articulamentum is formed on this first semiconductor chip; And
Second semiconductor chip is formed on this articulamentum, and this second semiconductor chip upper surface has a plurality of second electric connection pad, and its lower surface contacts with this articulamentum.
45. the manufacture method of buried chip encapsulation structure as claimed in claim 44, wherein this articulamentum is adhesion layer or metal level.
46. the manufacture method of buried chip encapsulation structure as claimed in claim 44 further is included in and forms a plurality of the 3rd vias in this second substrate, so that this second patterned line layer electrically connects this second electric connection pad.
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| CN2006101693012A CN101202259B (en) | 2006-12-13 | 2006-12-13 | Chip stack encapsulation structure, inner embedded type chip packaging structure and method of manufacture |
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| CN2006101693012A CN101202259B (en) | 2006-12-13 | 2006-12-13 | Chip stack encapsulation structure, inner embedded type chip packaging structure and method of manufacture |
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| CN102315136A (en) * | 2011-06-02 | 2012-01-11 | 日月光半导体制造股份有限公司 | Package structure and manufacturing method thereof |
| CN101964338B (en) * | 2009-07-24 | 2012-11-14 | 日月光半导体制造股份有限公司 | Semiconductor packaging part and manufacturing method thereof as well as chip-redistribution encapsulant |
| CN102956594A (en) * | 2011-08-16 | 2013-03-06 | 通用电气公司 | Power overlay structure with leadframe connections |
| CN105575825A (en) * | 2015-12-24 | 2016-05-11 | 合肥祖安投资合伙企业(有限合伙) | Chip packaging method and packaging assembly |
| US10269688B2 (en) | 2013-03-14 | 2019-04-23 | General Electric Company | Power overlay structure and method of making same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100446200C (en) * | 2005-02-28 | 2008-12-24 | 矽品精密工业股份有限公司 | Heat radiation type packaging structure and its making method |
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- 2006-12-13 CN CN2006101693012A patent/CN101202259B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101964338B (en) * | 2009-07-24 | 2012-11-14 | 日月光半导体制造股份有限公司 | Semiconductor packaging part and manufacturing method thereof as well as chip-redistribution encapsulant |
| CN102315136A (en) * | 2011-06-02 | 2012-01-11 | 日月光半导体制造股份有限公司 | Package structure and manufacturing method thereof |
| CN102956594A (en) * | 2011-08-16 | 2013-03-06 | 通用电气公司 | Power overlay structure with leadframe connections |
| CN102956594B (en) * | 2011-08-16 | 2017-07-18 | 通用电气公司 | The power overlay structure connected with lead frame |
| US10269688B2 (en) | 2013-03-14 | 2019-04-23 | General Electric Company | Power overlay structure and method of making same |
| CN105575825A (en) * | 2015-12-24 | 2016-05-11 | 合肥祖安投资合伙企业(有限合伙) | Chip packaging method and packaging assembly |
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| Publication number | Publication date |
|---|---|
| CN101202259B (en) | 2010-07-21 |
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