CN110098130B - System-level packaging method and packaging device - Google Patents
System-level packaging method and packaging device Download PDFInfo
- Publication number
- CN110098130B CN110098130B CN201910189755.3A CN201910189755A CN110098130B CN 110098130 B CN110098130 B CN 110098130B CN 201910189755 A CN201910189755 A CN 201910189755A CN 110098130 B CN110098130 B CN 110098130B
- Authority
- CN
- China
- Prior art keywords
- chip
- layer
- grounding
- electromagnetic shielding
- functional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
The application discloses a system-level packaging method and a packaging device, wherein the packaging method comprises the steps of forming a first electromagnetic shielding layer on a non-functional surface and a side surface adjacent to the non-functional surface of a chip, wherein the first electromagnetic shielding layer is electrically connected with a first grounding bonding pad on the functional surface of the chip; inversely installing at least one chip on a first surface of a substrate, wherein the functional surface faces the first surface, the first surface is provided with an exposed second grounding pad, a grounding layer is arranged in the substrate, and the second grounding pad is electrically connected with the grounding layer; and forming a conductive connecting piece on the first surface, wherein one end of the conductive connecting piece is electrically connected with the first electromagnetic shielding layer, and the other end of the conductive connecting piece is electrically connected with the second grounding bonding pad. By the mode, the manufacturing process for realizing the electromagnetic shielding between the chips can be simplified.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a system-in-package method and a package device.
Background
System In Package (SiP) is a package in which a plurality of different types of chips (e.g., high speed digital circuits, analog circuits, radio frequency circuits, etc.) are packaged in one package device to achieve high integration requirements. As the distance between chips gets closer and closer, the problem of electromagnetic interference between chips becomes more and more prominent.
In order to solve the problem of electromagnetic interference between chips, Albert Lin et al proposed a solution in the article "electric performance characterization for novel multiple components screening and verification on LTE modem SiP": the method comprises the steps of carrying out plastic package on the whole system-in-package device, etching a groove by utilizing laser, and filling the groove with an electromagnetic shielding material such as conductive adhesive, so that electromagnetic shielding among a plurality of chips in the system-in-package device is realized.
The inventor of the present application found in the long-term research process that the trench needs to be etched by using laser in the above method, and the process is complicated.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a system-level packaging method, which can simplify the manufacturing process for realizing the electromagnetic shielding between chips.
In order to solve the technical problem, the application adopts a technical scheme that: there is provided a system-in-package method, the packaging method comprising: forming a first electromagnetic shielding layer on a non-functional surface and a side surface adjacent to the non-functional surface of a chip, wherein the first electromagnetic shielding layer is electrically connected with a first grounding pad on the functional surface of the chip; inversely installing at least one chip on a first surface of a substrate, wherein the functional surface faces the first surface, the first surface is provided with an exposed second grounding pad, a grounding layer is arranged in the substrate, and the second grounding pad is electrically connected with the grounding layer; and forming a conductive connecting piece on the first surface, wherein one end of the conductive connecting piece is electrically connected with the first electromagnetic shielding layer, and the other end of the conductive connecting piece is electrically connected with the second grounding bonding pad.
Wherein, before the first electromagnetic shielding layer is formed on the non-functional surface and the side surface adjacent to the non-functional surface of the chip, the packaging method further comprises: providing a wafer, wherein the wafer is provided with a plurality of chips arranged in a matrix, and scribing grooves are formed in the positions of the wafer among the chips; forming a ground via on the functional surface of the chip, one end of the ground via being electrically connected to the first ground pad, and the other end of the ground via extending to the scribe line adjacent to the first ground pad; and cutting along the scribing grooves of the wafer, wherein the other end of the grounding path is flush with the side face of the chip.
Wherein before the dicing the scribe line of the wafer, the packaging method further comprises: arranging a first protection film on the grounding path; forming metal bumps on all the pads on the functional surface; and removing the first protective film.
Wherein, form first electromagnetic shield layer in the non-functional face of chip and with the side that non-functional face is adjacent, include: providing a fixing jig, wherein the fixing jig comprises a through hole, and a second protective film is arranged at the edge of the through hole; placing the chip on the fixing jig, wherein the metal salient points of the chip correspond to the through holes, and the grounding path is in contact with the second protective film; and forming the first electromagnetic shielding layer on the non-functional surface of the chip and the side surface of the chip by sputtering.
Wherein before the dicing along the scribe line of the wafer, the packaging method further comprises: forming an insulating layer on the functional surface of the chip, wherein the insulating layer is flush with the metal salient points, and the metal salient points are exposed out of the insulating layer; alternatively, before the forming the conductive connection member on the first surface, the packaging method further includes: and forming an insulating layer between the functional surface and the first surface of the chip, wherein the side surface of the insulating layer is an inclined surface.
Wherein the packaging method further comprises: forming a plastic packaging layer on the first surface of the substrate, wherein the plastic packaging layer covers at least one chip; and forming second electromagnetic shielding layers on the surface of the plastic packaging layer and the side surface of the substrate, wherein two ends of the grounding layer are exposed out of the side surface of the substrate, and the second electromagnetic shielding layers are electrically connected with the grounding layer.
In order to solve the above technical problem, another technical solution adopted by the present application is: providing a system-in-package device, the packaged device comprising: the chip comprises a functional surface and a non-functional surface which are arranged oppositely, and a first grounding bonding pad is arranged on the functional surface; the substrate is used for bearing the chip and comprises a first surface and a second surface which are arranged in an opposite way, the first surface is provided with an exposed second grounding pad, a grounding layer is arranged in the substrate, and the second grounding pad is electrically connected with the grounding layer; wherein the functional face faces the first surface; the first electromagnetic shielding layer covers the non-functional surface and the side surface adjacent to the non-functional surface of the chip, and is electrically connected with the first grounding bonding pad; the conductive connecting piece is located on the first surface of the substrate, one end of the conductive connecting piece is electrically connected with the first electromagnetic shielding layer, and the other end of the conductive connecting piece is electrically connected with the second grounding pad.
The functional surface of the chip is further provided with a grounding path, one end of the grounding path is electrically connected with the first grounding pad, the surface of the other end of the grounding path is flush with the side surface of the chip, and the first electromagnetic shielding layer covers the surface of the other end of the grounding path.
Wherein the packaged device further comprises: the insulating layer fills the area between the functional surface of the chip and the first surface of the substrate, the side surface of the insulating layer is an inclined surface, and the conductive connecting piece extends along the inclined surface.
The functional surface of the chip is also provided with a metal bump, and the metal bump extends from the surface of the first grounding bonding pad; and/or, the packaged device further comprises: a plastic sealing layer covering an outer surface of the first electromagnetic shielding layer and the first surface of the substrate; the second electromagnetic shielding layer covers the outer surface of the plastic packaging layer and the side surface of the substrate; wherein both ends of the ground layer are exposed from the side surface of the substrate, and the second electromagnetic shielding layer is electrically connected with the ground layer; and/or a via hole is arranged between the second grounding pad of the substrate and the grounding layer, and a conductive material is filled in the via hole.
The beneficial effect of this application is: different from the prior art, the system-in-package method provided by the present application includes: forming a first shielding layer on the non-functional surface and the side surface adjacent to the non-functional surface of the chip, wherein the first shielding layer is electrically connected with a first grounding bonding pad on the chip; flip-chip mounting at least one chip on a first surface of a substrate; and forming a conductive connecting piece on the first surface, wherein one end of the conductive connecting piece is electrically connected with the first electromagnetic shielding layer, and the other end of the conductive connecting piece is electrically connected with the second grounding bonding pad exposed on the substrate. The second grounding pad is electrically connected with the grounding layer in the substrate, so that the first electromagnetic shielding layer, the conductive connecting piece and the grounding layer can form a closed loop through the conductive connecting piece, and electromagnetic shielding among a plurality of chips in the system-in-package device is realized. Compared with the prior art, laser grooving and conductive adhesive filling are not needed, the process is simple and easy to achieve, and the shielding effect is good.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
fig. 1 is a schematic flow chart of an embodiment of a system-in-package method according to the present application;
FIG. 2 is a schematic structural diagram of an embodiment corresponding to steps S101-S105 in FIG. 1;
fig. 3 is a schematic flowchart illustrating an embodiment of a system in package method before step S101 in fig. 1;
FIG. 4 is a schematic structural diagram illustrating an embodiment of steps S201-S203 in FIG. 3;
FIG. 5 is a schematic structural diagram of another embodiment corresponding to step S102 in FIG. 1;
FIG. 6 is a schematic structural diagram of an embodiment of a system-in-package device according to the present application;
fig. 7 is a schematic structural diagram of another embodiment of the system-in-package device according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1-2, fig. 1 is a schematic flow chart diagram of an embodiment of a system-in-package method of the present application, and fig. 2 is a schematic structural diagram of an embodiment corresponding to steps S101-S105 in fig. 1, where the packaging method includes:
s101: the first electromagnetic shield layer 16 is formed on the non-functional side 120 of the chip 12 and the side surface 128 adjacent to the non-functional side 120, and the first electromagnetic shield layer 16 is electrically connected to the first ground pad 124 on the functional side 120 of the chip 12.
Specifically, referring to fig. 2a, the number of the first ground pads 124 disposed on the functional surface 120 of the chip 12 may be one or more, and may be set according to actual needs. For example, when one or more functional area modules on the chip 12 need to be electromagnetically shielded, the first ground pad 124 may be disposed on the functional area module. Further, other pads are provided on the functional surface 120 of the chip 12.
In this embodiment, the chip 12 may be formed by cutting the wafer 20, as shown in fig. 3 and fig. 4, fig. 3 is a schematic flow chart of an embodiment of the system-in-package method before step S101 in fig. 1, and fig. 4 is a schematic structural diagram of an embodiment of step S201 to step S203 in fig. 3.
S201: a wafer 20 is provided, the wafer 20 being provided with a plurality of chips 12 arranged in a matrix, the wafer 20 being provided with scribe lanes 14 at positions between the chips 12.
Specifically, as shown in fig. 4a, in the present embodiment, four first ground pads 124 may be disposed on the functional surface 120 of the chip 12, and the four first ground pads 124 may be disposed symmetrically or asymmetrically, which is not limited in the present application.
S202: a ground via 126 is formed on the functional surface 120 of the chip 12, one end (not labeled) of the ground via 126 is electrically connected to the first ground pad 124, and the other end (not labeled) of the ground via 126 extends to the scribe line 14 adjacent to the first ground pad 124.
Specifically, as shown in fig. 4b, the method for forming the ground via 126 may be similar to the metal re-wiring, for example, a sputtering method or the like may be adopted, and it is necessary to take care to make an insulation isolation from the functional surface 120 of the chip 12 when forming the ground via 126.
In addition, in the present embodiment, two adjacent chips 12a, 12b have a first ground via 126a and a second ground via 126b, respectively, and the first ground via 126a and the second ground via 126b are disposed opposite to each other and may be stacked up and down or end-contacted.
In addition, after the ground via 126 is formed, the packaging method provided by the present application may further include: providing a first protective film (for example, polyimide PI film or the like) on the ground via 126; forming metal bumps 121 on all the pads on the functional surface 120; and removing the first protective film. All of the pads include the first ground pad 124 and other pads on the functional surface 120.
S203: the cut is made along the scribe line 14 of the wafer 20 with the other end of the ground path 126 flush with the side 128 of the chip 12.
Specifically, as shown in fig. 4c and 2a, in the present embodiment, cutting may be performed with a cutting knife or a laser or the like.
In this embodiment, the first electromagnetic shielding layer 16 is made of a metal, such as at least one of aluminum, copper, chromium, gold, silver, nickel, and solder. The first electromagnetic shield layer 16 is electrically connected to the surface of the ground via 126 exposed from the side surface 128 of the chip 12, thereby electrically connecting the first electromagnetic shield layer 16 to the first ground pad 124. Of course, in other embodiments, the first electromagnetic shielding layer 16 may also extend to the functional surface 120 of the chip 12 to be electrically connected to the first ground pad 124.
In an application scenario, the step S101 specifically includes: providing a fixing jig 30, wherein the fixing jig 30 includes a through hole 300, and a second protective film 32 (e.g., a polyimide PI film or the like) is disposed at an edge of the through hole 300; placing the chip 12 on the fixing jig 30, wherein the metal bumps 121 of the chip 12 correspond to the through holes 300, and the ground vias 126 contact with the second protective film 32; the first electromagnetic shield layer 16 is sputter formed on the non-functional side 122 of the chip 12 and the side 128 of the chip 12. The metal bump 121 of the chip 12 corresponds to the through hole 300, that is, the orthographic projection of the metal bump 121 on the surface of the fixing jig 30 is located in the through hole 300, so that the metal bump 121 can be protected, and the probability of damage of the metal bump is reduced.
Of course, in other application scenarios, the implementation manner of the step S101 may also be other, for example, the second protective film 32 may be first disposed on the functional surface 120 of the chip 12, and the second protective film 32 covers the edge of the chip 12; then, the chip 12 is placed on the fixing jig 30; finally, the first electromagnetic shield layer 16 is formed by sputtering on the non-functional side 122 of the chip 12 and the side 128 of the chip 12.
S102: the at least one chip 12 is flip-chip mounted on the first surface 100 of the substrate 10, and the functional surface 120 faces the first surface 100, wherein the first surface 100 is provided with the exposed second ground pad 104, the substrate 10 is provided with the ground layer 106 inside, and the second ground pad 104 is electrically connected to the ground layer 106.
Specifically, as shown in fig. 2b, the substrate 10 may be provided directly from an upstream manufacturer, and the substrate 10 includes a first surface 100 and a second surface 102 disposed opposite to each other; the ground layer 106 may be made of metal, and the number of the ground layer 106 may be one or more layers, and two ends of the ground layer 106 may be flush with the side surface 108 of the substrate 10, that is, two ends of the ground layer 106 are exposed out of the substrate 10. In this embodiment, in order to electrically connect the second ground pad 104 and the ground layer 106, a via 101 may be disposed between the second ground pad 104 and the ground layer 106, the via 101 may be filled with a conductive material, and the conductive material, the second ground pad 104, and the ground layer 106 are electrically connected.
S103: a conductive connection 18 is formed at the first surface 100, one end of the conductive connection 18 being electrically connected to the first electromagnetic shield layer 16, and the other end of the conductive connection 18 being electrically connected to the second ground pad 104.
Specifically, as shown in fig. 2c, in order to electrically insulate all the pads on the chip 12 or the metal bumps 121 formed on all the pads from the conductive connecting members 18, so as to reduce the probability of short circuit of the chip 12, before the step S103, the packaging method provided by the present application further includes: an insulating layer 11 is formed between the functional surface 120 of the chip 12 and the first surface 100, and the side surface 110 of the insulating layer 11 is an inclined surface. The insulating layer 11 may be an insulating paste (e.g., epoxy resin, etc.), which overflows to the periphery of the chip 12 during the filling process and forms an inclined surface with a certain slope. When the conductive connecting member 18 is made of conductive adhesive, the step S103 includes: and forming conductive adhesive on the inclined surface by adopting a glue dispensing mode and the like. The application requires that the conductive adhesive has a certain viscosity, that is, the conductive adhesive can be attached to the surface of the insulating layer 11, so as to reduce the probability that the conductive adhesive is in poor contact with the first electromagnetic shielding layer 16 or the conductive adhesive contaminates the first surface 100 of the substrate 10.
In the above embodiment, the insulating layer 11 is formed after the chip 12 is flip-mounted on the first surface 100, and in other embodiments, the insulating layer 11 may be formed in advance, that is, before the chip 12 is flip-mounted on the first surface 100; for example, as shown in fig. 5, before the step S203 of cutting the scribe grooves 14 of the wafer 20, the packaging method provided by the present application further includes: forming an insulating layer 11a on the functional surface 120 of the chip 12, wherein the insulating layer 11a is flush with the metal bump 121, and the surface of the metal bump 121 flush with the insulating layer 11a is exposed from the insulating layer 11 a; at this time, the insulating layer 11a may be formed by pressing the wafer 20 with an insulating paste, that is, the insulating paste is pressed to be at the same horizontal line with the metal bumps 121, and the insulating paste adhered to the metal bumps 121 may be removed by grinding, scraping, or the like. After the subsequent dicing of the scribe grooves 14 of the wafer 20, the side surface 110a of the insulating layer 11a is perpendicular to the functional surface 120, and the side surface 1260 of the ground via 126 is exposed from the insulating layer 11 a.
In order to enhance the protection of the whole system-in-package device, the packaging method provided by the application further comprises: s104: a molding compound layer 13 is formed on the first surface 100 of the substrate 10, and the molding compound layer 13 covers at least one chip 12. Specifically, as shown in fig. 2d, the material of the molding layer 13 may be epoxy resin or the like; the plastic package layer 13 not only can play a role in protection, but also can increase the heat dissipation of the system-in-package device. The molding layer 13 fills the gap between the adjacent chips 12 and covers the outer surface 160 of the first electromagnetic shielding layer 16.
In order to achieve electromagnetic shielding between the system-in-package device and the external environment, the method provided by the present application may further include: s105: the second electromagnetic shielding layer 15 is formed on the outer surface 130 of the molding layer 13 and the side surface 108 of the substrate 10. Specifically, as shown in fig. 2e, the outer surface 130 of the molding layer 13 refers to the surface not covered by the substrate 10. The second electromagnetic shielding layer 15 may be made of metal, for example, at least one of aluminum, copper, chromium, gold, silver, nickel, and solder. A method of forming the second electromagnetic shield layer 15 may be a spraying method, an electroplating method, a sputtering method, or the like. In the present embodiment, both ends of the ground layer 106 located inside the substrate 10 are exposed from the side surface 108 of the substrate 10, so that the second electromagnetic shielding layer 15 is electrically connected to the ground layer 106, thereby achieving electromagnetic shielding of the entire system-in-package device from the external environment.
The system-in-package device provided by the present application is further described below from a structural point of view. Referring to fig. 6, fig. 6 is a schematic structural diagram of an embodiment of a system-in-package device according to the present application, the system-in-package device provided in the present application includes:
at least one chip 12 includes a functional surface 120 and a non-functional surface 122, which are disposed opposite to each other, and a first ground pad 124 is disposed on the functional surface 120. In this embodiment, in addition to the first ground pad 124, other pads and metal bumps 121 are disposed on the functional surface 120, one pad corresponds to one metal bump 121, the metal bumps 121 extend from the surface of the pad, and the chip 12 is electrically connected to the substrate 10 through the metal bumps 121. In addition, the functional surface 120 of the chip 12 is further provided with a ground via 126, one end of the ground via 126 is electrically connected to the first ground pad 124, the other end surface of the ground via 126 is flush with the side surface 128 of the chip 12, and the material of the ground via 126 may be metal.
A substrate 10 for carrying at least one component, e.g., at least one chip 12, wherein the chip 12 is flip-chip mounted to the substrate 10. The substrate 10 includes a first surface 100 and a second surface 102 opposite to each other, the functional surface 12 of the chip 12 faces the first surface 100, the first surface 100 is provided with a second exposed ground pad 104, the substrate 10 is internally provided with a ground layer 106, and the second ground pad 104 is electrically connected to the ground layer 106. In this embodiment, a via 101 is disposed between the second ground pad 104 and the ground layer 106 of the substrate 10, and the via 101 is filled with a conductive material through which the second ground pad 104 is electrically connected to the ground layer 106.
A first electromagnetic shield layer 16 covering the non-functional surface 122 of the chip 12 and the side surface 128 adjacent to the non-functional surface 122, wherein the first electromagnetic shield layer 16 is electrically connected to the first ground pad 124; in this embodiment, the material of the first electromagnetic shielding layer 16 may be a metal, such as at least one of aluminum, copper, chromium, gold, silver, nickel, and solder. The first electromagnetic shield layer 16 covers the other end surface of the ground via 126 so that the first electromagnetic shield layer 16 is electrically connected to the first ground pad 124 through the ground via 126.
And a conductive connector 18 located on the first surface 100 of the substrate 10, wherein one end of the conductive connector 18 is electrically connected to the first electromagnetic shielding layer 16, and the other end of the conductive connector 18 is electrically connected to the second ground pad 104. Since the second ground pad 104 is electrically connected to the ground layer 106 inside the substrate 10, the first electromagnetic shielding layer 16, the conductive connector 18 and the ground layer 106 can form a closed loop through the conductive connector 18, thereby achieving electromagnetic shielding among the plurality of chips 12 in the system-in-package device. Compared with the prior art, laser grooving and conductive adhesive filling are not needed, the process is simple and easy to achieve, and the shielding effect is good.
In one application scenario, in order to reduce the probability of the conductive connection element 18 being shorted to all pads of the chip 12 or the metal bumps 121 extending from the pad surface, the system-in-package device provided in the present application further includes: the insulating layer 11 fills the region between the functional surface 120 of the chip 12 and the first surface 100 of the substrate 10, the side surface 110 of the insulating layer 11 is an inclined surface, and the conductive connecting member 18 extends along the inclined surface.
In another application scenario, please refer to fig. 7, where fig. 7 is a schematic structural diagram of another embodiment of a system-in-package device according to the present application. The side 110a of the insulating layer 11a may also be perpendicular to the first surface 100. In fig. 7, the first electromagnetic shielding layer 16 does not contact the side surface 110a of the insulating layer 11a, but the first electromagnetic shielding layer 16 may extend to contact the side surface 110a of the insulating layer 11 a.
In another application scenario, in order to increase protection of the system-in-package device, please continue to refer to fig. 6, the system-in-package device provided in the present application further includes: a molding layer 13, wherein the molding layer 13 covers an outer surface (not labeled in fig. 6) of the first electromagnetic shielding layer 16 and the first surface 100 of the substrate 10, and the region between the adjacent chips 12 is filled with the molding layer 13; the material of the molding layer 13 may be epoxy resin.
In another application scenario, in order to achieve electromagnetic shielding between the system in package device and an external environment, the system in package device provided by the present application further includes: a second electromagnetic shielding layer 15, wherein the second electromagnetic shielding layer 15 covers the outer surface 130 of the plastic packaging layer 13 and the side surface 108 of the substrate 10; both ends of the ground layer 106 are exposed from the side surface 108 of the substrate 10, and the second electromagnetic shield layer 15 is electrically connected to the ground layer 106.
Of course, in other embodiments, the chip 12c in the system-in-package device may also be disposed on the substrate 10 in a face-up manner; as shown in fig. 6, at this time, the chip 12c needs to be plastic-packaged first, and then a third electromagnetic shielding layer 16a is formed on the first plastic-packaging layer 13a of the chip 12 c; and then carrying out overall plastic package on the system-in-package device. If the chip 12c does not need to be electromagnetically shielded, the third electromagnetic shielding layer 16a does not need to be provided, and at this time, the chip 12c does not need to be plastically packaged in advance, and the whole plastic packaging can be performed at a later stage.
In addition, in this embodiment, other components, such as a resistor, a capacitor, etc., may be disposed on the substrate 10 in the system in package device.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (8)
1. A system-in-package method, the method comprising:
forming a first electromagnetic shielding layer on a non-functional surface and a side surface adjacent to the non-functional surface of a chip, wherein the first electromagnetic shielding layer is electrically connected with a first grounding pad on the functional surface of the chip;
inversely installing at least one chip on a first surface of a substrate, wherein the functional surface faces the first surface, the first surface is provided with an exposed second grounding pad, a grounding layer is arranged in the substrate, and the second grounding pad is electrically connected with the grounding layer;
forming a conductive connecting piece on the first surface, wherein one end of the conductive connecting piece is electrically connected with the first electromagnetic shielding layer, and the other end of the conductive connecting piece is electrically connected with the second grounding pad;
before the first electromagnetic shielding layer is formed on the non-functional surface and the side surface adjacent to the non-functional surface of the chip, the packaging method further comprises the following steps:
providing a wafer, wherein the wafer is provided with a plurality of chips arranged in a matrix, and scribing grooves are formed in the positions of the wafer among the chips;
forming a ground via on the functional surface of the chip, one end of the ground via being electrically connected to the first ground pad, and the other end of the ground via extending to the scribe line adjacent to the first ground pad;
and cutting along the scribing grooves of the wafer, wherein the other end of the grounding path is flush with the side face of the chip.
2. The packaging method as claimed in claim 1, wherein before the dicing the scribe line of the wafer, the packaging method further comprises:
arranging a first protection film on the grounding path;
forming metal bumps on all the pads on the functional surface;
and removing the first protective film.
3. The method of claim 2, wherein forming a first electromagnetic shielding layer on the non-functional side and a side adjacent to the non-functional side of the chip comprises:
providing a fixing jig, wherein the fixing jig comprises a through hole, and a second protective film is arranged at the edge of the through hole;
placing the chip on the fixing jig, wherein the metal salient points of the chip correspond to the through holes, and the grounding path is in contact with the second protective film;
and forming the first electromagnetic shielding layer on the non-functional surface of the chip and the side surface of the chip by sputtering.
4. The packaging method according to claim 2,
before the dicing along the scribe line of the wafer, the packaging method further includes: forming an insulating layer on the functional surface of the chip, wherein the insulating layer is flush with the metal salient points, and the metal salient points are exposed out of the insulating layer; alternatively, the first and second electrodes may be,
before the forming of the conductive connection member on the first surface, the packaging method further comprises: and forming an insulating layer between the functional surface and the first surface of the chip, wherein the side surface of the insulating layer is an inclined surface.
5. The method of packaging of claim 1, further comprising:
forming a plastic packaging layer on the first surface of the substrate, wherein the plastic packaging layer covers at least one chip;
and forming second electromagnetic shielding layers on the surface of the plastic packaging layer and the side surface of the substrate, wherein two ends of the grounding layer are exposed out of the side surface of the substrate, and the second electromagnetic shielding layers are electrically connected with the grounding layer.
6. A system in a package device, the packaged device comprising:
the chip comprises a functional surface and a non-functional surface which are arranged oppositely, and a first grounding bonding pad is arranged on the functional surface;
the substrate is used for bearing the chip and comprises a first surface and a second surface which are arranged in an opposite way, the first surface is provided with an exposed second grounding pad, a grounding layer is arranged in the substrate, and the second grounding pad is electrically connected with the grounding layer; wherein the functional face faces the first surface;
the first electromagnetic shielding layer covers the non-functional surface and the side surface adjacent to the non-functional surface of the chip, and is electrically connected with the first grounding bonding pad;
the conductive connecting piece is positioned on the first surface of the substrate, one end of the conductive connecting piece is electrically connected with the first electromagnetic shielding layer, and the other end of the conductive connecting piece is electrically connected with the second grounding pad;
the functional surface of the chip is further provided with a grounding path, one end of the grounding path is electrically connected with the first grounding pad, the surface of the other end of the grounding path is flush with the side surface of the chip, and the first electromagnetic shielding layer covers the surface of the other end of the grounding path.
7. The packaged device of claim 6, further comprising:
the insulating layer fills the area between the functional surface of the chip and the first surface of the substrate, the side surface of the insulating layer is an inclined surface, and the conductive connecting piece extends along the inclined surface.
8. The packaged device of claim 6,
the functional surface of the chip is also provided with a metal bump, and the metal bump extends from the surface of the first grounding bonding pad; and/or the presence of a gas in the gas,
the packaged device further includes: a plastic sealing layer covering an outer surface of the first electromagnetic shielding layer and the first surface of the substrate; the second electromagnetic shielding layer covers the outer surface of the plastic packaging layer and the side surface of the substrate; wherein both ends of the ground layer are exposed from the side surface of the substrate, and the second electromagnetic shielding layer is electrically connected with the ground layer; and/or the presence of a gas in the gas,
a through hole is formed between the second grounding pad of the substrate and the grounding layer, and a conductive material is filled in the through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910189755.3A CN110098130B (en) | 2019-03-13 | 2019-03-13 | System-level packaging method and packaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910189755.3A CN110098130B (en) | 2019-03-13 | 2019-03-13 | System-level packaging method and packaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110098130A CN110098130A (en) | 2019-08-06 |
| CN110098130B true CN110098130B (en) | 2021-11-23 |
Family
ID=67443394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910189755.3A Active CN110098130B (en) | 2019-03-13 | 2019-03-13 | System-level packaging method and packaging device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110098130B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11600687B2 (en) | 2020-03-13 | 2023-03-07 | Samsung Display Co., Ltd. | Electronic device package and display device including the same |
| CN115868022A (en) * | 2020-07-31 | 2023-03-28 | 华为技术有限公司 | Packaging structure, manufacturing method thereof and device structure |
| CN112466849B (en) * | 2020-11-25 | 2022-05-17 | 杭州星阖科技有限公司 | Wafer level self-shielding packaging structure and manufacturing method thereof |
| CN112466850B (en) * | 2020-11-25 | 2022-07-01 | 杭州星阖科技有限公司 | Wafer level self-shielding packaging structure and manufacturing method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1293485A (en) * | 1999-10-15 | 2001-05-02 | 汤姆森无线电报总公司 | Electron element packaging method |
| CN102763205A (en) * | 2010-02-19 | 2012-10-31 | 松下电器产业株式会社 | High frequency module manufacturing method |
| CN103915408A (en) * | 2013-01-03 | 2014-07-09 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN105826211A (en) * | 2016-05-11 | 2016-08-03 | 苏州日月新半导体有限公司 | Semiconductor product, and tool and method for manufacturing the semiconductor product |
| CN108288614A (en) * | 2017-01-10 | 2018-07-17 | 株式会社迪思科 | The manufacturing method of semiconductor device chip and semiconductor device chip |
| CN108417529A (en) * | 2018-02-09 | 2018-08-17 | 武汉新芯集成电路制造有限公司 | A kind of lithographic method of contact hole |
| CN108735717A (en) * | 2017-04-13 | 2018-11-02 | 艾马克科技公司 | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9953929B2 (en) * | 2016-03-18 | 2018-04-24 | Intel Corporation | Systems and methods for electromagnetic interference shielding |
| US10229887B2 (en) * | 2016-03-31 | 2019-03-12 | Intel Corporation | Systems and methods for electromagnetic interference shielding |
-
2019
- 2019-03-13 CN CN201910189755.3A patent/CN110098130B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1293485A (en) * | 1999-10-15 | 2001-05-02 | 汤姆森无线电报总公司 | Electron element packaging method |
| CN102763205A (en) * | 2010-02-19 | 2012-10-31 | 松下电器产业株式会社 | High frequency module manufacturing method |
| CN103915408A (en) * | 2013-01-03 | 2014-07-09 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN105826211A (en) * | 2016-05-11 | 2016-08-03 | 苏州日月新半导体有限公司 | Semiconductor product, and tool and method for manufacturing the semiconductor product |
| CN108288614A (en) * | 2017-01-10 | 2018-07-17 | 株式会社迪思科 | The manufacturing method of semiconductor device chip and semiconductor device chip |
| CN108735717A (en) * | 2017-04-13 | 2018-11-02 | 艾马克科技公司 | Semiconductor device |
| CN108417529A (en) * | 2018-02-09 | 2018-08-17 | 武汉新芯集成电路制造有限公司 | A kind of lithographic method of contact hole |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110098130A (en) | 2019-08-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110098130B (en) | System-level packaging method and packaging device | |
| KR100511728B1 (en) | Compact semiconductor device capable of mounting a plurality of semiconductor chips with high density and method of manufacturing the same | |
| US8461689B2 (en) | Packaging structure having embedded semiconductor element | |
| US7888179B2 (en) | Semiconductor device including a semiconductor chip which is mounted spaning a plurality of wiring boards and manufacturing method thereof | |
| KR20180027679A (en) | Semiconductor package and method of fabricating the same | |
| US9337172B2 (en) | Semiconductor device | |
| CN104716103A (en) | Underfill Pattern with Gap | |
| US11610850B2 (en) | Electronic package and fabrication method thereof | |
| JP4093018B2 (en) | Semiconductor device and manufacturing method thereof | |
| US10811378B2 (en) | Electronic package and manufacturing method thereof | |
| CN113380768A (en) | Chip packaging structure and manufacturing method thereof | |
| US11721654B2 (en) | Ultra-thin multichip power devices | |
| US7649250B2 (en) | Semiconductor package | |
| CN111554620A (en) | Chip packaging method | |
| US20220344300A1 (en) | Electronic device and manufacturing method thereof | |
| US20220344175A1 (en) | Flip chip package unit and associated packaging method | |
| US11418002B2 (en) | Electronic package and method for fabricating the same | |
| CN109727933B (en) | Semiconductor packaging method and semiconductor packaging device | |
| CN111554629A (en) | Chip packaging method | |
| CN111554618A (en) | Chip packaging method | |
| CN113594105A (en) | Electronic package and manufacturing method thereof | |
| JP2006196734A (en) | Semiconductor device and its manufacturing method | |
| US20220344231A1 (en) | Flip chip package unit and associated packaging method | |
| KR100369394B1 (en) | substrate for semiconductor package and manufacturing method of semiconductor package using it | |
| CN116072554A (en) | Fan-out packaging method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220418 Address after: 226000 building 11, No. 226, Tongjing Avenue, Nantong City, Jiangsu Province Patentee after: Tongfutongke (Nantong) Microelectronics Co.,Ltd. Address before: No.288, Chongchuan Road, Nantong City, Jiangsu Province, 226000 Patentee before: TONGFU MICROELECTRONICS Co.,Ltd. |