CN108417529A - A kind of lithographic method of contact hole - Google Patents
A kind of lithographic method of contact hole Download PDFInfo
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- CN108417529A CN108417529A CN201810135245.3A CN201810135245A CN108417529A CN 108417529 A CN108417529 A CN 108417529A CN 201810135245 A CN201810135245 A CN 201810135245A CN 108417529 A CN108417529 A CN 108417529A
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- dielectric layer
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- lithographic method
- contact hole
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 56
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 230000000149 penetrating effect Effects 0.000 claims abstract description 9
- 239000002131 composite material Substances 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 81
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 5
- 239000011368 organic material Substances 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 239000003518 caustics Substances 0.000 abstract description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention relates to technical field of semiconductors more particularly to the lithographic method and composite wafer of a kind of contact hole, composite wafer includes the metal layer, etching barrier layer and dielectric layer stacked gradually from the bottom to top；It is characterized in that, lithographic method includes：Step S1 prepares the photoresist layer with etching pattern in the upper surface of dielectric layer；Step S2, the dielectric layer exposed using etching technics etching etching pattern, a preset thickness is thinned by the dielectric layer exposed；Step S3 widens etching pattern to expose the upper surface of more multiple dielectric layers；Step S4 repeats step S2 and step S3 several times, until penetrating dielectric layer and forming hierarchic structure in dielectric layer；Step S5 penetrates etching barrier layer by mask etching of dielectric layer, forms the contact hole with hierarchic structure of connection metal layer after penetrating dielectric layer；The hierarchic structure that abducent formation is from top to bottom presented can be formed, to avoid the residual of corrosive substance, ensure that the performance of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of lithographic methods of contact hole.
Background technology
In existing semiconductor technology, such as in the flash memory preparation process of 32nm, preparing the method that contact hole uses is,
Crystal column surface forms photoresist, by forming the photoresist with etching pattern after exposure imaging, then using primary etching in crystalline substance
Circular surfaces form contact hole.
But the contact hole formed in this way can have serious defect.Due to using the technique once etched, holding very much
The etching reactant and product used in each step is easily remained in the corner of each structure, and the generation of these substances is often
With certain corrosivity, such as with alkalescent, the surface of metal layer can be formed corrode in this way, to influence semiconductor device
The performance of part.
Invention content
In view of the above-mentioned problems, the present invention proposes a kind of lithographic method of contact hole, it is applied to a composite wafer, it is described multiple
Synthetic circle includes metal layer, etching barrier layer and the dielectric layer stacked gradually from the bottom to top；Wherein, the lithographic method includes：
Step S1 prepares the photoresist layer with etching pattern in the upper surface of the dielectric layer；
Step S2 etches the dielectric layer that the etching pattern exposes using an etching technics, will expose
A preset thickness is thinned in the dielectric layer；
Step S3 widens the etching pattern to expose the upper surface of more dielectric layers；
Step S4, repeating said steps S2 and the step S3 several times, until penetrating the dielectric layer and in being given an account of
Hierarchic structure is formed in electric layer；
Step S5 penetrates the etching barrier layer, shape after penetrating the dielectric layer by mask etching of the dielectric layer
At the contact hole with the hierarchic structure for connecting the metal layer.
Above-mentioned lithographic method, wherein the photoresist layer is organic material.
Above-mentioned lithographic method, wherein specific using the photoresist layer that burns under oxygen atmosphere in the step S3
Method widens the etching pattern
Above-mentioned lithographic method, wherein the step S3 is completed in the cavity of an etching machine bench.
Above-mentioned lithographic method, wherein during burning the photoresist layer, the etching machine bench is into the cavity
Product while being constantly passed through oxygen also after extracting burning in the cavity.
Above-mentioned lithographic method, wherein the preset thickness phase of the dielectric layer is thinned in each repeating said steps S2
Together.
Above-mentioned lithographic method, wherein the preset thickness of the dielectric layer is thinned not in each repeating said steps S2
It is identical.
Above-mentioned lithographic method, wherein further include between the step S1 and the step S2：
Intermediate steps there is the side wall of the etching pattern to pre-process the photoresist layer, in the photoresist layer
Side wall on form a protective layer.
Advantageous effect：A kind of lithographic method of contact hole proposed by the present invention can be formed and from top to bottom be presented to extending out
The hierarchic structure of the formation of exhibition ensure that the performance of semiconductor devices to avoid the residual of corrosive substance.
Description of the drawings
Fig. 1 is the step flow chart of the lithographic method of contact hole in one embodiment of the invention；
Fig. 2~5 are the structure for the contact hole that each step of the lithographic method of contact hole in one embodiment of the invention is formed
Schematic diagram.
Specific implementation mode
Invention is further explained with reference to the accompanying drawings and examples.
Embodiment one
In a preferred embodiment, as shown in Figure 1, it is proposed that it is multiple to be applied to one for a kind of lithographic method of contact hole
Synthetic circle 10, composite wafer 10 include metal layer 11, etching barrier layer 12 and the dielectric layer 13 stacked gradually from the bottom to top；Each step
Suddenly being formed by structure can be as shown in Figure 2-5；Wherein, which may include：
Step S1 prepares the photoresist layer 1 with etching pattern in the upper surface of dielectric layer 13；
Step S2, the dielectric layer 13 exposed using etching technics etching etching pattern, the dielectric layer that will be exposed
A preset thickness is thinned；
Step S3 widens etching pattern to expose the upper surface of more multiple dielectric layers 13；
Step S4 repeats step S2 and step S3 several times, until penetrating dielectric layer 13 and forming rank in dielectric layer 13
Terraced structure；
Step S5 is that mask etching penetrates etching barrier layer 12 with dielectric layer 13, forms connection after penetrating dielectric layer 13
The contact hole with hierarchic structure of metal layer 11.
In above-mentioned technical proposal, in step S3, since etching pattern is widened, this can make dielectric layer 13 be capped originally
Part also expose out, if performing etching at this time, since etch rate is identical, but the part that dielectric layer 13 etches for the first time
It is thinned, therefore second when etching, portion of the thinned thickness in the part being newly exposed still with first time etching
Dividing thinned overall thickness, there are gaps, to form stair-stepping structure.
In a preferred embodiment, photoresist layer can be organic material.
In above-described embodiment, it is preferable that in step S3, the specific method using the photoresist layer that burns under oxygen atmosphere is widened
Etching pattern.
In above-described embodiment, it is preferable that step S3 is completed in the cavity of an etching machine bench；
In above-described embodiment, it is preferable that during burning photoresist layer 1, etching machine bench can be not open close into cavity
Product while entering oxygen also after extracting burning in cavity, to avoid the product after burning from generating shadow to wafer
It rings, while reaching the balance of air pressure in cavity.
In above-mentioned technical proposal, burning is formed by temperature and may remain in 60 DEG C or so, to avoid excessively high temperature pair
The performance of wafer has an impact.
In a preferred embodiment, the preset thickness that dielectric layer 13 is thinned in each repetition step S2 is identical.
In a preferred embodiment, the preset thickness that dielectric layer 13 is thinned in each repetition step S2 differs.
In a preferred embodiment, further include between step S1 and step S2：
Intermediate steps there is the side wall of etching pattern to pre-process photoresist layer 1, to be formed on the side wall of photoresist layer
One protective layer.
In above-mentioned technical proposal, the upper surface of photoresist layer 1 can also be covered by forming protective layer；Form the gas that protective layer uses
Body can be tetrafluoride hydrogen or hydrogen or argon gas etc..
In conclusion a kind of lithographic method of contact hole proposed by the present invention, composite wafer includes heap successively from the bottom to top
Folded metal layer, etching barrier layer and dielectric layer；It is characterized in that, lithographic method includes：Step S1, in the upper surface of dielectric layer
Prepare the photoresist layer with etching pattern；Step S2, the dielectric layer exposed using etching technics etching etching pattern, will
A preset thickness is thinned in the dielectric layer exposed；Step S3 widens etching pattern to expose the upper surface of more multiple dielectric layers；Step
Rapid S4 repeats step S2 and step S3 several times, until penetrating dielectric layer and forming hierarchic structure in dielectric layer；Step S5,
After penetrating dielectric layer, etching barrier layer is penetrated by mask etching of dielectric layer, form connection metal layer has hierarchic structure
Contact hole；The hierarchic structure that abducent formation is from top to bottom presented can be formed, to avoid the residual of corrosive substance
It stays, ensure that the performance of semiconductor devices.
By description and accompanying drawings, the exemplary embodiments of the specific structure of specific implementation mode are given, based on present invention essence
God can also make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly will be evident.
Therefore, appended claims should regard the whole variations and modifications for covering the true intention and range of the present invention as.It is weighing
The range and content of any and all equivalences within the scope of sharp claim, are all considered as still belonging to the intent and scope of the invention.
Claims (8)
1. a kind of lithographic method of contact hole, is applied to a composite wafer, the composite wafer includes stacking gradually from the bottom to top
Metal layer, etching barrier layer and dielectric layer；It is characterized in that, the lithographic method includes：
Step S1 prepares the photoresist layer with etching pattern in the upper surface of the dielectric layer；
Step S2 etches the dielectric layer that the etching pattern exposes using an etching technics, will expose described in
A preset thickness is thinned in dielectric layer；
Step S3 widens the etching pattern to expose the upper surface of more dielectric layers；
Step S4, repeating said steps S2 and the step S3 several times, until penetrate the dielectric layer and in the dielectric layer
Middle formation hierarchic structure；
Step S5 penetrates the etching barrier layer, the company of being formed after penetrating the dielectric layer by mask etching of the dielectric layer
Connect the contact hole with the hierarchic structure of the metal layer.
2. lithographic method according to claim 1, which is characterized in that the photoresist layer is organic material.
3. lithographic method according to claim 2, which is characterized in that specific using in oxygen atmosphere in the step S3
The method of the lower burning photoresist layer widens the etching pattern.
4. lithographic method according to claim 3, which is characterized in that the step S3 is complete in the cavity of an etching machine bench
At.
5. lithographic method according to claim 4, which is characterized in that during burning the photoresist layer, the quarter
Product while erosion board is constantly passed through oxygen into the cavity also after extracting burning in the cavity.
6. lithographic method according to claim 1, which is characterized in that the dielectric layer is thinned in each repeating said steps S2
The preset thickness it is identical.
7. lithographic method according to claim 1, which is characterized in that the dielectric layer is thinned in each repeating said steps S2
The preset thickness differ.
8. lithographic method according to claim 1, which is characterized in that also wrapped between the step S1 and the step S2
It includes：
Intermediate steps there is the side wall of the etching pattern to pre-process the photoresist layer, in the side of the photoresist layer
A protective layer is formed on wall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810135245.3A CN108417529B (en) | 2018-02-09 | 2018-02-09 | Etching method of contact hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810135245.3A CN108417529B (en) | 2018-02-09 | 2018-02-09 | Etching method of contact hole |
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| Publication Number | Publication Date |
|---|---|
| CN108417529A true CN108417529A (en) | 2018-08-17 |
| CN108417529B CN108417529B (en) | 2021-08-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810135245.3A Active CN108417529B (en) | 2018-02-09 | 2018-02-09 | Etching method of contact hole |
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| Country | Link |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109817531A (en) * | 2019-02-02 | 2019-05-28 | 合肥鑫晟光电科技有限公司 | A kind of array substrate and preparation method thereof |
| CN110098130A (en) * | 2019-03-13 | 2019-08-06 | 通富微电子股份有限公司 | A kind of system-in-a-package method and packaging |
| CN111446164A (en) * | 2020-03-31 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Manufacturing method of edge-gentle-slope/step-shaped wafer |
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| CN1438544A (en) * | 2003-02-28 | 2003-08-27 | 北京大学 | Method for deep etching multi-layer high depth-width-ratio silicon stairs |
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Patent Citations (6)
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| CN1438544A (en) * | 2003-02-28 | 2003-08-27 | 北京大学 | Method for deep etching multi-layer high depth-width-ratio silicon stairs |
| CN104445051A (en) * | 2014-12-02 | 2015-03-25 | 中国科学院半导体研究所 | Method for preparing multi-stage steps on substrate |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109817531A (en) * | 2019-02-02 | 2019-05-28 | 合肥鑫晟光电科技有限公司 | A kind of array substrate and preparation method thereof |
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| CN110098130A (en) * | 2019-03-13 | 2019-08-06 | 通富微电子股份有限公司 | A kind of system-in-a-package method and packaging |
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| CN111446164A (en) * | 2020-03-31 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Manufacturing method of edge-gentle-slope/step-shaped wafer |
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| CN108417529B (en) | 2021-08-27 |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |