CN107464775A - A kind of forming method of semiconductor structure - Google Patents
A kind of forming method of semiconductor structure Download PDFInfo
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- CN107464775A CN107464775A CN201610392635.XA CN201610392635A CN107464775A CN 107464775 A CN107464775 A CN 107464775A CN 201610392635 A CN201610392635 A CN 201610392635A CN 107464775 A CN107464775 A CN 107464775A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
The present invention provides a kind of forming method of semiconductor structure, and methods described includes：Semiconductor substrate is provided, low k dielectric and hard mask layer are sequentially formed thereon；The first siliceous photoresist layer with channel patterns is formed on hard mask layer；The first siliceous photoresist layer of curing process；Planarization layer is formed on a semiconductor substrate, and the first siliceous photoresist layer is covered while filling channel patterns；The second photoresist layer with through-hole pattern is formed on planarization layer；Using the second photoresist layer as mask, etching planarization layer, hard mask layer and low k dielectric, to form partial through holes in low k dielectric；Remove the second photoresist layer and planarization layer；Using the siliceous photoresist layer of first with channel patterns exposed as mask, hard mask layer and low k dielectric are etched, to form groove and through hole for filling metal interconnecting layer wherein.According to the present invention, implementing dual damascene photoetching process can reduce by an etching process, reduce process costs.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of forming method of semiconductor structure.
Background technology
In semiconductor integrated circuit, the signal transmission between semiconductor devices needs highdensity metal interconnecting wires, so
And the big resistance and parasitic capacitance that these metal interconnecting wires are brought have become limitation RC (resistance capacitance)
Delay continues the principal element reduced.
In traditional semiconductor technology, metallic aluminium is typically used for the metal interconnecting wires between semiconductor devices, with
The development of semiconductor technology, part is substituted metal aluminum interconnecting by metal copper interconnecting line, because compared with aluminium, copper
With less resistance value, RC retardation ratio can be reduced using metal copper interconnecting line；On the other hand, low dielectric constant insulating material by with
Make the main component of the dielectric layer between metal level, reduce the parasitic capacitance between metal level, in actual applications, Wo Menyi
As low dielectric constant insulating material is referred to as low k dielectric.The damascene structure formed using Damascus technics is extensive
In semiconductor structure applied to production line back end (back end of line, BEOL).Prolong to reduce the RC of integrated circuit
Late, the RC performances of integrated circuit are improved, with the development of semiconductor technology, dielectric layer material in damascene structure is from oxidation
Silicon replaces with a kind of low k (dielectric constant) dielectric material, and replaces with ultra low k dielectric materials from low k dielectric.
The preparation method of existing damascene structure has a variety of, common methods to have：1. all-pass hole precedence method (full via
first)；2. partial through holes precedence method (partial via first)；3. full groove-priority method (full trench first)；
4. part of trench precedence method (partial trench first)；5. self aligned approach (self-alignment method).Super
It is typically preferential using part of trench in order to reduce damage of the etching to low k dielectric during the use of low k dielectric
Method, it is the step of being implemented successively according to existing exemplary dual damascene process with reference to figure 1A- Fig. 1 E.The technological process uses
Photoetching-etching-photoetching-etching (integration etching (All-in-one Etch)), the Cost Problems brought except complex process
Outside, to the plyability of channel patterns and through-hole pattern (OVL, overlay) and preferably through hole smoothing control (leveling
Control) all it is technical challenge.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of forming method of semiconductor structure, including：Semiconductor is provided
Substrate, low k dielectric and hard mask layer are sequentially formed on the semiconductor substrate；
The first siliceous photoresist layer with channel patterns is formed on the hard mask layer；
First siliceous photoresist layer described in curing process；
Planarization layer is formed on the semiconductor substrate, and the planarization layer covers while filling the channel patterns
The first siliceous photoresist layer；
The second photoresist layer with through-hole pattern is formed on the planarization layer；
Using second photoresist layer as mask, the planarization layer, hard mask layer and the low k dielectric are etched, with
Partial through holes are formed in the low k dielectric；
Remove second photoresist layer and the planarization layer；
There is the first siliceous photoresist layer of channel patterns as mask described in exposing, the hard mask layer and institute are etched
Low k dielectric is stated, to form groove and through hole for filling metal interconnecting layer in the low k dielectric.
In one example, the material of the described first siliceous photoresist layer is photosensitive material, and passes through height after exposure
Temperature processing cross-linkable solidifying.
In one example, the material of the described first siliceous photoresist layer is at least made up of following material：With acid-sensitive half
Silicon-containing polymer, light acid producing agent, dicyandiamide solution and the crosslinking being dispersed or dissolved in the dicyandiamide solution of side base
Agent.
In one example, the silicon-containing polymer with acid-sensitive half side base includes：Silsesquioxane skeleton polymer,
Siliceous acrylate copolymer, silane polymer, organosilane polymer or poly- (p- hydroxybenzyl silsesquioxane) polymerization
Thing, wherein, the weight ratio of silicon is 5%-50%.
In one example, the silicon-containing polymer with acid-sensitive half side base includes acid-sensitive side chain, the acid-sensitive side chain
Including tert-butyl group class group, acetyl base class group, adamantane group or lactone group.
In one example, side chain functionalities are included in the described first siliceous photoresist layer, after implementing exposure, the side chain
The 20%-80% of functional group replaces with hydroxyl, acidic group, carbonyl or amido.
In one example, the crosslinking agent crosslinks reaction with the photoresist after exposure under the high temperature conditions, described
Crosslinking agent includes：Melamine, methylol melamine, glycoluril, hydroxy alkyl amine, epoxies, epoxy amino resin, bivinyl list
Body.
In one example, the dicyandiamide solution includes at least one solvent, and the solvent is selected from and is made up of following material
Group：Propylene glycol monomethyl ether, mesitylene, d-limonen, methyl isobutyl alcohol methanol, ethoxyl ethyl propionate, butyrolactone, breast
The mixture of acetoacetic ester and above-mentioned substance.
In one example, the curing process is implemented using post bake baking process, temperature is 150 DEG C -250 DEG C, processing
Time is -10 minutes 0.5 minute.
In one example, lithography step, the curing process institute of the first siliceous photoresist layer with channel patterns are formed
The lithography step of the second photoresist layer of the step of stating the first siliceous photoresist layer and formation with through-hole pattern is in same photoetching
Complete in equipment, or completed in different lithographic equipments.
In one example, the planarization layer is the organic material layer without element silicon formed by spin coating.
In one example, the organic material layer includes carbon, oxygen, hydrogen, nitrogen, and the weight ratio of the carbon is more than
50%.
In one example, the hard mask layer is single layer structure or multilayer lamination structure.
In one example, formed with underlying metal interconnection structure in the Semiconductor substrate.
In one example, the surface of the underlying metal interconnection structure is gone out by the bottom-exposed of the through hole.
In one example, in addition to：Metal is filled in the groove and through hole, Damascus metal is formed and mutually links
Structure, Damascus metal interconnection structure electrically connect with the underlying metal interconnection structure.
According to the present invention, implementing dual-damascene technics can reduce by an etching process, reduce process costs；Simultaneously in processing procedure
During can obtain more preferable channel patterns and through-hole pattern plyability (OVL, overlay) and preferably through hole smoothing control
Make (leveling control), the through hole in the form of obtaining and there is more preferably side wall.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A-Fig. 1 E are the device that is obtained respectively the step of implementation successively according to existing exemplary dual damascene process
The schematic cross sectional view of part；
Fig. 2A-Fig. 2 F are the device that is obtained respectively the step of implementation successively according to the method for exemplary embodiment of the present one
The schematic cross sectional view of part；
Fig. 3 is flow chart the step of implementation successively according to the method for exemplary embodiment of the present one.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention
Semiconductor structure forming method.Obviously, execution of the invention is not limited to the technical staff of semiconductor applications and is familiar with
Specific details.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can be with
With other embodiment.
It should be appreciated that when using term "comprising" and/or " comprising " in this manual, it is indicated described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combinations thereof.
Figure 1A-Fig. 1 E show a kind of dual damascene process process.
First, as shown in Figure 1A, there is provided Semiconductor substrate 100, using chemical vapor deposition method in Semiconductor substrate 100
On sequentially form etching stopping layer 101, low k dielectric 102, cushion 103 and hard mask layer 104.
On a semiconductor substrate 100 formed with front-end devices, to put it more simply, being not shown in legend.The front-end devices
Refer to the device formed before BEOL, the concrete structure of front-end devices is not defined herein.
Generally use ultra low k dielectric materials form low k dielectric 102, and the ultra low k dielectric materials refer to dielectric constant (k
Value) it is less than 2 dielectric material.
As an example, cushion 103 is made up of TEOS (tetraethyl orthosilicate) layer, the effect of TEOS layers is filled out in follow-up grinding
Mechanical stress is avoided to cause to damage to the porous structure of ultra low k dielectric materials during the copper-connection metal filled.
Hard mask layer 104 is by the metal hard mask layer 104a and oxide hard-mask layer 104b structures that stack gradually from bottom to top
Into the structure of this double-deck hard mask layer can ensure Dual graphing or the craft precision of multiple graphical.
Then, as shown in Figure 1B, the first opening 105 is formed in hard mask layer 104, to expose the cushion 103 of lower section.
First opening 105 is used as the patterns of the grooves in copper metal interconnection structure, and it can include multiple with different characteristic size
Figure.
Formed first opening 105 method be：First, the first bottom anti-reflective is sequentially formed on above-mentioned hard mask layer 104
Penetrate coating and the first photoresist layer with channel patterns；Then, using first photoresist layer as described in mask etching first
Bottom antireflective coating and the hard mask layer 104, to form first opening in the hard mask layer；Finally, remove
First photoresist layer and first bottom antireflective coating.
Then, as shown in Figure 1 C, the second opening 106, the second opening are formed in cushion 103 and low k dielectric 102
106 are used as the pattern of the through hole in copper metal interconnection structure, and it can also include multiple figures with different characteristic size, its
Described in the second open bottom member-retaining portion low k dielectric 102, that is, formed with through-hole pattern second opening bottom not
Expose etching stopping layer.
Formed second opening 106 method be：First, on the above-mentioned hard mask layer 104 with the first patterns of openings according to
It is secondary to form planarization layer (SOC, spin on coating), the second bottom antireflective coating of Silicon-rich and with through-hole pattern
The trilamellar membrane (tri-layer) of second photoresist layer, wherein planarization layer SOC have good fillibility, to be sufficient filling with
There is flat surface while first opening；Then, using second photoresist layer as Silicon-rich described in mask etching
Second bottom antireflective coating, planarization layer SOC, cushion and the low k dielectric 102, with the cushion and described
First opening is formed in low k dielectric；Finally, second photoresist layer, the second bottom anti-reflective of the Silicon-rich are removed
Penetrate coating and the planarization layer SOC.
Then, as shown in figure iD, it is mask with hard mask layer 104, is etched (All-in-one Etch) using integration
Method etch buffer layers 103 and low k dielectric 102 (i.e. synchronous etch buffer layers 103 and low k dielectric 102), to be situated between in low k
The groove and through hole 107 for forming copper metal interconnection structure (it is used to fill metal interconnecting layer) are formed in electric layer 102.
Then, as referring to figure 1E, the etching stopping layer that groove and through hole 107 expose is etched through using dry method etch technology
101, so that groove and through hole 107 connect with the front-end devices being formed in Semiconductor substrate 100.
Then, before filling metal interconnecting layer in groove and through hole 107, etching last handling process is performed, before removal
Residue caused by etching process and impurity are stated, is ensured two when subsequent deposition copper metal diffusion impervious layer and copper metal Seed Layer
The deposition quality of person.
In above-mentioned technical process, the residue of the photoresist of formation easily blocks through hole, in turn results in copper metal interconnection
The failure of structure, in addition to the Cost Problems that complex process is brought, plyability to channel patterns and through-hole pattern and more preferable
Ground through hole smoothing control is all technical challenge.
[exemplary embodiment one]
Reference picture 2A- Fig. 2 F, the step of according to an exemplary embodiment of the present one method of illustrated therein is is implemented successively
The schematic cross sectional view of the device obtained respectively.
First, as shown in Figure 2 A, there is provided Semiconductor substrate 200, using chemical vapor deposition method in Semiconductor substrate 200
On sequentially form etching stopping layer 201, low k dielectric 202, cushion 203 and hard mask layer 204.
On semiconductor substrate 200 formed with front-end devices, to put it more simply, being not shown in legend.The front-end devices
Refer to the device formed before BEOL, the concrete structure of front-end devices is not defined herein, the front-end devices bag
Include underlying metal interconnection structure.
Material preferred SiCN, SiC, SiN or BN of etching stopping layer 201, its as subsequent etch low k dielectric 202 with
While forming the etching stopping layer of upper copper metal interconnecting layer, the copper in lower floor's copper metal interconnection layer can be prevented to be diffused into
In the dielectric substance layer (such as low k dielectric 202) of layer.
The constituent material of low k dielectric 202 can be selected from the common various low k-value dielectric materials in this area, including but not
It is 2.2 to be limited to silicate compound (Hydrogen Silsesquioxane, referred to as HSQ), k values that k values are 2.5-2.9
Methane-siliconic acid salt compound (Methyl Silsesquioxane, abbreviation MSQ) and use chemical gaseous phase depositing process (CVD)
Porous silica of formation etc..Generally use ultra low k dielectric materials form low k dielectric 202, the ultra low k dielectric
Material refers to the dielectric material that dielectric constant (k values) is less than 2.7.
Cushion 203 is made up of TEOS layers, and it is to avoid machinery should in the copper-connection metal of follow-up grinding filling that it, which is acted on,
Power causes to damage to the porous structure of ultra low k dielectric materials.
Hard mask layer 204 is single layer structure or multilayer lamination structure.As an example, in the present embodiment, hard mask layer
204 metal hard mask layer 204a and oxide hard-mask layer 204b including stacking gradually from bottom to top, this hard mask of bilayer
The structure of layer can ensure Dual graphing or the craft precision of multiple graphical, ensure in shape needed for hard mask layer 204
Into the depth of whole groove figures and the uniformity of side wall profile, i.e., first the channel patterns with different characteristic size are formed
Covered in oxide hard-mask layer 204b, then using oxide hard-mask layer 204b as mask etch metal hard mask layer 204a in firmly
The groove figure formed needed for being made in film layer 204.Metal hard mask layer 204a constituent material include TiN, BN, AlN or
It is arbitrarily combined, preferably TiN；Oxide hard-mask layer 204b constituent material includes SiO2, SiON etc., and require that its is relative
There is preferable etching selectivity in metal hard mask layer 204a constituent material.
Next, sequentially formed on hard mask layer 204 first bottom antireflective coating 205 and with channel patterns the
One siliceous photoresist layer 206.Wherein, have corresponding with the channel patterns first in the described first siliceous photoresist layer 206
Opening.
The material of first siliceous photoresist layer 206 is photosensitive material, and after exposure by high temperature (such as 150 DEG C with
On) processing cross-linkable solidifying, it is at least made up of following material：Silicon-containing polymer (pendant with acid-sensitive half side base
Acid-labile moiety), light acid producing agent, dicyandiamide solution and the friendship being dispersed or dissolved in the dicyandiamide solution
Join agent.
The silicon-containing polymer with acid-sensitive half side base includes：Silsesquioxane skeleton polymer, siliceous acrylic acid
Polymer, silane polymer, organosilane polymer, poly- (p- hydroxybenzyl silsesquioxane) (PHBS) polymer etc., its
In, the weight ratio of silicon is 5%-50%.The acid-sensitive side chain that above-mentioned substance includes is easy to be broken in the sour environment of low temperature, described
Acid-sensitive side chain includes tert-butyl group class group, acetyl base class group, adamantane group or lactone group etc..
The crosslinking agent can crosslink reaction with the photoresist after exposure under the high temperature conditions, and it includes：Melamine
Amine, methylol melamine, glycoluril, hydroxy alkyl amine, epoxies, epoxy amino resin, bivinyl monomer etc..
The dicyandiamide solution includes at least one solvent, and the solvent is selected from the group being made up of following material：Propane diols first
Ether (PGME), mesitylene, d-limonen, methyl isobutyl alcohol methanol, ethoxyl ethyl propionate (EEP), butyrolactone
(GBL), the mixture of ethyl lactate and above-mentioned substance.
The first siliceous photoresist layer 206 with channel patterns is formed by spin coating, exposure, developing process, implements exposure
Afterwards, the 20%-80% of the side chain functionalities included in the first siliceous photoresist layer 206 replaces with hydroxyl, acidic group, carbonyl or amine
Base.
Next, the first siliceous photoresist layer 206 described in curing process, the curing process is at ultraviolet light (UV) irradiation
Reason or heat treatment.The solidification can be performed in photoetching tracking or scanning tools.
As an example, bakeing solidification described in (hard bake) process implementing using post bake, temperature is 150 DEG C -250 DEG C, place
The reason time is 0.5min-10min.
Exemplarily, by taking the first siliceous photoresist layer based on polysiloxanes as an example, the principle of above-mentioned solidification is described in detail
And process.The polysiloxanes has following structural formula：
Wherein x=0.1-0.9, y=0.1-0.9, x+y=1；R1：Acid-labile group with some T, including tert-butyl group class
Group, acetyl base class group, adamantane group, lactone group or pyrrolidones etc.；R2：Polar group, to improve in alkali
Dissolution velocity in property solution；R3：The C1-C6 of straight chain, side chain or cyclic structure univalent hydrocarbyl group, wherein a=0 or 1；
R4：The C1-C6 of straight chain, side chain or cyclic structure univalent hydrocarbyl group, wherein b=0 or 1.
The first siliceous photoresist layer based on the polysiloxanes with above-mentioned structural formula is in crosslinking agent, acid and temperature
Collective effect environment under, the R1 changes into the R1 ' of depickling protection, and the R1 ' between different molecular is bonded to each other, so as to form tool
Have the first siliceous photoresist layer of rock-steady structure, it is this have by the first cured modified siliceous photoresist layer it is very strong firm
Property, while larger etching selectivity can be provided for follow-up etch process.
Then, as shown in Figure 2 B, the layered product (tri- being made up of trilaminate material is formed on semiconductor substrate 200
Layer), with the first siliceous photoresist layer 206 of the covering with channel patterns.
As an example, the layered product includes the planarization layer (SOC, spin on coating) being laminated from bottom to top
207th, the second bottom antireflective coating 208 of Silicon-rich and the second photoresist layer 209 with through-hole pattern.Using spin coating proceeding shape
Into planarization layer 207 and the second bottom antireflective coating 208 of Silicon-rich, implement the techniques such as spin coating, exposure, development and form the second light
Photoresist layer 209.
Wherein, planarization layer 207 has good fillibility, flat to have while first opening is sufficient filling with
Smooth surface.The purpose of formation planarization layer 207 has flat carrier table when being so that and being subsequently formed the second photoresist layer 209
Face so that the second photoresist layer 209 of formation has higher thickness evenness.The material of planarization layer 207 is to pass through spin coating
The organic material without element silicon formed, the organic material include carbon, oxygen, hydrogen, nitrogen, wherein, the weight of carbon
Than more than 50%.
Form photoetching process that the first siliceous photoresist layer 206 implemented, the first siliceous implementation of photoresist layer 206 is consolidated
The photoetching process that chemical industry skill and the second photoresist layer 209 of formation are implemented can be completed in same lithographic equipment, can also
Completed in different lithographic equipments.
Then, as shown in Figure 2 C, it is mask with the second photoresist layer 209, implementation first, which is etched through, exposes hard mask layer
204。
As an example, implementing the first etching using dry method etch technology, etchant source gas includes fluoro-gas, helium etc., pressure
The parameters such as power, bias power are adjusted according to the implementation size of through hole, are not specifically limited herein.
Then, as shown in Figure 2 D, be mask with the second photoresist layer 209 and planarization layer 207, implement second etching with
Part through-hole pattern is formed in low k dielectric 202, that is, the bottom of the through-hole pattern formed does not expose etching stopping layer 201.
As an example, implementing the second etching using dry method etch technology, etchant source gas includes fluoro-gas, helium etc., pressure
The parameters such as power, bias power are adjusted according to the implementation size of through hole, are not specifically limited herein.
Then, as shown in Figure 2 E, the second photoresist layer 209, the second bottom antireflective coating 208 of Silicon-rich and flat are removed
Change layer 207, expose the first photoresist layer 206.
As an example, remove the second photoresist layer 209, the second bottom antireflective coating 208 and planarization layer 207 of Silicon-rich
Can be with using plasma cineration technics.
Then, as shown in Figure 2 F, groove and complete through hole are formed in low k dielectric 202, and exposes lower floor's copper metal
Interconnection layer.
As an example, being first mask with the first siliceous photoresist layer 206, implement the 3rd etching with the hard mask layer
The channel patterns are formed, then using the hard mask layer with the channel patterns as mask, it is synchronous to implement integration etching (AIO)
Etch buffer layers 203 and low k dielectric 202, with low k dielectric 202 synchronous shape groove and through hole, the integration be etched in
Terminated when exposing etching stopping layer 201, in the process, the first siliceous bottom antireflective coating 205 of photoresist layer 206 and first
Removal is etched, finally, removes the etching stopping layer 201 exposed by through hole, so that through hole is with being formed at Semiconductor substrate 200
On front-end devices connection, can use dry method etch technology implement etching stopping layer 201 removal.
During implementing above-mentioned etching, the oxide hard-mask layer 204b in the hard mask layer is removed in the lump.
So far, the processing step that according to an exemplary embodiment of the present one method is implemented is completed.It is real according to the present invention
Applying dual-damascene technics can reduce by an etching process, reduce process costs；More preferable ditch can be obtained during processing procedure simultaneously
The plyability and preferably through hole smoothing control of groove pattern and through-hole pattern, the through hole in the form of obtaining and there is more preferably side wall.
Reference picture 3, it illustrated therein is flow the step of according to an exemplary embodiment of the present one method is implemented successively
Figure, for schematically illustrating the flow of manufacturing process.
In step 301, there is provided Semiconductor substrate, sequentially form low k dielectric and hard mask layer on a semiconductor substrate；
In step 302, the first siliceous photoresist layer with channel patterns is formed on hard mask layer；
In step 303, the first siliceous photoresist layer of curing process；
In step 304, planarization layer is formed on a semiconductor substrate, and covering first is siliceous while filling channel patterns
Photoresist layer；
In step 305, the second photoresist layer with through-hole pattern is formed on planarization layer；
Within step 306, using the second photoresist layer as mask, etching planarization layer, hard mask layer and low k dielectric, with
Partial through holes are formed in low k dielectric；
In step 307, the second photoresist layer and planarization layer are removed；
In step 308, using the siliceous photoresist layer of first with channel patterns exposed as mask, hard mask layer is etched
And low k dielectric, to form groove and through hole for filling metal interconnecting layer in low k dielectric.
[exemplary embodiment two]
Next, the making of whole semiconductor devices can be completed by subsequent technique, including：In the groove and through hole
Before middle filling copper metal, an etching last handling process is performed, to remove residue and impurity caused by foregoing etching process,
Deposition quality both when guarantee subsequent deposition copper metal diffusion impervious layer and copper metal Seed Layer, implement the etching post processing
Conventional wet clean process can be used.
Copper metal layer is formed in the groove and through hole, is electrically connected with lower floor copper metal interconnection layer.Form copper metal layer
It can use the various suitable technologies that be familiar with of those skilled in the art, such as electroplating technology and the chemistry then implemented
Mechanical milling tech, the purpose for implementing cmp are the table for the surface and metal hard mask layer 204a for making copper metal layer
Face is concordant, is formed before copper metal layer, and copper metal diffusion resistance need to be sequentially formed on the bottom and side wall of the groove and through hole
Barrier and copper metal Seed Layer, copper metal diffusion impervious layer can prevent expansion of the copper into low k dielectric 202 in copper metal layer
Dissipate, copper metal Seed Layer can strengthen the tack between copper metal layer and copper metal diffusion impervious layer, form copper metal diffusion
Barrier layer and copper metal Seed Layer can use the various suitable technologies that those skilled in the art are familiar with, for example, adopting
Copper metal diffusion impervious layer is formed with physical gas-phase deposition, copper is formed using sputtering technology or chemical vapor deposition method
Metal seed layer, the material of copper metal diffusion impervious layer are the group of metal, metal nitride or its combination, preferably Ta and TaN
Conjunction or Ti and TiN combination.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (16)
1. a kind of forming method of semiconductor structure, including：
Semiconductor substrate is provided, sequentially forms low k dielectric and hard mask layer on the semiconductor substrate；
The first siliceous photoresist layer with channel patterns is formed on the hard mask layer；
First siliceous photoresist layer described in curing process；
Planarization layer is formed on the semiconductor substrate, while the planarization layer fills the channel patterns described in covering
First siliceous photoresist layer；
The second photoresist layer with through-hole pattern is formed on the planarization layer；
Using second photoresist layer as mask, the planarization layer, hard mask layer and the low k dielectric are etched, with institute
State and partial through holes are formed in low k dielectric；
Remove second photoresist layer and the planarization layer；
There is the first siliceous photoresist layer of channel patterns as mask described in exposing, the hard mask layer and described low is etched
K dielectric layer, to form groove and through hole for filling metal interconnecting layer in the low k dielectric.
2. according to the method for claim 1, it is characterised in that the material of the first siliceous photoresist layer is photonasty material
Material, and pass through high-temperature process cross-linkable solidifying after exposure.
3. according to the method for claim 1, it is characterised in that the material of the first siliceous photoresist layer is at least by following
Material forms：Silicon-containing polymer, light acid producing agent, dicyandiamide solution with acid-sensitive half side base and it is dispersed or dissolved in institute
State the crosslinking agent in dicyandiamide solution.
4. according to the method for claim 3, it is characterised in that the silicon-containing polymer with acid-sensitive half side base includes：
Silsesquioxane skeleton polymer, siliceous acrylate copolymer, silane polymer, organosilane polymer or poly- (p- hydroxyl
Benzyl silsesquioxane) polymer, wherein, the weight ratio of silicon is 5%-50%.
5. according to the method for claim 3, it is characterised in that the silicon-containing polymer with acid-sensitive half side base includes acid
Quick side chain, the acid-sensitive side chain include tert-butyl group class group, acetyl base class group, adamantane group or lactone group.
6. according to the method for claim 1, it is characterised in that side chain function is included in the first siliceous photoresist layer
Group, after implementing exposure, the 20%-80% of the side chain functionalities replaces with hydroxyl, acidic group, carbonyl or amido.
7. according to the method for claim 3, it is characterised in that the crosslinking agent under the high temperature conditions with the photoetching after exposure
Glue crosslinks reaction, and the crosslinking agent includes：Melamine, methylol melamine, glycoluril, hydroxy alkyl amine, epoxies, epoxy
Amino resins, bivinyl monomer.
8. according to the method for claim 3, it is characterised in that the dicyandiamide solution includes at least one solvent, described molten
Agent is selected from the group being made up of following material：Propylene glycol monomethyl ether, mesitylene, d-limonen, methyl isobutyl alcohol methanol, ethoxy
Base ethyl propionate, butyrolactone, the mixture of ethyl lactate and above-mentioned substance.
9. according to the method for claim 1, it is characterised in that the curing process, temperature are implemented using post bake baking process
Spend for 150 DEG C -250 DEG C, processing time is -10 minutes 0.5 minute.
10. according to the method for claim 1, it is characterised in that form the first siliceous photoresist layer with channel patterns
Lithography step, described in curing process the step of the first siliceous photoresist layer and form the second photoresist layer with through-hole pattern
Lithography step completed in same lithographic equipment, or completed in different lithographic equipments.
11. according to the method for claim 1, it is characterised in that the planarization layer is by the not siliceous of spin coating formation
The organic material layer of element.
12. according to the method for claim 11, it is characterised in that the organic material layer includes carbon, oxygen, hydrogen, nitrogen,
The weight ratio of the carbon is more than 50%.
13. according to the method for claim 1, it is characterised in that the hard mask layer is single layer structure or multiple-level stack knot
Structure.
14. according to the method for claim 1, it is characterised in that interconnected in the Semiconductor substrate formed with underlying metal
Structure.
15. according to the method for claim 14, it is characterised in that the bottom gold is gone out by the bottom-exposed of the through hole
Belong to the surface of interconnection structure.
16. according to the method for claim 15, it is characterised in that also include：Metal is filled in the groove and through hole,
Damascus metal interconnection structure is formed, Damascus metal interconnection structure is electrically connected with the underlying metal interconnection structure
Connect.
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| CN108417529A (en) * | 2018-02-09 | 2018-08-17 | 武汉新芯集成电路制造有限公司 | A kind of lithographic method of contact hole |
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| CN108417529A (en) * | 2018-02-09 | 2018-08-17 | 武汉新芯集成电路制造有限公司 | A kind of lithographic method of contact hole |
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