CN104241114A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN104241114A
CN104241114A CN201310231922.9A CN201310231922A CN104241114A CN 104241114 A CN104241114 A CN 104241114A CN 201310231922 A CN201310231922 A CN 201310231922A CN 104241114 A CN104241114 A CN 104241114A
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China
Prior art keywords
layer
copper metal
hard mask
dielectric
interconnect structure
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CN201310231922.9A
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Chinese (zh)
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CN104241114B (en
Inventor
赵简
曹轶宾
王杭萍
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN201310231922.9A priority Critical patent/CN104241114B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02096—Cleaning only mechanical cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a method for manufacturing a semiconductor device. The method includes the steps of providing a semiconductor substrate; sequentially forming an etching stopping layer, a low-k dielectric layer, a buffering layer and a hard mask layer on the semiconductor substrate; forming first openings in the hard mask layer for exposing out the buffering layer; executing the wet-process cleaning process, wherein basic solvents are used as cleaning fluid for wet-process cleaning; forming second openings in the buffering layer and the low-k dielectric layer; forming copper metal interconnection structures in the low-k dielectric layer; forming copper metal layers in the copper metal interconnection structures. According to the method, the basic solvents are adopted for replacing dilute hydrofluoric acid to serve as the cleaning fluid for wet-process cleaning implemented after the first openings are formed, the defects generated when the second openings are subsequently formed can be effectively overcome, and an integration etching process window is improved.

Description

A kind of manufacture method of semiconductor device
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of method improving dual damascene process.
Background technology
In the back-end process (BEOL) of semiconductor device, usually adopt the copper metal interconnecting layer in dual damascene process formation semiconductor device, Figure 1A-Fig. 1 E shows a kind of dual damascene process process.
First, as shown in Figure 1A, provide Semiconductor substrate 100, adopt chemical vapor deposition method to form etching stopping layer 101, low k dielectric 102, resilient coating 103 and hard mask layer 104 successively on a semiconductor substrate 100.
Be formed with front-end devices on a semiconductor substrate 100, in order to simplify, do not give in legend and illustrating.Described front-end devices refers to the device formed before BEOL, does not limit at this to the concrete structure of front-end devices.Usual employing ultra low k dielectric materials forms low k dielectric 102, and described ultra low k dielectric materials refers to the dielectric material that dielectric constant (k value) is less than 2.Resilient coating 103 is by the OMCTS(prestox cyclisation tetrasiloxane stacked gradually from bottom to top) layer 103a and TEOS(tetraethoxysilane) layer 103b form, the effect of TEOS layer 103b avoids the porous structure of mechanical stress to ultra low k dielectric materials to cause damage when the copper-connection metal that follow-up grinding is filled, and the effect of OMCTS layer 103a is to increase adhesive force therebetween as the transition material layer between ultra low k dielectric materials and TEOS.Hard mask layer 104 is made up of the metal hard mask layer 104a stacked gradually from bottom to top and oxide hardmask layer 104b, and the structure of this double-deck hard mask layer can ensure the craft precision of Dual graphing or multiple graphical.
Then, as shown in Figure 1B, in hard mask layer 104, the first opening 105 is formed, to expose the resilient coating 103 of below.First opening 105 is used as the pattern of the groove in copper metal interconnect structure, and it can comprise multiple figure with different characteristic size.
Then, as shown in Figure 1 C, form the second opening 106 in resilient coating 103 and low k dielectric 102, described second opening 106 is used as the pattern of the through hole in copper metal interconnect structure, and it also can comprise multiple figure with different characteristic size.
Then, as shown in figure ip, with hard mask layer 104 for mask, perform integration etching (All-in-one Etch) technique etch buffer layers 103 and low k dielectric 102(and synchronous etch buffer layers 103 and low k dielectric 102), to form copper metal interconnect structure 107 in low k dielectric 102.
After formation first opening 105, need execution one wet cleaning processes to remove the etching residue that produces of hard mask layer 104 and impurity, to guarantee that the formation of follow-up second opening 106 has good process window.Hydrofluoric acid due to DHF(dilution) there is desirable cleaning efficiency, therefore, the hydrofluoric acid that those skilled in the art adopt DHF(to dilute usually) as the cleaning fluid of described wet-cleaned.But due to the constraint of device feature size, the one-tenth-value thickness 1/10 of the TEOS layer 103b in resilient coating 103 is less, and the loss problem of the TEOS that DHF causes is particularly outstanding.The key of this problem is, the loss of TEOS may cause exposing the part OMCTS layer 103a be positioned at below TEOS layer 103b, in the forming process of follow-up second opening 106, need the ODL(organic dielectric layer formed at first) there is chemical reaction form a kind of material having a strong impact on etching efficiency with the described part OMCTS layer 103a exposed, cause the depth value of the part figure in the second opening 106 too low, after enforcement integration etching, occur that the bottom of the part figure in the copper metal interconnect structure 107 as shown in Fig. 1 E does not contact with etching stopping layer 101, and then cause copper metal interconnect structure 107 to occur the problem of part interconnection open.The mechanism of the chemical reaction between above-mentioned OMCTS and ODL is: the free fluorine in residual DHF attacks the carbon in OMCTS, and induction produces the silicon key (Si-) be activated; BARC(bottom antireflective coating in order to strengthen ODL and formed above it) between tack, the HMDS(HMDS playing soakage layer effect is formed) above ODL, amido in HMDS and silicon key and free fluorine reconfigure and form Si-N-H-F group, and this group can cause the decline of etch-rate.
Therefore, need to propose a kind of method, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, form etching stopping layer, low k dielectric, resilient coating and hard mask layer successively on the semiconductor substrate; The first opening is formed, to expose described resilient coating in described hard mask layer; Perform wet cleaning processes, adopt basic solvent as the cleaning fluid of described wet-cleaned; The second opening is formed in described resilient coating and described low k dielectric; Copper metal interconnect structure is formed in described low k dielectric.
Further, the pH value of described basic solvent is 9.0-11.0.
Further, described first opening is used as the pattern of the groove in described copper metal interconnect structure, and described second opening is used as the pattern of the through hole in described copper metal interconnect structure.
Further, with described hard mask layer for mask, with resilient coating described in step etching and described low k dielectric, to form described copper metal interconnect structure in described low k dielectric.
Further, after described etching terminates, also comprise the etching stopping layer removed and exposed by described copper metal interconnect structure and the step implementing etching reprocessing.
Further, after described etching reprocessing, be also included in the step forming copper metal layer in described copper metal interconnect structure.
Further, before forming described copper metal layer, be also included in the step bottom of described copper metal interconnect structure and sidewall being formed successively copper metal diffusion barrier layer and copper metal seed layer.
Further, described resilient coating is made up of prestox cyclisation tetrasiloxane layer stacked from bottom to top and teos layer.
Further, described hard mask layer is made up of metal hard mask layer stacked from bottom to top and oxide hardmask layer.
Further, the constituent material of described metal hard mask layer is TiN, BN, AlN or its combination.
Further, the constituent material of described oxide hardmask layer comprises SiO 2or SiON, and relative to the constituent material of described metal hard mask layer, there is good etching selectivity.
According to the present invention, adopt basic solvent to substitute the cleaning fluid of hydrofluoric acid as the wet-cleaned implemented after formation first opening of dilution, effectively can avoid the defect occurred when producing follow-up formation the second opening, improve the process window of integration etching.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
The schematic cross sectional view of the device that Figure 1A-Fig. 1 D obtains respectively for the step implemented successively according to existing exemplary dual damascene process;
The schematic cross sectional view of the defect occurred after the exemplary dual damascene process of Fig. 1 E shown by enforcement Figure 1A-Fig. 1 D;
The schematic cross sectional view of the device that Fig. 2 A-Fig. 2 F obtains respectively for method is implemented successively according to an exemplary embodiment of the present invention step;
Fig. 3 is that method improves the flow chart of dual damascene process according to an exemplary embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the method for the improvement dual damascene process that the present invention proposes.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment]
Below, describe method according to an exemplary embodiment of the present invention with reference to Fig. 2 A-Fig. 2 F and Fig. 3 and improve the detailed step of dual damascene process.
With reference to Fig. 2 A-Fig. 2 F, the schematic cross sectional view of the device that the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively obtains respectively.
First, as shown in Figure 2 A, provide Semiconductor substrate 200, adopt chemical vapor deposition method to form etching stopping layer 201, low k dielectric 202, resilient coating 203 and hard mask layer 204 successively on semiconductor substrate 200.
Be formed with front-end devices on semiconductor substrate 200, in order to simplify, do not give in legend and illustrating.Described front-end devices refers to the device formed before BEOL, does not limit at this to the concrete structure of front-end devices.
Material preferred SiCN, SiC, SiN or BN of etching stopping layer 201, it with while the etching stopping layer forming upper copper metal interconnect structure, can prevent the copper in lower floor's copper metal interconnecting wires to be diffused in the dielectric substance layer (such as low k dielectric 202) on upper strata as subsequent etch low k dielectric 202.
The constituent material of low k dielectric 202 can be selected from the common various low k-value dielectric materials in this area, include but not limited to that k value is silicate compound (the Hydrogen Silsesquioxane of 2.5-2.9, referred to as HSQ), k value be 2.2 methane-siliconic acid salt compound (Methyl Silsesquioxane, be called for short MSQ), k value be the HOSP of 2.8 tM(advanced low-k materials of the mixture based on organic substance and Si oxide that Honeywell company manufactures) and k value are the SiLK of 2.65 tM(a kind of advanced low-k materials that Dow Chemical company manufactures) etc.Usual employing ultra low k dielectric materials forms low k dielectric 202, and described ultra low k dielectric materials refers to the dielectric material that dielectric constant (k value) is less than 2.
Resilient coating 203 comprises the OMCTS layer 203a and TEOS layer 203b that stack gradually from bottom to top, the effect of TEOS layer 203b avoids the porous structure of mechanical stress to ultra low k dielectric materials to cause damage when the copper-connection metal that follow-up grinding is filled, and the effect of OMCTS layer 203a is to increase adhesive force therebetween as the transition material layer between ultra low k dielectric materials and TEOS.
Hard mask layer 204 comprises the metal hard mask layer 204a and oxide hardmask layer 204b that stack gradually from bottom to top, the structure of this double-deck hard mask layer can ensure the craft precision of Dual graphing or multiple graphical, ensure the degree of depth of whole groove figure and the consistency of side wall profile of required formation in hard mask layer 204, namely first the channel patterns with different characteristic size is formed in oxide hardmask layer 204b, again with the groove figure of oxide hardmask layer 204b required formation for mask etch metal hard mask layer 204a makes in hard mask layer 204.The constituent material of metal hard mask layer 204a comprises TiN, BN, AlN or it combines arbitrarily, preferred TiN; The constituent material of oxide hardmask layer 204b comprises SiO 2, SiON etc., and require that it has good etching selectivity relative to the constituent material of metal hard mask layer 204a.
Then, as shown in Figure 2 B, in hard mask layer 204, the first opening 205 is formed, to expose the resilient coating 203 of below.First opening 205 is used as the pattern of the groove in copper metal interconnect structure, and it can comprise multiple figure with different characteristic size.
According to the situation of the figure of required formation, need twice or repeatedly implement the patterning process of described channel patterns, each enforcement includes following steps: on oxide hardmask layer 204b, form ODL layer (organic dielectric layer), BARC layer (bottom antireflective coating) and PR layer (photoresist layer) successively; Photoetching, development treatment are carried out to PR layer, to form channel patterns in PR layer; With the PR layer of patterning for mask, etch BARC layer, ODL layer and oxide hardmask layer 204b successively, in oxide hardmask layer 204b, form channel patterns; Adopt the PR layer of the technique removal patternings such as ashing, BARC layer and ODL layer.Finally, to form the oxide hardmask layer 204b of all required channel patterns wherein for mask, etching metal hard mask layer 204a, completes the making of the first opening 205.
Next, perform wet cleaning processes, adopt basic solvent (Alkaline solvent) as the cleaning fluid of described wet-cleaned.The preferred 9.0-11.0 of pH value of described basic solvent.The basic solvent meeting described pH value condition comprises the EKC produced du pont company, with regard to the functional component of EKC, comprises oxidant, etchant, chelating agent, pH value conditioning agent, corrosion inhibiter and water.
Then, as shown in Figure 2 C, form the second opening 206 in resilient coating 203 and low k dielectric 202, described second opening 206 is used as the pattern of the through hole in copper metal interconnect structure, and it also can comprise multiple figure with different characteristic size.
According to the situation of the figure of required formation, need twice or repeatedly implement the patterning process of described through-hole pattern, each enforcement includes following steps: form ODL layer, HMDS layer, BARC layer and PR layer successively on semiconductor substrate 200, cover the first opening 205; Photoetching, development treatment are carried out to PR layer, to form through-hole pattern in PR layer; With the PR layer of patterning for mask, etch BARC layer, HMDS layer, ODL layer, resilient coating 203 and part low k dielectric 202 successively, in resilient coating 203 and low k dielectric 202, form through-hole pattern; Adopt the PR layer of the technique removal patternings such as ashing, BARC layer, HMDS layer and ODL layer.
Because described basic solvent can not cause damage to the TEOS layer 203b in resilient coating 203, also would not cause the exposure of the OMCTS layer 203a below TEOS layer 203b, therefore, can not there is with OMCTS the chemical reaction forming Si-N-H-F group in the ODL of formation.
Then, as shown in Figure 2 D, with hard mask layer 204 for mask, perform the synchronous etch buffer layers 203 of integrated etching technics and low k dielectric 202, to form copper metal interconnect structure 207 in low k dielectric 202, namely synchronously form the groove in copper metal interconnect structure 207 and through hole.Described integration is etched in when exposing etching stopping layer 201 and stops.
Then, as shown in Figure 2 E, remove the etching stopping layer 201 exposed by copper metal interconnect structure 207, be communicated with the front-end devices be formed in Semiconductor substrate 200 to make copper metal interconnect structure 207.In the present embodiment, dry method etch technology is adopted to implement the removal of described etching stopping layer 201.Then, fill copper metal in copper metal interconnect structure 207 before, perform etching last handling process, to remove the residue and impurity that aforementioned etching process produces, the deposition quality both when ensureing subsequent deposition copper metal diffusion barrier layer and copper metal seed layer.
Then, as shown in Figure 2 F, in copper metal interconnect structure 207, copper metal layer 208 is formed.Form the copper metal layer 208 various suitable technology that those skilled in the art can be adopted to have the knack of, such as electroplating technology and the chemical mechanical milling tech implemented subsequently.Implementing the object of cmp, to be to make the surface of copper metal layer 208 concordant with the surface of hard mask layer 204.
Before forming copper metal layer 208, copper metal diffusion barrier layer 209 and copper metal seed layer 210 need be formed successively on the bottom of copper metal interconnect structure 207 and sidewall, copper metal diffusion barrier layer 209 can prevent copper in copper metal layer 208 to the diffusion in low k dielectric 202, and copper metal seed layer 210 can strengthen the tack between copper metal layer 208 and copper metal diffusion barrier layer 209.The various suitable technology that formation copper metal diffusion barrier layer 209 and copper metal seed layer 210 can adopt those skilled in the art to have the knack of, such as, adopt physical gas-phase deposition to form copper metal diffusion barrier layer 209, adopt sputtering technology or chemical vapor deposition method to form copper metal seed layer 210.The material of copper metal diffusion barrier layer 209 is metal, metal nitride or its combination, the combination of preferred Ta and TaN or the combination of Ti and TiN.。
So far, the processing step that the method according to an exemplary embodiment of the present invention that completes is implemented, next, can complete the making of whole semiconductor device by subsequent technique.According to the present invention, adopt basic solvent to substitute the cleaning fluid of hydrofluoric acid as the wet-cleaned implemented after formation first opening 205 of dilution, the defect occurred when can effectively avoid producing follow-up formation the second opening 206, improves the process window of integration etching.
With reference to Fig. 3, the method according to an exemplary embodiment of the present invention that illustrated therein is improves the flow chart of dual damascene process, for schematically illustrating the flow process of whole manufacturing process.
In step 301, provide Semiconductor substrate, form etching stopping layer, low k dielectric, resilient coating and hard mask layer successively on a semiconductor substrate;
In step 302, in hard mask layer, form the first opening, to expose resilient coating;
In step 303, perform wet cleaning processes, adopt basic solvent as the cleaning fluid of described wet-cleaned;
In step 304, in resilient coating and low k dielectric, the second opening is formed;
In step 305, in low k dielectric, copper metal interconnect structure is formed;
Within step 306, in copper metal interconnect structure, copper metal layer is formed.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.

Claims (11)

1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, forms etching stopping layer, low k dielectric, resilient coating and hard mask layer successively on the semiconductor substrate;
The first opening is formed, to expose described resilient coating in described hard mask layer;
Perform wet cleaning processes, adopt basic solvent as the cleaning fluid of described wet-cleaned;
The second opening is formed in described resilient coating and described low k dielectric;
Copper metal interconnect structure is formed in described low k dielectric.
2. method according to claim 1, is characterized in that, the pH value of described basic solvent is 9.0-11.0.
3. method according to claim 1, is characterized in that, described first opening is used as the pattern of the groove in described copper metal interconnect structure, and described second opening is used as the pattern of the through hole in described copper metal interconnect structure.
4. method according to claim 1, is characterized in that, with described hard mask layer for mask, with resilient coating described in step etching and described low k dielectric, to form described copper metal interconnect structure in described low k dielectric.
5. method according to claim 4, is characterized in that, after described etching terminates, also comprises the etching stopping layer removed and exposed by described copper metal interconnect structure and the step implementing etching reprocessing.
6. method according to claim 5, is characterized in that, after described etching reprocessing, is also included in the step forming copper metal layer in described copper metal interconnect structure.
7. method according to claim 6, is characterized in that, before forming described copper metal layer, is also included in the step bottom of described copper metal interconnect structure and sidewall being formed successively copper metal diffusion barrier layer and copper metal seed layer.
8. method according to claim 1, is characterized in that, described resilient coating is made up of prestox cyclisation tetrasiloxane layer stacked from bottom to top and teos layer.
9. method according to claim 1, is characterized in that, described hard mask layer is made up of metal hard mask layer stacked from bottom to top and oxide hardmask layer.
10. method according to claim 9, is characterized in that, the constituent material of described metal hard mask layer is TiN, BN, AlN or its combination.
11. methods according to claim 10, is characterized in that, the constituent material of described oxide hardmask layer comprises SiO 2or SiON, and relative to the constituent material of described metal hard mask layer, there is good etching selectivity.
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Publication number Priority date Publication date Assignee Title
CN107431009A (en) * 2015-03-26 2017-12-01 三菱电机株式会社 The manufacture method of semiconductor device
CN112863999A (en) * 2019-11-26 2021-05-28 中芯国际集成电路制造(上海)有限公司 Etching method
CN116130353A (en) * 2023-01-03 2023-05-16 芯众享(成都)微电子有限公司 Method for forming trench structure with complex geometric section on semiconductor surface

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CN1300291C (en) * 2002-09-09 2007-02-14 三菱瓦斯化学株式会社 Cleaning composition
CN101154046A (en) * 2006-09-30 2008-04-02 中芯国际集成电路制造(上海)有限公司 Manufacturing method for double-mosaic structure
CN102403269A (en) * 2011-11-30 2012-04-04 上海华力微电子有限公司 Method for dry etching of first metal layer

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Publication number Priority date Publication date Assignee Title
US20020081834A1 (en) * 2000-12-26 2002-06-27 Honeywell International Inc. Method for eliminating reaction between photoresist and OSG
CN1300291C (en) * 2002-09-09 2007-02-14 三菱瓦斯化学株式会社 Cleaning composition
CN101154046A (en) * 2006-09-30 2008-04-02 中芯国际集成电路制造(上海)有限公司 Manufacturing method for double-mosaic structure
CN102403269A (en) * 2011-11-30 2012-04-04 上海华力微电子有限公司 Method for dry etching of first metal layer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107431009A (en) * 2015-03-26 2017-12-01 三菱电机株式会社 The manufacture method of semiconductor device
CN107431009B (en) * 2015-03-26 2020-10-27 三菱电机株式会社 Method for manufacturing semiconductor device
CN112863999A (en) * 2019-11-26 2021-05-28 中芯国际集成电路制造(上海)有限公司 Etching method
CN112863999B (en) * 2019-11-26 2023-10-27 中芯国际集成电路制造(上海)有限公司 Etching method
CN116130353A (en) * 2023-01-03 2023-05-16 芯众享(成都)微电子有限公司 Method for forming trench structure with complex geometric section on semiconductor surface

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