CN104051324A - Forming method of metal interconnection structure - Google Patents
Forming method of metal interconnection structure Download PDFInfo
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- CN104051324A CN104051324A CN201310080598.5A CN201310080598A CN104051324A CN 104051324 A CN104051324 A CN 104051324A CN 201310080598 A CN201310080598 A CN 201310080598A CN 104051324 A CN104051324 A CN 104051324A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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Abstract
The invention relates to a forming method of a metal interconnection structure. The forming method comprises the following steps that: a semiconductor structure is provided, wherein a metal layer, a first interlayer dielectric layer, and a first mask layer are formed at the semiconductor structure from bottom to top, the first mask layer has a first mask pattern, and the metal layer contains Cu and the first mask layer contains Ti; first etching is carried out on the first interlayer dielectric layer along the first mask pattern of the first mask layer and is stopped before the metal layer is exposed; cleaning processing is carried out by using mixed gas containing fluorocarbon gas and Ar; second etching is carried out on the semiconductor structure that has been cleaned along the first mask pattern by using the first mask layer as the mask to expose the metal layer. According to the technical scheme, further cleaning processing is carried out before the metal layer is exposed, thereby solving a problem that burr occurs at the bottom of the metal interconnection structure in the prior art can be solved. Moreover, the method is simple and the effect is obvious.
Description
Technical field
The present invention relates to semiconductor process techniques, relate in particular to a kind of formation method of metal interconnect structure.
Background technology
At present, in integrated circuit fabrication process, conventionally adopt Damascus technics to form copper metal line and the metal throuth hole that is connected the copper metal line in adjacent levels; Damascus technics has been technique common in semiconductor technology processing procedure, the PCT application that correlation technique can be WO2010/007477 with reference to publication number.
In actual process process, on whole silicon chip, a lot of metal interconnected grooves and a lot of through hole coordinate formation metal interconnect structure.Below in conjunction with Fig. 1 to Fig. 5, briefly introduce existing Damascus technics with the metal interconnect structure that forms a through hole and metal interconnected groove intercommunication:
As shown in Figure 1, provide semiconductor structure, described semiconductor structure comprises from bottom to up: metal level 40, etching stop layer 41, first medium layer 32, hard mask layer 20, second medium layer 31 and photoresist layer 10.In photoresist layer 10, be formed with the etching figure 70 of through hole, in hard mask layer 20, be formed with the etching figure 80 of metal interconnected groove.The material of described metal level 40 is Cu, and the material of hard mask layer 20 is TiN, and the material of etching stop layer 41 is SiN.
As shown in Figure 2, utilize photoresist layer 10 for mask, etching second medium layer 31, and see through the etching figure 80 of the metal interconnected groove in described hard mask layer 20, and etch away the first medium layer 32 of segment thickness, form through hole 71.Wherein, described through hole 71 does not run through first medium layer 32.
As shown in Figure 3, remove second medium layer 31 and photoresist layer 10, expose described hard mask layer 20 and be formed on the etching figure 80 of the metal interconnected groove in hard mask layer 20.
As shown in Figure 4, taking hard mask layer 20 as mask, etching first medium layer 32, until expose etching stop layer 41, to form the metal interconnected groove 81 that is communicated with described through hole 71 in first medium layer 32, and the bottom of described through hole 71 is extended to the surface of etching stop layer 41.
As shown in Figure 5, etching stop layer 41 described in etching, makes through hole 71 bottom-exposed go out metal level 40.In this step, need to carry out over etching to the etching of etching stop layer 41, described over etching amount is 30%～150%, to guarantee that all through holes 71 on whole silicon chip all expose metal level 40, avoid filling after metal, the metal of filling in the through hole 71 in some region on silicon chip is not connected with the metal level 40 of its below, causes lower metal layer to open circuit.
Form the good damascene structure being formed by through hole 71 and metal interconnected groove 81 in first medium layer 32 after, in through hole 71 and metal interconnected groove 81, fill metal and form metal interconnect structure, to realize and being communicated with of metal level 40.The metal interconnect structure that above-mentioned technical process forms is a typical case, on silicon chip, also may there is in addition the metal interconnect structure of other form of metal interconnected groove 81 and through hole cooperation formation, such as: multiple through holes 71 are communicated with the structure of a metal interconnected groove 81 or in some regions, only have the structure of metal interconnected groove 81.
And through above-mentioned technical process, can find to have in the bottom of metal interconnected groove 81 some burr shape defects (defect) 5, the existence meeting of burr shape defect 5 exerts an influence to follow-up processing procedure, thereby the performance to the semiconductor device forming impacts, need a kind of method to solve this problem.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of metal interconnect structure, avoids the bottom of metal interconnected groove to occur the problem of burr shape defect.
For addressing the above problem, the invention provides a kind of formation method of metal interconnect structure, comprising:
Semiconductor structure is provided, and described semiconductor structure is formed with metal level, the first interlayer dielectric layer and the first mask layer from bottom to up, in described the first mask layer, has the first mask pattern, in described metal level, containing Cu, contains Ti in described the first mask layer;
Along the first mask pattern in the first mask layer, the first interlayer dielectric layer is carried out to the first etching, described first is etched in to expose before described metal level and stops;
Utilize the mist of fluorocarbon gases and Ar to carry out clean;
Continue taking the first mask layer as mask, along the first mask pattern, the semiconductor structure through clean is carried out to the second etching, to expose described metal level.
Optionally, described clean technique is 20mtorr～200mtorr for pressure in etching cavity is set, and power is less than 600W, utilizes the mist of CHF3 and Ar to carry out, and the range of flow of the mist of CHF3 and Ar is 20sccm～1500sccm.
Optionally, between described the first interlayer dielectric layer and metal level, also comprise one deck etching stop layer.
Optionally, described the second etching is for to carry out etching to described etching stop layer, and described the second etching carries out over etching, and over etching amount is 30%～150%.
Optionally, the material of described metal level is Cu, and the material of described the first mask layer is TiN.
Optionally, the material of described the first interlayer dielectric layer is low k dielectric layer, SiO
2, one in phosphorosilicate glass.
Optionally, be also formed with from bottom to up the second interlayer dielectric layer and the second mask layer on described the first mask layer, in described the second mask layer, have the second mask pattern, described the second mask pattern and the first mask pattern partially overlap.
Optionally, described the first mask pattern is metal interconnected groove figure, and the second mask pattern is via hole image.
Optionally, described the first etching is carried out taking the second mask layer as mask.
Optionally, after carrying out described the first etching, before carrying out described clean, also comprise step:
Remove the second mask layer and the second interlayer dielectric layer;
Taking the first mask pattern as the first interlayer dielectric layer described in mask etching, to form the metal interconnected groove being connected with the through hole of described the first etching formation in described the first interlayer dielectric layer.
Optionally, the material of described the first mask layer is TiN.
Optionally, described the second interlayer dielectric layer is organic coating.
Optionally, described the second mask layer is photoresist.
Optionally, the surface of described semiconductor structure is the first mask layer, and described the first mask pattern is metal interconnected groove figure or via hole image.
Compared with prior art, technical solution of the present invention has the following advantages:
Carrying out in the process of Damascus technics, before the lower metal layer of cupric exposes, utilize the mist of fluorocarbon gases and Ar to carry out clean.Fluorocarbon gases in described clean can play the removal effect to the polymer generation chemical reaction containing Ti, can produce very fast etching reaction.And the bond energy of chemical bond is more intense between fluorocarbon gases, in course of reaction, can not react with the oxide of silicon or silicon, in clean, can not cause damage to semiconductor structure.Ar in described clean has larger relative atomic weight, plays the effect of physical bombardment.Therefore through clean, can get rid of by the polymer containing Ti producing in etching containing the first mask layer of Ti.Expose the copper in lower metal layer carrying out again etching after clean, avoid copper and the interpolymer interaction containing Ti to produce the polymer that is difficult to removal, avoid the polymer deposition that is difficult to remove to hinder the etching to metal interconnected groove at metal interconnected bottom land, thereby avoided forming burr shape defect in the bottom of metal interconnected groove.
In addition, before exposing metal level, carry out clean, described clean is carried out in etching cavity, does not need to increase new equipment, does not also need complicated operation just can solve the problem that can occur in the bottom of metal interconnected groove burr in existing dual damascene process.
Brief description of the drawings
The schematic diagram that Fig. 1 to Fig. 5 is a kind of method that forms metal interconnect structure of providing in prior art;
Fig. 6 is the schematic diagram that only forms the effect of groove by the technique of prior art;
The schematic diagram that Fig. 7 to Figure 13 is the manufacture metal interconnect structure that provides in embodiment mono-;
The schematic diagram that Figure 14 to Figure 15 is the manufacture metal interconnect structure that provides in embodiment bis-.
Embodiment
In the process of existing making metal interconnect structure, inventor finds that metal interconnected groove 81 bottoms that connect with through hole 71 can produce burr; And inventor tests, if only carry out the etching of groove in dielectric layer, form groove 82 as shown in Figure 6, can find, described groove 82 bottoms are smooth, can not produce the phenomenon of burr.Accordingly, inventor's deduction, the generation of the burr 5 of metal interconnected groove 81 bottoms shown in Fig. 5 is relevant with the exposure of metal level 40.
Inventor, again through test repeatedly, finds: the material of hard mask layer 20 is generally TiN, and metal level 40 is generally Cu.In etching process, also can be etched away part as the TiN of hard mask layer, and produce the polymer containing Ti.These polymer containing Ti can be diffused in etching cavity or be deposited on the semiconductor structure being etched.Generally, in etching process, be deposited on the etching away containing the agent that can be etched of the polymer of Ti on semiconductor structure that be etched, can not affect the etching process of the film to wanted etching.But after copper comes out, Cu can with containing the polymer acting in conjunction of Ti, form the utmost point and be difficult to the polymer of removing.And after just exposing copper, also can continue etching (over etching), guarantee that the through hole on whole silicon chip all exposes copper.This etching process can make the degree of depth of metal interconnected groove 81 be deepened.If the polymer that is difficult to remove is deposited on the bottom of metal interconnected groove 81, in the process that can deepen in metal interconnected groove 81 degree of depth, stops the etching to metal interconnected groove 81 bottoms, thereby form burr in the final metal interconnected groove forming 81 bottoms.
Thus, inventor provides a kind of ways of addressing this issue, and its major way is the metal level 40(copper layer below opening 71 exposes completely) before, carry out clean, remove containing the polymer of Ti, and then carry out etching the copper of bottom is come out.Like this, efficiently solve in the process of utilizing Damascus technics to form metal interconnect structure, can form in the bottom of metal interconnected groove the problem of burr.Described clean is undertaken by Ar and fluorocarbon gases.Through the checking of inventor's test of many times, such method can effectively be avoided the generation of burr 5 in Fig. 4.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Embodiment mono-
In the present embodiment, elaborate in conjunction with Fig. 7 to Figure 13 the method that the formation metal interconnect structure providing in technical scheme of the present invention is provided in dual damascene process.
As shown in Figure 7, semiconductor structure is provided, described semiconductor structure comprises: metal level 400, cover described metal level 400 surfaces etching stop layer 401, be positioned at the dielectric layer 300 on described etching stop layer 401, and cover the second mask layer 100 of described dielectric layer 300.
In the present embodiment, the second mask layer 100 is photoresist, is wherein formed with the second mask pattern 700, the etching figure that described the second mask pattern 700 is through hole.
In the present embodiment, described dielectric layer 300 is multiplet, comprises successively from bottom to up the first interlayer dielectric layer 302, the first mask layer 200, the second interlayer dielectric layers 301.Wherein, the material of described the first interlayer dielectric layer 302 is silica, low K dielectric layer, phosphorosilicate glass etc.The material of described the second interlayer dielectric layer 301 is organic coating, is convenient to be etched and be removed.In described the first mask layer 200, be formed with the first mask pattern 800, described the first mask pattern 800 is metal interconnected groove etched figure.The material of the first mask layer 200 is titanium nitride.In other embodiments, described the first mask layer 200 can be also other material of containing Ti, or for top layer be the lamination layer structure that contains the material of Ti.
In the present embodiment, the material of described etching stop layer 401 is silicon nitride, for avoiding metal level 400 to be exposed when the etching dielectric layer 300.
In the present embodiment, the material of described metal level 400 is copper, and in other embodiments, described metal level 400 can be also the alloy that contains copper, or has the complex metal layer structure of copper layer.
In the present embodiment, between described the second mask layer 100 and the second interlayer dielectric layer 301, be also formed with bottom anti-reflection layer 101, as the auxiliary layer of photoresist (the second mask layer 100), the rete in photoetching process below protection is not subject to the impact of light.
In the present embodiment, between the first mask layer 200 and the first interlayer dielectric layer 302, can also form TEOS layer 201 by chemical vapor deposition method, described TEOS layer 201 can be used as the stress-buffer layer between the first mask layer 200 and the first interlayer dielectric layer 302.
As shown in Figure 8, utilizing the second mask layer 100 is mask, along the first interlayer dielectric layer 302 of the second mask pattern 700 etching bottom anti-reflection layer 101, the second interlayer dielectric layer 301, the first mask layer 200, TEOS layer 201 and segment thickness, forms through hole 701; Described through hole 701 does not penetrate described the first interlayer dielectric layer 302.
In the present embodiment, the technique that etching formation through hole 701 adopts is anisortopicpiston dry etching, and described etching technics can guarantee that the sidewall pattern of the through hole 701 forming has good up rightness.
As shown in Figure 9, remove the first interlayer dielectric layer 301, bottom anti-reflection layer 101 and the second mask layer 100, to the first mask pattern 800 exposing in described the first mask layer 200 and described the first mask layer 200.
As shown in figure 10, taking the first mask layer 200 as mask, along the first mask pattern 800 etching TEOS layers 201 and the first interlayer dielectric layer 302, form metal interconnected groove 801; Described metal interconnected groove 801 is connected with through hole 701.
In the process of the metal interconnected groove of formation, the degree of depth of through hole 701 continues to deepen in etching process, and the etching of this step proceeds to the bottom of through hole 701 and exposes described etching stop layer 401 surfaces.
In this step, in the time of etching TEOS layer 201 and the first interlayer dielectric layer 302, described the first mask layer 200 also can consume to some extent, thereby forms the polymer 9 containing Ti.Some can be deposited on the surface of described semiconductor structure containing the polymer 9 of Ti, the bottom of described metal interconnected groove 801 also can be deposited the polymer 9 of part containing Ti.
In other embodiments, the surface of described metal level 400 can not have etching stop layer 401 yet.Not having in the embodiment of etching stop layer 401, need to control being etched in this step and stop before exposing metal level 400.By comparison, in the present embodiment, increasing etching stop layer 401 can more easily control etching and not expose metal level 400.
As shown in figure 11, utilize the mist 50 of fluorocarbon gases and assist gas in etching cavity, to carry out clean, remove shown in Figure 10 containing Ti polymer 9.
In the present embodiment, described clean is essentially isotropic plasma dry etching, and etching is removed the polymer 9 containing Ti on semiconductor structure surface.The gas that described clean adopts is mainly fluorocarbon gases, and assist gas is Ar.Described fluorocarbon gases is the hydrocarbon of fluoridizing, and has one or several hydrogen atoms to be substituted by fluorine atom in hydrocarbon, comprises CHF
3, C
2h
5f, CF
4, C
2f
6deng in one or more.In clean, fluorocarbon gases can play the removal effect with the polymer generation chemical reaction containing Ti, can produce very fast etching reaction.And the bond energy of chemical bond is more intense between fluorocarbon gases, in course of reaction, can not react with the oxide of silicon or silicon, in clean, can not damage to some extent semiconductor structure.Ar has larger relative atomic weight, plays the effect of physical bombardment.
In the present embodiment, described clean is for utilizing CHF
3carry out with the mist of Ar.When described clean, it is 20mtorr～200mtorr that pressure is set in etching cavity, and power is less than 600W, CHF
3with the range of flow of the mist of Ar be 20sccm～1500sccm, wherein CHF
3with the volume ratio scope of Ar be 2:1 to 3:1.The technological parameters such as pressure in above-mentioned clean, power, flow, volume ratio are to work in coordination and interact to realize preferably to remove containing the effect of the polymer 9 of Ti.The degree that described clean need to be carried out is different and different with production requirement according to different technology conditions with the time, such as the setting of the concrete technology parameter in etching technics carries out above degree, clean, or the thickness of the first different mask layers 200 etc. situation difference all can affect degree and the time that described clean need to be carried out.In actual production, as long as the polymer 9 of the described Ti of containing is got rid of most of yield requirement that forms device that just can meet, do not need to remove completely.
As shown in figure 12, taking the first mask layer 200 as mask, etch away through hole 701 bottom etching stop layers 401 to exposing metal level 400.
Similarly to the prior art, in this step, need to carry out over etching to the etching of etching stop layer 401, to guarantee that on silicon chip, all through holes 701 bottoms are all exposed to metal level 400, avoid upper lower metal layer in the final metal interconnect structure forming to open circuit.Described over etching amount is 30%～150%.
In over etching process, the first interlayer dielectric layer 302 of described metal interconnected groove 801 bottoms agent etching that also can be etched, the degree of depth of metal interconnected groove 801 also continues to deepen.And passed through the clean in previous process, eliminate the polymer of most of Ti.In this step, even in etching, still the first mask layer 200 is consumed to some extent, can form a small amount of new polymer containing Ti.But, with in existing technique, do not carry out clean and compare, after clean, semiconductor structure surface is also considerably less containing the amount of the polymer of Ti, and with the amount that the meeting that the interaction of the metal level 400 of the cupric coming out produces is difficult to the polymer of removing be also little, the impact of the etching on this step also can be very little.Actual proof, after the polymer containing Ti is removed thoroughly before, finishes in the etching of this step, can form burr in metal interconnected groove 801 bottoms hardly.
Afterwards, as shown in figure 13, in through hole 701 and metal interconnected groove 801, fill metal, form dual damascene conductive structure 410, to realize and being communicated with of metal level 400.
In other embodiments, filling before metal, also comprise and remove remaining the first mask layer 200, the mode of removal is cmp.
Embodiment bis-
In the present embodiment, in conjunction with elaborate the method that the formation metal interconnect structure being provided in technical scheme of the present invention is provided in single Damascus technics as Figure 14 to Figure 15.
As shown in figure 14, provide semiconductor structure, described semiconductor structure comprises the interlayer dielectric layer 300 of metal level 400, individual layer, the first mask layer 100 forming on interlayer dielectric layer 300.
In the present embodiment, between interlayer dielectric layer 300 and the first mask layer 100, be also formed with TEOS layer 101, between metal level 400 and interlayer dielectric layer 300, be also formed with etching stop layer 401.
In the present embodiment, described the first mask layer 100 is TiN, wherein has the first mask pattern 800, the etching figure that described mask pattern 800 is through hole.In other embodiments, described the first mask pattern 800 can be also the etching figure of metal interconnected groove, and such structure is applicable to the single Damascus technics that forms separately through hole or form separately metal interconnected groove.
In the present embodiment, taking the first mask layer 100 as mask, the first mask pattern 800 in the first mask layer 100 carries out etching to TEOS layer 101 and interlayer dielectric layer 300, to form through hole.Described etching proceeds to via bottoms and exposes the surface of etching stop layer 401.Similar with embodiment mono-, in the present embodiment, meeting loss the first mask layer 100 in the time of etching interlayer dielectric layer 300, thus form containing the polymer deposition of Ti.
Similar with embodiment mono-, exposing behind the surface of etching stop layer 401, utilize CHF
3carry out clean with Ar, remove the polymer containing Ti, then etching stop layer 401 described in etching, and need to carry out over etching to the etching of etching stop layer 401, make the bottom-exposed of through hole go out metal level 400.Described clean utilizes the mist 50 of fluorocarbon gases and assist gas to carry out in etching cavity.Described clean has been removed the polymer containing Ti, avoid copper to come out and produced with the interpolymer interaction containing Ti the polymer that is difficult to removal, and then avoided the polymer that is difficult to remove to affect the effect of follow-up etching and the final metal interconnect structure forming of impact.
As shown in figure 15, in the through hole forming through previous step etching, fill metal, form single Damascus conductive structure 420, to realize and being communicated with of metal level 400.In the present embodiment, after filling metal, can also comprise the step of removing remaining the first mask layer 100, the mode of removal is cmp.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.
Although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (14)
1. a formation method for metal interconnect structure, is characterized in that, comprising:
Semiconductor structure is provided, and described semiconductor structure is formed with metal level, the first interlayer dielectric layer and the first mask layer from bottom to up, in described the first mask layer, has the first mask pattern, in described metal level, containing Cu, contains Ti in described the first mask layer;
Along the first mask pattern in the first mask layer, the first interlayer dielectric layer is carried out to the first etching, described first is etched in to expose before described metal level and stops;
Utilize the mist of fluorocarbon gases and Ar to carry out clean;
Continue taking the first mask layer as mask, along the first mask pattern, the semiconductor structure through clean is carried out to the second etching, to expose described metal level.
2. the formation method of metal interconnect structure as claimed in claim 1, is characterized in that, described clean technique is 20mtorr～200mtorr for pressure in etching cavity is set, and power is less than 600W, utilizes CHF
3carry out CHF with the mist of Ar
3with the range of flow of the mist of Ar be 20sccm～1500sccm.
3. the formation method of metal interconnect structure as claimed in claim 1, is characterized in that, between described the first interlayer dielectric layer and metal level, also comprises one deck etching stop layer.
4. the formation method of metal interconnect structure as claimed in claim 3, is characterized in that, described the second etching comprises carries out etching to described etching stop layer, and described the second etching carries out over etching, and over etching amount is 30%～150%.
5. the formation method of metal interconnect structure as claimed in claim 1, is characterized in that, the material of described metal level is Cu, and the material of described the first mask layer is TiN.
6. the formation method of metal interconnect structure as claimed in claim 1, is characterized in that, the material of described the first interlayer dielectric layer is low k dielectric layer, SiO
2, one in phosphorosilicate glass.
7. the formation method of metal interconnect structure as claimed in claim 1, it is characterized in that, on described the first mask layer, be also formed with from bottom to up the second interlayer dielectric layer and the second mask layer, in described the second mask layer, have the second mask pattern, described the second mask pattern and the first mask pattern partially overlap.
8. the formation method of metal interconnect structure as claimed in claim 7, is characterized in that, described the first mask pattern is metal interconnected groove figure, and the second mask pattern is via hole image.
9. the formation method of metal interconnect structure as claimed in claim 8, is characterized in that, described the first etching is carried out taking the second mask layer as mask.
10. the formation method of metal interconnect structure as claimed in claim 9, is characterized in that, after carrying out described the first etching, before carrying out described clean, also comprises step:
Remove the second mask layer and the second interlayer dielectric layer;
Taking the first mask pattern as the first interlayer dielectric layer described in mask etching, to form the metal interconnected groove being connected with the through hole of described the first etching formation in described the first interlayer dielectric layer.
The formation method of 11. metal interconnect structures as claimed in claim 7, is characterized in that, the material of described the first mask layer is TiN.
The formation method of 12. metal interconnect structures as claimed in claim 7, is characterized in that, described the second interlayer dielectric layer is organic coating.
The formation method of 13. metal interconnect structures as claimed in claim 7, is characterized in that, described the second mask layer is photoresist.
The formation method of 14. metal interconnect structures as claimed in claim 1, is characterized in that, the surface of described semiconductor structure is the first mask layer, and described the first mask pattern is metal interconnected groove figure or via hole image.
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| CN108305827A (en) * | 2017-01-11 | 2018-07-20 | 中芯国际集成电路制造(上海)有限公司 | A method of removal etching procedure residual polyalcohol |
| CN108751123A (en) * | 2018-05-21 | 2018-11-06 | 赛莱克斯微系统科技（北京）有限公司 | A kind of forming method of contact hole |
| CN112201580A (en) * | 2020-12-07 | 2021-01-08 | 中芯集成电路制造(绍兴)有限公司 | Contact hole etching method and manufacturing method of semiconductor device |
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