CN104979273A - Method of forming interconnection structure - Google Patents
Method of forming interconnection structure Download PDFInfo
- Publication number
- CN104979273A CN104979273A CN201410136507.XA CN201410136507A CN104979273A CN 104979273 A CN104979273 A CN 104979273A CN 201410136507 A CN201410136507 A CN 201410136507A CN 104979273 A CN104979273 A CN 104979273A
- Authority
- CN
- China
- Prior art keywords
- layer
- opening
- interlayer dielectric
- sacrifice layer
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The present invention provides a method of forming an interconnection structure. The method of forming the interconnection structure comprises the steps of forming an interlayer dielectric layer on a substrate; forming a barrier layer on the interlayer dielectric layer; forming a hard mask on the barrier layer, wherein a first opening penetrating the thickness of the hard mask is formed in the hard mask; filling a sacrificial layer in the first opening until the sacrificial layer covers the hard mask; patterning the sacrificial layer, and forming a second opening exposed out of the barrier layer in the sacrificial layer located in the first opening, wherein the second opening is less than the first opening; removing the barrier layer exposed from the second opening; etching the patterned sacrificial layer and the interlayer dielectric layer exposed from the second opening in the sacrificial layer to form a through hole; etching the interlayer dielectric layer exposed from the first opening and the interlayer dielectric layer exposed from the through hole by taking the hard mask as the mask, forming a groove in the interlayer dielectric layer exposed from the first opening, and enabling the through hole to penetrate the interlayer dielectric layer. The method of forming the interconnection structure of the present invention enables the damage to the interlayer dielectric layer to be reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to a kind of method forming interconnection structure.
Background technology
Along with the development of ic manufacturing technology, the integrated level of integrated circuit is more and more higher, and accordingly, in integrated circuit, the arrangement of the interconnection structure of semiconductor device is also more intensive.It is increasing on the impact of semiconductor device that the reason such as parasitic capacitance between interconnection structure and the RC that produces postpone (RC delay).
In order to solve the problem, prior art starts to adopt low k dielectric (low-k) or ultra low k dielectric materials (ultra low-k) to form the interlayer dielectric layer of interconnection structure, to reduce the parasitic capacitance between metal plug, and then reduces RC delay.
Meanwhile, prior art also adopts the less copper of resistance coefficient to replace the material of traditional aluminium as the metal plug in interconnection structure, to reduce the resistance of metal plug self.Meanwhile, because the fusing point of copper is high, and anti-electromigration ability is also stronger, relative to the metal plug of traditional aluminum, can carry higher current density, enters to be conducive to and improves the packaging density of the chip of formation.Particularly, prior art adopts Damascus (Damascene) or dual damascene (Dual Damascene) technique to form the metal plug of copper.
But above-mentioned low k dielectric or ultra low k dielectric materials are easy to sustain damage in dual damascene process process.Such as, the groove (Trench) and the through hole (Via) that are defined needs formation by photoresist is generally needed in dual damascene process, but photoresist needs to be divested (strip), because low k dielectric or ultra low k dielectric materials mostly are loose porous structure, not only easily be oxidized, and mechanical strength is low, the process removing photoresist is easy to cause damage to the interlayer dielectric layer of described low k dielectric or ultra low k dielectric materials.
So the damage that the interlayer dielectric layer how reducing low k dielectric or ultra low k dielectric materials is subject to, becomes those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves is to provide a kind of method forming interconnection structure, reduces the damage of interlayer dielectric layer when forming the interconnection structure of semiconductor as far as possible.
For solving the problem, the invention provides a kind of method forming interconnection structure, comprising:
Substrate is provided;
Form interlayer dielectric layer over the substrate;
Described interlayer dielectric layer forms barrier layer;
Described barrier layer forms hard mask, in described hard mask, is formed with the first opening running through described hard mask thickness;
Sacrifice layer is filled, until described sacrifice layer covers described hard mask in described first opening;
Graphical described sacrifice layer, formed at the sacrifice layer being arranged in the first opening and expose described barrier layer second opening, described second opening is less than described first opening;
Remove the barrier layer that the second opening exposes;
The interlayer dielectric layer that second opening in sacrifice layer after graphical and sacrifice layer exposes is etched, to form through hole;
With described hard mask for mask, etch interlayer dielectric layer that described first opening exposes and the interlayer dielectric layer that through hole exposes, in the interlayer dielectric layer that described first opening exposes, form groove and make described through hole run through described interlayer dielectric layer.
Optionally, the step of filling sacrifice layer in described first opening comprises: adopt the mode of spin coating or fluid chemistry vapour deposition to form described sacrifice layer.
Optionally, the step of filling sacrifice layer in described first opening comprises: the material of described sacrifice layer is one or more in low k dielectric, ultra low k dielectric materials, oxide material, nitride material, tetraethyl orthosilicate, silicon oxynitride, amorphous carbon and organic antireflection layer.
Optionally, graphical described sacrifice layer, the step forming the second opening at the sacrifice layer being arranged in the first opening comprises:
Described sacrifice layer forms anti-reflecting layer;
Anti-reflecting layer described in photoetching and sacrifice layer are to form described second opening;
Remove remaining anti-reflecting layer.
Optionally, the step forming anti-reflecting layer comprises: on described sacrifice layer, form amorphous carbon layer and dielectric anti reflective layer successively.
Optionally, the step forming anti-reflecting layer comprises: on described sacrifice layer, be formed with the anti-etching oxidant layer of motor spindle and the anti-reflecting layer based on silicon successively.
Optionally, adopt the mist of nitrogen and hydrogen to remove remaining anti-reflecting layer, or any one in employing oxygen, carbon dioxide, carbon monoxide remove remaining anti-reflecting layer.
Optionally, form the step of groove in interlayer dielectric layer after, also comprise:
Metal level is filled in described through hole and groove;
Metal level described in planarization removes unnecessary metal level, retains the metal level being arranged in described through hole and groove.
Optionally, the step forming interlayer dielectric layer over the substrate comprises: the interlayer dielectric layer forming low k dielectric on substrate.
Optionally, step substrate being formed the interlayer dielectric layer of low k dielectric comprises: form the low k dielectric that k value is less than 3.
Optionally, the step forming hard mask comprises, and forms the hard mask of titanium nitride or boron nitride material.
Optionally, etch the interlayer dielectric layer that the second opening in the sacrifice layer after graphical and sacrifice layer exposes, to be formed in the step of through hole, sacrifice layer is removed.
Compared with prior art, technical scheme of the present invention has the following advantages:
The present invention first at the first opening that described hard mask is formed, to define the follow-up groove formed in interlayer dielectric layer, then forms the second opening, to define the follow-up through hole formed in interlayer dielectric layer in sacrifice layer.Because described through hole is defined by the second opening in described sacrifice layer, and the second opening formed is only exposed on barrier layer, interlayer dielectric layer does not now expose, the mode of the through hole of the formation defined by photoresist in prior art, do not deposit in the prior art, the situation of interlayer dielectric layer while removing photoresist, can be damaged to.
In addition, with the sacrifice layer after graphical for mask, etch the interlayer dielectric layer that the second opening exposes, to be formed in the process of through hole, sacrifice layer can be completely removed, that is, without the need to arranging the step removing together sacrifice layer again, also can not cause because removing sacrifice layer and poly-injury is crossed to interlayer dielectric layer, therefore, the present invention can not increase the complexity that interconnection structure manufactures, and also improves the quality of interconnection structure simultaneously.
Accompanying drawing explanation
Fig. 1 to Fig. 9 is the structural representation that the present invention forms each step in method one embodiment of interconnection structure.
Embodiment
In the last part technology (backend of the line technology, BEOL) of semiconductor manufacturing, often use Damascus (Damascene) or dual damascene (Dual Damascene) technique formation interconnection structure.In the process, needing the size and the position that define groove and the through hole that will be formed by forming photoresist, after this, also needing photoresist to remove.Because low k or ultra low k dielectric materials are usually more loose porous, mechanical strength is very little, and very easily oxidized, so when removing photoresist, is easy to cause damage to the interlayer dielectric layer of low k or ultra low k dielectric materials.
Such as, wet-cleaned may be adopted under certain situation to remove photoresist, but be easy to oxidized due to the interlayer dielectric layer of low k or ultra low k dielectric materials, be easy to cause damage to interlayer dielectric layer in cleaning process; Dry method may be adopted in other situation to clean, but the lower low k of mechanical strength or ultra low k dielectric materials are also easy to be subject to the bombardment of plasma and damage.
Correspondingly, the invention provides a kind of method forming interconnection structure, described method comprises: provide substrate; Form interlayer dielectric layer over the substrate; Described interlayer dielectric layer forms barrier layer; Described barrier layer forms hard mask, in described hard mask, is formed with the first opening running through described hard mask thickness; Sacrifice layer is filled, until described sacrifice layer covers described hard mask in described first opening; Graphical described sacrifice layer, formed at the sacrifice layer being arranged in the first opening and expose described barrier layer second opening, described second opening is less than described first opening; Remove the barrier layer that the second opening exposes; The interlayer dielectric layer that second opening in sacrifice layer after graphical and sacrifice layer exposes is etched, to form through hole; With described hard mask for mask, etch interlayer dielectric layer that described first opening exposes and the interlayer dielectric layer that through hole exposes, in the interlayer dielectric layer that described first opening exposes, form groove and make described through hole run through described interlayer dielectric layer.
The present invention first at the first opening that described hard mask is formed, to define the follow-up groove formed in interlayer dielectric layer, then forms the second opening, to define the follow-up through hole formed in interlayer dielectric layer in sacrifice layer.Because described through hole is defined by the second opening in described sacrifice layer, and the second opening formed is only exposed on barrier layer, interlayer dielectric layer does not now expose, the mode of the through hole of the formation defined by photoresist in prior art, do not deposit in the prior art, the situation of interlayer dielectric layer while removing photoresist, can be damaged to.
In addition, with the sacrifice layer after graphical for mask, etch the interlayer dielectric layer that the second opening exposes, to be formed in the process of through hole, sacrifice layer can be completely removed, that is, without the need to arranging the step removing together sacrifice layer again, also can not cause because removing sacrifice layer and poly-injury is crossed to interlayer dielectric layer, therefore, the present invention can not increase the complexity that interconnection structure manufactures, and also improves the quality of interconnection structure simultaneously.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and elaborate to specific embodiments of the invention below in conjunction with accompanying drawing.
With reference to figure 1, provide substrate (not shown).Described substrate can be silicon substrate, silicon-on-insulator, silicon-Germanium substrate etc.In the present embodiment, the such as semiconductor device such as grid, source-drain area is defined by FEOL (frontend of the linetechnology, FEOL) in described substrate.Substrate surface may also be formed with metal plug or metal interconnecting wires.But the present invention is to this and be not construed as limiting.
Please continue to refer to Fig. 1, form interlayer dielectric layer 100 over the substrate, and dielectric layer 100 forms barrier layer 110 between described.
In the present embodiment, the low k dielectric that described interlayer dielectric layer 100 adopts k value to be less than 3 is formed, with the parasitic capacitance between the metal interconnecting wires reducing follow-up formation as far as possible.But it should be noted that, the present invention does not do any restriction for the k value of described interlayer dielectric layer 100, in other embodiments of the invention, the lower or higher material of k value can be adopted to form described interlayer dielectric layer 100, so the present invention should do not limited with this.
As shown in Figure 1, also it should be noted that, in the present embodiment, also be formed with etch stop layer 20 over the substrate, for playing the effect of etching stopping in the step of etching formation through hole and groove, and after the step forming through hole and groove, the etch stop layer 20 exposed by through hole is removed, so that after filling metal, the metal of filling contacts to realize being electrically connected with other parts such as metal level or metal plug being arranged in substrate.But described etch stop layer 20 is only the structure used in the present embodiment, should not limit the present invention with this.
Incorporated by reference to reference to figure 1 and Fig. 2, described interlayer dielectric layer 100 forms described layer of hard mask material 122, graphical described layer of hard mask material 122 forms hard mask 120, the first opening running through described hard mask 120 thickness is formed, for defining the size of groove in interlayer dielectric layer 100 in described hard mask 120.
In the present embodiment, described hard mask 120 can adopt titanium nitride (TiN) as material.But the present invention does not also limit this, such as boron nitride (BN) etc. also can as the material of described hard mask 120.
Particularly, the step of graphical described layer of hard mask material 122 comprises: in described layer of hard mask material 122, form anti-reflecting layer 210 and photoresist 220 successively.
Photoresist 220 described in photoetching, to form the opening 221 of expose portion anti-reflecting layer 210, wherein, the size d1 of described opening 221 is for defining the size of the follow-up groove (trench) formed in described interlayer dielectric layer 100.
In the present embodiment, described anti-reflecting layer 210 is bottom anti-reflection layer (Bottom Anti-ReflectCoating, BARC), but the present invention is not construed as limiting this.
With reference to figure 2, the step of graphical described layer of hard mask material 122 comprises: with in Fig. 1 by the photoresist 220 after photoetching for mask, etch the anti-reflecting layer 210 exposed, hard mask 120 and partial barrier 110, to form the first opening 121 shown in this Fig. 2; The size of described first opening 121 is basic identical with the size d1 of the opening 221 in photoresist 220.
Then photoresist 220 and anti-reflecting layer 210 is removed.
It should be noted that, in the present embodiment, formation described layer of hard mask material 122 before, also on described interlayer dielectric layer 100, form barrier layer 110, in subsequent etching process as etching barrier layer.
Particularly, described barrier layer 110 can adopt the materials such as such as silicon nitride to be formed, and has larger etching selection ratio between this material and described hard mask 120.But the present invention does not limit this, also other material can be adopted to form described barrier layer 110, such as, one or more combination of silica, tetraethyl orthosilicate (Tetra Ethyl Ortho Silicate, TEOS) or above-mentioned material.
In the present embodiment, the effect of etching stop layer, for etching to be formed in the step of described first opening 121 to described hard mask 120 follow-up, is played in described barrier layer 110.
As shown in Figure 3,121 filling sacrifice layers 300 in described first opening, until described sacrifice layer 300 covers described hard mask 120.Described sacrifice layer 300 in subsequent step as the etching mask of interlayer dielectric layer 100.
In addition, the material of sacrifice layer 300 can be identical with interlayer dielectric layer 100 or material character is close, sacrifice layer 300 is while as etching mask, himself is also thinned and even removes, that is, in subsequent step, form through hole in interlayer dielectric layer 100 after, described sacrifice layer 300 is also completely removed.
In the present embodiment, described sacrifice layer 300 adopts low k or ultra low k dielectric materials to be formed, such benefit is, selection and comparison between the sacrifice layer 300 of low k or ultra low k dielectric materials and described interlayer dielectric layer 100 is little, in subsequent steps, be conducive to removing described sacrifice layer 300 while the described interlayer dielectric layer 100 of etching, that is, be conducive to described sacrifice layer 300 to be removed while etching described interlayer dielectric layer 100.
It should be noted that, can after sacrifice layer 300 be removed completely, carry out again etching the step forming groove, correspondingly, before sacrifice layer 300 is removed completely, what in interlayer dielectric layer 100, etching was formed is through hole, and that is, the thickness of sacrifice layer 300 is relevant to the difference of the groove finally formed and via depth.The thickness of sacrifice layer 300 need meet the following conditions: be at least filled in described first opening and cover described hard mask, and the thickness of sacrifice layer 300 is preferably not more than the thickness of described interlayer dielectric layer 100 simultaneously.In actual process, the thickness of sacrifice layer 300 can according to etching technics of reality etc. because usually adjusting.
But, in other embodiments of the invention, the material of described sacrifice layer 300 can also be such as DUO(DUV Light Absorbing Oxide, a kind of antireflecting coating of SiO2 base, containing elements such as silicon, carbon, oxygen), as carbon oxide (Carbon Doped Oxide, oxide material, nitride material, tetraethyl orthosilicate, silicon oxynitride, amorphous carbon, the organic antireflection layer such as CDO), and the combination of one or more above-mentioned materials.
In the present embodiment, the mode of spin coating can be adopted to form described sacrifice layer 300, and this method relative cost is lower, and the sacrifice layer 300 formed is after the corresponding planarisation step of collocation (such as cmp etc.), has good flatness.But the present invention does not limit this, alternate manner also can be adopted to form described sacrifice layer 300, such as fluid chemistry vapour deposition (Fluidized Chemical VaporDeposition, FCVD) this mode has good filling capacity.
As shown in Figure 3 and Figure 4, graphical described sacrifice layer, removes and corresponds to shown in first opening 121(Fig. 2) in partial sacrificial layer, to form second opening on barrier layer, exposed portion in sacrifice layer.Wherein, described second opening is less than described first opening.
Particularly, the step of graphical described sacrifice layer comprises: on described sacrifice layer, form anti-reflecting layer 400 and photoresist 230 successively.
In the present embodiment, described anti-reflecting layer 400 comprises dielectric anti reflective layer 410 and amorphous carbon layer 420.
Photoresist 230 described in photoetching, to form the opening 231 of exposed portion dielectric anti reflective layer 410; The size d2 of described opening 231 is for defining the size of the through hole (via) formed in follow-up described interlayer dielectric layer 100 again.
It should be noted that, the present invention is for the concrete material of above-mentioned anti-reflecting layer 400, and the number of plies is not construed as limiting, in other embodiments of the invention, anti-reflecting layer 400 also can be the anti-etching oxidant layer of organic bottom (the organic under-layer resist be formed at successively on described sacrifice layer, ODL) and based on the anti-reflecting layer (Si-ARC) of Si, wherein said ODL layer is that a kind of normal collocation with described Si-ARC layer uses, and has the bottom anti-reflective material of certain filling capacity; Anti-reflecting layer 400 can also be the three-decker (tri-layer) that bottom anti-reflection layer, dielectric anti reflective layer and amorphous carbon are formed.
As shown in Figure 4, the step of graphical described sacrifice layer also comprises: with the photoresist 230 after photoetching for mask, etch the dielectric anti reflective layer 410 exposed from described opening 231, and amorphous carbon layer 420 and sacrifice layer 300, thus form the second opening 301 in described dielectric anti reflective layer and sacrifice layer 300.The part on described barrier layer 110 is exposed by described second opening 301.
Then remaining photoresist 230 and dielectric anti reflective layer 410 is removed, because interlayer dielectric layer 100 now has described sacrifice layer 300 to block, so the step removing photoresist 230 can not cause poly-injury to described interlayer dielectric layer 100.
In conjunction with reference to figure 5, after graphical described sacrifice layer 300, also remove remaining amorphous carbon layer 420.
In the present embodiment, dry etching can be adopted to remove described amorphous carbon layer 420.Oxygen specifically can be adopted as etching gas, and this gas is high for the selection and comparison of amorphous carbon layer 420, while not having influence on sacrifice layer 300 and barrier layer 110, can ensure the etching for amorphous carbon layer 420 greater efficiency as far as possible.
But the present invention is to this and do not limit, also can adopt the mist of nitrogen or hydrogen, or carbon dioxide, carbon monoxide remove described amorphous carbon layer 420.
When then removing remaining amorphous carbon layer 420, due to sacrifice layer 300 and barrier layer 110 block, poly-injury can not be caused to described interlayer dielectric layer 100.
With reference to figure 6, the interlayer dielectric layer 100 of the second opening 301 correspondence in the sacrifice layer 300 after graphical and sacrifice layer 300 is etched, to form through hole 102(with reference to figure 7).
Now, because the selection and comparison be all between the sacrifice layer 300 of low k dielectric, described interlayer dielectric layer 100 is little, while described interlayer dielectric layer 100 is etched, described sacrifice layer 300 is also being consumed, and namely the thickness of described sacrifice layer 300 is thinned and even removes.
In the present embodiment, after formation through hole 102, described sacrifice layer 300 is removed.
Ideal in order to ensure the sidewall profile of the through hole 102 formed, adopt dry etching in the present embodiment.And the etching parameters such as concrete such as etching agent, should, according to actual conditions, coordinate the material of described interlayer dielectric layer 100 to adjust, the present invention be restricted this.
Then with reference to figure 7, when described through hole 102 be etched the degree of depth increase gradually time, sacrifice layer 300 is also little by little consumed, and exposes the first opening 121 in hard mask 120.
In conjunction with reference to figure 8, with described hard mask 120 for mask, etch the interlayer dielectric layer that described first opening 121 exposes, until described through hole 102 runs through described interlayer dielectric layer 100, and form groove 101(trench in the interlayer dielectric layer 100 exposed at described first opening 121).
After the described through hole 102 of formation and groove 101, in the present embodiment, further comprising the steps of:
Remove the partial etching stop layer 20 be positioned at bottom through hole 102, expose substrate;
Metal level (not shown) is filled in described groove and through hole 102;
Unnecessary metal level is removed, to form the interconnection structure with damascene structure by flatening process.
In the present embodiment, described flatening process is cmp (CMP).
In the present embodiment, described metal interconnecting wires 50 adopts copper as material, electroplating technology can be adopted to fill described metal level, but, the present invention should do not limited with this, can also adopt as the other materials such as aluminium, tungsten formed as described in metal interconnecting wires 50, other techniques also can be adopted to form described metal level.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (12)
1. form a method for interconnection structure, it is characterized in that, comprising:
Substrate is provided;
Form interlayer dielectric layer over the substrate;
Described interlayer dielectric layer forms barrier layer;
Described barrier layer forms hard mask, in described hard mask, is formed with the first opening running through described hard mask thickness;
Sacrifice layer is filled, until described sacrifice layer covers described hard mask in described first opening;
Graphical described sacrifice layer, form at the sacrifice layer being arranged in the first opening the second opening exposing described barrier layer, described second opening is less than described first opening;
Remove the barrier layer that the second opening exposes;
The interlayer dielectric layer that second opening in sacrifice layer after graphical and sacrifice layer exposes is etched, to form through hole;
With described hard mask for mask, etch interlayer dielectric layer that described first opening exposes and the interlayer dielectric layer that through hole exposes, in the interlayer dielectric layer that described first opening exposes, form groove and make described through hole run through described interlayer dielectric layer.
2. the method for claim 1, is characterized in that, the step of filling sacrifice layer in described first opening comprises: adopt the mode of spin coating or fluid chemistry vapour deposition to form described sacrifice layer.
3. the method for claim 1, it is characterized in that, the step of filling sacrifice layer in described first opening comprises: the material of described sacrifice layer is one or more in low k dielectric, ultra low k dielectric materials, oxide material, nitride material, tetraethyl orthosilicate, silicon oxynitride, amorphous carbon and organic antireflection layer.
4. the method for claim 1, is characterized in that, graphical described sacrifice layer, and the step forming the second opening at the sacrifice layer being arranged in the first opening comprises:
Described sacrifice layer forms anti-reflecting layer;
Anti-reflecting layer described in photoetching and sacrifice layer are to form described second opening;
Remove remaining anti-reflecting layer.
5. method as claimed in claim 4, is characterized in that, the step forming anti-reflecting layer comprises: on described sacrifice layer, form amorphous carbon layer and dielectric anti reflective layer successively.
6. method as claimed in claim 4, is characterized in that, the step forming anti-reflecting layer comprises: on described sacrifice layer, be formed with the anti-etching oxidant layer of motor spindle and the anti-reflecting layer based on silicon successively.
7. method as claimed in claim 5, is characterized in that, adopts the mist of nitrogen and hydrogen to remove remaining anti-reflecting layer, or any one in employing oxygen, carbon dioxide and carbon monoxide removes remaining anti-reflecting layer.
8. the method for claim 1, is characterized in that, after forming the step of groove, also comprises in interlayer dielectric layer:
Metal level is filled in described through hole and groove;
Metal level described in planarization removes unnecessary metal level, retains the metal level being arranged in described through hole and groove.
9. the method for claim 1, is characterized in that, the step forming interlayer dielectric layer over the substrate comprises: the interlayer dielectric layer forming low k dielectric on substrate.
10. method as claimed in claim 9, it is characterized in that, the step that substrate is formed the interlayer dielectric layer of low k dielectric comprises: form the low k dielectric that k value is less than 3.
11. the method for claim 1, is characterized in that, the step forming hard mask comprises, and form the hard mask of titanium nitride or boron nitride material.
12. the method for claim 1, is characterized in that, etch the interlayer dielectric layer that the second opening in the sacrifice layer after graphical and sacrifice layer exposes, to be formed in the step of through hole, sacrifice layer is removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410136507.XA CN104979273B (en) | 2014-04-04 | 2014-04-04 | The method for forming interconnection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410136507.XA CN104979273B (en) | 2014-04-04 | 2014-04-04 | The method for forming interconnection structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104979273A true CN104979273A (en) | 2015-10-14 |
| CN104979273B CN104979273B (en) | 2018-02-16 |
Family
ID=54275659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410136507.XA Active CN104979273B (en) | 2014-04-04 | 2014-04-04 | The method for forming interconnection structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104979273B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112071804A (en) * | 2020-09-17 | 2020-12-11 | 长江存储科技有限责任公司 | Semiconductor device and manufacturing method thereof |
| CN113488392A (en) * | 2021-07-13 | 2021-10-08 | 武汉新芯集成电路制造有限公司 | Method for manufacturing integrated circuit device |
| CN114182202A (en) * | 2021-12-06 | 2022-03-15 | 江西省纳米技术研究院 | Micro-processing method for metal pattern of electronic device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106706172B (en) * | 2015-11-12 | 2021-04-02 | 上海丽恒光微电子科技有限公司 | Preparation method of pressure sensor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030008490A1 (en) * | 2001-07-09 | 2003-01-09 | Guoqiang Xing | Dual hardmask process for the formation of copper/low-k interconnects |
| CN1433062A (en) * | 2002-01-10 | 2003-07-30 | 联华电子股份有限公司 | Method of forming opening in low dielectric constant material |
| US20080145998A1 (en) * | 2002-12-31 | 2008-06-19 | Applied Materials, Inc. | Method of forming a low-k dual damascene interconnect structure |
-
2014
- 2014-04-04 CN CN201410136507.XA patent/CN104979273B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030008490A1 (en) * | 2001-07-09 | 2003-01-09 | Guoqiang Xing | Dual hardmask process for the formation of copper/low-k interconnects |
| CN1433062A (en) * | 2002-01-10 | 2003-07-30 | 联华电子股份有限公司 | Method of forming opening in low dielectric constant material |
| US20080145998A1 (en) * | 2002-12-31 | 2008-06-19 | Applied Materials, Inc. | Method of forming a low-k dual damascene interconnect structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112071804A (en) * | 2020-09-17 | 2020-12-11 | 长江存储科技有限责任公司 | Semiconductor device and manufacturing method thereof |
| CN113488392A (en) * | 2021-07-13 | 2021-10-08 | 武汉新芯集成电路制造有限公司 | Method for manufacturing integrated circuit device |
| CN113488392B (en) * | 2021-07-13 | 2022-08-02 | 武汉新芯集成电路制造有限公司 | Method for manufacturing integrated circuit device |
| CN114182202A (en) * | 2021-12-06 | 2022-03-15 | 江西省纳米技术研究院 | Micro-processing method for metal pattern of electronic device |
| CN114182202B (en) * | 2021-12-06 | 2023-11-24 | 江西省纳米技术研究院 | Micromachining method for metal pattern of electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104979273B (en) | 2018-02-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10978389B2 (en) | Semiconductor device and manufacturing method thereof | |
| US9613880B2 (en) | Semiconductor structure and fabrication method thereof | |
| CN107731739B (en) | Method for forming semiconductor structure | |
| CN1983552A (en) | Dual-damascene process | |
| CN105789111B (en) | The forming method of semiconductor structure | |
| KR20230163973A (en) | Semiconductor device and method for manufacturing the same | |
| CN109427578A (en) | Semiconductor structure and forming method thereof | |
| US6815331B2 (en) | Method for forming metal wiring layer of semiconductor device | |
| CN104979273A (en) | Method of forming interconnection structure | |
| CN101840859A (en) | Manufacturing method of semiconductor component | |
| CN103066014A (en) | Copper/ air gap preparation method | |
| CN104143528B (en) | The forming method of interconnection structure | |
| US7407886B2 (en) | Method for preparing a contact plug structure | |
| CN104124202A (en) | Formation method of dual damascene structure | |
| CN106356330B (en) | The forming method of semiconductor structure | |
| US20080160759A1 (en) | Method for fabricating landing plug contact in semiconductor device | |
| US9136164B2 (en) | Semiconductor device and fabrication method | |
| CN108962817A (en) | Semiconductor structure and forming method thereof | |
| TW202123335A (en) | Method of forming semiconductor device structure | |
| CN111293074A (en) | Semiconductor structure and forming method thereof | |
| US11810816B2 (en) | Chemical mechanical polishing topography reset and control on interconnect metal lines | |
| US20240087950A1 (en) | Wet etch process and methods to form air gaps between metal interconnects | |
| KR20070028873A (en) | Method for forming a dual damascene line of semiconductor | |
| JP2010114255A (en) | Manufacturing method for semiconductor device | |
| CN111128865A (en) | Damascus interconnection process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |