CN108962817A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108962817A CN108962817A CN201710363698.7A CN201710363698A CN108962817A CN 108962817 A CN108962817 A CN 108962817A CN 201710363698 A CN201710363698 A CN 201710363698A CN 108962817 A CN108962817 A CN 108962817A
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- interlayer dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
Abstract
A kind of semiconductor structure and forming method thereof, method include: offer substrate, have gate structure in substrate, have the first interlayer dielectric layer in the substrate that gate structure exposes, the first interlayer dielectric layer exposes at the top of gate structure；Remove the first interlayer dielectric layer；After removing the first interlayer dielectric layer, the second interlayer dielectric layer is formed in the substrate that gate structure exposes, and the second interlayer dielectric layer exposes at the top of gate structure, the relative dielectric constant of the relative dielectric constant of the second interlayer dielectric layer less than the first interlayer dielectric layer；Contact hole plug is formed in the second interlayer dielectric layer, contact hole plug is electrically connected with substrate.The present invention replaces the scheme of the first interlayer dielectric layer by using lesser second interlayer dielectric layer of relative dielectric constant, so as to reduce RC retardation ratio, and then improves the performance of semiconductor devices.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
In the semiconductor device, reduce RC retardation ratio (Resistance capacitance delay), can be improved and partly lead
The performance of body device.As the function of the development of semiconductor technology, the propulsion of technology node, device is gradually become strong, the collection of device
Higher and higher at spending, the characteristic size (Critical Dimension, CD) of device is also smaller and smaller, correspondingly, further subtracting
Small RC retardation ratio becomes one of the important measures for improving performance of semiconductor device.
The interconnection structure of semiconductor devices includes contact hole plug.Currently, in order to reduce RC retardation ratio, contact hole plug is adopted
Material is usually the lesser material of resistance value, such as cobalt or tungsten etc., to improve the performance of semiconductor devices.
But even if contact hole plug has chosen the lesser material of resistance value, the performance of semiconductor devices is still to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, optimizes the electricity of semiconductor devices
Performance.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: substrate is provided, it is described
There is gate structure in substrate, there is the first interlayer dielectric layer in the substrate that the gate structure exposes, first interlayer is situated between
Matter layer exposes at the top of the gate structure；Remove first interlayer dielectric layer；After removing first interlayer dielectric layer, in institute
It states and forms the second interlayer dielectric layer in the substrate of gate structure exposing, second interlayer dielectric layer exposes the gate structure top
Portion, the relative dielectric constant of second interlayer dielectric layer are less than the relative dielectric constant of first interlayer dielectric layer；Institute
It states and forms contact hole plug in the second interlayer dielectric layer, the contact hole plug is electrically connected with the substrate.
Optionally, the material of first interlayer dielectric layer is SiO2。
Optionally, the material of second interlayer dielectric layer is low k dielectric materials or ultra-low k dielectric material.
Optionally, the material of second interlayer dielectric layer is SiOC or SiOCH.
Optionally, after removing first interlayer dielectric layer, the second layer is formed in the substrate that the gate structure exposes
Between before dielectric layer, the forming method further include: form the first sacrificial layer in the substrate that the gate structure exposes, it is described
First sacrificial layer exposes at the top of the gate structure；Exposure mask is formed on the first sacrificial layer of part of the gate structure two sides
Layer；Using the mask layer as exposure mask, first sacrificial layer, substrate described in exposed portion are etched；Second interlayer is formed to be situated between
The step of matter layer includes: that after etching first sacrificial layer, the second interlayer dielectric layer is formed in the substrate of the exposing；It is formed
After second interlayer dielectric layer, the forming method further include: remaining first sacrificial layer of removal, in second interlayer
The contact openings for exposing the substrate are formed in dielectric layer；The step of contact hole plug is formed in second interlayer dielectric layer
Include: to fill conductive material into the contact openings, forms contact hole plug.
Optionally, the material of first sacrificial layer is polysilicon.
Optionally, the material of the mask layer is SiO2, SiN or TiN.
Optionally, the mask layer with a thickness ofExtremely
Optionally, the step of forming the second interlayer dielectric layer in the substrate of the exposing include: base in the exposing
Interlayer deielectric-coating is formed on bottom, the inter-level dielectric film covers at the top of the gate structure；It is formed on the inter-level dielectric film
Second sacrificial layer；Using flatening process, removal is higher than the second sacrificial layer and inter-level dielectric film at the top of the gate structure, remains
The remaining inter-level dielectric film is as the second interlayer dielectric layer.
Optionally, in the step of forming interlayer deielectric-coating in the substrate of the exposing, the thickness of the inter-level dielectric film
ForExtremely
Optionally, second sacrificial layer is tetraethyl orthosilicate layer or plasma enhanced oxidation layer.
Optionally, second sacrificial layer with a thickness ofExtremely
Optionally, the material of the contact hole plug is Co or W.
Optionally, in the step of substrate is provided, there is grid protection layer at the top of the gate structure；In the base of the exposing
In the step of forming the second interlayer dielectric layer on bottom, second interlayer dielectric layer exposes at the top of the grid protection layer.
Optionally, the material of the grid protection layer is silicon nitride.Correspondingly, the present invention also provides semiconductor structure, packet
It includes: substrate；Gate structure is located in the substrate；Interlayer dielectric layer, in the substrate that the gate structure exposes, and institute
It states interlayer dielectric layer to expose at the top of the gate structure, the material of the interlayer dielectric layer is low k dielectric materials or ultra-low k dielectric
Material；Contact hole plug is electrically connected in the interlayer dielectric layer of the gate structure two sides and with the substrate.
Optionally, the material of the interlayer dielectric layer is SiOC or SiOCH.
Optionally, the material of the contact hole plug is Co or W.
Optionally, the semiconductor structure further include: grid protection layer is located at the top of the gate structure；The interlayer
Dielectric layer exposes at the top of the grid protection layer.
Optionally, the material of the grid protection layer is silicon nitride.Compared with prior art, technical solution of the present invention has
It has the advantage that
The present invention forms the second inter-level dielectric in the substrate that gate structure exposes after removing the first interlayer dielectric layer
Layer, second interlayer dielectric layer expose at the top of the gate structure, the relative dielectric constant (k of second interlayer dielectric layer
Value) it is less than the relative dielectric constant of first interlayer dielectric layer；It is situated between by using lesser second interlayer of relative dielectric constant
Matter layer replaces first interlayer dielectric layer, so as to reduce RC retardation ratio, and then improves the performance of semiconductor devices.
In optinal plan, after removing first interlayer dielectric layer, formed in the substrate that the gate structure exposes
Before second interlayer dielectric layer, the forming method further include: form first in the substrate that the gate structure exposes and sacrifice
Layer, first sacrificial layer expose at the top of the gate structure；First sacrificial layer occupies second interlayer simultaneously and is situated between
The position of matter layer and contact hole plug, after forming second interlayer dielectric layer, remaining first sacrificial layer of removal, in institute
The contact openings for being formed in the second interlayer dielectric layer and exposing the substrate are stated, therefore eliminate the photoetching to form the contact openings
And etching technics, processing step is simplified, and advantageously reduce technology difficulty.
In optinal plan, the material of second interlayer dielectric layer is low k dielectric materials or ultra-low k dielectric material, is compared
Common inter-level dielectric layer material (such as SiO2), the dielectric constant of second interlayer dielectric layer is smaller, so as to so as to subtract
The effect of small RC retardation ratio is improved.
The present invention provides a kind of semiconductor structure, and the material of the interlayer dielectric layer of the semiconductor structure is low k dielectric material
Material or ultra-low k dielectric material, compared to common inter-level dielectric layer material (such as SiO2), Jie of interlayer dielectric layer of the present invention
Electric constant is smaller, so as to effectively reduce RC retardation ratio, and then improves the performance of semiconductor devices.
Detailed description of the invention
Fig. 1 to Figure 11 is the corresponding structural representation of each step in one embodiment of forming method of semiconductor structure of the present invention
Figure；
Figure 12 is the structural schematic diagram of one embodiment of semiconductor structure of the present invention.
Specific embodiment
It can be seen from background technology that even if contact hole plug has chosen the lesser material of resistance value, the performance of semiconductor devices is still
It is to be improved.
In order to solve the technical problem, the present invention by using lesser second interlayer dielectric layer of relative dielectric constant,
So as to reduce RC retardation ratio, and then improve the performance of semiconductor devices.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 11 is the corresponding structural representation of each step in one embodiment of forming method of semiconductor structure of the present invention
Figure.
With reference to Fig. 1, substrate (not shown) is provided, there is gate structure 100 in the substrate, the gate structure 100 reveals
There is the first interlayer dielectric layer 300, first interlayer dielectric layer 300 exposes 100 top of gate structure in substrate out.
The substrate provides technique platform for the formation of Subsequent semiconductor structure,
In the present embodiment, the substrate is used to form fin field effect pipe transistor, therefore in the step of providing substrate, institute
Stating substrate includes substrate (not shown) and discrete fin (not shown) on the substrate.Correspondingly, the grid knot
Structure 200 covers the partial sidewall and top surface of the fin across the fin.
In other embodiments, the substrate can be also used for forming planar transistor, and the substrate mutually should be plane base
Bottom.
In the present embodiment, the substrate is silicon substrate.In other embodiments, the material of the substrate can also for germanium,
SiGe, silicon carbide, GaAs or gallium indium, the substrate can also be the germanium on the silicon substrate or insulator on insulator
Substrate.
The material of the fin is identical as the material of the substrate.In the present embodiment, the material of the fin is silicon.At it
In his embodiment, the material of the fin can also be germanium, SiGe, silicon carbide, GaAs or gallium indium.
In the present embodiment, the gate structure 100 is metal gate (Metal Gate).Specifically, the gate structure 100
Metal layer 120 including work-function layer 110 and in the work-function layer 110；Between the work-function layer 110 and substrate
High-k gate dielectric layer (not shown) can also be formed with.
It should be noted that in the step of providing substrate, further includes: form side on the side wall of the gate structure 100
Wall 200；After forming the side wall 200, source and drain doping area (not shown) is formed in the substrate of 100 two sides of gate structure.
The material of the side wall 200 can be silica, silicon nitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, nitrogen oxygen
SiClx, boron nitride or boron carbonitrides, the side wall 200 can be single layer structure or laminated construction.In the present embodiment, the side wall
200 be laminated construction, and the side wall 200 includes the silicon oxide layer 210 on 100 side wall of gate structure and is located at
Silicon nitride layer 220 on 210 side wall of silicon oxide layer.
The source and drain doping area is for the source region (Source) or drain region (Drain) as semiconductor devices.Specifically, institute
Source and drain doping area is stated to be formed in the fin of 100 two sides of gate structure.
It should also be noted that, the substrate surface and 200 side wall of side wall are also formed with etching stop layer (CESL) 250,
In the etching process for being subsequently formed contact hole plug, for defining the etching work at the top of the etching stop layer 250
The stop position of skill, to avoid the problem that etching deficiency or over etching occurs in each region.In the present embodiment, the etching stopping
The material of layer 250 is silicon nitride.
First interlayer dielectric layer 300 is used to define the forming position and size of the gate structure 200.Specifically,
First interlayer dielectric layer 300 is formed on the substrate that the gate structure 100 exposes.
The material of first interlayer dielectric layer 300 is insulating dielectric materials.In the present embodiment, first inter-level dielectric
The material of layer 300 is SiO2(silica).In other embodiments, the material of first interlayer dielectric layer can also be SiN
(silicon nitride), SiON (silicon oxynitride) or SiCON (carbon silicon oxynitride).
In the present embodiment, first interlayer dielectric layer, 300 top with flushed at the top of the side wall 200.
In addition, in the present embodiment there is grid protection layer 150 at the top of the gate structure 100.
The grid protection layer 150 is used in subsequent technical process, to playing protection at the top of the gate structure 100
Effect.In the present embodiment, the material of the grid protection layer 150 is silicon nitride.
Specifically, the step of forming grid protection layer 150 includes: the gate structure of etching removal segment thickness
100, groove is formed in the side wall 200；Gate protection material is filled in the groove, and the gate protection material also covers
Cover 300 top of the first interlayer dielectric layer；Using flatening process, removal is higher than 300 top of the first interlayer dielectric layer
The gate protection material, the residue gate protection material in the groove is as grid protection layer 150.
In the present embodiment, flushed at the top of the top of the grid protection layer 150 and the side wall 200.In other embodiments
In, it may also be below at the top of the grid protection layer at the top of the side wall.
With reference to Fig. 2, first interlayer dielectric layer 300 (as shown in Figure 1) is removed.
By removing first interlayer dielectric layer 300, to be subsequently formed relative dielectric constant (k value) less than described first
Second interlayer dielectric layer of interlayer dielectric layer 300 provides spatial position.
In the present embodiment, first interlayer dielectric layer 300 is removed using wet-etching technology.First inter-level dielectric
The SiO of layer 3002, correspondingly, etching solution used by the wet-etching technology is hydrofluoric acid solution.In other embodiments
In, the technique for removing first interlayer dielectric layer can also be dry etch process.
It is formed with the grid protection layer 150 at the top of the gate structure 100, therefore is removing first inter-level dielectric
During layer 300, the grid protection layer 150 can be to playing a protective role at the top of the gate structure 100.
In conjunction with reference Fig. 3 to Fig. 9, after removing first interlayer dielectric layer 300 (as shown in Figure 1), in the grid knot
The second interlayer dielectric layer 500 (as shown in Figure 9), second interlayer dielectric layer are formed in the substrate (not shown) that structure 100 exposes
500 expose 100 top of gate structure, and the relative dielectric constant of second interlayer dielectric layer 500 is less than the first layer
Between dielectric layer 300 relative dielectric constant.
First interlayer dielectric layer is replaced by using lesser second interlayer dielectric layer 500 of relative dielectric constant
300 scheme so as to reduce RC retardation ratio, and then improves the performance of semiconductor devices.
Below with reference to attached drawing, elaborate to the step of forming the second interlayer dielectric layer 500.
In conjunction with reference Fig. 3 and Fig. 4,400 (such as Fig. 4 of the first sacrificial layer is formed in the substrate that the gate structure 100 exposes
It is shown), first sacrificial layer 400 exposes 100 top of gate structure.
First sacrificial layer 400 is that subsequent second interlayer dielectric layer that is formed by takes up space position, and described first is sacrificial
Domestic animal layer 400 can also take up space position for the subsequent contact hole plug that is formed by.
In the present embodiment, the material of first sacrificial layer 400 is polysilicon.Polycrystalline silicon material can be preferably subsequent
Flatening process or etching technics in play the role of stop-layer, and the processing compatibility of polycrystalline silicon material is preferable, can keep away
The introducing for exempting from first sacrificial layer 400 generates adverse effect to the performance of subsequent formed semiconductor structure；In addition, by adopting
Polysilicon is used as the scheme of 400 material of the first sacrificial layer, advantageously reduces subsequent removal first sacrificial layer 400
Technology difficulty.
Specifically, the step of forming the first sacrificial layer 400 includes: in the substrate that the gate structure 100 exposes
It is formed sacrificial material layer 450 (as shown in Figure 3), the sacrificial material layer 450 covers 150 top of grid protection layer；To institute
It states sacrificial material layer 450 and carries out planarization process；After the planarization process, returns and carve (Etch Back) remaining described sacrifice
Material layer 450 forms the first sacrificial layer 400.
By carrying out planarization process to the sacrificial material layer 450, to remove the sacrificial material layer of segment thickness
450, Process ba- sis is provided for the subsequent time quarter remaining sacrificial material layer 450, reduces the technology difficulty for returning carving technology；It is logical
Described time carving technology is crossed, the load effect as caused by the intensive area (Dense) and the sparse area (Iso) is avoided.That is, passing through institute
It states planarization process and returns the combination of carving technology, to improve the surface smoothness and described the of first sacrificial layer 400
The caliper uniformity of one sacrificial layer 400.
In the present embodiment, first sacrificial layer, 400 top with flushed at the top of the grid protection layer 150.
In the present embodiment, in the step of forming sacrificial material layer 450, the sacrificial material layer 450 with a thickness ofExtremelyWhile in order to make 400 top of the first sacrificial layer with flushing at the top of the grid protection layer 150,
Technology difficulty is reduced, after the planarization process, remaining 450 top of sacrificial material layer to the grid protection layer 150
The distance at top isExtremely
With reference to Fig. 5, mask layer 450 is formed on the first sacrificial layer of part 400 of 100 two sides of gate structure.
The mask layer 450 is also used to for the etch mask as the first sacrificial layer 400 described in subsequent etching described
Etching technics excessively in, to playing a protective role at the top of first sacrificial layer 400 of 450 lower section of the mask layer.
The material of the mask layer 450 can be SiO2, SiN or TiN.In the present embodiment, the material of the mask layer 450
For SiO2。
The mask layer 450 and subsequent second interlayer dielectric layer that formed are oxidation material, sacrificial when etching described first
When the mask layer 450 is retained after domestic animal layer 400, the formation of second interlayer dielectric layer is unaffected.
It should be noted that the thickness of the mask layer 450 is unsuitable too small, also should not be too large.If the mask layer 450
Thickness it is too small, during the first sacrificial layer 400 described in subsequent etching, the mask layer 450 is to first sacrificial layer
The protective effect at 400 tops is unobvious, and the etching technics is easy to make the first sacrificial layer 400 of 450 lower section of mask layer
At surface damage (Surface Damage)；If the thickness of the mask layer 450 is excessive, the waste of material is caused instead, and
Remove the mask layer 450 when, increase the difficulty of removal technique.For this purpose, in the present embodiment, the thickness of the mask layer 450
Degree isExtremely
Specifically, the step of forming mask layer 450 includes: to form mask material on first sacrificial layer 400
Layer, the mask layer also cover 250 top of etching stop layer, 150 top of 200 top of side wall and grid protection layer；
Photoresist layer (not shown) is formed on the part mask layer of 100 two sides of gate structure；With the photoresist
Layer is exposure mask, etches the mask layer, retains and is located on the first sacrificial layer of part 400 of 100 two sides of gate structure
Mask layer, as mask layer 450.
In the present embodiment, after forming the mask layer 450, retain the photoresist layer, the photoresist layer is at subsequent quarter
Etch mask is used as during losing first sacrificial layer 400.
It is exposure mask with the mask layer 450 with reference to Fig. 6, etches first sacrificial layer 400, substrate described in exposed portion.
The substrate exposed provides spatial position, and remaining first sacrificial layer to be subsequently formed the second interlayer dielectric layer
400 are taken up space position by the subsequent contact hole plug that formed.
Specifically, it is exposure mask with the photoresist layer and the mask layer 450, etches first sacrificial layer 400.
In the present embodiment, in order to retain first sacrificial layer 400 of 450 lower section of mask layer, etching described first
Technique used by sacrificial layer 400 is dry etch process, to be conducive to improve the shape of remaining first sacrificial layer 400
Looks.
It should be noted that can be covered to avoid the etching technics to described under the protective effect of the mask layer 450
First sacrificial layer 400 of 450 lower section of film layer causes surface damage, to be conducive to improve the formation matter of subsequent touch hole plug
Amount.
In the present embodiment, after etching first sacrificial layer 400, institute is removed in such a way that cineration technics or wet process remove photoresist
State photoresist layer.
In conjunction with reference Fig. 7, in the present embodiment, after removing the photoresist layer, the forming method further include: described in removal
Mask layer 450 (as shown in Figure 6).
In other embodiments, the mask layer can also be retained, and be subsequently formed second interlayer dielectric layer
The mask layer is removed in the process.
In conjunction with reference Fig. 8 and Fig. 9, after etching first sacrificial layer 400, the shape in the substrate (not shown) of the exposing
At the second interlayer dielectric layer 500 (as shown in Figure 9).
The relative dielectric constant of second interlayer dielectric layer 500 is less than first interlayer dielectric layer 300 (such as Fig. 1 institute
Show) relative dielectric constant.
Specifically, the material of second interlayer dielectric layer 500 is that (low k dielectric materials refer to opposite dielectric to low k dielectric materials
Constant is greater than or equal to 2.6, the dielectric material less than or equal to 3.9) or ultra-low k dielectric material (ultra-low k dielectric material refers to opposite Jie
Dielectric material of the electric constant less than 2.6), so as to so that the effect for reducing RC retardation ratio is improved.
In the present embodiment, the material of second interlayer dielectric layer 500 is SiOC.In other embodiments, described second
The material of interlayer dielectric layer can also be SiOCH.
Specifically, the step of forming the second interlayer dielectric layer 500 includes: to form interlayer in the substrate of the exposing
Deielectric-coating 510 (as shown in Figure 8), the inter-level dielectric film 510 cover 100 top of gate structure；In the inter-level dielectric
The second sacrificial layer 520 is formed on film 510；Using flatening process, removal is higher than second sacrifice at 100 top of gate structure
Layer 520 and inter-level dielectric film 510, the remaining inter-level dielectric film 510 are used as the second interlayer dielectric layer 500.
In the present embodiment, it is formed with grid protection layer 150 at the top of the gate structure 100, correspondingly, the inter-level dielectric
Film 510 covers 150 top of grid protection layer；In the flatening process the step of, removal is higher than the gate protection
Second sacrificial layer 520 and inter-level dielectric film 510 at 150 top of layer form the second interlayer dielectric layer 500 and expose the grid guarantor
150 top of sheath.
In the present embodiment, the flatening process is chemical mechanical milling tech.After the chemical mechanical milling tech,
Second interlayer dielectric layer, 500 top with flushed at the top of the grid protection layer 150.
It should be noted that the material of second interlayer dielectric layer 500 can be low k dielectric materials or ultra-low k dielectric
Material, during the grinding process easy to form organic residue larger to the grinding technics difficulty of second interlayer dielectric layer 500
Object, therefore by second sacrificial layer 520, it is pushed up making second interlayer dielectric layer 500 expose the grid protection layer 150
While portion, the excessive problem of 510 thickness of inter-level dielectric film is avoided the occurrence of, so as to reduce organic residue, is reduced
Grinding technics difficulty.
In the present embodiment, second sacrificial layer 520 is tetraethyl orthosilicate layer (Tetraethyl
Orthosilicate, TEOS) or plasma enhanced oxidation layer (Plasma Enhance Oxide, PEOX).
The thickness of the inter-level dielectric film 510 is unsuitable too small, also should not be too large.If the thickness of the inter-level dielectric film 510
Spend small, be easy to appear to form the too small problem of 500 thickness of the second interlayer dielectric layer, thus the inter-level dielectric film 510 to
150 top of grid protection layer is covered less；If the thickness of the inter-level dielectric film 510 is excessive, it is easy to increase grinding technics
Difficulty and organic residue.For this purpose, in the present embodiment, in the step of forming interlayer deielectric-coating 510 in the substrate of the exposing,
The inter-level dielectric film 510 with a thickness ofExtremely
The thickness of second sacrificial layer 520 is unsuitable too small, also should not be too large.If the thickness of second sacrificial layer 520
It spends small, is easily reduced the formation quality of second interlayer dielectric layer 500；If the thickness mistake of second sacrificial layer 520
Greatly, it accordingly will increase the process time, reduce grinding efficiency.For this purpose, in the present embodiment, second sacrificial layer 520 with a thickness ofExtremely
In conjunction with reference Figure 10, by Such analysis it is found that residue first sacrificial layer of 100 two sides of the gate structure
400 it is (as shown in Figure 9) take up space position for subsequent touch hole plug, therefore after forming second interlayer dielectric layer 500, institute
State forming method further include: remaining first sacrificial layer 400 of removal forms in second interlayer dielectric layer 500 and exposes
The contact openings 515 of the substrate (not shown).
The contact openings 515 provide spatial position for the formation of subsequent touch hole plug.
Specifically, with 250 top of etching stop layer for stop position, remaining first sacrificial layer of etching removal
400；After exposing the etching stop layer 250, the etching stop layer 250 is etched, exposes the substrate, is formed through described the
The contact openings 515 of two interlayer dielectric layers 500 and etching stop layer 250.
In the present embodiment, the contact openings 515 expose source and drain doping area (not shown).
In the present embodiment, using dry etch process, remaining first sacrificial layer 400 and the etching stopping are etched
Layer 250, to make the contact openings 515 that there is good pattern.
With reference to Figure 11, contact hole plug 550, the contact hole plug 550 are formed in second interlayer dielectric layer 500
It is electrically connected with the substrate.
The contact hole plug 550 is electrically connected with the realization of source and drain doping area (not shown), the contact hole plug 550
For realizing the electrical connection in semiconductor devices, it is also used to realize being electrically connected between device and device.
Specifically, the step of contact hole plug 550 are formed in second interlayer dielectric layer 500 includes: to connect to described
Conductive material is filled in touching 515 (as shown in Figure 10) of opening, the conductive material also covers second interlayer dielectric layer 500 and pushes up
Portion；Using flatening process, removal is higher than the conductive material at 150 top of grid protection layer, in the contact openings 515
The remaining conductive material is as contact hole plug 550.
In the present embodiment, the material of the contact hole plug 550 is Co, can be using chemical vapor deposition process, sputtering
Technique or electroplating technology form the contact hole plug 550.In other embodiments, the material of the contact hole plug can be with
It is W.
The resistance value of the material of the contact hole plug 550 is smaller, to be conducive to reduce RC retardation ratio.
It should be noted that before filling conductive material into the contact openings 515, the forming method further include:
Titanium layer (not shown) is formed in the side wall of the contact openings 515 and bottom；Forming titanium nitride layer on the titanium layer surface, (figure is not
Show).
The titanium layer not only the second interlayer dielectric layer with 515 side wall of the substrate of 515 bottom of contact openings and contact openings
500 have good adhesion, to be conducive to improve the formation quality of the titanium nitride layer, and can by annealing process with
Pasc reaction at the source and drain doping zone position in base material generates titanium silicide layer, to reduce the contact hole plug 550
Contact resistance.
The effect of the titanium nitride layer is: on the one hand, the titanium nitride layer can prevent in the contact openings 515
Used reactant when the contact hole plug 550 is formed to occur instead with the base material at the source and drain doping zone position
It answers, reactant used by being also possible to prevent reacts with titanium silicide layer is formed by；On the other hand, the titanium nitride layer is used
In contact openings 515 described in Yu Xiang when filling conductive material, it is glutinous in the contact openings 515 to improve the conductive material
Attached property, the titanium nitride layer can play the role of contact hole laying.
In the present embodiment, the first layer is replaced by using lesser second interlayer dielectric layer 500 of relative dielectric constant
Between dielectric layer 300 (as shown in Figure 1), so as to reduce RC retardation ratio, and then improve the performance of semiconductor devices.
In addition, first sacrificial layer 400 (as shown in Figure 4) occupies second interlayer dielectric layer 500 simultaneously and connects
The position of contact hole plug 550 passes through remaining first sacrificial layer of removal after forming second interlayer dielectric layer 500
400, so that the contact openings 515 (as shown in Figure 10) for exposing the substrate are formed in second interlayer dielectric layer 500, because
This eliminates the lithography and etching technique to form the contact openings 515, simplifies processing step, and advantageously reduces technique hardly possible
Degree.
With reference to Figure 12, the structural schematic diagram of one embodiment of semiconductor structure of the present invention is shown.Correspondingly, the present invention also mentions
For a kind of semiconductor structure.The semiconductor structure includes:
Substrate (not shown)；Gate structure 600 is located in the substrate；Interlayer dielectric layer 800 is located at the grid knot
In the substrate that structure 600 exposes, and the interlayer dielectric layer 800 exposes 600 top of gate structure, the interlayer dielectric layer
800 material is low k dielectric materials or ultra-low k dielectric material；Contact hole plug 850, positioned at 600 two sides of gate structure
It is electrically connected in interlayer dielectric layer 800 and with the substrate.
In the present embodiment, the semiconductor structure is fin field effect pipe transistor, therefore the substrate includes substrate (figure
Do not show) and discrete fin (not shown) on the substrate.Correspondingly, the gate structure 600 is across the fin,
And the partial sidewall and top surface of the covering fin.
In other embodiments, the semiconductor structure can also be planar transistor, and the substrate mutually should be plane base
Bottom.
In the present embodiment, the substrate is silicon substrate.In other embodiments, the material of the substrate can also for germanium,
SiGe, silicon carbide, GaAs or gallium indium, the substrate can also be the germanium on the silicon substrate or insulator on insulator
Substrate.
The material of the fin is identical as the material of the substrate.In the present embodiment, the material of the fin is silicon.At it
In his embodiment, the material of the fin can also be germanium, SiGe, silicon carbide, GaAs or gallium indium.
In the present embodiment, the gate structure 600 is metal gate (Metal Gate).Specifically, the gate structure 600
Metal layer 620 including work-function layer 610 and in the work-function layer 610；Between the work-function layer 610 and substrate
High-k gate dielectric layer (not shown) can also be formed with.
It should be noted that the semiconductor structure further include: side wall 700, positioned at the side wall of the gate structure 600
On；Source and drain doping area (not shown), in the substrate of 600 two sides of gate structure；Etching stop layer (CESL) 750, position
In on 200 side wall of the part substrate surface and the side wall.
The material of the side wall 700 can be silica, silicon nitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, nitrogen oxygen
SiClx, boron nitride or boron carbonitrides, the side wall 700 can be single layer structure or laminated construction.In the present embodiment, the side wall
700 be laminated construction, and the side wall 700 includes the silicon oxide layer 710 on 600 side wall of gate structure and is located at
Silicon nitride layer 720 on 710 side wall of silicon oxide layer.
The source and drain doping area is for the source region (Source) or drain region (Drain) as semiconductor devices.Specifically, institute
Source and drain doping area is stated to be located in the fin of 600 two sides of gate structure.
During the formation process of the contact hole plug 850, for defining etching at the top of the etching stop layer 750
The stop position of technique, to avoid the problem that etching deficiency or over etching occurs in each region.In the present embodiment, the etch-stop
Only the material of layer 750 is silicon nitride.
It should be noted the semiconductor structure further include: grid protection layer 650 is located at the gate structure 600
Top.
The grid protection layer 650 is used for during the formation process of the semiconductor structure, to the gate structure
600 tops play a protective role.In the present embodiment, the material of the grid protection layer 650 is silicon nitride.
In the present embodiment, the side wall 700 is located on 600 side wall of gate structure and 650 side wall of grid protection layer, institute
It states and is flushed at the top of the top and the side wall 700 of grid protection layer 650.In other embodiments, at the top of the grid protection layer
It may also be below at the top of the side wall.
The interlayer dielectric layer 800 is used to define the forming position and size of the gate structure 600.In the present embodiment,
800 top of the interlayer dielectric layer with flushed at the top of the side wall 700.
The material of the interlayer dielectric layer 800 is low k dielectric materials or ultra-low k dielectric material, is situated between compared to common interlayer
Matter layer material (such as SiO2), the dielectric constant of the interlayer dielectric layer 800 is smaller, so as to effectively reduce RC retardation ratio, into
And improve the performance of semiconductor devices.
In the present embodiment, the material of the interlayer dielectric layer 800 is SiOC.In other embodiments, the inter-level dielectric
The material of layer can also be SiOCH.
The contact hole plug 850 for realizing the electrical connection in semiconductor devices, be also used to realize device and device it
Between electrical connection.
Specifically, the contact hole plug 850 through the interlayer dielectric layer 800 and etching stop layer 750 and with it is described
Source and drain doping area (not shown) realizes electrical connection.
In the present embodiment, the material of the contact hole plug 850 is Co.In other embodiments, the contact hole plug
Material can also be W.
The resistance value of the material of the contact hole plug 850 is smaller, to be conducive to reduce RC retardation ratio.
It should be noted that the semiconductor structure further include: titanium layer is located at the contact hole plug 850 and the layer
Between between dielectric layer 800；Titanium silicide layer, between the contact hole plug 850 and the substrate；Titanium nitride layer is located at institute
It states between contact hole plug 850 and the titanium layer and between the contact hole plug 850 and the titanium silicide layer.
The titanium layer and the substrate, second interlayer dielectric layer 800 have good adhesion, to be conducive to mention
The formation quality of the high titanium nitride layer；The titanium silicide layer is by the titanium layer and the source and drain doping zone position base material
In pasc reaction generate, the titanium silicide layer for reducing the contact hole plug 850 contact resistance.
The effect of the titanium nitride layer is: on the one hand, the titanium nitride layer can prevent from forming the contact hole plug
Used reactant reacts with the base material at the source and drain doping zone position when 850, is also possible to prevent to be used
Reactant react with the titanium silicide layer；On the other hand, the titanium nitride layer is used to form the contact hole plug
When 850, the adhesion of 850 material of contact hole plug is improved, the titanium nitride layer can play the work of contact hole laying
With.
The material of the interlayer dielectric layer 800 of semiconductor structure of the present invention is low k dielectric materials or ultra-low k dielectric material
Material, compared to common inter-level dielectric layer material (such as SiO2), the dielectric constant of interlayer dielectric layer 800 of the present invention is smaller,
So as to effectively reduce RC retardation ratio, and then improve the performance of semiconductor devices.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, there is gate structure in the substrate, there is the first inter-level dielectric in the substrate that the gate structure exposes
Layer, first interlayer dielectric layer expose at the top of the gate structure；
Remove first interlayer dielectric layer；
After removing first interlayer dielectric layer, the second interlayer dielectric layer, institute are formed in the substrate that the gate structure exposes
It states the second interlayer dielectric layer to expose at the top of the gate structure, the relative dielectric constant of second interlayer dielectric layer is less than described
The relative dielectric constant of first interlayer dielectric layer；
Contact hole plug is formed in second interlayer dielectric layer, the contact hole plug is electrically connected with the substrate.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of first interlayer dielectric layer
Material is SiO2。
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of second interlayer dielectric layer
Material is low k dielectric materials or ultra-low k dielectric material.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of second interlayer dielectric layer
Material is SiOC or SiOCH.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that removal first interlayer dielectric layer
Afterwards, before forming the second interlayer dielectric layer in the substrate that the gate structure exposes, the forming method further include: described
The first sacrificial layer is formed in the substrate that gate structure exposes, first sacrificial layer exposes at the top of the gate structure；Described
Mask layer is formed on the first sacrificial layer of part of gate structure two sides；Using the mask layer as exposure mask, etches described first and sacrifice
Layer, substrate described in exposed portion；
The step of forming second interlayer dielectric layer includes: after etching first sacrificial layer, in the substrate of the exposing
Form the second interlayer dielectric layer；
After forming second interlayer dielectric layer, the forming method further include: remaining first sacrificial layer of removal, described
The contact openings for exposing the substrate are formed in second interlayer dielectric layer；
The step of contact hole plug is formed in second interlayer dielectric layer includes: to fill conduction material into the contact openings
Material forms contact hole plug.
6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the material of first sacrificial layer is
Polysilicon.
7. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the material of the mask layer is SiO2、
SiN or TiN.
8. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the mask layer with a thickness of
Extremely
9. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that formed in the substrate of the exposing
The step of second interlayer dielectric layer includes: the formation interlayer deielectric-coating in the substrate of the exposing, the inter-level dielectric film covering
At the top of the gate structure；
The second sacrificial layer is formed on the inter-level dielectric film；
Using flatening process, removal is higher than the second sacrificial layer and inter-level dielectric film at the top of the gate structure, described in residue
Inter-level dielectric film is as the second interlayer dielectric layer.
10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the shape in the substrate of the exposing
Between stratification the step of deielectric-coating in, the inter-level dielectric film with a thickness ofExtremely
11. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that second sacrificial layer is former silicon
Sour tetrem ester layer or plasma enhanced oxidation layer.
12. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the thickness of second sacrificial layer
ForExtremely
13. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the contact hole plug
For Co or W.
14. the forming method of semiconductor structure as described in claim 1, which is characterized in that described in the step of providing substrate
There is grid protection layer at the top of gate structure；
In the step of forming the second interlayer dielectric layer in the substrate of the exposing, second interlayer dielectric layer exposes the grid
At the top of the protective layer of pole.
15. the forming method of semiconductor structure as claimed in claim 14, which is characterized in that the material of the grid protection layer
For silicon nitride.
16. a kind of semiconductor structure characterized by comprising
Substrate；
Gate structure is located in the substrate；
Interlayer dielectric layer, in the substrate that the gate structure exposes, and the interlayer dielectric layer exposes the gate structure
Top, the material of the interlayer dielectric layer are low k dielectric materials or ultra-low k dielectric material；
Contact hole plug is electrically connected in the interlayer dielectric layer of the gate structure two sides and with the substrate.
17. semiconductor structure as claimed in claim 16, which is characterized in that the material of the interlayer dielectric layer be SiOC or
SiOCH。
18. semiconductor structure as claimed in claim 16, which is characterized in that the material of the contact hole plug is Co or W.
19. semiconductor structure as claimed in claim 16, which is characterized in that the semiconductor structure further include: gate protection
Layer is located at the top of the gate structure；
The interlayer dielectric layer exposes at the top of the grid protection layer.
20. semiconductor structure as claimed in claim 19, which is characterized in that the material of the grid protection layer is silicon nitride.
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