CN108962817B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN108962817B
CN108962817B CN201710363698.7A CN201710363698A CN108962817B CN 108962817 B CN108962817 B CN 108962817B CN 201710363698 A CN201710363698 A CN 201710363698A CN 108962817 B CN108962817 B CN 108962817B
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layer
interlayer dielectric
dielectric layer
substrate
forming
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CN108962817A (en
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蒋莉
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein a grid structure is arranged on the substrate, a first interlayer dielectric layer is arranged on the substrate exposed out of the grid structure, and the top of the grid structure is exposed out of the first interlayer dielectric layer; removing the first interlayer dielectric layer; after removing the first interlayer dielectric layer, forming a second interlayer dielectric layer on the substrate exposed out of the grid structure, wherein the second interlayer dielectric layer is exposed out of the top of the grid structure, and the relative dielectric constant of the second interlayer dielectric layer is smaller than that of the first interlayer dielectric layer; and forming a contact hole plug in the second interlayer dielectric layer, wherein the contact hole plug is electrically connected with the substrate. According to the invention, the scheme that the second interlayer dielectric layer with smaller relative dielectric constant is adopted to replace the first interlayer dielectric layer is adopted, so that the RC delay can be reduced, and the performance of the semiconductor device is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In a semiconductor device, reducing an RC delay (Resistance capacitance delay) can improve the performance of the semiconductor device. With the development of semiconductor technology and the advance of technology nodes, the functions of devices are continuously powerful, the integration level of the devices is higher and higher, and the feature size (CD) of the devices is smaller and smaller, and accordingly, further reduction of RC delay becomes one of important measures for improving the performance of semiconductor devices.
An interconnect structure of a semiconductor device includes a contact hole plug. At present, in order to reduce RC delay, the material used for the contact plug is usually a material with a smaller resistance value, such as cobalt or tungsten, so as to improve the performance of the semiconductor device.
However, even if the contact plug is made of a material having a small resistance, the performance of the semiconductor device is still to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can optimize the electrical performance of a semiconductor device.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a grid structure is arranged on the substrate, a first interlayer dielectric layer is arranged on the substrate exposed out of the grid structure, and the first interlayer dielectric layer is exposed out of the top of the grid structure; removing the first interlayer dielectric layer; after removing the first interlayer dielectric layer, forming a second interlayer dielectric layer on the substrate exposed out of the grid structure, wherein the second interlayer dielectric layer is exposed out of the top of the grid structure, and the relative dielectric constant of the second interlayer dielectric layer is smaller than that of the first interlayer dielectric layer; and forming a contact hole plug in the second interlayer dielectric layer, wherein the contact hole plug is electrically connected with the substrate.
Optionally, the first interlayer dielectric layer is made of SiO2。
Optionally, the second interlayer dielectric layer is made of a low-k dielectric material or an ultra-low-k dielectric material.
Optionally, the second interlayer dielectric layer is made of SiOC or SiOCH.
Optionally, after removing the first interlayer dielectric layer, before forming a second interlayer dielectric layer on the substrate exposed by the gate structure, the forming method further includes: forming a first sacrificial layer on the substrate exposed out of the grid structure, wherein the first sacrificial layer exposes out of the top of the grid structure; forming a mask layer on partial first sacrificial layers on two sides of the grid structure; etching the first sacrificial layer by taking the mask layer as a mask to expose part of the substrate; the step of forming the second interlayer dielectric layer comprises the following steps: after the first sacrificial layer is etched, a second interlayer dielectric layer is formed on the exposed substrate; after the second interlayer dielectric layer is formed, the forming method further comprises the following steps: removing the rest of the first sacrificial layer, and forming a contact opening exposing the substrate in the second interlayer dielectric layer; the step of forming a contact hole plug in the second interlayer dielectric layer comprises the following steps: and filling a conductive material into the contact opening to form a contact hole plug.
Optionally, the material of the first sacrificial layer is polysilicon.
Optionally, the maskThe material of the layer is SiO2SiN or TiN.
Optionally, the thickness of the mask layer is
Figure BDA0001300953990000025
To
Figure BDA0001300953990000026
Optionally, the step of forming a second interlayer dielectric layer on the exposed substrate includes: forming an interlayer dielectric film on the exposed substrate, wherein the interlayer dielectric film covers the top of the grid structure; forming a second sacrificial layer on the interlayer dielectric film; and removing the second sacrificial layer and the interlayer dielectric film which are higher than the top of the grid structure by adopting a planarization process, and taking the residual interlayer dielectric film as a second interlayer dielectric layer.
Optionally, in the step of forming the interlayer dielectric film on the exposed substrate, the thickness of the interlayer dielectric film is
Figure BDA0001300953990000021
To
Figure BDA0001300953990000022
Optionally, the second sacrificial layer is a tetraethoxysilane layer or a plasma enhanced oxide layer.
Optionally, the thickness of the second sacrificial layer is
Figure BDA0001300953990000023
To
Figure BDA0001300953990000024
Optionally, the material of the contact hole plug is Co or W.
Optionally, in the step of providing the substrate, a gate protection layer is disposed on the top of the gate structure; and in the step of forming a second interlayer dielectric layer on the exposed substrate, the second interlayer dielectric layer exposes the top of the grid electrode protection layer.
Optionally, the gate protection layer is made of silicon nitride. Accordingly, the present invention also provides a semiconductor structure comprising: a substrate; the grid structure is positioned on the substrate; the interlayer dielectric layer is positioned on the substrate exposed out of the grid structure, is exposed out of the top of the grid structure, and is made of a low-k dielectric material or an ultra-low-k dielectric material; and the contact hole plug is positioned in the interlayer dielectric layers at two sides of the grid structure and is electrically connected with the substrate.
Optionally, the interlayer dielectric layer is made of SiOC or SiOCH.
Optionally, the material of the contact hole plug is Co or W.
Optionally, the semiconductor structure further includes: the grid electrode protection layer is positioned at the top of the grid electrode structure; the interlayer dielectric layer is exposed out of the top of the grid electrode protection layer.
Optionally, the gate protection layer is made of silicon nitride. Compared with the prior art, the technical scheme of the invention has the following advantages:
after removing the first interlayer dielectric layer, forming a second interlayer dielectric layer on the substrate with the exposed grid structure, wherein the second interlayer dielectric layer is exposed out of the top of the grid structure, and the relative dielectric constant (k value) of the second interlayer dielectric layer is smaller than that of the first interlayer dielectric layer; the second interlayer dielectric layer with smaller relative dielectric constant is adopted to replace the first interlayer dielectric layer, so that RC delay can be reduced, and the performance of the semiconductor device is improved.
In an alternative, after removing the first interlayer dielectric layer, before forming a second interlayer dielectric layer on the substrate exposed by the gate structure, the forming method further includes: forming a first sacrificial layer on the substrate exposed out of the grid structure, wherein the first sacrificial layer exposes out of the top of the grid structure; the first sacrificial layer occupies the positions of the second interlayer dielectric layer and the contact hole plug at the same time, after the second interlayer dielectric layer is formed, the residual first sacrificial layer is removed, and a contact opening exposing the substrate is formed in the second interlayer dielectric layer, so that photoetching and etching processes for forming the contact opening are omitted, the process steps are simplified, and the process difficulty is reduced.
In an alternative, the material of the second interlayer dielectric layer is a low-k dielectric material or an ultra-low-k dielectric material, compared with a common interlayer dielectric layer material (such as SiO)2) And the dielectric constant of the second interlayer dielectric layer is smaller, so that the effect of reducing RC delay can be improved.
The invention provides a semiconductor structure, wherein the material of an interlayer dielectric layer of the semiconductor structure is a low-k dielectric material or an ultra-low-k dielectric material, and is compared with a common interlayer dielectric layer material (such as SiO)2) The dielectric constant of the interlayer dielectric layer is smaller, so that RC delay can be effectively reduced, and the performance of a semiconductor device is improved.
Drawings
Fig. 1 to 11 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the present invention;
FIG. 12 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As known from the background art, even if the contact plug is made of a material with a small resistance, the performance of the semiconductor device is still to be improved.
In order to solve the technical problem, the second interlayer dielectric layer with a smaller relative dielectric constant is adopted, so that the RC delay can be reduced, and the performance of the semiconductor device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 11 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1, a substrate (not shown) is provided, the substrate having a gate structure 100 thereon, the substrate on which the gate structure 100 is exposed having a first interlayer dielectric layer 300 thereon, and the first interlayer dielectric layer 300 is exposed on the top of the gate structure 100.
The substrate provides a process platform for the formation of subsequent semiconductor structures,
in this embodiment, the base is used to form a finfet transistor, and thus in the step of providing the base, the base includes a substrate (not shown) and a discrete fin (not shown) on the substrate. Accordingly, the gate structure 200 spans the fin and covers a portion of the sidewalls and the top surface of the fin.
In other embodiments, the substrate may also be used to form a planar transistor, the substrate being correspondingly a planar substrate.
In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The material of the fin portion is the same as that of the substrate. In this embodiment, the fin portion is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the Gate structure 100 is a Metal Gate (Metal Gate). Specifically, the gate structure 100 includes a work function layer 110 and a metal layer 120 on the work function layer 110; a high-k gate dielectric layer (not shown) may also be formed between the work function layer 110 and the substrate.
It should be noted that, in the step of providing a substrate, the method further includes: forming a side wall 200 on the side wall of the gate structure 100; after the side walls 200 are formed, source-drain doped regions (not shown) are formed in the substrate on both sides of the gate structure 100.
The material of the sidewall 200 may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 200 may be a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacer 200 is a stacked structure, and the sidewall spacer 200 includes a silicon oxide layer 210 located on a sidewall of the gate structure 100, and a silicon nitride layer 220 located on a sidewall of the silicon oxide layer 210.
The Source-Drain doped region is used as a Source region (Source) or a Drain region (Drain) of the semiconductor device. Specifically, the source-drain doped regions are formed in the fin portions on both sides of the gate structure 100.
It should be further noted that an etching stop layer (CESL)250 is further formed on the surface of the substrate and the side wall of the side wall 200, and in the subsequent etching process for forming the contact hole plug, the top of the etching stop layer 250 is used for defining the stop position of the etching process, so that the problem of insufficient etching or over etching in each region is avoided. In this embodiment, the material of the etch stop layer 250 is silicon nitride.
The first interlayer dielectric layer 300 is used to define the formation position and size of the gate structure 200. Specifically, the first interlayer dielectric layer 300 is formed on the substrate where the gate structure 100 is exposed.
The first interlayer dielectric layer 300 is made of an insulating dielectric material. In this embodiment, the first interlayer dielectric layer 300 is made of SiO2(silicon oxide). In other embodiments, the material of the first interlayer dielectric layer may also be SiN (silicon nitride), SiON (silicon oxynitride) or SiCON (silicon oxycarbonitride).
In this embodiment, the top of the first interlayer dielectric layer 300 is flush with the top of the sidewall spacer 200.
In addition, in the present embodiment, the gate structure 100 has a gate protection layer 150 on top.
The gate protection layer 150 is used to protect the top of the gate structure 100 during subsequent processes. In this embodiment, the gate protection layer 150 is made of silicon nitride.
Specifically, the step of forming the gate protection layer 150 includes: etching to remove a part of the thickness of the gate structure 100, and forming a groove in the sidewall spacer 200; filling a grid electrode protection material in the groove, wherein the grid electrode protection material also covers the top of the first interlayer dielectric layer 300; and removing the gate protection material higher than the top of the first interlayer dielectric layer 300 by using a planarization process, wherein the rest of the gate protection material in the groove is used as a gate protection layer 150.
In this embodiment, the top of the gate protection layer 150 is flush with the top of the sidewall spacer 200. In other embodiments, the top of the gate protection layer may be lower than the top of the sidewall.
Referring to fig. 2, the first interlayer dielectric layer 300 (shown in fig. 1) is removed.
By removing the first interlayer dielectric layer 300, a spatial position is provided for the subsequent formation of a second interlayer dielectric layer having a relative dielectric constant (k value) smaller than that of the first interlayer dielectric layer 300.
In this embodiment, the first interlayer dielectric layer 300 is removed by a wet etching process. SiO of the first interlayer dielectric layer 3002Correspondingly, the etching solution adopted by the wet etching process is a hydrofluoric acid solution. In other embodiments, the process of removing the first interlayer dielectric layer may also be a dry etching process.
The gate protection layer 150 is formed on the top of the gate structure 100, so that the gate protection layer 150 can protect the top of the gate structure 100 during the process of removing the first interlayer dielectric layer 300.
Referring to fig. 3 to 9, after removing the first interlayer dielectric layer 300 (shown in fig. 1), a second interlayer dielectric layer 500 (shown in fig. 9) is formed on the substrate (not shown) exposed by the gate structure 100, wherein the second interlayer dielectric layer 500 is exposed at the top of the gate structure 100, and the relative dielectric constant of the second interlayer dielectric layer 500 is smaller than that of the first interlayer dielectric layer 300.
By adopting the scheme that the second interlayer dielectric layer 500 with a smaller relative dielectric constant is adopted to replace the first interlayer dielectric layer 300, the RC delay can be reduced, and the performance of the semiconductor device is improved.
The step of forming the second interlayer dielectric layer 500 will be described in detail below with reference to the accompanying drawings.
Referring to fig. 3 and 4 in combination, a first sacrificial layer 400 is formed on the substrate where the gate structure 100 is exposed (as shown in fig. 4), and the first sacrificial layer 400 exposes the top of the gate structure 100.
The first sacrificial layer 400 occupies a space position for a subsequently formed second interlayer dielectric layer, and the first sacrificial layer 400 can also occupy a space position for a subsequently formed contact hole plug.
In this embodiment, the material of the first sacrificial layer 400 is polysilicon. The polysilicon material can better play a role of a stop layer in a subsequent planarization process or an etching process, has better process compatibility, and can avoid the introduction of the first sacrificial layer 400 from generating adverse effects on the performance of a subsequently formed semiconductor structure; in addition, the scheme of using polysilicon as the material of the first sacrificial layer 400 is beneficial to reducing the process difficulty of subsequently removing the first sacrificial layer 400.
Specifically, the step of forming the first sacrificial layer 400 includes: forming a sacrificial material layer 450 (as shown in fig. 3) on the substrate exposed by the gate structure 100, wherein the sacrificial material layer 450 covers the top of the gate protection layer 150; planarizing the sacrificial material layer 450; after the planarization process, the sacrificial material layer 450 is etched Back (Etch Back) to form a first sacrificial layer 400.
The sacrificial material layer 450 is subjected to planarization treatment to remove a part of the thickness of the sacrificial material layer 450, so that a process foundation is provided for the subsequent back etching of the residual sacrificial material layer 450, and the process difficulty of the back etching process is reduced; by the etch-back process, loading effects caused by Dense (Dense) and sparse (Iso) regions are avoided. That is, the planarization process and the etch-back process are combined to improve the surface flatness of the first sacrificial layer 400 and the thickness uniformity of the first sacrificial layer 400.
In this embodiment, the top of the first sacrificial layer 400 is flush with the top of the gate protection layer 150.
In this embodiment, in the step of forming the sacrificial material layer 450, the thickness of the sacrificial material layer 450 is
Figure BDA0001300953990000071
To
Figure BDA0001300953990000074
In order to reduce the process difficulty while the top of the first sacrificial layer 400 is flush with the top of the gate protection layer 150, the distance from the top of the sacrificial material layer 450 to the top of the gate protection layer 150 after the planarization process is set to
Figure BDA0001300953990000072
To
Figure BDA0001300953990000073
Referring to fig. 5, a mask layer 450 is formed on portions of the first sacrificial layer 400 at both sides of the gate structure 100.
The mask layer 450 is used as an etching mask for subsequent etching of the first sacrificial layer 400, and is also used for protecting the top of the first sacrificial layer 400 below the mask layer 450 during the etching process.
The material of the mask layer 450 may be SiO2SiN or TiN. In this embodiment, the material of the mask layer 450 is SiO2。
The mask layer 450 and a subsequently formed second interlayer dielectric layer are both made of an oxide material, and when the mask layer 450 is retained after the first sacrificial layer 400 is etched, the formation of the second interlayer dielectric layer is not affected.
It should be noted that the thickness of the mask layer 450 is not too small or too large. If the thickness of the mask layer 450 is too small, the mask layer 450 has an insignificant protective effect on the top of the first sacrificial layer 400 during the subsequent etching process of the first sacrificial layer 400, and the etching process is prone to cause Surface Damage (Surface Damage) to the first sacrificial layer 400 below the mask layer 450; if the thickness of the mask layer 450 is too large, material is wasted, and the difficulty of the removal process is increased when the mask layer 450 is removed. To this end, in this embodiment, the maskThe thickness of layer 450 is
Figure BDA0001300953990000081
To
Figure BDA0001300953990000082
Specifically, the step of forming the mask layer 450 includes: forming a mask material layer on the first sacrificial layer 400, wherein the mask material layer also covers the top of the etching stop layer 250, the top of the sidewall spacers 200 and the top of the gate protection layer 150; forming a photoresist layer (not shown) on portions of the mask material layer on both sides of the gate structure 100; and etching the mask material layer by taking the photoresist layer as a mask, and reserving the mask material layer on the partial first sacrificial layer 400 positioned at the two sides of the gate structure 100 as a mask layer 450.
In this embodiment, after the mask layer 450 is formed, the photoresist layer is retained, and the photoresist layer serves as an etching mask in the subsequent etching process of the first sacrificial layer 400.
Referring to fig. 6, the mask layer 450 is used as a mask to etch the first sacrificial layer 400, so as to expose a portion of the substrate.
The exposed substrate provides a space position for the subsequent formation of a second interlayer dielectric layer, and the remaining first sacrificial layer 400 occupies the space position for the subsequent formation of a contact hole plug.
Specifically, the first sacrificial layer 400 is etched by using the photoresist layer and the mask layer 450 as masks.
In this embodiment, in order to retain the first sacrificial layer 400 below the mask layer 450, a dry etching process is used as a process for etching the first sacrificial layer 400, so as to improve the appearance of the remaining first sacrificial layer 400.
It should be noted that, under the protection of the mask layer 450, the surface damage of the first sacrificial layer 400 below the mask layer 450 caused by the etching process can be avoided, so that the formation quality of the subsequent contact hole plug can be improved.
In this embodiment, after the first sacrificial layer 400 is etched, the photoresist layer is removed by an ashing process or a wet photoresist removal method.
With reference to fig. 7, in this embodiment, after removing the photoresist layer, the forming method further includes: the masking layer 450 is removed (as shown in fig. 6).
In other embodiments, the mask layer may be further retained, and the mask layer may be removed in a subsequent process of forming the second interlayer dielectric layer.
Referring to fig. 8 and 9 in combination, after the first sacrificial layer 400 is etched, a second interlayer dielectric layer 500 (shown in fig. 9) is formed on the exposed substrate (not shown).
The relative dielectric constant of the second interlayer dielectric layer 500 is less than the relative dielectric constant of the first interlayer dielectric layer 300 (shown in fig. 1).
Specifically, the material of the second interlayer dielectric layer 500 is a low-k dielectric material (the low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (the ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), so that the effect of reducing the RC delay can be improved.
In this embodiment, the second interlayer dielectric layer 500 is made of SiOC. In other embodiments, the material of the second interlayer dielectric layer may also be SiOCH.
Specifically, the step of forming the second interlayer dielectric layer 500 includes: forming an interlayer dielectric film 510 on the exposed substrate (as shown in fig. 8), wherein the interlayer dielectric film 510 covers the top of the gate structure 100; forming a second sacrificial layer 520 on the interlayer dielectric film 510; and removing the second sacrificial layer 520 and the interlayer dielectric film 510 which are higher than the top of the gate structure 100 by adopting a planarization process, and taking the rest of the interlayer dielectric film 510 as a second interlayer dielectric layer 500.
In this embodiment, a gate protection layer 150 is formed on the top of the gate structure 100, and correspondingly, the interlayer dielectric film 510 covers the top of the gate protection layer 150; in the step of the planarization process, the second sacrificial layer 520 and the interlayer dielectric film 510 higher than the top of the gate protection layer 150 are removed, and the formed second interlayer dielectric layer 500 exposes the top of the gate protection layer 150.
In this embodiment, the planarization process is a chemical mechanical polishing process. After the chemical mechanical polishing process, the top of the second interlayer dielectric layer 500 is flush with the top of the gate protection layer 150.
It should be noted that the material of the second interlayer dielectric layer 500 may be a low-k dielectric material or an ultra-low-k dielectric material, the difficulty of the grinding process for the second interlayer dielectric layer 500 is high, and organic residues are easily formed in the grinding process, so that the problem of the overlarge thickness of the interlayer dielectric film 510 is avoided while the second interlayer dielectric layer 500 is exposed out of the top of the gate protection layer 150 through the second sacrificial layer 520, so that the organic residues can be reduced, and the difficulty of the grinding process is reduced.
In this embodiment, the second sacrificial layer 520 is a Tetra Ethyl Ortho Silicate (TEOS) layer or a Plasma Enhanced Oxide (PEOX) layer.
The thickness of the interlayer dielectric film 510 should not be too small or too large. If the thickness of the interlayer dielectric film 510 is too small, the problem that the thickness of the formed second interlayer dielectric layer 500 is too small is likely to occur, so that the interlayer dielectric film 510 at least covers the top of the gate protection layer 150; if the thickness of the interlayer dielectric film 510 is too large, the difficulty of the grinding process and organic residue are easily increased. For this reason, in the present embodiment, in the step of forming the interlayer dielectric film 510 on the exposed substrate, the thickness of the interlayer dielectric film 510 is
Figure BDA0001300953990000101
To
Figure BDA0001300953990000102
The thickness of the second sacrificial layer 520 should not be too small, nor too large. If the thickness of the second sacrificial layer 520 is too small, the formation quality of the second interlayer dielectric layer 500 is easily reduced; if said first isThe thickness of the two sacrificial layers 520 is too large, which increases the process time and decreases the polishing efficiency. For this purpose, in this embodiment, the thickness of the second sacrificial layer 520 is
Figure BDA0001300953990000103
To
Figure BDA0001300953990000104
Referring to fig. 10, from the foregoing analysis, the remaining first sacrificial layers 400 (as shown in fig. 9) on both sides of the gate structure 100 occupy the space for the subsequent contact hole plugs, and thus after the second interlayer dielectric layer 500 is formed, the forming method further includes: the remaining first sacrificial layer 400 is removed, and a contact opening 515 exposing the substrate (not shown) is formed in the second interlayer dielectric layer 500.
The contact opening 515 provides a spatial location for subsequent contact hole plug formation.
Specifically, with the top of the etching stop layer 250 as a stop position, the remaining first sacrificial layer 400 is removed by etching; after the etching stop layer 250 is exposed, the etching stop layer 250 is etched to expose the substrate, and a contact opening 515 penetrating through the second interlayer dielectric layer 500 and the etching stop layer 250 is formed.
In this embodiment, the contact opening 515 exposes the source/drain doped region (not shown).
In this embodiment, a dry etching process is adopted to etch the remaining first sacrificial layer 400 and the etching stop layer 250, so that the contact opening 515 has a good appearance.
Referring to fig. 11, a contact hole plug 550 is formed in the second interlayer dielectric layer 500, and the contact hole plug 550 is electrically connected to the substrate.
The contact hole plug 550 is electrically connected to the source/drain doped region (not shown), and the contact hole plug 550 is used for realizing electrical connection in a semiconductor device and also for realizing electrical connection between devices.
Specifically, the step of forming the contact hole plug 550 in the second interlayer dielectric layer 500 includes: filling the contact opening 515 (shown in fig. 10) with a conductive material, wherein the conductive material also covers the top of the second interlayer dielectric layer 500; the conductive material above the top of the gate protection layer 150 is removed by a planarization process, and the remaining conductive material in the contact opening 515 serves as a contact hole plug 550.
In this embodiment, the contact plug 550 is made of Co, and the contact plug 550 may be formed by a chemical vapor deposition process, a sputtering process, or an electroplating process. In other embodiments, the material of the contact hole plug may also be W.
The resistance value of the material of the contact hole plug 550 is small, thereby contributing to reduction of RC delay.
Before filling the contact opening 515 with the conductive material, the forming method further includes: forming a titanium layer (not shown) on the sidewalls and bottom of the contact opening 515; a titanium nitride layer (not shown) is formed on the surface of the titanium layer.
The titanium layer has good adhesion with the substrate at the bottom of the contact opening 515 and the second interlayer dielectric layer 500 on the side wall of the contact opening 515, so that the formation quality of the titanium nitride layer is improved, and the titanium nitride layer can react with silicon in the substrate material at the position of the source-drain doped region through an annealing process to generate a titanium silicide layer so as to reduce the contact resistance of the contact hole plug 550.
The titanium nitride layer functions as: on one hand, the titanium nitride layer can prevent a reactant used in forming the contact hole plug 550 in the contact opening 515 from reacting with the substrate material at the source/drain doping region, and also can prevent a reactant used from reacting with the formed titanium silicide layer; on the other hand, the titanium nitride layer is used to improve adhesion of a conductive material in the contact opening 515 when the contact opening 515 is filled with the conductive material, and the titanium nitride layer may function as a contact hole liner layer.
In this embodiment, the second interlayer dielectric layer 500 with a smaller relative dielectric constant is used to replace the first interlayer dielectric layer 300 (as shown in fig. 1), so that the RC delay can be reduced, and the performance of the semiconductor device can be improved.
In addition, the first sacrificial layer 400 (as shown in fig. 4) occupies the positions of the second interlayer dielectric layer 500 and the contact hole plug 550 at the same time, and after the second interlayer dielectric layer 500 is formed, the contact opening 515 (as shown in fig. 10) exposing the substrate is formed in the second interlayer dielectric layer 500 by removing the remaining first sacrificial layer 400, so that the photolithography and etching processes for forming the contact opening 515 are omitted, the process steps are simplified, and the process difficulty is reduced.
Referring to fig. 12, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown. Correspondingly, the invention also provides a semiconductor structure. The semiconductor structure includes:
a substrate (not shown); a gate structure 600 on the substrate; the interlayer dielectric layer 800 is positioned on the substrate where the gate structure 600 is exposed, the interlayer dielectric layer 800 is exposed out of the top of the gate structure 600, and the interlayer dielectric layer 800 is made of a low-k dielectric material or an ultra-low-k dielectric material; and a contact hole plug 850 positioned in the interlayer dielectric layer 800 at both sides of the gate structure 600 and electrically connected to the substrate.
In this embodiment, the semiconductor structure is a finfet transistor, and thus the substrate includes a substrate (not shown) and discrete fins (not shown) on the substrate. Accordingly, the gate structure 600 spans the fin and covers a portion of the sidewalls and the top surface of the fin.
In other embodiments, the semiconductor structure may also be a planar transistor, and the substrate is correspondingly a planar substrate.
In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The material of the fin portion is the same as that of the substrate. In this embodiment, the fin portion is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the Gate structure 600 is a Metal Gate (Metal Gate). Specifically, the gate structure 600 includes a work function layer 610 and a metal layer 620 on the work function layer 610; a high-k gate dielectric layer (not shown) may also be formed between the work function layer 610 and the substrate.
In addition, the semiconductor structure further includes: a sidewall spacer 700 on a sidewall of the gate structure 600; source and drain doped regions (not shown) in the substrate at both sides of the gate structure 600; and an etch stop layer (CESL)750 located on a portion of the substrate surface and the sidewall of the sidewall spacer 200.
The material of the sidewall 700 may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 700 may be a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacer 700 is a stacked structure, and the sidewall spacer 700 includes a silicon oxide layer 710 on the sidewall of the gate structure 600 and a silicon nitride layer 720 on the sidewall of the silicon oxide layer 710.
The Source-Drain doped region is used as a Source region (Source) or a Drain region (Drain) of the semiconductor device. Specifically, the source-drain doped regions are located in the fin portions on both sides of the gate structure 600.
In the process of forming the contact hole plug 850, the top of the etch stop layer 750 is used to define the stop position of the etching process, so as to avoid the problem of insufficient etching or over etching in each region. In this embodiment, the material of the etch stop layer 750 is silicon nitride.
It should be further noted that the semiconductor structure further includes: a gate protection layer 650 on top of the gate structure 600.
The gate protection layer 650 is used to protect the top of the gate structure 600 during the formation process of the semiconductor structure. In this embodiment, the gate protection layer 650 is made of silicon nitride.
In this embodiment, the sidewall spacers 700 are located on the sidewalls of the gate structure 600 and the gate protection layer 650, and the top of the gate protection layer 650 is flush with the top of the sidewall spacers 700. In other embodiments, the top of the gate protection layer may be lower than the top of the sidewall.
The interlayer dielectric layer 800 is used to define the formation position and size of the gate structure 600. In this embodiment, the top of the interlayer dielectric layer 800 is flush with the top of the sidewall spacer 700.
The interlayer dielectric layer 800 is made of a low-k dielectric material or an ultra-low-k dielectric material, compared with a common interlayer dielectric layer material (such as SiO)2) The dielectric constant of the interlayer dielectric layer 800 is small, so that the RC delay can be effectively reduced, and the performance of the semiconductor device is improved.
In this embodiment, the material of the interlayer dielectric layer 800 is SiOC. In other embodiments, the material of the interlayer dielectric layer may also be SiOCH.
The contact hole plugs 850 are used to realize electrical connections within the semiconductor device and also to realize electrical connections from device to device.
Specifically, the contact hole plug 850 penetrates through the interlayer dielectric layer 800 and the etch stop layer 750 and is electrically connected to the source/drain doped region (not shown).
In this embodiment, the contact hole plug 850 is made of Co. In other embodiments, the material of the contact hole plug may also be W.
The resistance value of the material of the contact hole plug 850 is small, thereby contributing to reduction of RC delay.
In addition, the semiconductor structure further includes: the titanium layer is positioned between the contact hole plug 850 and the interlayer dielectric layer 800; a titanium silicide layer between the contact hole plug 850 and the substrate; a titanium nitride layer between the contact hole plug 850 and the titanium layer, and between the contact hole plug 850 and the titanium silicide layer.
The titanium layer has good adhesiveness with the substrate and the second interlayer dielectric layer 800, so that the formation quality of the titanium nitride layer is improved; the titanium silicide layer is generated by the reaction of the titanium layer and silicon in the substrate material at the position of the source-drain doped region, and the titanium silicide layer is used for reducing the contact resistance of the contact hole plug 850.
The titanium nitride layer functions as: on one hand, the titanium nitride layer can prevent a reactant used in forming the contact hole plug 850 from reacting with a substrate material at the source/drain doping region, and can also prevent a reactant used from reacting with the titanium silicide layer; on the other hand, the titanium nitride layer is used to improve the adhesion of the material of the contact hole plug 850 when forming the contact hole plug 850, and the titanium nitride layer may function as a contact hole liner layer.
The material of the interlayer dielectric layer 800 of the semiconductor structure is a low-k dielectric material or an ultra-low-k dielectric material, which is compared with the common interlayer dielectric layer material (such as SiO)2) The dielectric constant of the interlayer dielectric layer 800 is smaller, so that the RC delay can be effectively reduced, and the performance of a semiconductor device is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a grid structure is arranged on the substrate, a first interlayer dielectric layer is arranged on the substrate exposed out of the grid structure, and the first interlayer dielectric layer is exposed out of the top of the grid structure;
removing the first interlayer dielectric layer;
after removing the first interlayer dielectric layer, forming a second interlayer dielectric layer on the substrate exposed out of the grid structure, wherein the second interlayer dielectric layer is exposed out of the top of the grid structure, and the relative dielectric constant of the second interlayer dielectric layer is smaller than that of the first interlayer dielectric layer;
forming a contact hole plug in the second interlayer dielectric layer, wherein the contact hole plug is electrically connected with the substrate, and the step of forming the contact hole plug in the second interlayer dielectric layer comprises the following steps: removing the first sacrificial layer to form a contact opening; and filling a conductive material into the contact opening, wherein the first sacrificial layer is positioned on the substrate at two sides of the gate structure and penetrates through the second interlayer dielectric layers at two sides of the gate structure, and the top of the first sacrificial layer is flush with the top of the gate structure.
2. The method of claim 1, wherein the first interlevel dielectric layer is formed of SiO2。
3. The method of claim 1, wherein the second interlevel dielectric layer is formed of a low-k dielectric material or an ultra-low-k dielectric material.
4. The method of claim 1, wherein the second interlevel dielectric layer is SiOC or SiOCH.
5. The method of forming a semiconductor structure of claim 1, wherein after removing the first interlevel dielectric layer, prior to forming a second interlevel dielectric layer over the substrate over which the gate structure is exposed, the method further comprising: forming a first sacrificial layer on the substrate exposed out of the grid structure, wherein the first sacrificial layer exposes out of the top of the grid structure; forming a mask layer on partial first sacrificial layers on two sides of the grid structure; etching the first sacrificial layer by taking the mask layer as a mask to expose part of the substrate;
the step of forming the second interlayer dielectric layer comprises the following steps: after the first sacrificial layer is etched, a second interlayer dielectric layer is formed on the exposed substrate;
after the second interlayer dielectric layer is formed, the forming method further comprises the following steps: removing the rest of the first sacrificial layer, and forming a contact opening exposing the substrate in the second interlayer dielectric layer;
the step of forming a contact hole plug in the second interlayer dielectric layer comprises the following steps: and filling a conductive material into the contact opening to form a contact hole plug.
6. The method of forming a semiconductor structure according to claim 5, wherein a material of the first sacrificial layer is polysilicon.
7. The method of claim 5, wherein the mask layer is made of SiO2SiN or TiN.
8. The method of claim 5, wherein the mask layer has a thickness of
Figure FDA0002664805240000021
To
Figure FDA0002664805240000022
9. The method of forming a semiconductor structure of claim 5, wherein forming a second interlevel dielectric layer over the exposed substrate comprises: forming an interlayer dielectric film on the exposed substrate, wherein the interlayer dielectric film covers the top of the grid structure;
forming a second sacrificial layer on the interlayer dielectric film;
and removing the second sacrificial layer and the interlayer dielectric film which are higher than the top of the grid structure by adopting a planarization process, and taking the residual interlayer dielectric film as a second interlayer dielectric layer.
10. The method of forming a semiconductor structure of claim 9, wherein an interlayer is formed over the exposed substrateIn the step of dielectric film, the thickness of the interlayer dielectric film is
Figure FDA0002664805240000023
To
Figure FDA0002664805240000024
11. The method of claim 9, wherein the second sacrificial layer is a tetraethoxyorthosilicate layer or a plasma enhanced oxide layer.
12. The method of forming a semiconductor structure of claim 9, wherein the second sacrificial layer has a thickness of
Figure FDA0002664805240000025
To
Figure FDA0002664805240000026
13. The method for forming a semiconductor structure according to claim 1, wherein a material of the contact hole plug is Co or W.
14. The method of claim 1, wherein in the step of providing a substrate, a gate protection layer is provided on top of the gate structure;
and in the step of forming a second interlayer dielectric layer on the exposed substrate, the second interlayer dielectric layer exposes the top of the grid electrode protection layer.
15. The method of forming a semiconductor structure of claim 14, wherein a material of the gate protection layer is silicon nitride.
16. A semiconductor structure, comprising:
a substrate;
the grid structure is positioned on the substrate;
the interlayer dielectric layer is positioned on the substrate exposed out of the grid structure, is exposed out of the top of the grid structure, and is made of a low-k dielectric material or an ultra-low-k dielectric material;
and the contact hole plug is positioned in the interlayer dielectric layers at the two sides of the grid structure and is electrically connected with the substrate, and the contact hole plug is formed by removing the first sacrificial layer and then filling a conductive material, wherein the first sacrificial layer is positioned on the substrate at the two sides of the grid structure and penetrates through the interlayer dielectric layers at the two sides of the grid structure, and the top of the first sacrificial layer is flush with the top of the grid structure.
17. The semiconductor structure of claim 16, wherein the material of the interlevel dielectric layer is SiOC or SiOCH.
18. The semiconductor structure of claim 16, wherein a material of the contact hole plug is Co or W.
19. The semiconductor structure of claim 16, wherein the semiconductor structure further comprises: the grid electrode protection layer is positioned at the top of the grid electrode structure;
the interlayer dielectric layer is exposed out of the top of the grid electrode protection layer.
20. The semiconductor structure of claim 19, wherein a material of the gate protection layer is silicon nitride.
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