CN108321089B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN108321089B
CN108321089B CN201710036237.9A CN201710036237A CN108321089B CN 108321089 B CN108321089 B CN 108321089B CN 201710036237 A CN201710036237 A CN 201710036237A CN 108321089 B CN108321089 B CN 108321089B
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forming
interlayer dielectric
etching
dielectric layer
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CN108321089A (en
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张城龙
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

A semiconductor structure and a method of forming the same, the method comprising: forming a substrate, wherein the substrate comprises a substrate, a fin part positioned on the substrate, a grid electrode structure crossing the fin part, source and drain doped regions positioned in the fin parts at two sides of the grid electrode structure, and a first etching stop layer covering the source and drain doped regions; forming a protective layer on top of the gate structure; forming an interlayer dielectric layer on the first etching stop layer and the protective layer; etching the interlayer dielectric layer above the source-drain doped region by taking the first etching stop layer as a stop layer to form a first through hole; etching the interlayer dielectric layer above the gate structure by taking the protective layer as a stop layer to form a second through hole; etching the first etching stop layer along the first through hole to form a first contact hole exposing the source drain doped region; carrying out a pre-amorphization injection process on the source-drain doped region; and after the pre-amorphization injection process, removing the etching protection layer at the bottom of the second through hole to form a second contact hole exposing the grid structure. Through the protective layer, the damage of the grid structure and the source-drain doped region can be prevented.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of semiconductor process technology, the size of semiconductor devices is continuously reduced. The development of the semiconductor process technology mainly comprises the introduction of a high-K gate dielectric layer, a stress engineering technology, pocket ion implantation and continuous optimization of materials and device structures. As the feature size of the device is further reduced, however, planar transistors face significant challenges due to the increasingly significant short channel effects, process variations, reduced reliability, and the like. Fin field effect transistors have a fully depleted fin, lower dopant ion concentration fluctuation, higher carrier mobility, lower parasitic junction capacitance, and higher area usage efficiency than planar transistors, and thus have received much attention.
In a semiconductor manufacturing process, after semiconductor devices are formed on a substrate, it is necessary to connect the semiconductor devices together to form a circuit using a plurality of metal layers including an interconnection line and a contact hole plug formed in a contact hole, the contact hole plug in the contact hole connecting the semiconductor devices, the interconnection line connecting the contact hole plugs on different semiconductor devices to form a circuit. For example: the contact hole plug formed on the fin field effect transistor comprises a contact hole plug electrically connected with the grid structure and a contact hole plug electrically connected with the source drain doped region.
However, the conventional process for forming the contact hole plug easily causes the electrical performance of the semiconductor device to be degraded.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can optimize the electrical performance of a semiconductor device.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: forming a substrate, wherein the substrate comprises a substrate, fin parts which are positioned on the substrate separately, a grid electrode structure which stretches across the fin parts and covers the top surfaces and the side wall surfaces of part of the fin parts, source and drain doped regions which are positioned in the fin parts on two sides of the grid electrode structure, and a first etching stop layer which covers the source and drain doped regions; forming a protective layer on top of the gate structure; forming an interlayer dielectric layer on the first etching stop layer and the protective layer; etching the interlayer dielectric layer above the source-drain doped region by taking the first etching stop layer as a stop layer, and forming a first through hole exposing the first etching stop layer in the interlayer dielectric layer between the grid structures; etching the interlayer dielectric layer above the grid structure by taking the protective layer as a stop layer, and forming a second through hole exposing the protective layer in the interlayer dielectric layer above the grid structure; after the second through hole is formed, etching the first etching stop layer along the first through hole to form a first contact hole which penetrates through the interlayer dielectric layer and the first etching stop layer and exposes the source drain doping area; carrying out a pre-amorphization injection process on the source drain doped region at the bottom of the first contact hole; after the pre-amorphization injection process, removing the protective layer at the bottom of the second through hole to form a second contact hole which penetrates through the interlayer dielectric layer and the protective layer and exposes the gate structure; and filling conductive materials into the first contact hole and the second contact hole to form a first contact hole plug electrically connected with the source drain doping region and a second contact hole plug electrically connected with the grid structure.
Accordingly, the present invention also provides a semiconductor structure comprising: the substrate comprises a substrate, fin parts, a grid structure, source and drain doped regions and a first etching stop layer, wherein the fin parts are positioned on the substrate in a discrete mode, the grid structure stretches across the fin parts and covers the partial top surfaces and the side wall surfaces of the fin parts, the source and drain doped regions are positioned in the fin parts on two sides of the grid structure, and the first etching stop layer covers partial source and drain doped regions; a protective layer on a portion of the top of the gate structure; the interlayer dielectric layer is positioned on the substrate and the protective layer; the first contact hole plug penetrates through the interlayer dielectric layer and the first etching stop layer between the grid electrode structures and is electrically connected with the source drain doped region; and the second contact hole plug penetrates through the interlayer dielectric layer and the protective layer above the grid structure and is electrically connected with the grid structure.
Compared with the prior art, the technical scheme of the invention has the following advantages:
before forming an interlayer dielectric layer, forming a protective layer on the top of a gate structure, and then forming a first through hole exposing the first etching stop layer by taking the first etching stop layer as a stop layer and forming a second through hole exposing the protective layer by taking the protective layer as a stop layer; on one hand, the protective layer can protect the top of the grid structure, so that the adverse effect of a subsequent pre-amorphization injection process on the source-drain doped region on the grid structure is avoided; on the other hand, in the process of forming the second through hole, the first etching stop layer can protect the source and drain doped region, and the damage of the process of forming the second contact hole to the source and drain doped region can be reduced through the protective layer; by combining the two aspects, the protective layer can prevent the grid structure from being damaged and the source-drain doped region from being damaged, so that the electrical performance of the semiconductor device can be optimized.
In an alternative scheme, the protective layer at the bottom of the second through hole is removed through an adhesion layer deposition pre-cleaning process to form a second contact hole, and the influence of the adhesion layer deposition pre-cleaning process on the source and drain doped region is small, so that the damage of the process for forming the second contact hole to the source and drain doped region can be reduced.
The present invention provides a semiconductor structure, comprising: a protective layer on a portion of the top of the gate structure; the interlayer dielectric layer is positioned on the substrate and the protective layer; the first contact hole plug penetrates through the interlayer dielectric layer and the first etching stop layer between the grid electrode structures and is electrically connected with the source drain doped region; and the second contact hole plug penetrates through the interlayer dielectric layer and the protective layer above the grid structure and is electrically connected with the grid structure. When the first contact hole plug and the second contact hole plug are formed, on one hand, the protective layer is used for protecting the top of the grid structure, so that the adverse effect of a pre-amorphization injection process of a source-drain doped region on the grid structure can be avoided; on the other hand, when the interlayer dielectric layer above the gate structure is etched, the first etching stop layer is used for protecting the source-drain doped region, the influence of the process of removing the protective layer to expose the gate structure on the source-drain doped region is small, and the damage to the source-drain doped region can be reduced through the protective layer; by combining the two aspects, the protective layer can prevent the grid structure from being damaged and the source-drain doped region from being damaged, so that the electrical property of the semiconductor structure can be optimized.
Drawings
FIGS. 1-4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
FIGS. 5 and 6 are schematic structural diagrams corresponding to steps in another method for forming a semiconductor structure;
fig. 7 to 23 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As is known from the background art, the process of forming the contact hole plug is liable to cause degradation of the electrical characteristics of the semiconductor device. The reason for this is now analyzed in conjunction with an inventive method of forming a semiconductor structure.
With combined reference to fig. 1 to 4, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown. The method comprises the following steps:
referring to fig. 1, a base is formed, and the base includes a substrate 100, a fin 110 located on the substrate 100 separately, a gate structure 150 crossing the fin 110 and covering a portion of a top surface and a sidewall surface of the fin 110, source and drain doped regions 125 located in the fin 110 on both sides of the gate structure 150, and an etch stop layer 140 covering the source and drain doped regions 125.
With continued reference to fig. 1, an interlayer dielectric layer 151 is formed on the substrate where the gate structure 150 is exposed, wherein the top of the interlayer dielectric layer 151 is higher than the top of the gate structure 150.
Referring to fig. 2, with the etching stop layer 140 as a stop layer, etching the interlayer dielectric layer 151 above the source-drain doped region 125, and forming a first opening 152 exposing the etching stop layer 140 in the interlayer dielectric layer 151 between the gate structures 150; and etching the interlayer dielectric layer 151 above the gate structure 150, and forming a second opening 153 exposing the gate structure 150 in the interlayer dielectric layer 151 above the gate structure 150.
Referring to fig. 3, the etch stop layer 140 is etched along the first opening 152 (shown in fig. 2), and a third opening 154 penetrating the interlayer dielectric layer 151 and the etch stop layer 140 and exposing the source/drain doped region 125 is formed.
Referring to fig. 4, a pre-amorphization implant (PAI) process 160 is performed on the source drain doped region 125 at the bottom of the third opening 154.
However, since the gate structure 150 is exposed by the second opening 153, the gate structure 150 is also subjected to the pre-amorphization implantation process 160 during the pre-amorphization implantation process 160 performed on the source/drain doped region 125, which may adversely affect the gate structure 150 and further degrade the electrical performance of the semiconductor device.
In order to avoid the influence of the pre-amorphization implantation process on the gate structure, another forming process is adopted, and the pre-amorphization implantation process is carried out before the gate structure is exposed. With combined reference to fig. 5 and 6, schematic structural diagrams corresponding to steps in another method for forming a semiconductor structure are shown. The forming method comprises the following steps:
referring to fig. 5, a fourth opening 252 penetrating through the interlayer dielectric layer 251 and the etch stop layer 240 between the gate structures 250 is formed, and the source/drain doped region 225 is exposed by the fourth opening 252; and performing a pre-amorphization implantation process 260 on the source-drain doped region 225 at the bottom of the fourth opening 252.
Referring to fig. 6, a fifth opening 253 is formed in the interlayer dielectric layer 251 above the gate structure 250, and the fifth opening 253 exposes the gate structure 250.
Since the gate structure 250 is covered by the interlayer dielectric layer 251 when the pre-amorphization implantation process 260 is performed on the source-drain doped region 225, the interlayer dielectric layer 251 protects the gate structure 250, so that the gate structure 250 is prevented from being affected by the pre-amorphization implantation process 260.
However, when the fifth opening 253 is formed, since the source/drain doped region 225 is exposed, the process for forming the fifth opening 253 is prone to damage the source/drain doped region 225, and accordingly, the electrical performance of the semiconductor device may be reduced.
In order to solve the technical problem, before an interlayer dielectric layer is formed, a protective layer is formed on the top of a gate structure, a first through hole exposing the first etching stop layer is formed by taking the first etching stop layer as a stop layer, and a second through hole exposing the protective layer is formed by taking the protective layer as a stop layer; on one hand, the protective layer can protect the top of the grid structure, so that the adverse effect of a subsequent pre-amorphization injection process on the source-drain doped region on the grid structure is avoided; on the other hand, in the process of forming the second through hole, the first etching stop layer can protect the source and drain doped region, and the damage of the process of forming the second contact hole to the source and drain doped region can be reduced through the protective layer; by combining the two aspects, the protective layer can prevent the grid structure from being damaged and the source-drain doped region from being damaged, so that the electrical performance of the semiconductor device can be optimized.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 7 to 23 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 7 to 12 in combination, fig. 7 is a perspective view, and fig. 8 is a cross-sectional view of fig. 7 along a cut line AA1, and a base is formed, where the base includes a substrate 300, discrete fins 310 located on the substrate 300, a gate structure 350 (shown in fig. 12) crossing the fins 310 and covering part of the top surface and the sidewall surface of the fins 310, source and drain doped regions 325 located in the fins 310 on both sides of the gate structure 350, and a first etch stop layer 340 covering the source and drain doped regions 325.
The steps for forming the substrate will be described in detail below with reference to the accompanying drawings.
Referring collectively to fig. 7 and 8, the substrate 300 provides a process platform for subsequent formation of semiconductor structures.
In this embodiment, the substrate 300 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The material of the fin 310 is the same as the material of the substrate 300. In this embodiment, the fin 310 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In another embodiment, the formed semiconductor structure is a planar transistor, the base is a planar base, the planar base is a silicon substrate, a germanium substrate, a silicon germanium substrate or a silicon carbide substrate, a silicon-on-insulator substrate or a germanium-on-insulator substrate, a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), and the gate structure is subsequently formed on the planar base.
Specifically, the steps of forming the substrate 300 and the fin 310 include: providing an initial substrate; forming a patterned fin hard mask layer (not shown) on the surface of the initial substrate; etching the initial substrate by taking the fin part hard mask layer as a mask, wherein the etched initial substrate is taken as a substrate 300, and a protrusion on the surface of the substrate 300 is taken as a fin part 310; and removing the fin hard mask layer.
Referring to fig. 9, fig. 9 is a schematic diagram of the structure of fig. 8, a dummy gate structure 320 is formed across the fin 310, and the dummy gate structure 320 further covers a portion of the top surface and the sidewall surface of the fin 310.
In this embodiment, a process of forming a high-k gate dielectric layer and then forming a gate electrode layer (high-k metal gate last) is adopted, so that the dummy gate structure 320 occupies a space for a metal gate structure of a semiconductor structure to be formed later.
The dummy gate structure 320 is a single-layer structure or a stacked structure. The dummy gate structure 320 includes a dummy gate layer; or the dummy gate structure 320 includes a dummy oxide layer and a dummy gate layer on the dummy oxide layer. The dummy gate layer is made of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon, and the dummy oxide layer is made of silicon oxide or silicon oxynitride.
After the dummy gate structure 320 is formed, the forming method further includes: a side wall 330 is formed on the side wall of the dummy gate structure 320, and the side wall 330 is used for defining the position of the source-drain doped region in the subsequent process.
The side wall 330 is made of a material different from that of the interlayer dielectric layer formed subsequently. The sidewall 330 may be made of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride, and the sidewall 330 may have a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacers 330 are single-layer structures, and the material of the sidewall spacers 330 is silicon nitride.
With continued reference to fig. 9, source and drain doped regions 325 are formed in the fin 310 on both sides of the dummy gate structure 320.
In this embodiment, the source-drain doped region 325 in the fin 310 between the adjacent dummy gate structures 320 is shared by the transistors to which the two dummy gate structures 320 belong.
Referring to fig. 10, a first etch stop layer 340 is formed to cover the source drain doped region 325.
The surface of the first etching stop layer 340 is used to define an etching stop position of a subsequent contact hole forming process, so as to avoid etching damage to the source/drain doped region 325.
In this embodiment, the first etching stop layer 340 further covers the dummy gate structure 320 and the fin portion 310, and the material of the first etching stop layer 340 is different from the material of the subsequently formed interlayer dielectric layer.
In this embodiment, the first etch stop layer 340 is made of silicon nitride. In other embodiments, the material of the first etch stop layer may also be silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.
With reference to fig. 11 and fig. 12, it should be noted that after the first etch stop layer 340 is formed, the forming method further includes: forming a bottom interlayer dielectric layer 351 on the substrate exposed by the pseudo gate structure 320; removing the dummy gate structure 320, and forming a gate opening (not shown) in the bottom interlayer dielectric layer 351; a gate structure 350 is formed within the gate opening (as shown in fig. 12).
The bottom interlayer dielectric layer 351 provides a process platform for the subsequent formation of a contact hole plug. The bottom interlayer dielectric layer 351 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride. In this embodiment, the bottom interlayer dielectric layer 351 is made of silicon oxide.
Specifically, the step of forming the bottom interlayer dielectric layer 351 includes: forming a bottom interlayer dielectric film on the substrate exposed out of the dummy gate structure 320, wherein the top of the bottom interlayer dielectric film is higher than the top of the dummy gate structure 320; and grinding to remove the bottom interlayer dielectric film higher than the top of the dummy gate structure 320 to form the bottom interlayer dielectric layer 351, wherein the top of the bottom interlayer dielectric layer 351 is flush with the top of the dummy gate structure 320, and the first etching stop layer 340 higher than the top of the bottom interlayer dielectric layer 351 is also ground to remove to expose the top of the dummy gate structure 320.
In this embodiment, the gate structure 350 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) on the gate dielectric layer.
The gate dielectric layer is made of a high-k gate dielectric material, wherein the high-k gate dielectric material refers to a gate dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the gate dielectric layer is made of HfO2. In other embodiments, the gate dielectric layer may also be made of HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2Or Al2O3。
In this embodiment, the material of the gate electrode layer is W. In other embodiments, the material of the gate electrode layer may also be Al, Cu, Ag, Au, Pt, Ni, or Ti.
It should be noted that, in other embodiments, the gate structure may also be formed by a process of forming a high-k gate dielectric layer and forming a metal gate (high-k first metal gate first). Accordingly, the step of forming the substrate comprises: providing an initial substrate; etching the initial substrate to form a substrate and discrete fin parts positioned on the substrate; forming a gate structure crossing the fin portion, wherein the gate structure also covers part of the top surface and the side wall surface of the fin portion; forming source and drain doped regions in the fin parts on two sides of the grid structure; forming a first etching stop layer covering the source drain doped region; and forming a bottom interlayer dielectric layer on the substrate exposed out of the grid structure, wherein the top of the bottom interlayer dielectric layer is flush with the top of the grid structure.
Referring to fig. 13, a protective layer (not labeled) is formed on top of the gate structure 350.
The protective layer is used as a stop layer for the etching step when the interlayer dielectric layer above the gate structure 350 is subsequently etched, and is also used for protecting the gate structure 350 when the source-drain doped region 325 is subsequently subjected to a pre-amorphization implantation (PAI) process.
In this embodiment, the protection layer has a stacked structure. Accordingly, the step of forming a protective layer on top of the gate structure 350 includes: forming an ion-doped mask layer 361 on top of the gate structure 350; a second etching stop layer 362 is formed on the ion-doped mask layer 361, and the second etching stop layer 362 is made of a different material from the ion-doped mask layer 361.
The second etching stop layer 362 is used as a stop layer for an etching step when an interlayer dielectric layer above the gate structure 350 is subsequently etched, and the ion-doped mask layer 361 is used for protecting the gate structure 350 when a pre-amorphization implantation process is subsequently performed on the source-drain doped region 325.
The ion-doped mask layer 361 has a good blocking effect on doped ions, so that the gate structure 350 can be protected in a subsequent pre-amorphization implantation process; and the ion-doped mask layer 361 is a material easy to remove, so that damage to the gate structure 350 and the source-drain doped region 325 caused by a subsequent process for etching the ion-doped mask layer 361 can be reduced.
In this embodiment, the material of the ion-doped mask layer 361 is silicon oxide. In other embodiments, the material of the ion-doped mask layer may also be silicon oxycarbide or silicon carbonitride.
It should be noted that the thickness of the ion-doped mask layer 361 is not too small or too large. If the thickness of the ion-doped mask layer 361 is too small, the ion-doped mask layer 361 has a relatively poor blocking effect on doped ions when a pre-amorphization implantation process is performed subsequently, and the effect of protecting the gate structure 350 is difficult to achieve; if the thickness of the ion-doped mask layer 361 is too large, the process cost is wasted, the integration level of the semiconductor structure is not improved, and the process difficulty of subsequently etching the ion-doped mask layer 361 is increased. Therefore, in this embodiment, the thickness of the ion-doped mask layer 361 is set as
Figure BDA0001211910320000091
To
Figure BDA0001211910320000092
In order to improve the manufacturing efficiency, in this embodiment, the second etch stop layer 362 and the first etch stop layer 340 are made of the same material, so that the second etch stop layer 362 and the first etch stop layer 340 can be etched in the same subsequent process.
In this embodiment, the first etch stop layer 340 is made of silicon nitride, and correspondingly, the second etch stop layer 362 is also made of silicon nitride. In other embodiments, the material of the second etch stop layer may also be silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.
Note that the thickness of the second etch stop layer 362 is not too small, nor too large. If the thickness of the second etching stop layer 362 is too small, the second etching stop layer 362 is difficult to be used as a stop layer for the etching step when the interlayer dielectric layer above the gate structure 350 is subsequently etched, so that the ion-doped mask layer 361 or the gate structure 350 is easily damaged by etching; if the thickness of the second etching stop layer 362 is too large, the process difficulty of the subsequent etching of the second etching stop layer 362 is easily increased, and the process is not required to be performedThe method is favorable for improving the integration level of the semiconductor structure. For this reason, in this embodiment, the thickness of the second etch stop layer 362 is
Figure BDA0001211910320000101
To
Figure BDA0001211910320000102
In this embodiment, the ion-doped mask layer 361 is formed by a chemical vapor deposition process. Therefore, in the step of forming the ion-doped mask layer 361, the ion-doped mask layer 361 further covers the top of the bottom interlayer dielectric layer 351, the top of the first etching stop layer 340 and the top of the sidewall spacers 330.
With continued reference to fig. 13, an interlevel dielectric layer 352 is formed over the first etch stop layer 340 and the protective layer (not labeled).
The interlayer dielectric layer 352 provides a process platform for forming a contact hole plug on the gate structure 350, and also provides a process platform for forming a Back End Of Line (BEOL) metal layer.
The interlayer dielectric layer 352 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, in order to simplify the process, the interlayer dielectric layer 352 and the bottom interlayer dielectric layer 351 may be etched in the same process, and the material of the interlayer dielectric layer 352 is the same as that of the bottom interlayer dielectric layer 351. Specifically, the interlayer dielectric layer 352 is made of silicon oxide.
In the step of forming the interlayer dielectric layer 352, the interlayer dielectric layer 352 is located on top of the bottom interlayer dielectric layer 351 and the protective layer, because the bottom interlayer dielectric layer 351 is formed on the substrate.
Since the protection layer also covers the top of the bottom interlayer dielectric layer 351, the top of the first etching stop layer 340 and the top of the sidewall spacers 330, the interlayer dielectric layer 352 is located on the protection layer. Specifically, the interlayer dielectric layer 352 is formed on the second etch stop layer 362.
With reference to fig. 13 to fig. 15, the first etching stop layer 340 is used as a stop layer, the interlayer dielectric layer 352 above the source/drain doped region 325 is etched, and a first through hole 353 (shown in fig. 15) exposing the first etching stop layer 340 is formed in the interlayer dielectric layer 352 between the gate structures 350.
The first through hole 353 provides a process foundation for subsequently forming a first contact hole exposing the source-drain doped region 325.
The step of forming the first through hole 353 will be described in detail below with reference to the accompanying drawings.
Referring to fig. 13, a capping layer 410 is formed on the interlayer dielectric layer 352; a first masking material layer 420 is formed on the capping layer 410.
The top surface of the covering layer 410 is a flat surface, which provides a process platform for the subsequent formation of the first masking material layer 420, so that the pattern transfer can be better realized. In this embodiment, the capping Layer 410 is an Organic Dielectric Layer (ODL), and the capping Layer 410 is formed by a spin-on coating process.
The first masking material layer 420 provides a process foundation for the subsequent formation of a patterned first masking layer. The first masking material layer 420 is a dielectric antireflective layer.
In this embodiment, the first mask material layer 420 is a silicon-containing dielectric anti-reflection layer, and the first mask material layer 420 is formed by a chemical vapor deposition process. In other embodiments, the material of the first mask material layer may also be silicon oxynitride or low-temperature silicon oxide.
With continued reference to fig. 13, a patterned first photoresist layer 430 is formed on the first masking material layer 420, wherein the first photoresist layer 430 has a first pattern opening 431 therein exposing a portion of the first masking material layer 420, and the first pattern opening 431 exposes the first masking material layer 420 between adjacent gate structures 350.
In this embodiment, the first pattern opening 431 is used to define a pattern of a first via hole to be formed subsequently.
Referring to fig. 14, the first photoresist layer 430 is used as a mask, the first mask material layer 420 is etched along the first pattern opening 431 (shown in fig. 13), a first opening 421 penetrating the first mask material layer 420 is formed, and the remaining first mask material layer 420 is used as a first mask layer 422.
When a first through hole exposing the source/drain doped region 325 is formed by an etching process, the first mask layer 422 is used as an etching mask.
In this embodiment, the first mask material layer 420 is etched by a plasma dry etching process. Specifically, the main etching gas adopted by the plasma dry etching process is CF4. In other embodiments, CHF may also be employed3、C2F6One or a combination of several kinds of fluorine-based gases is used as the main etching gas.
It should be noted that, after the first mask layer 422 is formed, the first photoresist layer 430 is removed. In this embodiment, the first photoresist layer 430 is removed by a wet stripping or ashing process.
Referring to fig. 15, with the first mask layer 422 as a mask, the cover layer 410 and the interlayer dielectric layer 352 are etched along the first opening 421 (as shown in fig. 14), a first through hole 353 is formed in the interlayer dielectric layer 352 between the adjacent gate structures 350, and the first through hole 353 exposes the first etching stop layer 340 above the source-drain doped region 325.
Specifically, the step of forming the first through hole 353 includes: and sequentially etching the covering layer 410, the interlayer dielectric layer 352, the second etching stop layer 362, the ion-doped mask layer 361 and the bottom interlayer dielectric layer 351 along the first opening 421 by using the first mask layer 422 as a mask to form a first through hole 353 exposing the first etching stop layer 340.
In the step of sequentially etching the covering layer 410, the interlayer dielectric layer 352, the second etching stop layer 362, the ion-doped mask layer 361 and the bottom interlayer dielectric layer 351 along the first opening 421, the first etching stop layer 340 is used as a stop layer of the etching process.
The true bookIn an embodiment, the second etch stop layer 362 and the ion-doped mask layer 361 are etched by using a plasma dry etching process. Specifically, in the step of forming the first through hole 353, the main etching gas used for etching the second etching stop layer 362 is CH2F2Or CHF3Or CH3F; the main etching gas used for etching the ion-doped mask layer 361 is CF4、C4F6Or C4F8. The etching time may be determined according to the thicknesses of the second etch stop layer 362 and the ion-doped mask layer 361.
Referring to fig. 16, after the first via 353 is formed, the first mask layer 422 (shown in fig. 15) and the capping layer 410 (shown in fig. 15) are removed.
In this embodiment, the first mask layer 422 and the covering layer 410 are removed by a dry etching process. In another embodiment, the first mask layer and the capping layer may be removed by a wet etching process.
Referring to fig. 17 to fig. 19, the protection layer (not labeled) is used as a stop layer to etch the interlayer dielectric layer 352 above the gate structure 350, and a second through hole 354 (shown in fig. 19) exposing the protection layer is formed in the interlayer dielectric layer 352 above the gate structure 350.
The second via 354 is followed by forming a second contact hole exposing the gate structure 350 to provide a process foundation.
The step of forming the second through hole 354 will be described in detail below with reference to the accompanying drawings.
Referring to fig. 17, a filling layer 440 is formed in the first via 353 (shown in fig. 16), wherein the filling layer 440 also covers the top of the interlayer dielectric layer 352; a second masking material layer 450 is formed on the fill layer 440.
The material of the filling layer 440 is different from the materials of the interlayer dielectric layer 352, the protective layer and the bottom interlayer dielectric layer 351, and the filling layer 440 is a material which is easy to remove, so that damage to the interlayer dielectric layer 352, the protective layer and the bottom interlayer dielectric layer 351 caused by a subsequent process for removing the filling layer 440 can be reduced.
In this embodiment, the material of the filling layer 440 is an odl (organic Dielectric layer) material, the filling layer 440 is formed by a spin-on coating process, and the top of the filling layer 440 is higher than the top of the interlayer Dielectric layer 352. In other embodiments, the material of the filling layer may also be a duo (deep UV Light Absorbing oxide) material. Wherein said DUO material is a siloxane polymer material comprising CH3-SiOXSi-OH, or SiOH3And the like.
The second masking material layer 450 provides a process foundation for the subsequent formation of a patterned second masking layer. The detailed description of the second mask material layer 450 can refer to the corresponding description of the first mask material layer 420, and is not repeated herein.
With continued reference to fig. 17, a patterned second photoresist layer 460 is formed on the second masking material layer 450, wherein the second photoresist layer 460 has a second pattern opening 461 exposing a portion of the second masking material layer 450, and the second pattern opening 461 exposes the second masking material layer 450 above the gate structure 350.
In this embodiment, the second pattern opening 461 is used for defining the pattern of the second via hole to be formed subsequently.
Referring to fig. 18, using the second photoresist layer 460 (shown in fig. 17) as a mask, etching the second masking material layer 450 (shown in fig. 17) along the second pattern opening 461 (shown in fig. 17) to form a second opening (not shown) penetrating through the second masking material layer 450, and leaving the second masking material layer 450 as a second masking layer 451; after the second mask layer 451 is formed, removing the second photoresist layer 460; the second mask layer 451 is used as a mask, the filling layer 440 and the interlayer dielectric layer 352 are etched along the second opening, a second through hole 354 is formed in the interlayer dielectric layer 352 above the gate structure 350, and the second through hole 354 exposes a protection layer (not shown) above the gate structure 350.
In this embodiment, the protection layer includes an ion-doped mask layer 361 and a second etching stop layer 362 on the ion-doped mask layer 361, so in the step of etching the filling layer 440 and the interlayer dielectric layer 352 along the second opening, the second etching stop layer 362 is used as a stop layer of the etching process, and the second through hole 354 exposes the second etching stop layer 362 above the gate structure 350.
Referring to fig. 19, after the second via hole 354 is formed, the second mask layer 451 (shown in fig. 18) and the filling layer 440 (shown in fig. 18) are removed.
In this embodiment, the second mask layer 451 and the filling layer 440 are removed by a dry etching process. In another embodiment, the second mask layer and the filling layer may be removed by a wet etching process. After the second mask layer 451 and the filling layer 440 are removed, the first via hole 353 is exposed.
Referring to fig. 20, after the second via hole 354 is formed, the first etching stop layer 340 is etched along the first via hole 353 (shown in fig. 19), and a first contact hole 355 penetrating through the interlayer dielectric layer 352 and the first etching stop layer 340 and exposing the source/drain doped region 325 is formed.
The first contact hole 355 provides a spatial location for the subsequent formation of a first contact hole plug.
It should be noted that, since the materials of the first etch stop layer 340 and the second etch stop layer 362 are the same, in the step of etching the first etch stop layer 340 along the first via 355, the second etch stop layer 362 is also etched along the second via 354 (as shown in fig. 19), an initial contact hole 356 penetrating through the interlayer dielectric layer 352 and the second etch stop layer 362 is formed above the gate structure 350, and the initial contact hole 356 exposes the ion-doped mask layer 361.
In this embodiment, a plasma dry etching process is used to etch the first etch stop layer 340 and the second etch stop layer 362. Specifically, the first etch stop layer 340 and the second etch stop layer 362 are made of silicon nitride, and the main etching gas adopted by the plasma dry etching process is fluorine-based gas including CF4、C4F6Or C4F8。
Referring to fig. 21, a pre-amorphization implantation process 370 is performed on the source-drain doped region 325 at the bottom of the first contact hole 355.
It should be noted that, since the ion-doped mask layer 361 is formed on the top of the gate structure 350, the ion-doped mask layer 361 plays a role in protecting the gate structure 350 during the pre-amorphization implantation process 370, so as to prevent the pre-amorphization implantation process 370 from adversely affecting the gate structure 350.
Referring to fig. 22, after the pre-amorphization implantation process 370 (shown in fig. 21), the passivation layer (not shown) at the bottom of the second via hole 354 is removed, and a second contact hole 357 penetrating the interlayer dielectric layer 352 and the passivation layer and exposing the gate structure 350 is formed.
The second contact hole 357 provides a spatial location for the subsequent formation of a second contact hole plug.
Specifically, the step of forming the second contact hole 357 includes: the ion-doped mask layer 361 at the bottom of the initial contact hole 356 (as shown in fig. 21) is removed, and a second contact hole 357 penetrating through the interlayer dielectric layer 352, the second etching stop layer 362 and the ion-doped mask layer 361 and exposing the gate structure 350 is formed.
In this embodiment, the ion-doped mask Layer 361 is removed by a Glue Layer deposition Pre-clean (GLDP) process.
Subsequent process steps include forming a first contact plug in the first contact hole 355 and a second contact hole plug in the second contact hole 357, and before forming the first contact plug and the second contact hole plug, in order to improve adhesiveness of the first contact plug in the first contact hole 355 and adhesiveness of the second contact hole 357 in the second contact hole plug, the forming method further includes: an adhesion layer (glue layer) is formed on the bottom and sidewalls of the first contact hole 355 and the bottom and sidewalls of the second contact hole 357.
In the step of forming the adhesion layer, an adhesion layer deposition precleaning process is performed on the first contact hole 355 and the second contact hole 357 to remove a native oxide (native oxide) in the first contact hole 355 and the second contact hole 357.
The ion-doped mask layer 361 is made of silicon oxide, so that the ion-doped mask layer 361 at the bottom of the initial contact hole 356 can be removed in the process of removing the natural oxide layer through the adhesion layer deposition pre-cleaning process, and the damage of the adhesion layer deposition pre-cleaning process to the source-drain doped region 325 is small, so that the influence of the process for forming the second contact hole 357 on the source-drain doped region 325 can be reduced, and the improvement of the electrical performance of the formed semiconductor device is facilitated.
Specifically, the adhesion layer deposition pre-cleaning process comprises the following steps: providing Ar plasma; and bombarding (sputter) the ion-doped mask layer by adopting Ar plasma. The Ar plasma also bombards the first contact hole 355.
Accordingly, after the second contact hole 357 is formed, an adhesive layer (not shown) is formed on sidewalls and a bottom of the first contact hole 355 and sidewalls and a bottom of the second contact hole 357. Specifically, the adhesion layer includes a titanium layer (not shown) and a titanium nitride layer (not shown) on the titanium layer.
Referring to fig. 23, the first contact hole 355 (shown in fig. 22) and the second contact hole 357 (shown in fig. 22) are filled with a conductive material, and a first contact hole plug 501 electrically connected to the source/drain doped region 325 and a second contact hole plug 502 electrically connected to the gate structure 350 are formed.
The first contact hole plug 501 and the second contact hole plug 502 are used for realizing electrical connection in the semiconductor device and also for realizing electrical connection between the semiconductor device and the semiconductor device.
Specifically, the step of forming the first contact hole plug 501 and the second contact hole plug 502 includes: filling the first contact hole 355 and the second contact hole 357 with a conductive material, wherein the conductive material is also positioned on the top of the interlayer dielectric layer 352; and carrying out planarization treatment on the conductive material, removing the conductive material higher than the top of the interlayer dielectric layer 352, forming a first contact hole plug 501 in a first contact hole 355 between adjacent gate structures 350, wherein the first contact hole plug 501 is electrically connected with the source-drain doped region 325, forming a second contact hole plug 502 in a second contact hole 357 on the gate structure 350, and the second contact hole plug 502 is electrically connected with the gate structure 350.
In this embodiment, the material of the first contact hole plug 501 and the second contact hole plug 502 is W, and the first contact hole plug 501 and the second contact hole plug 502 may be formed by a chemical vapor deposition process, a sputtering process, or an electroplating process. In other embodiments, the material of the first and second contact hole plugs may also be a metal material such as Al, Cu, Ag, or Au.
In this embodiment, before forming the interlayer dielectric layer 352 (as shown in fig. 14), a protection layer (not shown) is formed on top of the gate structure 350 (as shown in fig. 14), and then the first etching stop layer 340 (as shown in fig. 15) is used as a stop layer to form a first via 353 (as shown in fig. 15) exposing the first etching stop layer 340, and the protection layer is used as a stop layer to form a second via 354 (as shown in fig. 18) exposing the protection layer. On one hand, the protection layer may protect the top of the gate structure 350, so as to avoid the adverse effect of the pre-amorphization implantation process 370 (as shown in fig. 21) performed on the source/drain doped region 325 on the gate structure 350; on the other hand, when the interlayer dielectric layer 352 above the gate structure 350 is etched, the first etching stop layer 340 may protect the source/drain doped region 325, and the process of removing the protective layer to expose the gate structure 350 has little influence on the source/drain doped region 325, so that damage to the source/drain doped region 325 may be reduced by the protective layer; in combination with the above two aspects, the protective layer can prevent the gate structure 350 from being damaged and the source/drain doped region 325 from being damaged, so as to optimize the electrical performance of the semiconductor structure.
With continued reference to fig. 23, a schematic diagram of a semiconductor structure in accordance with an embodiment of the present invention is shown. Accordingly, the present invention also provides a semiconductor structure comprising:
the substrate comprises a substrate 300, a fin portion 310 located on the substrate 300, a gate structure 350 crossing the fin portion 310 and covering partial top surface and side wall surface of the fin portion 310, source and drain doped regions 325 located in the fin portion 310 on two sides of the gate structure 350, and a first etching stop layer 340 covering partial source and drain doped regions 325; a protective layer (not labeled) on top of a portion of the gate structure 350; an interlayer dielectric layer 352 on the substrate and the protective layer; a first contact hole plug 501 penetrating through the interlayer dielectric layer 352 and the first etching stop layer 340 between the gate structures 350 and electrically connected to the source/drain doped region 325; and a second contact hole plug 502 penetrating through the interlayer dielectric layer 352 and the protective layer above the gate structure 350 and electrically connected to the gate structure 350.
In this embodiment, the substrate 300 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The material of the fin 310 is the same as the material of the substrate 300. In this embodiment, the fin 310 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In another embodiment, the semiconductor structure is a planar transistor, the substrate is a planar substrate, the planar substrate is a silicon substrate, a germanium substrate, a silicon germanium substrate or a silicon carbide substrate, a silicon-on-insulator substrate or a germanium-on-insulator substrate, a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate), the gate structure 350 is located on the planar substrate, and the source and drain doped regions 325 are located in the planar substrates on both sides of the gate structure 350.
In this embodiment, the gate structure 350 includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer. The source-drain doped region 325 in the fin 310 between the adjacent gate structures 350 is shared by the transistors to which the two gate structures 350 belong.
The gate dielectric layer is made of a high-k gate dielectric material, wherein the high-k gate dielectric material refers to a gate dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the gate dielectric layer is made of HfO2. In other embodiments, the gate dielectric layer may also be made of HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2Or Al2O3。
In this embodiment, the material of the gate electrode layer is W. In other embodiments, the material of the gate electrode layer may also be Al, Cu, Ag, Au, Pt, Ni, or Ti.
The surface of the first etching stop layer 340 is used to define an etching stop position in the formation process of the first contact hole plug 501, so as to avoid etching damage to the source/drain doped region 325 caused by an etching process.
In this embodiment, the first etch stop layer 340 further covers the fin portion 310, and the material of the first etch stop layer 340 is different from the material of the interlayer dielectric layer 352.
In this embodiment, the first etch stop layer 340 is made of silicon nitride. In other embodiments, the material of the first etch stop layer may also be silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.
In addition, the semiconductor structure further includes: and a bottom interlayer dielectric layer 351 located on the substrate between the gate structures 350, wherein the bottom interlayer dielectric layer 351 covers the first etching stop layer 340, and the top of the bottom interlayer dielectric layer 351 is flush with the top of the gate structures 350.
The bottom interlayer dielectric layer 351 provides a process platform for forming the first contact hole plug 501 electrically connected with the source-drain doped region 325. Correspondingly, the protection layer is also located on the bottom interlayer dielectric layer 351, and the first contact hole plug 501 penetrates through the interlayer dielectric layer 352, the protection layer and the first etching stop layer 340 between the gate structures 350.
The bottom interlayer dielectric layer 351 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride. In this embodiment, the bottom interlayer dielectric layer 351 is made of silicon oxide.
The interlayer dielectric layer 352 provides a process platform for forming the first contact hole plug 501 and the second contact hole plug 502.
The interlayer dielectric layer 352 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, in order to improve process compatibility, the material of the interlayer dielectric layer 352 is the same as that of the bottom interlayer dielectric layer 351. Specifically, the interlayer dielectric layer 352 is made of silicon oxide.
The protective layer is used as a stop layer for the etching step when the interlayer dielectric layer 352 above the gate structure 350 is etched, and is also used for protecting the gate structure 350 when a pre-amorphization implantation Process (PAI) is performed on the source-drain doped region 325.
In this embodiment, the protection layer is a stacked structure, and the protection layer includes: an ion-doped masking layer 361 on top of the portion of the gate structure 350; a second etching stop layer 362 on the ion-doped mask layer 361, wherein the second etching stop layer 362 is made of a different material than the ion-doped mask layer 361.
Correspondingly, the second contact hole plug 502 penetrates through the interlayer dielectric layer 352, the second etching stop layer 362 and the ion-doped mask layer 361 above the gate structure 350.
The second etching stop layer 362 is used as a stop layer for an etching step when the interlayer dielectric layer 352 above the gate structure 350 is etched, and the ion-doped mask layer 361 is used for protecting the gate structure 350 when a pre-amorphization implantation process is performed on the source-drain doped region 325.
The ion-doped mask layer 361 has a good blocking effect on doped ions, so that the gate structure 350 can be protected during the pre-amorphization implantation process; and the ion-doped mask layer 361 is a material easy to remove, so that in the process of forming the second contact hole plug 502, the damage of the process of removing the ion-doped mask layer 361 to the gate structure 350 and the source-drain doped region 325 can be reduced. In this embodiment, the material of the ion-doped mask layer 361 is silicon oxide. In other embodiments, the material of the ion-doped mask layer may also be silicon oxycarbide or silicon carbonitride.
It should be noted that the thickness of the ion-doped mask layer 361 is not too small or too large. If the thickness of the ion-doped mask layer 361 is too small, when the pre-amorphization implantation process is performed, the blocking effect of the ion-doped mask layer 361 on doped ions is relatively poor, so that the pre-amorphization implantation process easily causes adverse effects on the gate structure 350; if the thickness of the ion-doped mask layer 361 is too large, the process cost is wasted, the integration level of the semiconductor structure is not improved, and the process difficulty of removing the ion-doped mask layer 361 is increased easily. Therefore, in this embodiment, the thickness of the ion-doped mask layer 361 is set as
Figure BDA0001211910320000201
To
Figure BDA0001211910320000202
In order to improve the manufacturing efficiency, in this embodiment, the second etch stop layer 362 and the first etch stop layer 340 are made of the same material, so that the second etch stop layer 362 and the first etch stop layer 340 can be etched in the same process. In this embodiment, the first etch stop layer 340 is made of silicon nitride, and correspondingly, the second etch stop layer 362 is also made of silicon nitride. In other embodiments, the material of the second etch stop layer may also be silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.
Note that the thickness of the second etch stop layer 362 is not too small, nor too large. If the second etching stopsThe thickness of the layer 362 is too small, and the second etching stop layer 362 is difficult to be used as a stop layer in the etching step when the interlayer dielectric layer 352 above the gate structure 350 is etched in the process of forming the first contact hole plug 501, so that the gate structure 350 is easily damaged by etching; if the thickness of the second etching stop layer 362 is too large, the difficulty of the process for etching the second etching stop layer 362 is easily increased, and the improvement of the integration level of the semiconductor structure is not facilitated. For this reason, in this embodiment, the thickness of the second etch stop layer 362 is
Figure BDA0001211910320000203
To
Figure BDA0001211910320000204
The first contact hole plug 501 is electrically connected with the source-drain doped region 325, the second contact hole plug 502 is electrically connected with the gate structure 350, and the first contact hole plug 501 and the second contact hole plug 502 are used for realizing electrical connection in a semiconductor device and also used for realizing electrical connection between the semiconductor device and the semiconductor device.
In this embodiment, the material of the first contact hole plug 501 and the second contact hole plug 502 is W. In other embodiments, the material of the first and second contact hole plugs may also be a metal material such as Al, Cu, Ag, or Au.
The semiconductor structure of the present embodiment includes: a protective layer (not labeled) on top of a portion of the gate structure 350; an interlayer dielectric layer 352 on the substrate and the protective layer; a first contact hole plug 501 penetrating through the interlayer dielectric layer 352 and the first etching stop layer 340 between the gate structures 350 and electrically connected to the source/drain doped region 325; and a second contact hole plug 502 penetrating through the interlayer dielectric layer 352 and the protective layer above the gate structure 350 and electrically connected to the gate structure 350. When the first contact hole plug 501 and the second contact hole plug 502 are formed, on one hand, the protective layer is used for protecting the top of the gate structure 350, so that adverse effects on the gate structure 350 caused by a pre-amorphization implantation Process (PAI) of the source-drain doped region 325 can be avoided; on the other hand, when the interlayer dielectric layer 352 above the gate structure 350 is etched, the first etching stop layer 340 is used for protecting the source/drain doped region 325, and the influence of the process of removing the protective layer to expose the gate structure 350 on the source/drain doped region 325 is small, so that the damage to the source/drain doped region 325 can be reduced through the protective layer; in combination with the above two aspects, the protective layer can prevent the gate structure 350 from being damaged and the source/drain doped region 325 from being damaged, so as to optimize the electrical performance of the semiconductor structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. A method of forming a semiconductor structure, comprising:
forming a substrate, wherein the substrate comprises a substrate, fin parts which are positioned on the substrate separately, a grid electrode structure which stretches across the fin parts and covers the top surfaces and the side wall surfaces of part of the fin parts, source and drain doped regions which are positioned in the fin parts on two sides of the grid electrode structure, and a first etching stop layer which covers the source and drain doped regions;
forming a protective layer on top of the gate structure, comprising: forming an ion-doped mask layer on the top of the gate structure; forming a second etching stop layer on the ion-doped mask layer, wherein the second etching stop layer is made of a material different from that of the ion-doped mask layer; the material of the ion-doped mask layer is easy to remove;
forming an interlayer dielectric layer on the first etching stop layer and the protective layer;
etching the interlayer dielectric layer above the source-drain doped region by taking the first etching stop layer as a stop layer, and forming a first through hole exposing the first etching stop layer in the interlayer dielectric layer between the grid structures;
etching the interlayer dielectric layer above the gate structure by taking a second etching stop layer in the protective layer as a stop layer, and forming a second through hole exposing the protective layer in the interlayer dielectric layer above the gate structure;
after the second through hole is formed, etching the first etching stop layer along the first through hole to form a first contact hole which penetrates through the interlayer dielectric layer and the first etching stop layer and exposes the source drain doping area; etching the second etching stop layer along the second through hole to form an initial contact hole which penetrates through the interlayer dielectric layer and the second etching stop layer and exposes the ion-doped mask layer;
carrying out a pre-amorphization injection process on the source drain doped region at the bottom of the first contact hole;
after the pre-amorphization injection process, removing the ion-doped mask layer at the bottom of the initial contact hole to form a second contact hole which penetrates through the interlayer dielectric layer, the second etching stop layer and the ion-doped mask layer and exposes the gate structure;
and filling conductive materials into the first contact hole and the second contact hole to form a first contact hole plug electrically connected with the source drain doping region and a second contact hole plug electrically connected with the grid structure.
2. The method of claim 1, wherein the ion-doped mask layer is made of silicon oxide, silicon oxycarbide, or silicon carbide; the second etching stop layer is made of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride.
3. The method of claim 1, wherein the ion-doped mask layer has a thickness of
Figure FDA0002904983120000021
To
Figure FDA0002904983120000022
4. The method of forming a semiconductor structure of claim 1, wherein the second etch stop layer has a thickness of
Figure FDA0002904983120000023
To
Figure FDA0002904983120000024
5. The method of forming a semiconductor structure of claim 1, wherein the process of etching the second etch stop layer is a plasma dry etch process.
6. The method of claim 5, wherein the second etch stop layer is formed of silicon nitride, and wherein a main etching gas of the plasma dry etching process is a fluorine-based gas comprising CF4、C4F6Or C4F8。
7. The method of claim 1, wherein the ion-doped mask layer at the bottom of the initial contact hole is removed by an adhesion layer deposition precleaning process.
8. The method of forming a semiconductor structure of claim 7, wherein the adhesion layer deposition precleaning process comprises: providing Ar plasma; and bombarding the ion-doped mask layer by adopting Ar plasma.
9. The method of forming a semiconductor structure of claim 1, wherein a material of the first etch stop layer is silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.
10. The method for forming a semiconductor structure according to claim 1, wherein the step of forming a first contact hole penetrating through the interlayer dielectric layer and the first etching stop layer and exposing the source-drain doped region comprises: forming a covering layer on the interlayer dielectric layer;
forming a first mask material layer on the covering layer;
forming a patterned first photoresist layer on the first mask material layer, wherein the first photoresist layer has a first pattern opening therein for exposing a portion of the first mask material layer, and the first pattern opening exposes the first mask material layer between adjacent gate structures;
etching the first mask material layer along the first pattern opening by taking the first photoresist layer as a mask to form a first opening penetrating through the first mask material layer, and taking the residual first mask material layer as a first mask layer;
removing the first photoresist layer;
etching the covering layer and the interlayer dielectric layer along the first opening by taking the first mask layer as a mask, forming a first through hole in the interlayer dielectric layer between the adjacent grid electrode structures, and exposing the first etching stop layer above the source drain doped region from the first through hole;
and after the first through hole is formed, removing the first mask layer and the covering layer.
11. The method of claim 1, wherein forming a second via in the interlevel dielectric layer over the gate structure that exposes the protective layer comprises: forming a filling layer in the first through hole, wherein the filling layer also covers the top of the interlayer dielectric layer;
forming a second mask material layer on the filling layer;
forming a patterned second photoresist layer on the second mask material layer, wherein the second photoresist layer is internally provided with a second pattern opening for exposing a part of the second mask material layer, and the second pattern opening exposes the second mask material layer above the gate structure;
etching the second mask material layer along the second pattern opening by taking the second photoresist layer as a mask to form a second opening penetrating through the second mask material layer, and taking the residual second mask material layer as a second mask layer;
after the second mask layer is formed, removing the second photoresist layer;
etching the filling layer and the interlayer dielectric layer along the second opening by taking the second mask layer as a mask, and forming a second through hole in the interlayer dielectric layer above the grid structure, wherein the second through hole exposes the protective layer above the grid structure;
and after the second through hole is formed, removing the second mask layer and the filling layer.
12. The method of forming a semiconductor structure of claim 1, wherein the step of forming a substrate comprises: providing an initial substrate; etching the initial substrate to form a substrate and discrete fin parts positioned on the substrate; forming a pseudo-gate structure crossing the fin part, wherein the pseudo-gate structure also covers part of the top surface and the side wall surface of the fin part; forming source and drain doped regions in the fin parts on two sides of the pseudo gate structure; forming a first etching stop layer covering the source drain doped region; forming a bottom interlayer dielectric layer on the substrate exposed out of the pseudo gate structure; removing the pseudo gate structure, and forming a gate opening in the bottom interlayer dielectric layer; forming a gate structure in the gate opening;
in the step of forming an interlayer dielectric layer on the first etching stop layer and the protective layer, the interlayer dielectric layer is positioned on the tops of the bottom interlayer dielectric layer and the protective layer;
and in the step of forming the first through hole, etching the interlayer dielectric layer and the bottom interlayer dielectric layer above the source-drain doped region to form the first through hole penetrating through the interlayer dielectric layer between the grid structures and the bottom interlayer dielectric layer.
13. The method of forming a semiconductor structure of claim 12, wherein forming the bottom interlevel dielectric layer comprises: forming a bottom interlayer dielectric film on the substrate exposed out of the pseudo gate structure, wherein the bottom interlayer dielectric film is higher than the top of the pseudo gate structure; grinding and removing a bottom interlayer dielectric film higher than the top of the pseudo gate structure to form a bottom interlayer dielectric layer, wherein the bottom interlayer dielectric layer is exposed out of the top of the pseudo gate structure;
in the step of forming a protective layer on top of the gate structure, the protective layer is also on top of the bottom interlevel dielectric layer;
and in the step of forming the interlayer dielectric layer on the first etching stop layer and the protective layer, forming the interlayer dielectric layer on the protective layer.
14. The method of forming a semiconductor structure of claim 1, wherein the step of forming a substrate comprises: providing an initial substrate; etching the initial substrate to form a substrate and discrete fin parts positioned on the substrate; forming a gate structure crossing the fin portion, wherein the gate structure also covers part of the top surface and the side wall surface of the fin portion; forming source and drain doped regions in the fin parts on two sides of the grid structure; and forming a first etching stop layer covering the source-drain doped region.
15. A semiconductor structure formed by the method of forming a semiconductor structure of any of claims 1 to 14, comprising:
the substrate comprises a substrate, fin parts, a grid structure, source and drain doped regions and a first etching stop layer, wherein the fin parts are positioned on the substrate in a discrete mode, the grid structure stretches across the fin parts and covers the partial top surfaces and the side wall surfaces of the fin parts, the source and drain doped regions are positioned in the fin parts on two sides of the grid structure, and the first etching stop layer covers partial source and drain doped regions;
a protective layer on a portion of the top of the gate structure;
the interlayer dielectric layer is positioned on the substrate and the protective layer;
the first contact hole plug penetrates through the interlayer dielectric layer and the first etching stop layer between the grid electrode structures and is electrically connected with the source drain doped region;
the second contact hole plug penetrates through the interlayer dielectric layer and the protective layer above the grid structure and is electrically connected with the grid structure;
the protective layer includes: an ion-doped mask layer on top of the gate structure portion; the second etching stop layer is positioned on the ion-doped mask layer and is made of different materials from the ion-doped mask layer; the material of the ion-doped mask layer is easy to remove.
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