CN107591366B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN107591366B CN107591366B CN201610527878.XA CN201610527878A CN107591366B CN 107591366 B CN107591366 B CN 107591366B CN 201610527878 A CN201610527878 A CN 201610527878A CN 107591366 B CN107591366 B CN 107591366B
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Abstract
A semiconductor structure and method of forming the same, the semiconductor structure comprising: providing a substrate; forming a metal gate structure on a substrate, wherein the metal gate structure comprises a gate dielectric layer, a work function layer positioned on the gate dielectric layer and a metal layer positioned on the work function layer; forming a barrier layer on the top of the metal gate structure; forming an interlayer dielectric layer on the substrate between the metal gate structures; forming a contact hole plug penetrating through the interlayer dielectric layer; and after the contact hole plug is formed, annealing the substrate. After a metal gate structure is formed, a barrier layer is formed on the top of the metal gate structure; the barrier layer is used for protecting the metal gate structure in the subsequent annealing process, and easy-to-diffuse atoms in the annealing process are prevented from diffusing into the work function layer of the metal gate structure, so that the work function value of the work function layer is prevented from being influenced, and the electrical performance of the semiconductor device can be optimized.
Description
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method for forming the same.
Background
The principal semiconductor devices of integrated circuits, particularly very large scale integrated circuits, are metal-oxide-semiconductor field effect transistors (MOS transistors). With the continuous development of integrated circuit manufacturing technology, the technology node of the semiconductor device is continuously reduced, and the geometric dimension of the semiconductor device is continuously reduced following moore's law. As semiconductor device dimensions are reduced to a certain extent, various secondary effects due to the physical limitations of semiconductor devices continue to emerge, and scaling down of feature sizes of semiconductor devices becomes increasingly difficult. Among them, in the field of semiconductor manufacturing, how to solve the problem of large leakage current of a semiconductor device is the most challenging. The leakage current of the semiconductor device is large and is mainly caused by the fact that the thickness of a traditional gate dielectric layer is continuously reduced.
The solution proposed at present is to use a high-k gate dielectric material instead of the conventional silicon dioxide gate dielectric material and use metal as the gate electrode to avoid fermi level pinning effect and boron penetration effect between the high-k material and the conventional gate electrode material. The introduction of the high-k metal gate reduces the leakage current of the semiconductor device.
Although the introduction of high-k metal gates can improve the electrical performance of semiconductor devices to some extent, the electrical performance of semiconductor devices formed by the prior art needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can optimize the electrical performance of a semiconductor device.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a metal gate structure on the substrate, wherein the metal gate structure comprises a gate dielectric layer, a work function layer located on the gate dielectric layer, and a metal layer located on the work function layer; forming a barrier layer on the top of the metal gate structure; forming an interlayer dielectric layer on the substrate between the metal gate structures; forming a contact hole plug penetrating through the interlayer dielectric layer; and after the contact hole plug is formed, annealing the substrate.
Accordingly, the present invention also provides a semiconductor structure comprising: a substrate; a metal gate structure on the substrate, the metal gate structure including a gate dielectric layer, a work function layer on the gate dielectric layer, and a metal layer on the work function layer; the barrier layer is positioned at the top of the metal gate structure; and the interlayer dielectric layer is positioned on the substrate between the metal gate structures.
Compared with the prior art, the technical scheme of the invention has the following advantages:
after a metal gate structure is formed, a barrier layer is formed on the top of the metal gate structure; the barrier layer is used for protecting the metal gate structure in the subsequent annealing treatment process. And preventing the easily-diffused atoms in the annealing treatment from diffusing into the work function layer of the metal gate structure, thereby preventing the work function value of the work function layer from being influenced and further optimizing the electrical performance of the semiconductor device.
In an alternative scheme, the annealing treatment is performed in a hydrogen-containing atmosphere, and the material of the barrier layer is a carbon-containing material (such as carbon-rich silicon carbonitride, SiBCN, SiOCN or SiCN), wherein carbon atoms can better adsorb hydrogen atoms to form carbon-hydrogen bonds, so that the diffusion of the hydrogen atoms can be effectively blocked, and the protection effect on the work function layer can be further improved.
In an alternative, the step of forming the protective layer includes: removing a part of the thickness of the metal gate structure, and forming a groove in the bottom interlayer dielectric layer; and forming the barrier layer at the bottom and the side wall of the groove. Before the annealing treatment is performed on the substrate, the forming method further comprises: and forming a low-K dielectric layer which is filled in the groove on the barrier layer. The low-K dielectric layer is beneficial to reducing the parasitic capacitance values of the metal gate structure and the rear-section metal layer, so that the operation speed of the semiconductor device is improved.
The invention provides a semiconductor structure, which comprises a barrier layer positioned at the top of a metal gate structure, wherein the barrier layer is used for protecting the metal gate structure in the annealing treatment for forming the semiconductor structure and preventing easily-diffused atoms in the annealing treatment from diffusing into a work function layer of the metal gate structure, so that the influence on the work function value of the work function layer is avoided, and the electrical performance of a semiconductor device can be optimized.
Drawings
Fig. 1 to 19 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As is known from the background art, the electrical properties of the semiconductor devices formed by the prior art need to be improved. The reason is analyzed in combination with a method for forming a semiconductor structure, which comprises:
providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, and the substrate comprises an N-type region and a P-type region; forming a pseudo gate structure which crosses the fin part and covers part of the side wall surface and the top surface of the fin part; forming source-drain doped regions in the fin parts on the two sides of the pseudo gate structure; forming a bottom interlayer dielectric layer on the substrate between the fin parts, wherein the top of the bottom interlayer dielectric layer is flush with the top of the pseudo gate structure; removing the pseudo gate structure, forming a first opening in the interlayer dielectric layer at the bottom of the N-type region, and forming a second opening in the interlayer dielectric layer at the bottom of the P-type region; forming a high-K gate dielectric layer on the bottom and the side wall of the first opening and the bottom and the side wall of the second opening, wherein the high-K gate dielectric layer also covers the top of the bottom interlayer dielectric layer; forming a P-type work function layer on the high-K gate dielectric layer; removing the P-type work function layer of the N-type region; forming an N-type work function layer on the high-K gate dielectric layer of the N-type region, wherein the N-type work function layer also covers the P-type work function layer of the P-type region; forming a metal material which is filled in the first opening and the second opening on the N-type work function layer; removing a metal material higher than the top of the bottom interlayer dielectric layer to form a metal layer, and removing an N-type work function layer, a P-type work function layer and a high-K gate dielectric layer which are higher than the top of the bottom interlayer dielectric layer, wherein the high-K gate dielectric layer, the N-type work function layer and the metal layer in the first opening form the first metal gate structure, and the high-K gate dielectric layer, the P-type work function layer, the N-type work function layer and the metal layer in the second opening form the second metal gate structure; forming an interlayer dielectric layer covering the bottom interlayer dielectric layer, the first metal gate structure and the second metal gate structure; forming a contact hole plug in the interlayer dielectric layer and the bottom interlayer dielectric layer, wherein the contact hole plug is contacted with the source drain doped region; and annealing the substrate by using hydrogen-containing gas.
However, in the annealing process, hydrogen atoms or hydrogen isotope atoms are easy-to-diffuse atoms and easily diffuse into the work function layers of the first metal gate structure and the second metal gate structure, which increases the work function value of the work function layer and further degrades the electrical performance of the semiconductor device. And since the P-type work function layer is covered by the N-type work function layer, a diffusion path of the hydrogen atom or the hydrogen isotope atom to the N-type work function layer is smaller than a diffusion path of the hydrogen atom to the P-type work function layer, so that the problem of electrical performance degradation of the N-type semiconductor device is particularly serious.
In order to solve the technical problem, a barrier layer is formed on the top of the metal gate structure; the barrier layer is used for protecting the metal gate structure in the subsequent annealing treatment process. And preventing the easily-diffused atoms in the annealing treatment from diffusing into the work function layer, thereby preventing the work function value of the work function layer from being influenced and further optimizing the electrical performance of the semiconductor device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 19 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1 and fig. 2 together, wherein fig. 1 is a perspective view of a semiconductor structure (only two fins are shown), and fig. 2 is a schematic cross-sectional view along AA1 of fig. 1, a substrate is provided.
The substrate provides a process platform for the subsequent formation of a semiconductor structure. The substrate includes a first region I (shown in fig. 2) and a second region II (shown in fig. 2). In this embodiment, the first region I is used to form an N-type device, and the second region II is used to form a P-type device. In another embodiment, the first region is used to form a P-type device and the second region is used to form an N-type device. In other embodiments, the substrate can also be used to form only N-type devices or only P-type devices.
In the present embodiment, taking the formed semiconductor structure as a fin field effect transistor as an example, the base includes a substrate 100 and a fin (not labeled) protruding from the substrate 100. Correspondingly, the fin protruding from the substrate 100 in the first region I is a first fin 110, and the fin protruding from the substrate 100 in the second region II is a second fin 120. In another embodiment, the semiconductor structure is a planar transistor and the substrate is a planar substrate.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the fin is the same as the material of the substrate 100. In this embodiment, the fin portion is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
Specifically, the process steps for forming the substrate 100 and the fin portion include: providing an initial substrate; forming a patterned hard mask layer 200 on the surface of the initial substrate; and etching the initial substrate by taking the hard mask layer 200 as a mask, wherein the etched initial substrate is taken as the substrate 100, and the protrusion on the surface of the substrate 100 is taken as a fin part.
In this embodiment, after the substrate 100 and the fin portion are formed, the hard mask layer 200 on the top of the fin portion is remained. The hard mask layer 200 is made of silicon nitride, and when a planarization process is performed subsequently, the top surface of the hard mask layer 200 is used for defining a stop position of the planarization process, so that the top of the fin portion is protected.
With reference to fig. 3, it should be noted that after the substrate 100 and the fin portion are formed, the forming method further includes: and forming an isolation structure 101 on the substrate 100 between the fins, wherein the top of the isolation structure 101 is lower than the top of the fins.
The isolation structure 101 serves as an isolation structure of the semiconductor structure and is used for isolating adjacent devices. In this embodiment, the isolation structure 101 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
Specifically, the step of forming the isolation structure 101 includes: forming an isolation film on the substrate 100 between the fins, wherein the top of the isolation film is higher than the top of the hard mask layer 200 (shown in FIG. 2); removing the isolation film higher than the top of the hard mask layer 200; removing a part of the thickness of the isolation film to form an isolation structure 101; the hard mask layer 200 is removed.
Referring to fig. 4 to 12 in combination, fig. 4 is a schematic cross-sectional view along the extending direction of the fin portion (e.g., the direction of BB1 in fig. 1), and a metal gate structure (not shown) is formed on the substrate, where the metal gate structure includes a gate dielectric layer 200 (shown in fig. 12), a work function layer (not shown) on the gate dielectric layer 200, and a metal layer 240 (shown in fig. 12) on the work function layer.
In this embodiment, the metal gate structure is formed by a process of forming a high-k gate dielectric layer and then forming a metal gate (high-k metal gate). The following detailed description will be made in conjunction with the accompanying drawings.
Referring to fig. 4, after the substrate is provided, a dummy gate structure is formed on the fin, and the dummy gate structure crosses the fin and covers a part of the sidewall surface and the top surface of the fin.
The dummy gate structure occupies a spatial position for a metal gate structure to be formed subsequently. In this embodiment, the step of forming the dummy gate structure includes: forming a first dummy gate structure 111 crossing the first fin 110 and covering a part of the sidewall surface and the top surface of the first fin 110, and forming a second dummy gate structure 121 crossing the second fin 120 and covering a part of the sidewall surface and the top surface of the second fin 120.
It should be noted that, the forming method of the dummy gate structure further includes: and forming a side wall 130 on the side walls of the first dummy gate structure 111 and the second dummy gate structure 121. In this embodiment, the sidewall spacer 130 is made of silicon nitride.
Continuing to refer to fig. 4, forming first source-drain doped regions 112 in the first fin portions 110 on both sides of the first dummy gate structure 111; and forming second source-drain doped regions 122 in the second fin portions 120 on two sides of the second dummy gate structure 121.
With continued reference to fig. 4, a bottom interlayer dielectric layer 102 is formed on the substrate between the dummy gate structures (not labeled), and the top of the bottom interlayer dielectric layer 102 is flush with the top of the dummy gate structures.
The bottom interlayer dielectric layer 102 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the bottom interlayer dielectric layer 102 is made of silicon oxide.
Referring to fig. 5, the dummy gate structure (not shown) is removed, and an opening (not shown) is formed in the bottom interlayer dielectric layer 102.
The opening provides a spatial location for the subsequent formation of a metal gate structure. In this embodiment, the first dummy gate structure 111 is removed (as shown in fig. 4), and a first opening 113 is formed in the bottom interlayer dielectric layer 102; the second dummy gate structure 121 is removed (as shown in fig. 4), and a second opening 123 is formed in the bottom interlayer dielectric layer 102.
Referring to fig. 6, a gate dielectric layer 200 is formed on the bottom and sidewalls of the first opening 113 and the bottom and sidewalls of the second opening 123.
In this embodiment, the gate dielectric layer 200 is made of a high-k gate dielectric material, wherein the high-k gate dielectric material refers to a gate dielectric material having a relative dielectric constant greater than that of silicon oxide. In this embodiment, the gate dielectric layer 200 is made of HfO2The gate dielectric layer 200 is also located on top of the interlayer dielectric layer 102. In other embodiments, the gate dielectric layer may also be made of HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2Or Al2O3。
It should be noted that, in order to enable a good interface performance between the formed gate dielectric layer 200 and the substrate, so as to improve the formation quality of the gate dielectric layer 200, before forming the gate dielectric layer 200, the forming method further includes: an interface layer 140 is formed at the bottom of the first opening 113 and the bottom of the second opening 123. In this embodiment, the interfacial layer 140 is formed by a thermal oxidation process, and the material of the interfacial layer 140 is silicon oxide.
Referring to fig. 7, a first work function layer 210 is formed on the gate dielectric layer 200.
The first work function layer 210 in the first opening 113 is subsequently removed, and the first work function layer 210 in the second opening 123 remains, where the first work function layer 210 is used to adjust the threshold voltage of the second region II semiconductor structure.
In this embodiment, the second region ii is used to form a P-type device; accordingly, the first work function layer 210 is a P-type work function material having a work function in a range of 5.1ev to 5.5ev, for example, 5.2ev, 5.3ev, or 5.4 ev. In this embodiment, the first work function layer 210 is formed by an atomic layer deposition process, and the material of the first work function layer 210 is TiN. In other embodiments, the material of the first work function layer may also be TaN, TiSiN, or TaSiN; the first work function layer may also be formed using a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 8, a filling layer 201 filling the first opening 113 (shown in fig. 7) and the second opening 123 (shown in fig. 7) is formed on the first work function layer 210.
The material of the filling layer 201 is different from that of the first work function layer 210, and is a material that is easy to remove, so that the subsequent process of removing the filling layer 201 does not damage the first work function layer 210. In this embodiment, the material of the filling layer 201 is an odl (organic Dielectric layer) material, the filling layer 201 is formed by a spin-on coating process, and the top of the filling layer 201 is flush with the top of the first work function layer 210. In other embodiments, the material of the filling layer may also be a BARC (Bottom Anti-Reflective Coating) material or a duo (deep UV light absorbing oxide) material. Wherein said DUO material is a siloxane polymer material comprising CH3-SiOXSi-OH, or SiOH3And the like.
With continued reference to fig. 8, a photoresist layer 202 is formed on the filling layer 201 and the first work function layer 210 of the second region II.
Referring to fig. 9, the filling layer 201 and the first work function layer 210 in the first opening 113 are removed.
Specifically, the photoresist layer 202 (as shown in fig. 8) is used as a mask, and a dry etching process is used to remove the filling layer 201 and the first work function layer 210 in the first opening 113; the photoresist layer 202 is removed.
Referring to fig. 10, the filling layer 201 (as shown in fig. 9) in the second opening 123 is removed to expose the surface of the first work function layer 210 in the second opening 123.
In this embodiment, the filling layer 201 in the second opening 123 is removed by etching using a dry etching process. Specifically, the etching gas adopted by the dry etching process comprises CF4Or CHF3. In other embodiments, the filling layer in the second opening may also be removed by etching using a wet etching process.
Referring to fig. 11, a second work function layer 220 is formed on the gate dielectric layer 200 within the first opening 113.
The second work function layer 220 is used to adjust the threshold voltage of the first I region semiconductor structure.
In this embodiment, the first region I is used to form an N-type device; accordingly, the second work function layer 220 is an N-type work function material having a work function in a range of 3.9ev to 4.5ev, such as 4ev, 4.1ev, or 4.3 ev. In this embodiment, the second work function layer 220 is formed by an atomic layer deposition process, and the second work function layer 220 is further located on the top of the first work function layer 210; the material of the second work function layer 220 is TiAl. In other embodiments, the material of the second work function layer may also be TaAlN, TiAlN, MoN, TaCN, and AlN; the second work function layer may also be formed using a chemical vapor deposition process or a physical vapor deposition process.
It should be noted that, in order to save a mask for reducing the process difficulty, after the second work function layer 220 is formed, the second work function layer 220 on top of the first work function layer 210 is retained.
It should be further noted that, after the second work function layer 220 is formed, the forming method further includes: a cap layer 230 is formed on the second work function layer 220. The metal layer formed subsequently has easily diffused ions, and the cap layer 230 can block the easily diffused ions from diffusing into the second work function layer 220, so as to prevent the work function value of the second work function layer 220 from becoming large. In this embodiment, the capping layer 230 is made of TiN or TaN. .
Referring to fig. 12, a metal layer 240 is formed to fill the first opening 113 (shown in fig. 11) and the second opening 123 (shown in fig. 11).
The metal layer 240 is made of Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the metal layer 240 is W.
Specifically, the process steps of forming the metal layer 240 include: filling a metal material in the first opening 113 and the second opening 123, wherein the top of the metal material is higher than the top of the second work function layer 220; and grinding to remove the metal material higher than the top of the bottom interlayer dielectric layer 102 to form the metal layer 303, and further grinding to remove the cap layer 230, the second work function layer 220, the first work function layer 210 and the gate dielectric layer 200 higher than the top of the bottom interlayer dielectric layer 102. The gate dielectric layer 200, the second work function layer 220, the cap layer 230 and the metal layer 240 located in the first opening 113 form a metal gate structure of the first region I; the gate dielectric layer 200, the first work function layer 210, the second work function layer 220, the cap layer 230 and the metal layer 240 located in the second opening 123 form a metal gate structure of the second region II.
In another embodiment, the metal gate structure is formed by a process of forming a high-k gate dielectric layer and forming a metal gate (high-k first metal gate first). Correspondingly, the step of forming the metal gate structure on the substrate comprises: forming a metal gate structure on the fin portion, wherein a first region metal gate structure crosses the first fin portion and covers part of the side wall surface and the top surface of the first fin portion, and a second region metal gate structure crosses the second fin portion and covers part of the side wall surface and the top surface of the second fin portion; after the metal gate structure is formed, the forming method further comprises the following steps: forming a first source drain doped region in the first fin parts at two sides of the first region metal gate structure; and forming second source-drain doped regions in the second fin parts on two sides of the second region metal gate structure.
Referring collectively to fig. 13-15, a barrier layer 311 is formed atop the metal gate structure (as shown in fig. 15).
The barrier layer 311 is used to protect the metal gate structure during a subsequent annealing process.
The material of the barrier layer 311 is a carbon-containing material. In this embodiment, the Carbon-containing material is Carbon-Rich silicon carbonitride (Carbon Rich Nitride). In other embodiments, the carbon-containing material may also be SiBCN, SiOCN, or SiCN. Wherein, the carbon-rich silicon carbonitride refers to a silicon carbonitride material with higher carbon content. The subsequent annealing treatment is generally performed in a hydrogen-containing atmosphere, and carbon atoms can better adsorb hydrogen atoms in the annealing treatment to form carbon-hydrogen bonds, so that the diffusion of hydrogen atoms can be effectively blocked, the diffusion of hydrogen atoms into the first work function layer 210 and the second work function layer 220 can be reduced or avoided, and further, adverse effects on the first work function layer 210 and the second work function layer 220 can be avoided.
It should be noted that the carbon content in atomic percent should not be too low or too high. If the atomic percentage content of carbon is too low, the carbon atoms have poor ability to adsorb hydrogen atoms during the subsequent annealing treatment, thereby resulting in poor ability of the barrier layer 311 to block diffusion of hydrogen atoms; if the atomic percentage content Of carbon is too high, the relative dielectric constant Of the barrier layer 311 is easily too high, and thus the parasitic capacitance between the metal gate structure and a subsequently formed Back End Of Line (BEOL) metal layer is easily too high, thereby reducing the operation rate Of the semiconductor device. For this reason, in the present embodiment, the carbon content of the carbon-rich silicon carbonitride is 3 to 15 atomic%.
It should be noted that the thickness of the barrier layer 311 is not too thin, nor too thick. If the thickness of the barrier layer 311 is too thin, the barrier layer 311 has poor ability to block the diffusion of hydrogen atoms; if the thickness of the blocking layer 311 is too thick, the relative dielectric constant of the blocking layer 311 is easily too high, and thus the parasitic capacitance between the metal gate structure and a metal layer formed subsequently is too high, and further the semiconductor device is causedThe running speed of the member decreases. For this reason, in this embodiment, the thickness of the barrier layer 311 is
To
In this embodiment, the step of forming the blocking layer 311 on top of the metal gate structure includes: removing part of the thickness of the metal gate structure, and forming a groove 241 (as shown in fig. 13) in the bottom interlayer dielectric layer 102 of the first region I and the second region II; the barrier layer 311 is formed within the groove 241.
In this embodiment, a dry etching process is used to remove a portion of the thickness of the metal gate structure. In other embodiments, a wet etching process or a combination of a dry etching process and a wet etching process may be further used to remove the metal gate structure.
It should be noted that the depth of the groove 241 is not too small, nor too large. If the depth is too small, a process window for forming the barrier layer 311 is easily too small, so that the formation quality of the barrier layer 311 is reduced, and the capability of the barrier layer 311 for blocking the diffusion of hydrogen atoms is further reduced; if the depth is too large, that is, the height of the remaining metal gate structure is too small, the performance of the metal gate structure is easily reduced, and thus the electrical performance of the semiconductor device is reduced. For this purpose, in this embodiment, the depth of the groove is
To
In this embodiment, the barrier layer 311 is formed on the bottom and the sidewall of the groove 241. After forming the barrier layer 311, the forming method further includes: a low-K dielectric layer 321 (as shown in fig. 15) filling the groove 241 is formed on the barrier layer 311, and the top of the low-K dielectric layer 321 is flush with the top of the bottom interlayer dielectric layer 102.
In this embodiment, the low-K dielectric layer 321 is made of a low-K dielectric material (the low-K dielectric material refers to a dielectric material having a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9). The low-K dielectric layer 321 is beneficial to reducing the parasitic capacitance of the metal gate structure and the back-end metal layer, thereby being beneficial to improving the operation speed of the semiconductor device. In this embodiment, the low-K dielectric layer 321 is SiBCN. In other embodiments, the material of the low-K dielectric layer may also be SiON, SiOCN, or SiBN.
Specifically, the step of forming the barrier layer 311 and the low-K dielectric layer 321 includes: forming a barrier film 310 (shown in fig. 14) conformally covering the bottom and sidewalls of the recess 241, the barrier film 310 further covering the top of the bottom interlevel dielectric layer 102; forming a low-K dielectric film 320 on the barrier film 310 (as shown in fig. 14), wherein the low-K dielectric film 320 fills the groove 241; and removing the low-K dielectric film 320 and the barrier film 310 which are higher than the top of the bottom interlayer dielectric layer 102 by adopting a planarization process, wherein the rest of the barrier film 310 is the barrier layer 311, and the rest of the low-K dielectric film 320 is the low-K dielectric layer 321.
In this embodiment, the process of forming the barrier film 310 is an atomic layer deposition process. Specifically, the barrier film 310 is made of carbon-rich silicon carbonitride, and the process parameters of the atomic layer deposition process include: the precursor introduced into the atomic layer deposition chamber is a precursor containing Si, C and O, the process temperature is 300-600 ℃, the pressure is 1-500 mTorr, the total gas flow of the precursor is 300-5000 sccm, and the deposition times are 10-100 times.
When the process temperature is lower than 300 ℃, the deposition speed of each deposition process is easily caused to be too slow, so that the thickness of the barrier film 310 is thin, or the process time needs to be increased to reach a target thickness value, so that the formation efficiency of the barrier film 310 is reduced; when the process temperature is higher than 600 degrees celsius, thermal decomposition of the precursor is easily caused, thereby introducing a phenomenon like chemical vapor deposition, which in turn affects the purity and step coverage of the barrier film 310, eventually reducing the formation quality of the barrier film 310. Based on the set process temperature, the chamber pressure, the total gas flow of the precursor, and the deposition times are set within reasonable range values, so that high purity and good step coverage of the barrier film 310 are ensured, the formed barrier film 310 meets a target thickness value, and the formation quality of the barrier film 310 is improved.
In this embodiment, the process of forming the low K dielectric film 320 is an atomic layer deposition process. Specifically, the process parameters of the atomic layer deposition process include: introducing a precursor including SiH into the atomic layer deposition chamber2Cl2、NH3、BHXAnd CHXThe process temperature is 300 ℃ to 650 ℃, and the total gas flow of the precursor is 200sccm to 5000 sccm.
Referring to fig. 16, an interlayer dielectric layer 400 is formed on the substrate between the metal gate structures (not shown).
The interlayer dielectric layer 400 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 400 is made of silicon oxide.
In this embodiment, the metal gate structure is formed by a process of forming a high-k gate dielectric layer and then forming a metal gate (high-k metal gate), and the bottom interlayer dielectric layer 102 is formed on the substrate between the metal gate structures (not labeled); correspondingly, in the step of forming the interlayer dielectric layer 400, the interlayer dielectric layer 400 is located on the top of the bottom interlayer dielectric layer 102 and the metal gate structure. In another embodiment, the metal gate structure is formed by a process of forming a high-k gate dielectric layer and forming a metal gate (high-k first metal gate first); correspondingly, in the step of forming the interlayer dielectric layer, the top of the interlayer dielectric layer is flush with the top of the metal gate structure.
Referring to fig. 17 and 18 in combination, a contact hole plug 420 (shown in fig. 18) is formed through the interlayer dielectric layer 400.
The contact hole plug 420 is used to implement electrical connection within the semiconductor device and also to implement electrical connection between devices. In this embodiment, the material of the contact hole plug 420 is W. The contact hole plug 420 may be formed using a chemical vapor deposition process, a sputtering process, or an electroplating process. In other embodiments, the material of the contact hole plug may also be a metal material such as Al, Cu, Ag, or Au.
Specifically, the step of forming the contact hole plug 420 includes: forming contact holes 410 (as shown in fig. 17) in the interlayer dielectric layer 400 and the bottom interlayer dielectric layer 102, wherein the contact holes 410 expose the first source drain doped region 112 and the second source drain doped region 122; forming a contact hole plug 420 (as shown in fig. 18) filling the contact hole 410, wherein the contact hole plug 420 contacts the first source drain doped region 112 and the second source drain doped region 122.
Referring to fig. 19, after the contact hole plugs 420 are formed, an annealing process 500 is performed on the substrate.
The annealing treatment 500 is performed in a hydrogen-containing atmosphere. Specifically, the annealing treatment 500 is performed in an atmosphere containing hydrogen atoms or hydrogen isotope atoms. During the annealing process 500, hydrogen atoms or hydrogen isotope atoms are diffused into the fin portion under the metal gate structure through the contact hole plug 420 to improve the interface state performance between the metal gate structure and the fin portion, and the annealing process 500 is also used for stress relief between subsequent Back End Of Line (BEOL) layers, thereby improving the electrical performance and reliability performance Of the semiconductor device.
In this embodiment, the process parameters of the annealing process 500 include: the pressure is one atmosphere, the reactant gas is hydrogen or deuterium, and the gas flow rate of the reactant gas is 0.5 standard liters per minute to 10 standard liters per minute. The hydrogen-containing gas is a hydrogen atom or an isotope atom of hydrogen. In other embodiments, the hydrogen-containing gas may also include tritium atoms.
The annealing temperature of the annealing treatment 500 is not preferably too high nor too low. If the annealing temperature of the annealing treatment 500 is too high, the doped ion distribution is easily affected, thereby reducing the electrical performance of the semiconductor device; if the annealing temperature Of the annealing treatment 500 is too low, the effect Of improving the interface state performance between the metal gate structure and the fin portion and the stress relief effect for the subsequent Back End Of Line (BEOL) interlayer is not obvious enough. For this reason, in this embodiment, the annealing temperature of the annealing treatment 500 is 200 to 450 degrees celsius, and the process time is 10 to 120 minutes.
After the metal gate structure is formed, a barrier layer 311 (as shown in fig. 15) is formed on the top of the metal gate structure, and the barrier layer 311 is used for protecting the metal gate structure during an annealing process 500 (as shown in fig. 19) and preventing the hydrogen atoms from diffusing into the second work function layer 220 and the first work function layer 210, so as to prevent the work function values of the second work function layer 220 and the first work function layer 210 from being affected, so that the threshold voltage of the semiconductor device is within a preset target value, and further, the electrical performance of the semiconductor device can be optimized.
With continued reference to fig. 19, the present invention also provides a semiconductor structure comprising:
a substrate; a metal gate structure (not labeled) on the substrate, the metal gate structure comprising a gate dielectric layer 200, a work function layer (not labeled) on the gate dielectric layer 200, and a metal layer 240 on the work function layer; a barrier layer 311 on top of the metal gate structure; an interlayer dielectric layer 400 on the substrate between the metal gate structures; and a contact hole plug 420 penetrating the interlayer dielectric layer 400.
The substrate includes a first region I and a second region II. In this embodiment, the semiconductor structure of the first region I is an N-type device, and the semiconductor structure of the second region II is a P-type device. In another embodiment, the semiconductor structure of the first region is a P-type device, and the semiconductor structure of the second region is an N-type device. In other embodiments, the semiconductor structure on the substrate can also include only N-type devices or only P-type devices.
In this embodiment, taking the formed semiconductor structure as a fin field effect transistor as an example, the substrate includes a substrate 100 and a fin portion protruding from the substrate 100. Correspondingly, the fin protruding from the substrate 100 in the first region I is a first fin 110, and the fin protruding from the substrate 100 in the second region II is a second fin 120. In another embodiment, the semiconductor structure is a planar transistor and the substrate is a planar substrate.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the fin is the same as the material of the substrate 100. In this embodiment, the fin portion is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In addition, the semiconductor structure further includes: and the isolation structure 101 is positioned on the substrate 100 between the fins, and the top of the isolation structure 101 is lower than the top of the fins. The isolation structure 101 serves as an isolation structure of the semiconductor structure and is used for isolating adjacent devices. In this embodiment, the isolation structure 101 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
In this embodiment, the first region I metal gate structure crosses over the first fin 110 and covers a portion of the sidewall surface and the top surface of the first fin 110; the second region II metal gate structure crosses over the second fin 120 and covers a portion of the sidewall surface and the top surface of the second fin 120.
The gate dielectric layer 200 is made of a high-k gate dielectric material, wherein the high-k gate dielectric material refers to a gate dielectric material having a relative dielectric constant greater than that of silicon oxide. In this embodiment, the gate dielectric layer 200 is made of HfO2. In other embodiments, the gate dielectric layer may also be made of HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO2Or Al2O3。
In addition, the semiconductor structure further includes: an interfacial layer 140 between the gate dielectric layer 200 and the fin. The interface layer 140 is used to improve the interface performance between the gate dielectric layer 200 and the substrate, and also used to improve the formation quality of the gate dielectric layer 200. In this embodiment, the interface layer 140 is made of silicon oxide.
In this embodiment, the work function layer includes a first work function layer 210 on the second I-gate dielectric layer 200, and a second work function layer 220 on the first I-gate dielectric layer 200.
The first work function layer 210 is used to adjust a threshold voltage of the semiconductor structure of the second region II. In this embodiment, the semiconductor structure of the second region ii is a P-type device; accordingly, the first work function layer 210 is a P-type work function material having a work function in a range of 5.1ev to 5.5ev, for example, 5.2ev, 5.3ev, or 5.4 ev. In this embodiment, the first work function layer 210 is made of TiN. In other embodiments, the material of the first work function layer may also be TaN, TiSiN, or TaSiN.
The second work function layer 220 is used to adjust a threshold voltage of the semiconductor structure of the first region I. In this embodiment, the semiconductor structure of the first region I is an N-type device; accordingly, the second work function layer 220 is an N-type work function material having a work function in a range of 3.9ev to 4.5ev, such as 4ev, 4.1ev, or 4.3 ev. In this embodiment, the material of the second work function layer 220 is TiAl. In other embodiments, the material of the second work function layer may also be TaAlN, TiAlN, MoN, TaCN, and AlN.
The metal layer 240 is made of Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the metal layer 240 is W.
In addition, the semiconductor structure further includes: a capping layer 230 between the metal layer 240 and the second work function layer 220. The metal layer 240 has easily diffusible ions, and the cap layer 230 can block the easily diffusible ions from diffusing into the second work function layer 220, so as to prevent the work function value of the second work function layer 220 from becoming large. In this embodiment, the capping layer 230 is made of TiN or TaN.
In this embodiment, the barrier layer 311 is used to protect the metal gate structure during the annealing process for forming the semiconductor structure.
The material of the barrier layer 311 is a carbon-containing material. In this embodiment, the Carbon-containing material is Carbon-Rich silicon carbonitride (Carbon Rich Nitride). In other embodiments, the carbon-containing material may also be SiBCN, SiOCN, or SiCN. Wherein, the carbon-rich silicon carbonitride refers to a silicon carbonitride material with higher carbon content. The annealing treatment is generally performed in a hydrogen-containing atmosphere, and carbon atoms can better adsorb hydrogen atoms in the annealing treatment to form carbon-hydrogen bonds, so that the effect of blocking hydrogen atom diffusion can be effectively achieved, the hydrogen atoms are reduced or prevented from diffusing into the first work function layer 210 and the second work function layer 220, and further adverse effects on the first work function layer 210 and the second work function layer 220 can be avoided.
It should be noted that the carbon content in atomic percent should not be too low or too high. If the atomic percentage content of carbon is too low, the carbon atoms have a poor ability to adsorb hydrogen atoms during the annealing treatment, resulting in a poor ability of the barrier layer 311 to block diffusion of hydrogen atoms; if the atomic percentage content of carbon is too high, the relative dielectric constant of the blocking layer 311 is too high, which may easily result in too high parasitic capacitance between the metal gate structure and a back-end metal layer (not shown), thereby reducing the operation speed of the semiconductor device. For this reason, in the present embodiment, the carbon content of the carbon-rich silicon carbonitride is 3 to 15 atomic%.
It should be noted that the thickness of the barrier layer 311 is not too thin, nor too thick. If the thickness of the barrier layer 311 is too thin, the barrier layer 311 has poor ability to block the diffusion of hydrogen atoms; if the thickness of the barrier layer 311 is too thick, the dielectric constant of the barrier layer 311 is easily too high, and thus the parasitic capacitance between the metal gate structure and the back-end metal layer is causedToo high, which in turn leads to a decrease in the operating speed of the semiconductor device. For this reason, in this embodiment, the thickness of the barrier layer 311 is
To
In addition, the semiconductor structure further includes: a bottom interlayer dielectric layer 102 on the substrate between the metal gate structures, wherein the top of the bottom interlayer dielectric layer 102 is higher than the top of the metal gate structures; accordingly, the interlayer dielectric layer 400 is located on top of the bottom interlayer dielectric layer 102 and the metal gate structure.
The interlayer dielectric layer 400 and the bottom interlayer dielectric layer 102 are made of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride. In this embodiment, the material of the interlayer dielectric layer 400 and the bottom interlayer dielectric layer 102 is silicon oxide.
It should be further noted that the semiconductor structure further includes: a low-K dielectric layer 321 located on top of the barrier layer 311, wherein the top of the low-K dielectric layer 321 is flush with the top of the bottom interlayer dielectric layer 102; the barrier layer 311 is also located between the low-K dielectric layer 321 and the bottom interlayer dielectric layer 102. That is, the interlevel dielectric layer 400 covers the top of the bottom interlevel dielectric layer 102, barrier layer 311, and low-K dielectric layer 321.
In this embodiment, the low-K dielectric layer 321 is made of a low-K dielectric material (the low-K dielectric material refers to a dielectric material having a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9). The low-K dielectric layer 321 is beneficial to reducing the parasitic capacitance of the metal gate structure and the back-end metal layer, thereby being beneficial to improving the operation speed of the semiconductor device. In this embodiment, the low-K dielectric layer 321 is SiBCN. In other embodiments, the material of the low-K dielectric layer may also be SiON, SiOCN, or SiBN.
In addition, the low-K dielectricThe thickness of layer 321 should not be too thin nor too thick. If the thickness of the low-K dielectric layer 321 is too thin, the effect of reducing the parasitic capacitance is not obvious; if the thickness of the low-K dielectric layer 321 is too thick, that is, the height of the metal gate structure is too small, the performance of the metal gate structure is easily reduced, thereby reducing the electrical performance of the semiconductor device. For this reason, in this embodiment, the thickness of the low-K dielectric layer 321 is
To
The contact hole plug 420 is used to implement electrical connection within the semiconductor device and also to implement electrical connection between devices. In this embodiment, the material of the contact hole plug 420 is W. In other embodiments, the material of the contact hole plug may also be a metal material such as Al, Cu, Ag, or Au.
It should be noted that, in this embodiment, the contact hole plug 420 further penetrates through the bottom interlayer dielectric layer 102 and contacts the first source/drain doped region 112 and the second source/drain doped region 122.
It should be further noted that, in this embodiment, the semiconductor structure further includes: the first source-drain doped regions 112 are positioned in the first fin portions 110 on two sides of the first region I metal gate junction; and the second source-drain doped regions 122 are positioned in the second fin portions 120 at two sides of the second region II metal gate structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (16)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a metal gate structure on the substrate, wherein the metal gate structure comprises a gate dielectric layer, a work function layer located on the gate dielectric layer and a metal layer located on the work function layer, a bottom interlayer dielectric layer is formed on the substrate between the metal gate structures, and the top of the bottom interlayer dielectric layer is flush with the top of the metal gate structure;
forming a barrier layer on top of the metal gate structure, comprising: removing part of the thickness of the metal gate structure, forming a groove in the bottom interlayer dielectric layer, and forming the barrier layer at the bottom and the side wall of the groove;
forming a low-K dielectric layer which is filled in the groove on the barrier layer, wherein the top of the low-K dielectric layer is flush with the top of the bottom interlayer dielectric layer;
forming an interlayer dielectric layer on the top of the bottom interlayer dielectric layer and the top of the low-K dielectric layer;
forming a contact hole plug penetrating through the interlayer dielectric layer and the bottom interlayer dielectric layer;
and after the contact hole plug is formed, annealing the substrate.
2. The method of forming a semiconductor structure of claim 1, wherein the material of the barrier layer is carbon-rich silicon carbonitride, SiBCN, or SiOCN;
the carbon-rich silicon carbonitride comprises 3 to 15 atomic percent of carbon.
3. The method of forming a semiconductor structure of claim 1, wherein the barrier layer has a thickness of
To
4. The method of claim 1, wherein the semiconductor structure is a fin field effect transistor;
in the step of providing the substrate, the substrate comprises a substrate and a fin part protruding out of the substrate;
the step of forming a metal gate structure on the substrate comprises: forming a metal gate structure on the fin portion, wherein the metal gate structure stretches across the fin portion and covers part of the side wall surface and the top surface of the fin portion; after the metal gate structure is formed, the forming method further comprises the following steps: forming source and drain doped regions in the fin parts on two sides of the metal gate structure; in the step of forming an interlayer dielectric layer on the substrate between the metal gate structures, the top of the interlayer dielectric layer is flush with the top of the metal gate structures;
alternatively, the first and second electrodes may be,
after providing the substrate, the method of forming further comprises: forming a pseudo-gate structure on the fin portion, wherein the pseudo-gate structure stretches across the fin portion and covers part of the side wall surface and the top surface of the fin portion; forming source and drain doped regions in the fin parts on two sides of the pseudo gate structure; forming a bottom interlayer dielectric layer on the substrate between the pseudo gate structures, wherein the top of the bottom interlayer dielectric layer is flush with the top of the pseudo gate structures; removing the pseudo gate structure, and forming an opening in the bottom interlayer dielectric layer; the step of forming a metal gate structure on the substrate comprises: forming a metal gate structure in the opening, wherein the top of the metal gate structure is flush with the top of the bottom interlayer dielectric layer; and in the step of forming an interlayer dielectric layer on the substrate between the metal gate structures, the interlayer dielectric layer is positioned on the bottom interlayer dielectric layer and the top of the metal gate structures.
5. The method of forming a semiconductor structure of claim 4, wherein the step of forming a contact hole plug through the interlevel dielectric layer comprises: forming a contact hole in the interlayer dielectric layer and the bottom interlayer dielectric layer, wherein the contact hole exposes the source drain doped region;
and forming a contact hole plug which is filled in the contact hole, wherein the contact hole plug is contacted with the source drain doped region.
6. The method of claim 1, wherein the low-K dielectric layer is formed of a material selected from the group consisting of SiON, SiOCN, SiBN, and SiBCN.
7. The method of forming a semiconductor structure of claim 1, wherein forming the barrier layer and the low-K dielectric layer comprises: forming a barrier film conformally covering the bottom and the side walls of the groove, wherein the barrier film also covers the bottom interlayer dielectric layer;
forming a low-K dielectric film on the barrier film, wherein the groove is filled with the low-K dielectric film;
and removing the low-K dielectric film and the barrier film which are higher than the top of the bottom interlayer dielectric layer by adopting a planarization process.
8. The method of forming a semiconductor structure of claim 7, wherein the process of forming the barrier film is an atomic layer deposition process.
9. The method of claim 8, wherein the barrier film is made of carbon-rich silicon carbonitride, and the atomic layer deposition process comprises the following process parameters: and introducing a precursor containing Si, C and O into the atomic layer deposition chamber, wherein the process temperature is 300-600 ℃, the pressure is 1-500 mTorr, the total gas flow of the precursor is 300-5000 sccm, and the deposition times are 10-100.
10. The method of forming a semiconductor structure of claim 1, wherein said annealing is performed in a hydrogen-containing atmosphere.
11. A semiconductor structure, comprising:
a substrate;
a metal gate structure on the substrate, the metal gate structure including a gate dielectric layer, a work function layer on the gate dielectric layer, and a metal layer on the work function layer;
the barrier layer is positioned at the top of the metal grid structure and is positioned between the low-K dielectric layer and the bottom interlayer dielectric layer;
a low-K dielectric layer located on the barrier layer;
a bottom interlayer dielectric layer on the substrate between the metal gate structures, wherein the top of the bottom interlayer dielectric layer is flush with the top of the low-K dielectric layer,
the interlayer dielectric layer is positioned at the top of the bottom interlayer dielectric layer and the top of the low-K dielectric layer;
and the contact hole plug penetrates through the interlayer dielectric layer and the bottom interlayer dielectric layer.
12. The semiconductor structure of claim 11, wherein the material of the barrier layer is carbon-rich silicon carbonitride, SiBCN, or SiOCN;
the carbon-rich silicon carbonitride contains 3 to 15 atomic percent of carbon.
13. The semiconductor structure of claim 11, wherein the barrier layer has a thickness of
To
14. The semiconductor structure of claim 11, wherein the low-K dielectric layer has a thickness of
To
15. The semiconductor structure of claim 11, wherein the material of the low-K dielectric layer is SiON, SiOCN, SiBN, or SiBCN.
16. The semiconductor structure of claim 11, wherein the semiconductor structure is a fin field effect transistor, and the base comprises a substrate and a fin protruding from the substrate;
the metal gate structure stretches across the fin part and covers part of the side wall surface and the top surface of the fin part;
the semiconductor structure further includes: and the source drain doped regions are positioned in the fin parts at two sides of the metal grid structure.
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| CN104810368A (en) * | 2014-01-28 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Cmos transistor and forming method thereof |
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