TWI757193B - Semiconductor memory structure and the method for forming the same - Google Patents

Abstract

A semiconductor memory structure includes a semiconductor substrate, a bit line disposed on the semiconductor substrate, a dielectric liner disposed on a side of the bit line, a capacitor contact disposed on the semiconductor substrate, and a filler disposed on the semiconductor substrate. The bit line extends along a first direction. The dielectric liner includes a first nitride liner disposed on sidewalls of the bit line, an oxide liner disposed on sidewalls of the first nitride liner, and a second nitride liner disposed on sidewalls of the oxide liner. In a second direction perpendicular to the first direction, the capacitor contact is spaced apart from the bit line only by the first nitride liner, the oxide liner, and the second nitride liner. In the second direction, the width of the filler is greater than the width of the capacitor contact. A method for forming the semiconductor memory structure is also provided.

Description

Semiconductor memory structure and method of forming the same

The present disclosure relates to a semiconductor memory structure, and more particularly, to capacitive contacts for dynamic random access memory.

Dynamic Random Access Memory (DRAM) devices are widely used in consumer electronic products. In order to increase the device density within a DRAM device and improve its overall performance, current DRAM device fabrication techniques continue to strive towards the miniaturization of device size.

However, as component sizes continue to shrink, many challenges arise. For example, in the self-aligned etching process, it is difficult to remove the material at the corners, so that the subsequently formed capacitive contacts are prone to short circuits at the corners. Therefore, the industry still needs to improve the manufacturing method of the DRAM device to overcome the problems caused by the shrinking device size.

An embodiment of the present invention provides a semiconductor memory structure, which includes a semiconductor substrate, a bit line disposed on the semiconductor substrate, a dielectric liner disposed on one side of the bit line, a capacitor contact member disposed on the semiconductor substrate, and A filler provided on a semiconductor substrate. The bit line extends along the first direction. The dielectric liner includes a first nitride liner disposed on the sidewall of the bit line, an oxide liner disposed on the sidewall of the first nitride liner, and a first nitride liner disposed on the sidewall of the oxide liner Dinitride liner. In a second direction perpendicular to the first direction, the capacitive contact is spaced from the bit line by the first nitride liner, the oxide liner, and the second nitride liner. In the second direction, the width of the filler is greater than the width of the capacitive contact.

An embodiment of the present invention provides a method for forming a semiconductor memory structure, which includes providing a semiconductor substrate; forming a plurality of bit lines on the semiconductor substrate; forming a dielectric lining layer on the sidewalls of the bit lines; forming a dielectric material layer on Between the bit lines; an opening is formed in the dielectric material layer, wherein a sidewall of the opening exposes a portion of the second nitride liner; along the sidewall of the opening, a portion of the second nitride is removed laterally lining until the oxide lining is exposed; forming fillers in the openings; and replacing the remaining layers of dielectric material with capacitive contacts. The bit line extends along the first direction. The steps of forming the dielectric lining layer include: forming a first nitride lining layer on the sidewalls of the bit lines; forming an oxide lining layer on the sidewalls of the first nitride lining layer; and forming a second nitride lining layer on the sidewalls on the sidewalls of the oxide liner.

10: Semiconductor memory structure

100: Semiconductor substrate

110: Isolation parts

200: bit line

210, 220: Cover

230, 240, 250: Conductive layer

260, 270, 280: Dielectric layer

300: Dielectric liner

305: Spacer

310: first nitride liner

320, 320': oxide liner

330, 330', 330": Second Nitride Liner

400, 400’, 400”: Dielectric material layers

500: Strip photoresist

600: Filler

700: Capacitive Contacts

C: Notch

H,H',H": opening

D1: first direction

D2: Second direction

Le,Le',Lm,Lm': distance/width

R: rounded corners

Z: height direction

In order to make the features and advantages of the present invention more obvious and easy to understand, different embodiments are given below and described in detail with the accompanying drawings as follows: FIG. 1 illustrates the formation of a semiconductor memory structure according to some embodiments of the present invention. Stereoscopic view at different stages.

FIG. 2 is a cross-sectional view of a semiconductor memory structure corresponding to the line A-A' in FIG. 1, according to some embodiments of the present invention.

3-5 are perspective views illustrating different stages of forming a semiconductor memory structure according to some embodiments of the present invention.

FIG. 6 is a partial top view of the semiconductor memory structure corresponding to FIG. 5 according to some embodiments of the present invention.

FIG. 7 is a perspective view illustrating various stages of forming a semiconductor memory structure according to some embodiments of the present invention.

FIG. 8 is a partial top view of the semiconductor memory structure corresponding to FIG. 7 according to some embodiments of the present invention.

FIG. 9 is a perspective view illustrating various stages of forming a semiconductor memory structure according to some embodiments of the present invention.

FIG. 10 is a partial top view of the semiconductor memory structure corresponding to FIG. 9 according to some embodiments of the present invention.

FIG. 11 is a perspective view illustrating various stages of forming a semiconductor memory structure according to some embodiments of the present invention.

FIG. 12 is a partial top view of the semiconductor memory structure corresponding to FIG. 11 according to some embodiments of the present invention.

FIGS. 13-14 are perspective views illustrating different stages of forming a semiconductor memory structure according to some embodiments of the present invention.

The present disclosure is more fully described below with reference to the drawings of embodiments of the present invention. However, the present disclosure can also be practiced in various different embodiments and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the figures may be exaggerated for clarity, and the same or similar reference numbers indicate the same or similar elements throughout the various figures.

In the embodiment of the present invention, by removing part of the dielectric lining layer, the problem of short circuits at the corners due to the short distance between a plurality of capacitor contacts formed subsequently can be reduced, thereby improving the semiconductor performance.

FIG. 1 is a perspective view illustrating various stages of forming a semiconductor memory structure according to some embodiments of the present invention. FIG. 2 is a cross-sectional view of a semiconductor memory structure corresponding to the line A-A' in FIG. 1, according to some embodiments of the present invention. In some embodiments, the semiconductor memory structure 10 is part of a dynamic random access memory (DRAM) array.

As shown in FIGS. 1 and 2, a semiconductor substrate 100 is provided. In some embodiments, the semiconductor substrate 100 may be an elemental semiconductor substrate, such as a silicon substrate, or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate, or a gallium arsenide substrate. In some embodiments, the semiconductor substrate 100 may be a semiconductor-on-insulator (SOI) substrate.

As shown in FIG. 2 , a spacer member 110 is provided on the semiconductor substrate 100 . In some embodiments, isolation features 110 are disposed in the semiconductor substrate 100 to define active regions. In some embodiments, the isolation features 110 may include nitrides or oxides, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and/or combinations thereof. The formation of the isolation features 110 may include a patterning process (such as a lithography process and an etching process), a deposition process (such as chemical vapor deposition (CVD)), a planarization process (such as chemical mechanical polishing, CMP)). In some embodiments, the etching process may include a dry etching process, such as reactive ion etching (RIE), neutral beam etch (NBE), inductive coupled plasma etch ), a suitable etching process or a combination of the above, etc.

In some embodiments, word lines (not shown) are further embedded in the semiconductor substrate. In some embodiments, the word line acts as a gate and includes a gate dielectric layer, a gate liner, and a gate electrode (not shown).

As shown in FIG. 1 and FIG. 2 , a plurality of bit lines 200 are formed on the semiconductor substrate 100 and extend along the first direction D1 . In some embodiments, bit line 200 includes conductive layers 230, 240, and 250 and dielectric layers 260, 270, and 280 thereon. By the upper dielectric layers 260 , 270 and 280 , the underlying film layers (eg, the conductive layers 230 , 240 and 250 ) can be protected from damage in subsequent processes.

In some embodiments, conductive layers 230, 240, and 250 comprise doped polysilicon, metal, or metal nitride, such as tungsten (W), titanium (Ti), and titanium nitride (TiN) etc. In some embodiments, the dielectric layers 260, 270 and 280 comprise nitrides or oxides, such as silicon nitride or silicon oxide, or the like.

As shown in FIG. 2 , the bit line 200 disposed on the isolation member 110 (or the isolation region) further includes cap layers 210 and 220 , which are disposed between the conductive layer 230 and the isolation member 110 . In some embodiments, the capping layers 210 and 220 may include silicon oxide (eg, thermal silicon oxide, tetraethylorthosilicate (TEOS) oxide), silicon nitride (SiN), or silicon oxynitride (SiON). In some embodiments, the conductive layer 230 in the bit line 200 not disposed on the isolation feature 110 (or the active region) further extends into the semiconductor substrate 100 .

As shown in FIGS. 1 and 2 , a dielectric liner 300 is formed on the sidewalls of the bit lines 200 . In detail, the step of forming the dielectric liner 300 includes conformally forming a first nitride material layer (not shown) on the top surface and sidewall of the bit line 200 and on the semiconductor substrate 100 ; Conformally forming an oxide material layer (not shown) on the first nitride material layer; removing the first nitride material layer on the top surface of the bit line 200 and the top surface of the semiconductor substrate 100 and oxide material layers to form the first nitride lining layer 310 and the oxide lining layer 320; finally, conformally form the second nitride lining layer 330 on the top surface of the bit line 200, the oxide lining layer The sidewalls of 320 are on the semiconductor substrate 100 .

In some embodiments, after the step of forming the first nitride material lining layer, it further includes forming spacers 305 on both sides of the conductive layer 230 extending to the semiconductor substrate 100 to effectively isolate the conductive layer 230 from the subsequently formed capacitors contacts and avoid short circuits.

In some embodiments, the first and second nitride liners 310 and 330 comprise the same material, eg, silicon nitride, and the oxide liner 320 comprises silicon oxide.

In some embodiments, the oxide liner 320 is sandwiched between the first nitride liner 310 and the second nitride liner 330, so as to prevent parasitic capacitance from being generated between the bit line 200 and the subsequently formed capacitive contacts .

Next, please refer to FIGS. 3-4 . FIGS. 3-4 are perspective views illustrating different stages of forming a semiconductor memory structure according to some embodiments of the present invention.

As shown in FIG. 3 , a layer of dielectric material 400 is blanketly formed between and over the bit lines 200 . Specifically, the dielectric material layer 400 is formed on the dielectric liner 300 and completely fills the gaps between the bit lines 200 .

In some embodiments, the material of the dielectric material layer 400 may include silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass ( fluoronated silicate glass (FSG), organosilicate glass ₍ OSG), _SiOxCy , spin-on glass (SOG), low-k dielectric materials, other suitable materials, and the like. In some embodiments, the formation of the dielectric material layer 400 may include a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) etc.

As shown in FIG. 4 , a planarization process is performed to remove part of the dielectric material layer 400 , so that the top surface of the remaining dielectric material layer 400 ′ is flush with the dielectric liner 300 on the top surface of the bit line 200 . Next, in the second direction perpendicular to the first direction D1 In the direction D2, strip-shaped photoresists 500 are formed on top surfaces of the dielectric liner 300 and the remaining dielectric material layers 400' at intervals.

In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) or etch back process. In some embodiments, the formation of strip photoresist 500 may include a lithography process including photoresist coating, pre-exposure bake, exposure using a mask, development, and the like.

Next, please refer to FIGS. 5-6. FIG. 5 is a perspective view illustrating different stages of forming a semiconductor memory structure according to some embodiments of the present invention. FIG. 6 is a partial top view of the semiconductor memory structure corresponding to FIG. 5 according to some embodiments of the present invention.

As shown in FIGS. 5-6, a portion of the dielectric material layer 400' and a portion of the second nitride liner layer 330 are removed. In detail, the strip photoresist 500 is used as an etching mask to remove the dielectric material layer 400 ′ outside directly below the strip photoresist 500 , and the bit line 200 and the dielectric liner 300 are not substantially removed. The opening H is formed, and the dielectric material layer 400 ″ directly under the strip photoresist 500 is left. Next, the strip photoresist 500 is removed, and the top surface of the bit line 200 and the semiconductor substrate 100 are removed. The second nitride liner 330 leaves only the second nitride liner 330 ′ on the sidewall of the bit line 200 .

Here, "substantially no removal/etching" may include no removal/etching at all, slight removal/etching (compared to less than 3% of the thickness of the target).

In some embodiments, the sidewall of the opening H exposes a portion of the second nitride liner 330', and the bottom of the opening H exposes the semiconductor substrate 100. In some embodiments, the opening H has a rounded corner R, which is located on the sidewall of the second nitride liner 330' superior. In some embodiments, in the first direction D1 , the openings H and the dielectric material layers 400 ″ are staggered.

As shown in FIG. 6 , the opening H is defined by the sidewalls of the dielectric liner 300 and the dielectric material layer 400 ″.

In some embodiments, the removal of a portion of the dielectric material layer 400' includes an etching process, such as dry etching with etching selectivity. For example, an etching gas with a high carbon-to-fluorine ratio (eg, C ₄ F ₈ ) is used to achieve a high selectivity ratio of the dielectric material layer 400 ′ to the bit line 200 and the dielectric liner 300 . In some embodiments, the ratio of the etch rate of the dielectric material layer 400' to the etch rate of the bit line 200 and the dielectric liner 300 is about 10:1-30:1, eg, about 15:1-25 :1.

In some embodiments, the removal of a portion of the second nitride liner 330 includes an etching process, such as anisotropic dry etching using a high hydrogen-containing gas (eg, CH ₂ F ₂ ), to remove the The second nitride liner 330 on the semiconductor substrate 100 is substantially not removed from the second nitride liner 330 on the sidewalls of the bit line 200 .

In some embodiments, in the height direction Z, the height of the bit line 200 may be substantially unchanged before and after the etching process to remove a portion of the second nitride liner 330 . In other embodiments, in the height direction Z, the film layer above the bit line 200, such as the dielectric layer 280, may be partially removed by the etching process that removes part of the second nitride liner 330, Therefore, the height of the bit line 200 after the etching process is lower than that before the etching process in which part of the second nitride liner 330 is removed.

Since the etching process cannot completely remove the dielectric material layer 400' located outside the strip photoresist 500, for example, part of the dielectric material layer 400' to be removed It may remain at the corners, so the formed opening H has a rounded corner R, and the opening H has only the maximum width Lm in the first direction D1, but due to the formation of the rounded corner, the width of the opening H in the bit line 200 is reduced to Le (Le<Lm). That is to say, the distance Lm between the two dielectric material layers 400 ″ is reduced to Le near the bit line 200 due to the rounded corners.

Since the remaining dielectric material layers 400 ″ will be replaced with capacitor contacts later, the distance between the dielectric material layers 400 ″ is too close, resulting in an excessive distance between two capacitor contacts near the bit line 200 The problem of short circuit occurs. The embodiments of the present invention will describe the means for solving the above problems, so as to overcome the short circuit problem of the capacitive contacts. For details, please refer to the following description.

Next, please refer to FIGS. 7-10. FIGS. 7 and 9 are perspective views illustrating different stages of forming a semiconductor memory structure according to some embodiments of the present invention. FIGS. 8 and 10 are partial top views of the semiconductor memory structures corresponding to FIGS. 7 and 9, respectively, according to some embodiments of the present invention.

As shown in FIGS. 7-8 , along the sidewall of the opening H, a portion of the second nitride liner 330 ′ is laterally removed until the oxide liner 320 is exposed to form a discontinuous second nitride liner 330 ″. In some embodiments, the opening H is enlarged along the second direction D2 and remains as it is along the first direction D1 to form the opening H′. Compared with the opening H, the rounded corner R of the opening H′ is closer to the Metaline 200.

In some embodiments, the opening H′ exposes the second nitride liner 330 ″ and the oxide liner 320 at the same time. In some embodiments, in the first direction D1 , the second nitride liner 330 ″ and the opening H 'Staggered.

In some embodiments, the removal of a portion of the second nitride liner 330 ′ includes an etching process, such as isotropic dry etching with etching selectivity, to etch the second nitride liner 330 exposed on the sidewalls on both sides of the opening . For example, dry etching using a hydrogen-containing gas (eg, CH ₂ F ₂ or CH ₃ F, etc.) is used to achieve a high selectivity ratio of the second nitride liner 330 ′ to the oxide liner 320 . In some embodiments, the ratio of the etch rate for the second nitride liner 330' to the etch rate for the oxide liner 320 is greater than about 25:1, eg, about 25:1-40:1. Furthermore, in this embodiment, the oxide liner 320 can serve as an etch stop layer.

As shown in FIGS. 9-10, along the sidewall of the opening H', a portion of the oxide liner 320 is laterally removed until the first nitride liner 310 is exposed, so as to form a discontinuous oxide liner 320' . In some embodiments, the opening H' is enlarged along the second direction D2 while remaining the same along the first direction D1 to form the opening H". Compared with the opening H', the rounded corner R of the opening H' is closer to the bit cell Line 200.

In some embodiments, the opening H" exposes the second nitride liner 330", the oxide liner 320' and the first nitride liner 310 simultaneously. In some embodiments, in the first direction D1, the oxide liner 320' is staggered with the openings H".

In some embodiments, the oxide liner 320 ′ and the dielectric material layer 400 ″ include the same material, such as silicon oxide. In this embodiment, due to the thickness of the dielectric material layer 400 ″ in the second direction D2 Much larger than the oxide liner 320', so even if a portion of the oxide liner 320' is removed, the dielectric material layer 400" may not be substantially removed.

In some embodiments, the removal of a portion of the oxide liner 320 includes an etching process, such as wet etching with etch selectivity, to etch the oxide liner 320 exposed on the sidewalls on both sides of the opening. In addition, in this etching process, the first nitride liner layer 310 can serve as an etch stop layer.

In embodiments using wet etching, the etch selectivity may be controlled using an etchant, eg, oxides may be etched substantially without etching nitrides. The etchant used in the wet etching may include buffered oxide etch (BOE), diluted hydrofluoric acid (diluted HF, DHF), and the like.

Since part of the second nitride lining layer 330 ′ and the oxide lining layer 320 are removed, the fillet R is pushed from the center of the opening to the bit line 200 along the second direction D2 , so that in the first direction D1 two two The distance between the electrical material layers 400 ″ (which will be replaced by the capacitive contacts later) can be maintained substantially the same (Le' is approximately equal to Lm') to avoid short-circuiting of the capacitive contacts formed later.

Next, please refer to FIGS. 11-12. FIG. 11 is a perspective view illustrating different stages of forming a semiconductor memory structure according to some embodiments of the present invention. FIG. 12 is a partial top view of the semiconductor memory structure corresponding to FIG. 11 according to some embodiments of the present invention.

As shown in Figures 11-12, a filler 600 is formed in the opening H". In some embodiments, the filler 600 may include a nitride, such as silicon nitride, silicon oxynitride, etc. In some embodiments, the filler Formation of element 600 includes depositing a fill material in a deposition process, and then removing excess fill material in a planarization process or an etch process such that the top surface of fill element 600 is substantially flush with the top surface of bit line 200. In some implementations In an example, the top surface of filler 600, the top surface of bit line 200, and the top surface of dielectric material layer 400" are substantially coplanar.

In some embodiments, since the filler 600 completely covers the opening H", the filler 600 also has rounded corners R. In this embodiment, the rounded corners R directly contact the dielectric liner 300, eg, simultaneously directly contact the first and Second nitride liner layers 310 and 330 ″ and oxide liner layer 320 .

In some embodiments, the filler 600 and the first nitride liner 310 comprise the same material, eg, silicon nitride. That is, there is no boundary between the first nitride liner 310 and the filler 600 . In the embodiment in which the first nitride liner 310 and the filling member 600 are both silicon nitride, in the second direction D2, the bit lines 200 and the silicon nitride are staggered.

In some embodiments, the filler 600 and the dielectric material layer 400" comprise different materials, for example, the filler 600 comprises silicon nitride and the dielectric material layer 400" comprises silicon oxide, so as to facilitate subsequent selective removal of the dielectric material Layer 400".

Next, referring to FIGS. 13-14, the dielectric material layer 400" is replaced with the capacitive contact 700. In detail, the dielectric material layer 400" is completely removed to form the notch C; and the notch is filled with conductive material C, to form capacitive contacts 700 .

In some embodiments, in the second direction D2, the capacitive contact 700 is spaced from the bit line 200 by the first nitride liner 310, the oxide liner 320', and the second nitride liner 330", while the The filler 600 is only spaced from the bit line 200 by the first nitride liner 310. It can also be said that the width of the filler 600 is larger than that of the capacitor contact 700 in the second direction D2 between any two element lines 200. width.

In the embodiment of the present invention, the first nitride lining layer 310 , the oxide lining layer 320 ′, and the second nitride lining layer 330 ″ are disposed between the capacitor contact 700 and the bit line 200 , and the space between the filling member 600 and the bit line 200 is Disposing the first nitride lining layer 310 in between can further reduce the problem of short circuit while ensuring the overall electrical properties.

In some embodiments, the rounded corners R of the fillers 600 directly contact the dielectric liner 300 and do not substantially directly contact the capacitive contacts 700 , so as to reduce the possibility of a short circuit between two capacitive contacts 700 . In some embodiments, in the first direction D1, the capacitive contacts 700 and the fillers 600 are staggered.

Compared with the case of not removing part of the nitride liner and oxide liner, the embodiment of the present invention removes part of the nitride liner and oxide liner, and pushes the fillet of the filler to the dielectric liner In the layer, the short circuit problem caused by the short distance between the rounded corners near the bit lines can be reduced.

In some embodiments, the removal of the dielectric material layer 400 ″ includes an etching process, such as a wet etch with etch selectivity, to etch the dielectric material layer 400 ″ until the sidewalls of the filler 600 are fully exposed. In some embodiments, the notch C extends and exposes the top surface of the semiconductor substrate 100 between the fillers 600 .

In some embodiments, the etchant used in the wet etching may include a buffered oxide etchant (BOE) to completely remove the dielectric material layer without substantially removing the filler 600 and dielectric liner 300 400”.

In some embodiments, the conductive material may include doped polysilicon, metal, or metal silicide, or the like. The metal may include tungsten, aluminum, copper, gold, silver, alloys of the above, or other suitable metallic materials. The metal silicide may include cobalt silicide.

It should be noted that additional components, such as capacitors, metal layers, dielectric layers, etc., may still be formed after the capacitive contact 700 is formed to complete the fabrication of memory devices such as dynamic random access memory (DRAM).

To sum up, in the embodiment of the present invention, by removing part of the nitride lining layer and the oxide lining layer, the distance between the two capacitor contacts near the bit line can be increased, thereby reducing the short circuit situation.

Although the present invention is disclosed in the foregoing embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the appended patent application.

10: Semiconductor memory structure

100: Semiconductor substrate

200: bit line

300: Dielectric liner

310: first nitride liner

320': oxide liner

330": Second Nitride Liner

600: Filler

700: Capacitive Contacts

D1: first direction

D2: Second direction

R: rounded corners

Z: height direction

Claims (10)

A semiconductor memory structure comprising: a semiconductor substrate; a bit line, disposed on the semiconductor substrate and extending along a first direction; A dielectric liner is disposed on one side of the bit line, wherein the dielectric liner includes: a first nitride liner disposed on the sidewall of the bit line; an oxide liner disposed on the sidewall of the first nitride liner; and a second nitride lining layer disposed on the sidewall of the oxide lining layer; A capacitive contact is disposed on the semiconductor substrate, wherein in a second direction perpendicular to the first direction, the capacitive contact is formed by the first nitride liner, the oxide liner and the second a nitride liner spaced from the bit line; and A filling member is disposed on the semiconductor substrate, wherein in the second direction, the width of the filling member is larger than the width of the capacitive contact member. The semiconductor memory structure of claim 1, wherein in the first direction, the first nitride lining layer is continuously arranged, and the oxide lining layer and the second nitride lining layer are discontinuously arranged. The semiconductor memory structure of claim 1, wherein in the top view, the filler has a rounded corner, wherein the rounded corner directly contacts the dielectric liner. The semiconductor memory structure of claim 3, wherein the rounded corner does not directly contact the capacitive contact. The semiconductor memory structure of claim 1, wherein in the first direction, the filler and the capacitive contact are staggered. The semiconductor memory structure of claim 1, wherein in the second direction, the filler is spaced from the bit line only by the first nitride liner. A method for forming a semiconductor memory structure, comprising: providing a semiconductor substrate; forming a plurality of bit lines on the semiconductor substrate, and the bit lines extend along a first direction; A dielectric liner is formed on the sidewalls of the bit lines, wherein the step of forming the dielectric liner includes: forming a first nitride liner on the sidewalls of the bit lines; forming an oxide liner on the sidewalls of the first nitride liner; and forming a second nitride liner on the sidewall of the oxide liner; forming a layer of dielectric material between the bit lines; forming an opening in the dielectric material layer, wherein a sidewall of the opening exposes a portion of the second nitride liner; along sidewalls of the opening, laterally removing a portion of the second nitride liner until the oxide liner is exposed; forming a filler in the opening; and The remaining layer of dielectric material is replaced with a capacitive contact. The method for forming a semiconductor memory structure of claim 7, wherein the step of laterally removing a portion of the second nitride liner comprises expanding the opening along a second direction perpendicular to the first direction. The method for forming a semiconductor memory structure of claim 7, wherein the step of forming the dielectric material layer comprises: depositing a dielectric material on the dielectric liner; and The dielectric material is planarized to form the layer of dielectric material, wherein the top surface of the layer of dielectric material is flush with the top surface of the dielectric liner. The method for forming a semiconductor memory structure of claim 7, wherein the step of forming the second nitride lining layer comprises: forming the second nitride lining layer on the top surfaces of the bit lines, and forming the second nitride lining layer on the bit lines. on the semiconductor substrate between the element lines; and The step of forming the opening further includes: removing the second nitride liner on the top surface of the bit lines and on the semiconductor substrate between the bit lines to expose the semiconductor substrate.

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