CN114695118A - Transistor device with self-aligned contact structure, electronic device and forming method - Google Patents

Transistor device with self-aligned contact structure, electronic device and forming method Download PDF

Info

Publication number
CN114695118A
CN114695118A CN202011599509.4A CN202011599509A CN114695118A CN 114695118 A CN114695118 A CN 114695118A CN 202011599509 A CN202011599509 A CN 202011599509A CN 114695118 A CN114695118 A CN 114695118A
Authority
CN
China
Prior art keywords
layer
self
gate
aligned contact
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011599509.4A
Other languages
Chinese (zh)
Inventor
林盈志
张峰溢
苏廷锜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Pengxin Microintegrated Circuit Manufacturing Co ltd
Original Assignee
Guangzhou Integrated Circuit Technology Research Institute Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangzhou Integrated Circuit Technology Research Institute Co ltd filed Critical Guangzhou Integrated Circuit Technology Research Institute Co ltd
Priority to CN202011599509.4A priority Critical patent/CN114695118A/en
Priority to PCT/CN2021/141850 priority patent/WO2022143585A1/en
Publication of CN114695118A publication Critical patent/CN114695118A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The invention discloses a method for forming a transistor device with a self-aligned contact structure, which comprises the following steps: forming a plurality of gate structures on a semiconductor substrate, the gate structures including gates and sidewall spacers formed on opposing sidewalls of the gates; depositing a layer of insulating material above the gate structure to form an insulating layer; cutting the insulating layer to form a covering layer above the grid structure; the capping layer is cut to form a self-aligned contact element over the semiconductor substrate, wherein a width of the capping layer is greater than a width of the gate structure, the self-aligned contact element being electrically insulated from the gate structure by the capping layer and the sidewall spacer. Thereby avoiding metal residues on the sidewall spacers in the prior art; the height load of the finally formed NMOS/PMOS grid is difficult to control; the chamber door used in the process of recessing the gate structure is difficult to maintain (polymer rich).

Description

Transistor device with self-aligned contact structure, electronic device and forming method
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a transistor device having a self-aligned contact structure, a method of forming the same, and an electronic device including the transistor device.
Background
The semiconductor integrated circuit industry is experiencing rapid growth. Technological advances in integrated circuit design and materials have produced generations of integrated circuits where each generation has smaller and more complex circuits than the previous generation. In the process of integrated circuit development, the geometric dimensions are gradually shrinking.
As the size of integrated circuits is reduced, the distance between the self-aligned contact structure and the gate is reduced, and thus the probability of short circuit to generate leakage current is increased. When a transistor device having a self-aligned contact structure is conventionally manufactured, after a gate structure 102 is formed on a semiconductor substrate 101 by a gate polishing process, a recess operation needs to be performed on the gate structure; then depositing an insulating layer 103 on the recessed gate structure; then polishing treatment is carried out; finally, self-aligned contact elements 104 are formed on the polished gate structure by dicing. Thereby forming the transistor device shown in fig. 1. Transistor devices produced by this method have the following problems:
1. the sidewall spacers 105 have metal gate residue thereon;
2. the height load of the finally formed NMOS/PMOS grid is difficult to control;
on one hand, due to the etching selection ratio of the metal material and the high-K dielectric material in the metal grid, the heights of the metal material and the high-K dielectric material in the same metal grid are different; on the other hand, since the semiconductor substrate is provided with the gate Dense region (Dense) and the sparse region (Iso), the volume ratio of the metal material to the high-K dielectric material in different regions is different, which results in different heights of the same material in different metal gates. As shown in fig. 2, three different heights occur during the gate etch back process.
3. By-products (e.g. metal fluorides, Ti) generated during the recess gate structurexFyOr TaxFy) Resulting in the use of an etch chamber that is difficult to maintain.
In the etching process, the metal material reacts with etching gas, and the generated by-products are easily deposited above the metal grid to influence the etching effect; the generated byproducts are easily deposited in the etching chamber, and the use of the etching equipment is influenced.
Disclosure of Invention
The invention aims to provide a method for forming a transistor device with a self-aligned contact structure.
The technical scheme adopted by the invention is as follows: a method of forming a transistor device having a self-aligned contact structure is constructed, comprising the steps of:
forming a plurality of gate structures on a semiconductor substrate, the gate structures including gates and sidewall spacers formed on opposing sidewalls of the gates;
depositing a layer of insulating material above the gate structure to form an insulating layer;
cutting the insulating layer to form a covering layer above the gate structure;
forming a self-aligned contact element over the semiconductor substrate, wherein a width of the capping layer is greater than a width of the gate structure, the self-aligned contact element being electrically insulated from the gate structure by the capping layer and the sidewall spacer.
In the method for forming a transistor device with a self-aligned contact structure provided by the invention, the step of cutting the insulating layer to form a covering layer located above the gate structure comprises the following steps:
forming a photoresist layer over the insulating layer;
forming one or more openings in the photoresist layer by an etching process;
cutting the insulating layer through the one or more openings to form the capping layer.
In the method for forming a transistor device having a self-aligned contact structure provided by the present invention, the step of cutting the capping layer to form a self-aligned contact element over the semiconductor substrate includes:
depositing an interlayer dielectric layer above the covering layer;
forming a light resistance layer on the interlayer medium layer;
forming one or more openings in the photoresist layer by an etching process;
cutting the cover layer through the one or more openings to form the self-aligned contact elements.
According to another aspect of the present invention, there is also provided a transistor device having a self-aligned contact structure, including:
a plurality of gate structures located over a semiconductor substrate, each of the gate structures including a gate and sidewall spacers formed on opposing sidewalls of the gate;
a covering layer formed on the surface of the gate structure; and
a self-aligned contact element over the semiconductor substrate, wherein a width of the capping layer is greater than a width of the gate structure, the self-aligned contact element being electrically insulated from the gate structure by the capping layer and the sidewall spacer.
In the transistor device with the self-aligned contact structure, the sidewall spacer comprises a sidewall spacer and an etching barrier layer.
In the transistor device with the self-aligned contact structure provided by the invention, the side wall is silicon dioxide, silicon nitride or a composition thereof. The etching barrier layer is silicon nitride.
In the transistor device with the self-aligned contact structure, the gate is a metal gate and comprises a high-K material layer and a metal layer.
In the transistor device with the self-aligned contact structure, the covering layer is silicon nitride.
The transistor device with the self-aligned contact structure and the forming method thereof have the following beneficial effects: the invention deposits the insulating layer above the gate structure, cuts the insulating layer to form the covering layer with the width larger than that of the gate structure, and then forms the self-aligned contact element on the cut covering layer, wherein the self-aligned contact element formed by the method is partially overlapped with the gate structure and is electrically insulated from the gate structure through the covering layer and the side wall spacer, thereby avoiding the metal residue on the side wall spacer in the prior art; the height load of the finally formed NMOS/PMOS grid is difficult to control; the chamber door used in the process of recessing the gate structure is difficult to maintain (polymer rich).
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts:
fig. 1 is a cross-sectional view of a transistor device having a self-aligned contact structure formed in accordance with the prior art;
fig. 2 is a flow chart illustrating a method for forming a transistor device with a self-aligned contact structure according to an embodiment of the invention;
fig. 3-9 are cross-sectional views of stages in a method for forming a self-aligned contact structure according to the invention.
Detailed Description
While various embodiments or examples are disclosed below to practice various features of embodiments of the invention, embodiments of specific components and arrangements thereof are described below to illustrate embodiments of the invention. These examples are merely illustrative and should not be construed as limiting the scope of the embodiments of the present invention. For example, references in the specification to a first feature being formed over a second feature include embodiments in which the first feature is in direct contact with the second feature, and embodiments in which there are additional features between the first and second features, i.e., the first and second features are not in direct contact. Moreover, where specific reference numerals or designations are used in various embodiments, these are merely used to identify the embodiments of the invention, and are not intended to identify particular relationships between the various embodiments and/or structures discussed.
Furthermore, spatially relative terms, such as "below … …", "below", "lower", "above", "upper" and the like, may be used herein for ease of describing the relationship of one element(s) or feature(s) to another element(s) or feature(s) in the drawings and include different orientations of the device in use or operation and the orientation depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.
Although the steps in some of the described embodiments are performed in a particular order, these steps may be performed in other logical orders. In various embodiments, some of the described steps may be replaced or omitted, and other operations may be performed before, during, and/or after the described steps in embodiments of the invention. Other features may be added to the semiconductor device structure in embodiments of the present invention. Some features may be replaced or omitted in different embodiments.
The embodiment of the invention provides a method for forming a transistor device with a self-aligned contact structure, which comprises the steps of depositing an insulating layer above a gate structure, cutting the insulating layer to form a covering layer with the width larger than that of the gate structure, and then forming a self-aligned contact element, wherein the formed self-aligned contact element is electrically insulated from the gate structure through the covering layer and a side wall spacer, so that metal residues on the side wall spacer in the prior art are avoided; the height load of the finally formed NMOS/PMOS grid is difficult to control; the chamber door used in the process of recessing the gate structure is difficult to maintain (polymer rich).
Fig. 2 is a flow chart illustrating a method 20 for forming a transistor device having a self-aligned contact structure according to an embodiment of the present invention; fig. 3-9 are schematic cross-sectional views of stages in a method of forming a self-aligned contact structure according to the invention. The following describes the embodiment of the present invention with reference to the flowchart of fig. 2 and the cross-sectional views of fig. 3 to 9.
As illustrated in fig. 2 and 3, the method 20 begins with step 201 by providing a substrate 301 having a gate structure formed thereon, the gate structure including a gate and sidewall spacers.
In some embodiments, the substrate 301 in fig. 3 may be a semiconductor substrate, which may include an elemental semiconductor, such as silicon (Si), germanium (Ge), etc.; compound semiconductors such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), and the like; alloy semiconductors such as silicon germanium alloy (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium phosphide (GaInAsP), or combinations thereof.
Next, a gate structure is formed on the substrate 301, the gate structure including a gate and sidewall spacers formed on opposing sidewalls of the gate. In some embodiments, the gate electrode may comprise polysilicon, a metal (e.g., tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, the like, or combinations thereof), a metal alloy, a metal nitride (e.g., tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride, the like, or combinations thereof), a metal silicide (e.g., tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, the like, or combinations thereof), a metal oxide (e.g., ruthenium oxide, indium tin oxide, the like, or combinations thereof), other suitable materials, or combinations thereof. The gate electrode may be patterned by forming an electrode material on the substrate 301 using a chemical vapor deposition process (e.g., Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD)), a Physical Vapor Deposition (PVD) (e.g., resistance heating evaporation, electron beam evaporation, or sputtering), an electroplating process, an atomic layer deposition (ald) process, other suitable processes, or a combination thereof, and then forming the gate electrode by patterning using a photolithography and etching process.
In some embodiments, sidewall spacers are formed on opposing sidewalls of the gate. The sidewall spacers may be an oxide, a nitride, an oxynitride, a high-k material, a low-k material, or a combination thereof. The precursor material or reaction gas for forming the sidewall spacers may include Triethoxysilane (TRIES), Tetraethoxysilane (TEOS), bistriutylamino silane (BTBAS), O2、N2O, NO, other gases or materialsOr a combination of the foregoing. In some embodiments, the spacer material may be conformally deposited over the gate structure and substrate using chemical vapor deposition (e.g., High Density Plasma Chemical Vapor Deposition (HDPCVD), Atmospheric Pressure Chemical Vapor Deposition (APCVD), low pressure chemical vapor deposition, or plasma assisted chemical vapor deposition), atomic layer deposition, other suitable techniques, or a combination thereof, followed by an anisotropic etch back of the spacer material, leaving sidewall spacers on both sides of the gate.
In a preferred embodiment of the present invention, the gate is a metal gate, and the metal gate includes a high-K material layer 3021 and a metal layer 3022; the sidewall spacer includes a sidewall 3031 and an etch barrier layer 3032. The side wall is silicon dioxide, silicon nitride or a composition thereof. The etching barrier layer is silicon nitride. The forming process of the metal grid structure comprises the following steps of 1) depositing a polycrystalline silicon grid layer on a semiconductor substrate; 2) forming a semiconductor substrate provided with a polycrystalline silicon pattern by adopting photoetching and etching technologies based on a polycrystalline silicon grid mask; 3) forming a sidewall spacer adjacent to the gate on the semiconductor substrate in step 2); 4) the polysilicon is etched and a metal gate is deposited.
As illustrated in fig. 2 and 4, the method 20 continues with step 202 by depositing an insulating layer 304 over the gate structure. In some embodiments, the insulating layer 304 is a silicon nitride (silicon nitride) material in some embodiments. The insulating layer 304 may be formed using a suitable deposition process (e.g., a Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD)) or other suitable processes, or combinations thereof.
As shown in fig. 2 and 7, the method 20 continues with step 203 in which the insulating layer 304 is cut to form a capping layer 305 over the gate structure, as shown in fig. 7, wherein the width of the capping layer 305 is greater than the width of the gate structure, and the capping layer is silicon nitride, which is used because the silicon nitride has a good etching ratio with respect to the interlayer dielectric layer material. Specifically, as shown in fig. 5, first, a triple-layer photoresist layer 306 is formed over the insulating layer 304; in some embodiments, a three-layer mask layer may be formed over the insulating layer using chemical vapor deposition (e.g., high density plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, or plasma-assisted chemical vapor deposition), atomic layer deposition, physical vapor deposition process, electroplating, spin-on coating, other suitable techniques, or a combination thereof; then, as shown in fig. 6, one or more openings 307 are formed in the top layer of the triple photoresist layer by etching process; finally, the insulating layer is cut through the one or more openings to form the capping layer 305.
In the step of cutting the insulating layer to form the covering layer above the gate structure, the adopted covering layer mask can directly use the polycrystalline silicon gate mask, and only the horizontal position of the mask is required to be changed when the mask is used. The invention changes the existing manufacturing process, but the materials and equipment of the invention can generally continue to use the original materials, and the fluctuation of the production line transformation is small. It should be noted that, the size of the cover layer can be corrected by etching on the basis of using the polysilicon gate mask.
As illustrated in fig. 2 and 9, the method 20 continues with step 204 of forming a self-aligned contact element 308 over the semiconductor substrate 301, the self-aligned contact element 308 being electrically insulated from the gate structure by the capping layer 305 and the sidewall spacers, as illustrated in fig. 9. Specifically, as shown in fig. 8, first, an interlayer dielectric layer 310 is deposited over the capping layer 305; then forming a three-layer light resistance layer above the interlayer medium layer 310; in some embodiments, a triple layer photoresist layer may be formed over an insulating layer using chemical vapor deposition (e.g., high density plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, or plasma-assisted chemical vapor deposition), atomic layer deposition, physical vapor deposition process, electroplating, spin-on coating (spin-on coating), other suitable techniques, or combinations thereof; one or more openings 309 are then formed in the top layer of the tri-layer photoresist layer by an etching process, which may include a dry etching process (e.g., reactive ion etching, anisotropic plasma etching), a wet etching process, or a combination thereof, in some embodiments; finally, the cover layer is cut through the one or more openings to form self-aligned contact elements 308.
The self-aligned contact element of the invention is connected with the source/drain of the semiconductor substrate.
The present invention also provides an electronic device comprising a transistor device having a self-aligned contact structure fabricated according to the method of an exemplary embodiment of the present invention. The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including the transistor device. The electronic device has better performance due to the use of the transistor device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (9)

1. A method of forming a transistor device having a self-aligned contact structure, comprising:
forming a plurality of gate structures on a semiconductor substrate, the gate structures including gate gates and sidewall spacers formed on opposing sidewalls of the gate;
depositing a layer of insulating material above the gate structure to form an insulating layer;
cutting the insulating layer to form a covering layer above the gate structure;
forming a self-aligned contact element over the semiconductor substrate, wherein a width of the capping layer is greater than a width of the gate structure, the self-aligned contact element being electrically insulated from the gate structure by the capping layer and the sidewall spacer.
2. The method according to claim 1, wherein the step of cutting the insulating layer to form a covering layer over the gate structure comprises:
forming a photoresist layer over the insulating layer;
forming one or more openings in the photoresist layer by an etching process;
cutting the insulating layer through the one or more openings to form the capping layer.
3. The method of claim 1, wherein the step of forming a self-aligned contact element over the semiconductor substrate comprises:
depositing an interlayer dielectric layer above the covering layer;
forming a light resistance layer on the interlayer medium layer;
forming one or more openings in the photoresist layer by an etching process;
cutting the cover layer through the one or more openings to form the self-aligned contact elements.
4. A transistor device having a self-aligned contact structure, comprising:
a plurality of gate structures located over a semiconductor substrate, each of the gate structures including a gate and sidewall spacers formed on opposing sidewalls of the gate;
a covering layer formed on the surface of the gate structure; and
a self-aligned contact element over the semiconductor substrate, wherein a width of the capping layer is greater than a width of the gate structure, the self-aligned contact element being electrically insulated from the gate structure by the capping layer and the sidewall spacer.
5. The transistor device with the self-aligned contact structure according to claim 4, wherein the sidewall spacers comprise a sidewall spacer and an etch stop layer.
6. The transistor device with the self-aligned contact structure according to claim 5, wherein the sidewall spacers are silicon dioxide, silicon nitride or a combination thereof; the etching barrier layer is silicon nitride.
7. The transistor device with the self-aligned contact structure according to claim 4, wherein the gate is a metal gate comprising a high-K material layer and a metal layer.
8. The transistor device with the self-aligned contact structure according to claim 4, wherein the capping layer is silicon nitride.
9. An electronic device comprising the transistor device of claims 4-8.
CN202011599509.4A 2020-12-29 2020-12-29 Transistor device with self-aligned contact structure, electronic device and forming method Pending CN114695118A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202011599509.4A CN114695118A (en) 2020-12-29 2020-12-29 Transistor device with self-aligned contact structure, electronic device and forming method
PCT/CN2021/141850 WO2022143585A1 (en) 2020-12-29 2021-12-28 Transistor device having self-aligned contact structure, electronic apparatus, and forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011599509.4A CN114695118A (en) 2020-12-29 2020-12-29 Transistor device with self-aligned contact structure, electronic device and forming method

Publications (1)

Publication Number Publication Date
CN114695118A true CN114695118A (en) 2022-07-01

Family

ID=82131695

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011599509.4A Pending CN114695118A (en) 2020-12-29 2020-12-29 Transistor device with self-aligned contact structure, electronic device and forming method

Country Status (2)

Country Link
CN (1) CN114695118A (en)
WO (1) WO2022143585A1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7504287B2 (en) * 2007-03-22 2009-03-17 Advanced Micro Devices, Inc. Methods for fabricating an integrated circuit
US8202776B2 (en) * 2009-04-22 2012-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method for protecting a gate structure during contact formation
US9384988B2 (en) * 2013-11-19 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Gate protection caps and method of forming the same
CN105762108B (en) * 2014-12-19 2019-03-29 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN108962817B (en) * 2017-05-22 2020-11-27 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Also Published As

Publication number Publication date
WO2022143585A1 (en) 2022-07-07

Similar Documents

Publication Publication Date Title
KR102376508B1 (en) Integrated circuit devices and method for manufacturing the same
US11948839B2 (en) Power reduction in finFET structures
TWI736884B (en) Method for forming semiconductor device
KR20190013342A (en) Integrated Circuit devices
US11569125B2 (en) Etch profile control of interconnect structures
US10770361B2 (en) Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal
CN102487048A (en) Method for forming semiconductor device
US20190273149A1 (en) Wet process assisted approach for selective barrier metal patterning on high-k metal gate
US11101353B2 (en) Semiconductor device and method of manufacture
US20220293765A1 (en) Semiconductor structure with metal cap layer and method for manufacturing the same
TW202017014A (en) Method of forming semiconductor device
US11646373B2 (en) Vertical field effect transistor with bottom spacer
US20220077001A1 (en) Profile control of a gap fill structure
US20230215866A1 (en) Integrated circuit devices and methods of manufacturing the same
CN114695118A (en) Transistor device with self-aligned contact structure, electronic device and forming method
CN113161321A (en) Semiconductor structure and method of forming a semiconductor structure
CN113224006A (en) Metal gate modulator and in-situ forming method thereof
US20230386912A1 (en) Contact Structure For Semiconductor Device
US11476191B2 (en) Low resistance interconnect structure for semiconductor device
US20230068965A1 (en) Contact structure for semiconductor device
US20220216113A1 (en) Method for manufacturing metal oxide semiconductor transistor
US20230282729A1 (en) Work-Function Metal in Transistors and Method Forming Same
CN114678422A (en) Semiconductor structure and forming method thereof
CN117672834A (en) Method for preparing semiconductor structure and semiconductor structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20240308

Address after: 518000, Building D, 101, Zhongke Valley Industrial Park, Zhonghuan Avenue, Shanxia Community, Pinghu Street, Longgang District, Shenzhen City, Guangdong Province

Applicant after: Shenzhen Pengxin Microintegrated Circuit Manufacturing Co.,Ltd.

Country or region after: China

Address before: No. 16, Chuangxin Avenue, Ningxi street, Zengcheng District, Guangzhou, Guangdong 511300

Applicant before: Guangzhou integrated circuit technology Research Institute Co.,Ltd.

Country or region before: China