CN114678422A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN114678422A
CN114678422A CN202011568825.5A CN202011568825A CN114678422A CN 114678422 A CN114678422 A CN 114678422A CN 202011568825 A CN202011568825 A CN 202011568825A CN 114678422 A CN114678422 A CN 114678422A
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Prior art keywords
conductive
dielectric layer
forming
opening
layer
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CN202011568825.5A
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Chinese (zh)
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郑二虎
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202011568825.5A priority Critical patent/CN114678422A/en
Publication of CN114678422A publication Critical patent/CN114678422A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the method comprises the following steps: providing a substrate; forming a plurality of source-drain structures in the substrate; forming a first dielectric layer on the substrate and the surfaces of the source drain structures; forming a first conductive structure positioned on the surface of the source drain structure in the first dielectric layer; after the first conductive structure is formed, a sacrificial layer is formed on the top surface of the first conductive structure by adopting a selective film forming process; and after the sacrificial layer is formed, forming a second dielectric layer on the surface of the first dielectric layer, wherein the sacrificial layer and the second dielectric layer are made of different materials. Thus, the performance and reliability of the formed semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in the integrated circuit is continuously reduced, so that the operation speed of the whole integrated circuit can be effectively increased. As the size of the components is required to be smaller and smaller, the size of the conductive structures formed in connection with the semiconductor devices is correspondingly smaller and smaller.
However, the performance and reliability of existing semiconductor structures still remain to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aim to improve the performance and reliability of the formed semiconductor structure while realizing the self-alignment process of etching.
To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: a substrate; a plurality of source-drain structures located in the substrate; the first dielectric layers are positioned on the surfaces of the substrate and the source drain structures; the first conductive structure is positioned in the first dielectric layer and positioned on the surface of the source drain structure, and the top surface of the first conductive structure is flush with the surface of the first dielectric layer; a conductive protection structure on a top surface of the first conductive structure; and the second dielectric layer is positioned on the surface of the first dielectric layer and is also positioned on the side wall surface of the conductive protection structure, and the material of the second dielectric layer is different from that of the conductive protection structure.
Optionally, the material of the first conductive structure comprises cobalt, ruthenium or tungsten.
Optionally, the thickness of the conductive protection structure ranges from 50 angstroms to 200 angstroms.
Optionally, the material of the conductive protection structure includes a dielectric material or a metal compound.
Optionally, the second dielectric layer and the conductive protection structure further have a first conductive opening therein, where the first conductive opening exposes a portion of the top surface of the first conductive structure; the semiconductor structure further includes: a second conductive structure located within the first conductive opening.
Optionally, the method further includes: the first dielectric layer is also positioned on the side wall surface of the side wall, and the conductive protection structure and the gate protection structure are made of the same material.
Optionally, the thickness of the gate protection structure ranges from 50 angstroms to 200 angstroms.
Optionally, in a direction perpendicular to the extending direction of the gate structure, a second conductive opening is further formed in the second dielectric layer, and a part of the top surface of the gate structure is exposed by the second conductive opening; a third conductive structure located within the second conductive opening.
Optionally, the base includes a substrate and a plurality of fin structures located on the substrate, and the gate structure crosses over the fin structures.
Optionally, the method further includes: and the third dielectric layer is positioned on the surface of the second dielectric layer and the surface of the conductive protection structure.
The technical solution of the present invention also provides a semiconductor structure, including: a substrate; a plurality of source-drain structures located in the substrate; the first dielectric layers are positioned on the surfaces of the substrate and the source drain structures; the first conductive structure is positioned in the first dielectric layer and positioned on the surface of the source drain structure, and the top surface of the first conductive structure is flush with the surface of the first dielectric layer; a sacrificial layer on a top surface of the first conductive structure; and the second dielectric layer is positioned on the surface of the first dielectric layer and is also positioned on the side wall surface of the sacrificial layer, and the material of the second dielectric layer is different from that of the sacrificial layer.
Optionally, the material of the first conductive structure comprises cobalt, ruthenium or tungsten.
Optionally, the material of the sacrificial layer includes titanium nitride or a metal material.
Optionally, the metal material includes: tungsten, ruthenium or platinum.
Optionally, the material of the sacrificial layer comprises a dielectric material.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate; forming a plurality of source-drain structures in the substrate; forming a first dielectric layer on the substrate and the surfaces of the source drain structures; forming a first conductive structure positioned on the surface of the source drain structure in the first dielectric layer; after the first conductive structure is formed, a sacrificial layer is formed on the top surface of the first conductive structure by adopting a selective film forming process; and after the sacrificial layer is formed, forming a second dielectric layer on the surface of the first dielectric layer, wherein the sacrificial layer and the second dielectric layer are made of different materials.
Optionally, the material of the first conductive structure comprises cobalt, ruthenium or tungsten.
Optionally, the material of the second dielectric layer includes a dielectric material or a metal compound.
Optionally, the material of the sacrificial layer is a dielectric material; the method for forming the semiconductor structure further comprises the following steps: etching part of the sacrificial layer until a first conductive opening is formed in the second dielectric layer, wherein the first conductive opening exposes part of the top surface of the first conductive structure; and forming a second conductive structure in the first conductive opening.
Optionally, the material of the sacrificial layer includes titanium nitride or a metal material, and the selective film forming process includes a selective metal electroless plating process.
Optionally, the metal material includes: tungsten, ruthenium or platinum.
Optionally, the process parameters of the selective metal electroless plating process include: the pressure range is 20 Pa to 100 Pa; the gases used included: SiH4、H2、WF6Wherein, WF6The gas flow range of (2) sccm to 50 sccm; the temperature range is 100 ℃ to 400 ℃.
Optionally, the method further includes: after the second dielectric layer is formed, etching back and removing the sacrificial layer, and forming a first opening in the second dielectric layer, wherein the first opening exposes the top surface of the first conductive structure; and forming a conductive protection structure in the first opening, wherein the conductive protection structure is made of a material different from that of the second dielectric layer.
Optionally, the process for etching back the sacrificial layer includes a plasma etching process, and process parameters of the plasma etching process include: pressure ranges from 40 mTorr to 300 mTorr; the source power range is 500 watts to 1500 watts; the gases used included: SiH4HBr and SF6One or more of (a).
Optionally, the material of the conductive protection structure includes a dielectric material or a metal compound.
Optionally, the method further includes: forming a conductive opening mask layer on the second dielectric layer and the conductive protection structure, wherein the conductive opening mask layer is internally provided with a first conductive mask opening, and the first conductive mask opening exposes part of the surface of the conductive protection structure and part of the surface of the second dielectric layer adjacent to the conductive protection structure; etching part of the conductive protection structure by taking the conductive opening mask layer and the second dielectric layer as masks until a first conductive opening is formed in the second dielectric layer and the conductive protection structure, and the first conductive opening exposes part of the top surface of the first conductive structure; and forming a second conductive structure in the first conductive opening.
Optionally, in the process of etching a part of the conductive protection structure, the etching selection ratio of the conductive protection structure to the second dielectric layer is more than 5: 1.
Optionally, the method further includes: and forming a third dielectric layer on the surface of the second dielectric layer and the surface of the conductive protection structure before etching part of the conductive protection structure.
Optionally, the method further includes: before the first conductive structure is formed, a plurality of grid structures, grid protection structures located on the top surfaces of the grid structures and side walls located on the side wall surfaces of the grid structures and the grid protection structures are formed on the surface of the substrate, the first dielectric layer is also located on the side wall surfaces of the side walls, and the conductive protection structures and the grid protection structures are made of the same material.
Optionally, the thickness of the gate protection structure ranges from 50 angstroms to 200 angstroms.
Optionally, the conductive opening mask layer is further provided with a plurality of second conductive mask openings, and the second conductive mask openings expose part of the gate protection structure; the method for forming the semiconductor structure further comprises the following steps: etching the gate protection structure while etching the conductive protection structure until a second conductive opening is formed in the second dielectric layer and the gate protection structure, wherein the second conductive opening exposes part of the top surface of the gate structure; and forming a third conductive structure in the second conductive opening.
Optionally, the base includes a substrate and a plurality of fin structures located on the substrate, and the gate structure crosses over the fin structures.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, after the first conductive structure is formed, the sacrificial layer is formed on the top surface of the first conductive structure by adopting a selective film forming process, so that the sacrificial layer can be only positioned on the top surface of the first conductive structure; meanwhile, after the sacrificial layer is formed, a second dielectric layer which is different from the sacrificial layer in material is formed on the surface of the first dielectric layer, so that the second dielectric layer and the sacrificial layer can have different etching rates in the subsequent sacrificial layer etching process, on one hand, when the sacrificial layer is made of dielectric material, the sacrificial layer can be directly used as a conductive protection structure, and through the different etching rates, partial sacrificial layer can be etched in the subsequent process to form a conductive opening exposing the first conductive structure, so that the etching self-alignment process is realized. On the other hand, when the sacrificial layer is made of a non-dielectric material, a space can be provided for forming a conductive protection structure which is made of a dielectric material and is different from the second dielectric layer on the top surface of the first conductive structure after the sacrificial layer is removed easily at different etching rates, so that the second dielectric layer and the conductive protection structure can have different etching rates in the subsequent process of etching the conductive protection structure, and further, the etching self-alignment process can be realized when part of the conductive protection structure is etched subsequently to form a conductive opening exposing the first conductive structure. On the basis, in the process of forming the sacrificial layer or the conductive protection structure, no etching process is carried out on the material of the first conductive structure, so that after the first conductive structure is formed, the influence of the etching process on the first conductive structure is small, and further, in the semiconductor structure, the consistency of the electrical characteristics of the first conductive structures in all the regions is high, so that the stability of the electrical characteristics of the semiconductor structure is improved, and the performance and the reliability of the semiconductor structure are improved. In conclusion, the semiconductor structure can improve the stability of the electrical characteristics of the semiconductor structure and the performance and reliability of the semiconductor structure while realizing the self-alignment process of etching to form the conductive opening.
Drawings
FIGS. 1-3 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 4 to 14 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, the performance and reliability of existing semiconductor structures still remain to be improved.
The reason why the performance and reliability of the semiconductor structure still remain to be improved is described in detail below with reference to the accompanying drawings.
Fig. 1 to 3 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a base 100 is provided, where the base 100 includes a substrate (not shown) and a plurality of fin structures (not shown) located on the substrate and separated from each other; a first dielectric layer (not shown) is formed on the surface of the substrate 100, and the first dielectric layer covers a portion of the sidewall surface of the fin structure.
With reference to fig. 1, a second dielectric layer 110 is formed on the surface of the first dielectric layer, the second dielectric layer 110 has a plurality of gate openings (not shown) crossing the fin structure, and the gate openings expose the surface and a portion of the sidewall surface of the fin structure; and forming a gate structure 120, a gate protection structure 130 located on the top surface of the gate structure 120, and sidewalls 140 located on the sidewall surfaces of the gate structure 120 and the gate protection structure 130 in the gate opening.
Referring to fig. 2, a first conductive opening mask layer (not shown) is formed on the top surface of the gate protection structure 130, the top surface of the sidewall 140, and the surface of the second dielectric layer 110, and the first conductive opening mask layer has a plurality of first conductive mask openings (not shown); etching the second dielectric layer 110 by using the first conductive opening mask layer as a mask until the surface of the substrate 100 is exposed to form a first conductive opening (not shown); an initial conductive structure 150 is formed within the first conductive opening.
The initial conductive structure 150 is made of cobalt, so that the parasitic resistance of the subsequently formed conductive structure is small due to the material characteristics of cobalt.
Referring to fig. 3, the initial conductive structure 150 is etched back to form a first conductive structure 151, and a conductive protection structure opening (not shown) located on the first conductive structure 151 is formed in the second dielectric layer 110; a conductive guard structure 160 is formed within the conductive guard structure opening.
Then, forming a second conductive opening mask layer (not shown) on the surface of the conductive protection structure 160 and the surface of the second dielectric layer 110, where the second conductive opening mask layer has a plurality of second conductive mask openings (not shown), and the second conductive mask openings expose a part of the conductive protection structure 160 and the top surfaces of the sidewalls 140; etching a part of the conductive protection structure 160 by using the second conductive opening mask layer as a mask until the top surface of the first conductive structure 151 is exposed, and forming a second conductive opening (not shown) in the conductive protection structure 160 and the second dielectric layer 110; a second conductive structure (not shown) is formed within the second conductive opening, and the second conductive structure is electrically connected to the first conductive structure 151.
In the above embodiment, the conductive protection structure 160 having a Critical Dimension (CD) smaller than the limit dimension of the conventional photolithography process can be formed by etching back the initial conductive structure 150 to form the conductive protection structure opening. On this basis, since the material of the formed conductive protection structure 160 is different from the material of the sidewall 140, the etching self-alignment process can be realized in the process of forming the second conductive opening by using different etching rates for the material of the conductive protection structure 160 and the material of the sidewall 140.
Specifically, in the vertical direction of the extending direction of the gate structure 120, the width of the second conductive mask opening is greater than the width of the second conductive opening (the second conductive mask opening not only exposes the top surface of the conductive protection structure 160, but also exposes a part of the top surface of the sidewall 140), so as to increase the process window of the etching process for forming the second conductive opening, and reduce the difficulty of the photolithography process. Meanwhile, through the self-alignment process of the etching, a second conductive opening with the critical dimension smaller than the width of the second conductive mask opening can be formed.
However, while the self-aligned process of the etching is realized, since the chemical stability of cobalt is poor, therefore, when the initial conductive structure 150 is etched back, the chemical reaction during the etching process is active, the uniformity of the thickness, etc. of the etch by-products formed on the surface of the initial conductive structure 150 is poor, and thus, the difficulty in controlling the etching process for etching back the initial conductive structure 150 is high, resulting in poor consistency between the conductive structures 151 in each region in the formed semiconductor structure, for example, the surface roughness of the conductive structures 151 is not uniform in each region, the height H (shown in fig. 3) of the conductive structures 151 is not uniform in each region, etc., resulting in poor uniformity of electrical characteristics between the conductive structures 151 in each region in the semiconductor structure, the electrical characteristics of the semiconductor structure are unstable, and the performance and reliability of the semiconductor structure are poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, where after a first conductive structure is formed, a selective film formation process is used to form a sacrificial layer on a top surface of the first conductive structure, and after the sacrificial layer is formed, a second dielectric layer is formed on a surface of the first dielectric layer, where the sacrificial layer and the second dielectric layer are made of different materials, so that a self-alignment process of etching is implemented, and at the same time, performance and reliability of the formed semiconductor structure are improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 14 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 4, a substrate is provided.
In this embodiment, the base includes a substrate 200 and a plurality of fin structures 201 located on the substrate 200 and separated from each other.
The material of the substrate 200 comprises a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.
In other embodiments, the fin structure comprises: the fin structure comprises a plurality of fin sacrificial layers arranged in a direction vertical to the surface of the substrate, and nano sheets positioned between the adjacent fin sacrificial layers.
Referring to fig. 5, a plurality of source and drain structures 202 are formed in the substrate.
In this embodiment, the method for forming the plurality of source/drain structures 202 includes: forming a plurality of mutually-separated false gate structures 209 on the surface of the substrate; forming a side wall 210 on the side wall surface of the dummy gate structure 209; forming source and drain openings (not shown) in the fin structures 201 on two sides of the dummy gate structure 209; and forming a source-drain structure 202 in the source-drain opening by adopting an epitaxial growth process.
In the process of forming the source-drain structure 202, the sidewall spacers 210 are used to define a formation position of the source-drain structure 202.
In this embodiment, the material of the dummy gate structure 209 includes polysilicon.
In this embodiment, the dummy gate structure 209 is also used to define a pattern of a gate structure in a subsequent process of forming the gate structure.
In other embodiments, the dummy gate structure is directly used as a gate structure.
In this embodiment, the method for forming the dummy gate structure 209 includes: forming a dummy gate material film (not shown) on the substrate covering the surface of the fin structure 201; and patterning the dummy gate material film until the surface of the substrate is exposed so as to form a plurality of mutually discrete dummy gate structures 209 on the substrate, wherein the dummy gate structures 209 cross over the fin structure 201, and the top surface of the dummy gate structures 209 is higher than the top surface of the fin structure 201.
The forming process of the dummy gate material film comprises the following steps: an epitaxial growth process, or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, among others.
In this embodiment, the method for forming the sidewall spacers 210 includes: depositing a side wall material film (not shown) on the surface of the substrate and the surface of the dummy gate structure 209; and etching the side wall material film back by adopting an anisotropic etching process until the side wall material film on the surface of the substrate and on the top surface of the pseudo gate structure 209 is removed, and forming a side wall 210 on the side wall of the pseudo gate structure 209.
The material of the sidewall spacers 210 includes a low-k dielectric material (k is less than 3.9), or a combination of low-k dielectric materials. The low-k dielectric material comprises SiOC, SiOCN, SiBCN and the like.
Referring to fig. 6, a first dielectric layer 220 is formed on the substrate and the surfaces of the source/drain structures 202, and the first dielectric layer 220 is also located on the sidewall surface of the sidewall spacer 210.
The first dielectric layer 220 provides support for the subsequent formation of the gate structure and the first conductive structure.
In this embodiment, the first dielectric layer 220 is made of silicon oxide.
In other embodiments, the material of the first dielectric layer includes at least one of SiOCH, SiOH, and SiCN.
In this embodiment, the method for forming the first dielectric layer 220 includes: forming a first dielectric material layer (not shown) on the dummy gate structure 209 and the substrate surface, wherein the surface of the first dielectric material layer is higher than the top surface of the dummy gate structure 209; and flattening the first dielectric material layer until the top surface of the pseudo gate structure 209 is exposed.
The forming process of the first dielectric material layer comprises the following steps: a spin coating process, a deposition process such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, etc.
The process for flattening the first medium material layer comprises the following steps: etch back process or chemical mechanical polishing process.
In this embodiment, before forming the first dielectric material layer, an etching stop layer (not shown) is formed on the substrate surface, the surface of the source/drain structure 202, and the sidewall of the sidewall spacer 210.
The side wall 210 and the source-drain structure 202 can be protected by the etching stop layer in the subsequent etching process for forming the first conductive opening, so that the damage to the surfaces of the side wall 210 and the source-drain structure 202 caused by the etching process is reduced, and the performance of the semiconductor structure is improved.
In this embodiment, the material of the etch stop layer includes silicon nitride.
In this embodiment, before forming the dummy gate structure 209, a base dielectric layer (not shown) is further formed on the surface of the substrate 200, and the base dielectric layer is further located on a portion of a sidewall surface of the fin structure 201. The substrate dielectric layer has the following functions: electrically isolating between adjacent fin structures 201 and between the semiconductor device and the substrate.
With reference to fig. 6, after the first dielectric layer 220 is formed, the dummy gate structure 209 is removed, and a plurality of gate openings (not shown) are formed in the first dielectric layer 220; filling the gate opening with a gate structure material to form a plurality of initial gate structures 211 on the substrate, the initial gate structures 211 crossing the fin structures 201, the sidewalls 210 being on the sidewalls of the initial gate structures 211, and the source drain structures 202 being on the substrate on both sides of the initial gate structures 211.
In this embodiment, the method for forming the initial gate structure 211 includes: forming a gate dielectric material layer (not shown) on the surface of the first dielectric layer 220 and the inner wall surface of the gate opening; forming a work function material layer (not shown) on the surface of the gate dielectric material layer; forming a gate electrode material layer (not shown) on the surface of the work function material layer, wherein the gate electrode material layer fills the gate opening; and flattening the gate electrode material layer, the work function material layer and the gate dielectric material layer until the surface of the first dielectric layer 220 is exposed to form the initial gate structure 211.
Referring to fig. 7, the initial gate structure 211 is etched back to form a gate structure 212, and a gate protection structure opening (not shown) is formed in the first dielectric layer 220, wherein the gate protection structure opening exposes a top surface of the gate structure 212; a gate protection structure 213 is formed in the gate protection structure opening, and the gate protection structure 213 is located on the top surface of the gate structure 212.
In this embodiment, the gate structure 212 includes: a gate dielectric layer (not shown) on the inner wall surface of the gate opening, a work function layer (not shown) on the surface of the gate dielectric layer, and a gate electrode layer (not shown) on the surface of the work function layer.
The material of the gate dielectric layer comprises a high dielectric constant material (the dielectric constant is larger than 3.9). The high dielectric constant material includes: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, or the like.
The material of the gate electrode layer includes a metal material such as: one or more of tungsten, copper, aluminum, titanium and tantalum.
The material of the work function layer comprises titanium nitride, tantalum nitride or titanium aluminum.
Specifically, the gate structures 212 are formed by back-etching the initial gate structure 211, so that correspondingly, the plurality of gate structures 212 are located on the substrate, the plurality of gate structures 212 are also located in the first dielectric layer 220, the gate structures 212 cross the fin structure 201, the source-drain structures 202 are located in the substrate on both sides of the gate structures 212, and the side walls 210 are located on the side wall surfaces of the gate structures 212.
In this embodiment, the sidewall spacers 210 are also located on the sidewall surfaces of the gate protection structure 213.
In this embodiment, on one hand, the gate protection structure 213 is used to define the position of the sacrificial layer in the subsequent process of forming the sacrificial layer. Specifically, by forming the gate protection structure 213, the first dielectric layer 220 and the sidewall spacers 210, a sacrificial layer can be formed only on the top surface of the first conductive structure by a subsequent process of forming a sacrificial layer, that is, a selective film forming process. On the other hand, the gate protection structure 213 can protect the gate structure 212 in subsequent etching and other processes, and reduce damage to the gate structure 212 caused by the etching and other processes, thereby improving the performance of the semiconductor structure.
Moreover, by selecting a material different from that of the sidewall 210 to form the gate protection structure 213, the sidewall 210 and the gate protection structure 213 can have different etching rates in an etching process for forming a second conductive opening in the subsequent process, so that the self-alignment of a conductive opening pattern is realized when the second conductive opening is formed in the subsequent process.
In this embodiment, the material of the gate protection structure 213 includes silicon nitride.
In this embodiment, the process of etching back the initial gate structure 211 includes at least one of a dry etching process and a wet etching process.
In this embodiment, the method for forming the gate protection structure 213 further includes: forming a gate protection structure material layer (not shown) in the gate protection structure opening and on the surface of the first dielectric layer 220; and flattening the gate protection structure material layer until the surface of the first dielectric layer 220 is exposed.
The process of forming the gate protection structure material layer includes a spin coating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The process for flattening the gate protection structure material layer comprises a chemical mechanical polishing process, a dry etching process or a wet etching process and the like.
In the present embodiment, the thickness of the gate protection structure 213 ranges from 50 angstroms to 200 angstroms.
The thickness of the gate protection structure 213 is too thin, which, on one hand, makes the process of forming the gate protection structure 213 more difficult, and on the other hand, is not conducive to protecting the gate structure 212 in the subsequent etching process and the like, resulting in poor performance of the semiconductor structure. The gate protection structure 213 is too thick, which increases the aspect ratio of the subsequently formed second conductive opening, not only increases the difficulty of the etching process for etching and forming the second conductive opening, resulting in the deterioration of the appearance of the formed second conductive opening, but also is not beneficial to filling the material of the third conductive structure in the second conductive opening, increases the risk of having defects such as voids in the formed third conductive structure, and also causes the deterioration of the performance of the semiconductor structure. Therefore, when a suitable thickness range is selected, that is, the thickness range of the gate protection structure 213 is 50 angstroms to 200 angstroms, the process difficulty of subsequently forming the second conductive opening and the third conductive structure can be reduced, and simultaneously, the morphology and the quality of the third conductive structure are improved, and the defects in the third conductive structure are reduced, so as to improve the performance of the semiconductor structure.
Referring to fig. 8, after the gate protection structure 213 is formed, a first conductive structure 230 located on the surface of the source/drain structure 202 is formed in the first dielectric layer 220.
In this embodiment, the material of the first conductive structure 230 includes cobalt. Therefore, under the material characteristic that the resistance of cobalt is small, the parasitic resistance of the formed first conductive structure 230 is small, which is beneficial to better improving the performance of the semiconductor structure.
In other embodiments, the material of the first conductive structure comprises ruthenium or tungsten.
Specifically, the method of forming the first conductive structure 230 includes: etching the first dielectric layer 220 between the adjacent gate structures 212 until the surface of the source drain structure 202 is exposed, and forming an opening (not shown) in the first dielectric layer 220; forming a first conductive structure material layer in the opening, on the surface of the first dielectric layer 220, on the top surface of the gate protection structure 213 and on the top surface of the sidewall 210; and flattening the first conductive structure material layer until the surface of the first dielectric layer 220, the top surface of the gate protection structure 213 and the top surfaces of the side walls 210 are exposed, so as to form a first conductive structure 230.
Referring to fig. 9, after the first conductive structure 230 is formed, a sacrificial layer 240 is formed on the top surface of the first conductive structure 230 by a selective film forming process.
In this embodiment, the material of the sacrificial layer 240 is a metal material, and the selective film forming process includes a selective metal electroless plating process.
In this embodiment, the sacrificial layer 240 is used to define the shape and position of the conductive protection structure to be formed later. Specifically, in this embodiment, a space can be provided for forming the conductive protection structure by removing the sacrificial layer 240.
Specifically, in the present embodiment, a selective metal electroless plating process is used to form a sacrificial layer 240 on the top surface of the first conductive structure 230.
In this embodiment, since a space is provided for forming the conductive protection structure by removing the sacrificial layer 240, requirements on the pattern precision and quality of the formed sacrificial layer 240 are low, and the difficulty of the process for forming the sacrificial layer 240 is reduced.
In this embodiment, the process parameters of the selective metal electroless plating process include: the pressure range is 20 Pa to 100 Pa; the gases used included: SiH4、H2、WF6Wherein, WF6The gas flow range of (2) sccm to 50 sccm; the temperature range is 100 ℃ to 400 ℃.
In this embodiment, the material of the sacrificial layer 240 includes tungsten. Therefore, under the material characteristic that the material stability of tungsten is high, the material stability of the formed sacrificial layer 240 is high, which is beneficial to reducing the difficulty of the process for etching the sacrificial layer 240, and is beneficial to reducing the influence of the process for etching the sacrificial layer 240 on the first conductive structure 230 better, so as to improve the performance of the semiconductor structure.
In other embodiments, the metallic material comprises ruthenium or platinum.
In other embodiments, the material of the sacrificial layer comprises titanium nitride.
The sacrificial layer 240 has a thickness ranging from 50 angstroms to 200 angstroms. Specifically, in this embodiment, the thickness of the sacrificial layer 240 is used to define the thickness of the conductive protection structure to be formed later.
In another embodiment, the material of the sacrificial layer is a dielectric material. In particular, in another embodiment, the sacrificial layer directly serves as a conductive protection structure.
Referring to fig. 10, after the sacrificial layer 240 is formed, a second dielectric layer 250 is formed on the surface of the first dielectric layer 220, and the sacrificial layer 240 and the second dielectric layer 250 are made of different materials.
Since a sacrificial layer is formed on the top surface of the first conductive structure 230 by a selective film forming process after the first conductive structure 230 is formed, the sacrificial layer can be only on the top surface of the first conductive structure 230; meanwhile, after the sacrificial layer is formed, the second dielectric layer 250 made of a material different from that of the sacrificial layer is formed on the surface of the first dielectric layer 220, so that the second dielectric layer 250 and the sacrificial layer can have different etching rates in a subsequent sacrificial layer etching process.
Specifically, in the present embodiment, the material of the sacrificial layer 240 is a non-dielectric material. Through the different etching rates, the sacrificial layer 240 made of a non-dielectric material can be removed easily, so as to provide a space for forming a conductive protection structure made of a dielectric material, which is different from the material of the second dielectric layer 250, on the top surface of the first conductive structure 230. On this basis, in the subsequent process of etching the conductive protection structure, different etching rates can be applied to the second dielectric layer 250 and the conductive protection structure, and then, when a part of the conductive protection structure is subsequently etched to form a conductive opening exposing the first conductive structure 230, a self-aligned process of etching can be realized.
In another embodiment, the material of the sacrificial layer is a dielectric material, and the sacrificial layer can directly serve as a conductive protection structure. Through the different etching rates, the etching self-alignment process can be realized when part of the sacrificial layer is etched in the subsequent process to form the conductive opening exposing the first conductive structure.
On this basis, in the process of forming the sacrificial layer 240 (in this embodiment) or the conductive protection structure (in another embodiment), there is no etching process for the material of the first conductive structure 230, so that after the first conductive structure 230 is formed, the etching process has a small influence on the first conductive structure 230, and further, in the semiconductor structure, the consistency of the electrical characteristics of the first conductive structures 230 in each region is high, thereby improving the stability of the electrical characteristics of the semiconductor structure, and improving the performance and reliability of the semiconductor structure. In conclusion, the semiconductor structure can improve the stability of the electrical characteristics of the semiconductor structure and the performance and reliability of the semiconductor structure while realizing the self-alignment process of etching to form the conductive opening.
In this embodiment, the method for forming the second dielectric layer 250 includes: forming a second dielectric material layer on the surface of the first dielectric layer 220, the top surface of the gate protection structure 213, the top surface of the sidewall 210, and the surface of the sacrificial layer 240; and planarizing the second dielectric material layer until the top surface of the sacrificial layer 240 is exposed.
The process of forming the second dielectric material layer includes a spin-on process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.
The process for planarizing the second dielectric material layer comprises a dry etching process, a wet etching process or a chemical mechanical polishing process.
In this embodiment, the material of the second dielectric layer 250 includes a dielectric material or a metal compound. Specifically, the dielectric material includes SiCO, SiCN, SiN, SiOCN, or SiBCN. The metal compound comprises TiN, AlN, TiO or AlO.
Specifically, in this embodiment, the second dielectric layer 250 is SiCO.
Referring to fig. 11, after the second dielectric layer 250 is formed, the sacrificial layer 240 is etched back and removed, and a first opening 251 is formed in the second dielectric layer 250, wherein the first opening 251 exposes the top surface of the first conductive structure 230.
The first opening 251 provides a space for forming a conductive protection structure.
In this embodiment, the process of etching back the sacrificial layer 240 includes a plasma etching process, and process parameters of the plasma etching process include: pressure ranges from 40 mTorr to 300 mTorr; the source power range is 500 watts to 1500 watts; the gases used included: SiH4HBr and SF6One or more of (a).
Referring to fig. 12, a conductive protection structure 260 is formed in the first opening 251, wherein the conductive protection structure 260 and the second dielectric layer 250 are made of different materials.
Specifically, the conductive protection structure 260 is located on the top surface of the first conductive structure 230.
Since the conductive protection structure 260 is located on the top surface of the first conductive structure 230, the distance between the subsequently formed second conductive structure and the top surface of the gate structure 213 is large, and the risk of short circuit between the second conductive structure and the gate structure 213 is small, so that a thinner gate protection structure 213 can be formed. Because the thin gate protection structure 213 can be formed, the dummy gate structure 209 and the first conductive structure 230 with small height can be formed, so that the material filling during the formation of the dummy gate structure 209 and the first conductive structure 230 is facilitated, the process window for forming the dummy gate structure 209 and the first conductive structure 230 is further increased, and the process difficulty for forming the semiconductor structure is reduced.
The material of the conductive protection structure 260 includes a dielectric material or a metal compound. Specifically, the dielectric material includes SiCO, SiCN, SiN, SiOCN, or SiBCN. The metal compound comprises TiN, AlN, TiO or AlO.
In this embodiment, the material of the conductive protection structure 260 is the same as the material of the gate protection structure 213. That is, the conductive protection structure 260 is made of silicon nitride.
Since the material of the conductive protection structure 260 is the same as that of the gate protection structure 213, the conductive protection structure 260 and the gate protection structure 213 can be etched simultaneously to form the first conductive opening and the second conductive opening, so that the process steps and time for forming the semiconductor structure are reduced, and the efficiency for forming the semiconductor structure is improved.
In this embodiment, the method for forming the conductive protection structure 260 includes: forming a conductive protection structure material layer on the surface of the second dielectric layer 250 and in the first opening 251; and flattening the conductive protection structure material layer until the surface of the second dielectric layer 250 is exposed.
The process of forming the conductive protection structure material layer includes a spin coating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.
The process for planarizing the conductive protection structure material layer comprises a dry etching process, a wet etching process or a chemical mechanical polishing process.
Referring to fig. 13, a conductive opening mask layer 280 is formed on the second dielectric layer 250 and the conductive protection structure 260, wherein the conductive opening mask layer 280 has a first conductive mask opening 281 therein, and the first conductive mask opening 281 exposes a portion of the surface of the conductive protection structure 260 and a portion of the surface of the second dielectric layer 250 adjacent to the conductive protection structure 260; and etching a part of the conductive protection structure 260 by using the conductive opening mask layer 280 and the second dielectric layer 250 as masks until a first conductive opening 271 is formed in the second dielectric layer 250 and the conductive protection structure 260, wherein a part of the top surface of the first conductive structure 230 is exposed by the first conductive opening 271.
Since the first conductive mask opening 281 not only exposes a portion of the surface of the conductive protection structure 260, but also exposes a portion of the surface of the second dielectric layer 250 adjacent to the conductive protection structure 260, a process window of a photolithography process for forming the first conductive mask opening 281 is increased, and a process difficulty is reduced.
The first conductive opening 271 provides a space for a second conductive structure to be formed subsequently.
In this embodiment, in the process of etching a portion of the conductive protection structure 260, the etching selection ratio of the conductive protection structure 260 to the second dielectric layer 250 is greater than 5: 1. Thus, with the larger etching selection ratio, a self-aligned process of etching can be realized when the first conductive opening 271 is formed.
In this embodiment, the conductive mask layer 280 further has a plurality of second conductive mask openings 282 therein, and the second conductive mask openings 282 expose a portion of the gate protection structure 213.
In this embodiment, the method for forming a semiconductor structure further includes: and etching the gate protection structure 213 while etching the conductive protection structure 260 until a second conductive opening 272 is formed in the second dielectric layer 250 and the gate protection structure 213, wherein the second conductive opening 272 exposes a part of the top surface of the gate structure 212.
The second conductive opening 272 provides a space for a third conductive structure to be formed subsequently.
In other embodiments, a portion of the conductive protection structure 260 and a portion of the gate protection structure 213 are etched separately.
In another embodiment, the sacrificial layer directly serves as a conductive protection structure. The method for forming the semiconductor structure further comprises the following steps: and etching part of the sacrificial layer until a first conductive opening is formed in the second dielectric layer, wherein the first conductive opening exposes part of the top surface of the first conductive structure.
In this embodiment, before etching a portion of the conductive protection structure 260, a third dielectric layer 270 is formed on the surface of the second dielectric layer 250 and the surface of the conductive protection structure 260.
In this embodiment, after the first conductive opening 271 is formed, the conductive opening mask layer 280 is removed.
Referring to fig. 14, a second conductive structure 291 is formed in the first conductive opening 271.
In this embodiment, a third conductive structure 292 is formed within the second conductive opening 272 at the same time as the second conductive structure 291 is formed.
The method of forming the second and third conductive structures 291 and 292 includes: forming a conductive material layer (not shown) in the first conductive opening 271, the second conductive opening 272, and the surface of the third dielectric layer 270; and planarizing the conductive material layer until the surface of the third dielectric layer 270 is exposed.
The process of forming the conductive material layer includes a spin-on process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The process for planarizing the conductive material layer includes a dry etching process, a wet etching process or a chemical mechanical polishing process.
Accordingly, the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 10, including: a substrate 200; a plurality of source-drain structures 202 located within the substrate 200; the first dielectric layer 220 is positioned on the surface of the substrate 200 and the surfaces of the source drain structures 202; a first conductive structure 230 located in the first dielectric layer 220 and located on the surface of the source drain structure 202, wherein the top surface of the first conductive structure 230 is flush with the surface of the first dielectric layer 220; a sacrificial layer 240 on a top surface of the first conductive structure 230; and a second dielectric layer 250 positioned on the surface of the first dielectric layer 220, wherein the second dielectric layer 250 is also positioned on the sidewall surface of the sacrificial layer 240, and the material of the second dielectric layer 250 is different from that of the sacrificial layer 240.
In this embodiment, the base includes a substrate 200 and a plurality of fin structures 201 located on the substrate 200 and separated from each other.
The material of the substrate 200 comprises a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The group III-V element multicomponent semiconductor material includes InP, GaAs, GaP, InAs, InSb, InGaAs, InGaAsP, etc.
In other embodiments, the fin structure comprises: the fin structure comprises a plurality of fin sacrificial layers arranged in a direction vertical to the surface of the substrate, and nano sheets positioned between the adjacent fin sacrificial layers.
In the present embodiment, the material of the first conductive structure 230 includes cobalt.
In other embodiments, the material of the first conductive structure comprises ruthenium or tungsten.
In this embodiment, the material of the sacrificial layer 240 includes tungsten.
In other embodiments, the material of the sacrificial layer comprises titanium nitride, ruthenium, or platinum.
In another embodiment, the material of the sacrificial layer is a dielectric material. In particular, in another embodiment, the sacrificial layer directly serves as a conductive protection structure.
In the present embodiment, the thickness of the sacrificial layer 240 ranges from 50 angstroms to 200 angstroms.
In this embodiment, the first dielectric layer 220 is made of silicon oxide.
In other embodiments, the material of the first dielectric layer includes at least one of SiOCH, SiOH, and SiCN.
In this embodiment, the material of the second dielectric layer 250 includes a dielectric material or a metal compound. Specifically, the dielectric material includes SiCO, SiCN, SiN, SiOCN, or SiBCN. The metal compound comprises TiN, AlN, TiO or AlO.
Specifically, in this embodiment, the second dielectric layer 250 is SiCO.
In this embodiment, the semiconductor structure further includes: the semiconductor structure comprises a plurality of gate structures 212, gate protection structures 213 and side walls 210, wherein the gate structures 212 are located on the surface of the substrate 200, the gate protection structures 213 are located on the top surfaces of the gate structures 212, the side walls 210 are located on the side wall surfaces of the gate structures 212 and the gate protection structures 213, the first dielectric layer 220 is also located on the side wall surfaces of the side walls 210, the gate structures 212 cross the fin portion structures 202, and the source drain structures 202 are located in the substrate 200 on two sides of the gate structures 212.
In this embodiment, the gate structure 212 includes: a gate dielectric layer (not shown) on the surface of the substrate 200 and in the first dielectric layer 220, a work function layer (not shown) on the surface of the gate dielectric layer, and a gate electrode layer (not shown) on the surface of the work function layer.
The material of the gate dielectric layer comprises a high dielectric constant material (the dielectric constant is larger than 3.9). The high dielectric constant material includes: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, or the like.
The material of the gate electrode layer includes a metal material such as: one or more of tungsten, copper, aluminum, titanium and tantalum.
The material of the work function layer comprises titanium nitride, tantalum nitride or titanium aluminum.
In other embodiments, the material of the gate structure 212 comprises polysilicon.
In this embodiment, the material of the gate protection structure 213 includes silicon nitride.
In the present embodiment, the thickness of the gate protection structure 213 ranges from 50 angstroms to 200 angstroms.
In this embodiment, the material of the sidewall spacers 210 includes a low-k dielectric material or a combination of low-k dielectric materials. The low-k dielectric material comprises SiOC, SiOCN, SiBCN and the like.
In this embodiment, the semiconductor structure further includes: an etch stop layer (not shown) on the sidewalls of the sidewalls 210.
In this embodiment, the material of the etch stop layer includes silicon nitride.
Accordingly, the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 14, including: a substrate 200; a plurality of source-drain structures 202 located within the substrate 200; the first dielectric layer 220 is positioned on the substrate 200 and the surfaces of the source drain structures 202; a first conductive structure 230 located in the first dielectric layer 220 and located on the surface of the source drain structure 202, wherein the top surface of the first conductive structure 230 is flush with the surface of the first dielectric layer 220; a conductive protection structure 260 on a top surface of the first conductive structure 230; and a second dielectric layer 250 located on the surface of the first dielectric layer 220, wherein the second dielectric layer 250 is also located on the sidewall surface of the conductive protection structure 260, and the material of the second dielectric layer 250 is different from that of the conductive protection structure 260.
In this embodiment, the base includes a substrate 200 and a plurality of fin structures 201 located on the substrate 200 and separated from each other.
The material of the substrate 200 comprises a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.
In other embodiments, the fin structure comprises: the fin structure comprises a plurality of fin sacrificial layers arranged in a direction vertical to the surface of the substrate, and nano sheets positioned between the adjacent fin sacrificial layers.
In this embodiment, the material of the first conductive structure 230 includes cobalt.
In other embodiments, the material of the first conductive structure comprises ruthenium or tungsten.
In this embodiment, the first dielectric layer 220 is made of silicon oxide.
In other embodiments, the material of the first dielectric layer includes at least one of SiOCH, SiOH, and SiCN.
In this embodiment, the material of the second dielectric layer 250 includes a dielectric material or a metal compound. Specifically, the dielectric material includes SiCO, SiCN, SiN, SiOCN, or SiBCN. The metal compound comprises TiN, AlN, TiO or AlO.
Specifically, in this embodiment, the second dielectric layer 250 is SiCO.
In this embodiment, the second dielectric layer 250 and the conductive protection structure 260 further have a first conductive opening 271 (as shown in fig. 13), and the first conductive opening 271 exposes a portion of the top surface of the first conductive structure 230.
In this embodiment, the semiconductor structure further includes: a second conductive structure 291 located within the first conductive opening 271.
In this embodiment, the semiconductor structure further includes: the semiconductor structure comprises a plurality of gate structures 212, gate protection structures 213 and side walls 210, wherein the gate structures 212 are located on the surface of the substrate 200, the gate protection structures 213 are located on the top surfaces of the gate structures 212, the side walls 210 are located on the side wall surfaces of the gate structures 212 and the gate protection structures 213, the first dielectric layer 220 is also located on the side wall surfaces of the side walls 210, the gate structures 212 cross the fin portion structures 202, and the source drain structures 202 are located in the substrate 200 on two sides of the gate structures 212.
In this embodiment, the material of the gate protection structure 213 includes silicon nitride.
The material of the conductive protection structure 260 includes a dielectric material or a metal compound. Specifically, the dielectric material includes SiCO, SiCN, SiN, SiOCN, or SiBCN. The metal compound comprises TiN, AlN, TiO or AlO.
In this embodiment, the conductive protection structure 260 is made of the same material as that of the gate protection structure 213. That is, the conductive protection structure 260 is made of silicon nitride.
In the present embodiment, the thickness of the gate protection structure 213 ranges from 50 angstroms to 200 angstroms.
In the present embodiment, the thickness of the conductive protection structure 260 ranges from 50 angstroms to 200 angstroms.
In this embodiment, the gate structure 212 includes: a gate dielectric layer (not shown) on the surface of the substrate 200 and in the first dielectric layer 220, a work function layer (not shown) on the surface of the gate dielectric layer, and a gate electrode layer (not shown) on the surface of the work function layer.
The material of the gate dielectric layer comprises a high dielectric constant material (the dielectric constant is larger than 3.9). The high dielectric constant material includes: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, or the like.
The material of the gate electrode layer includes a metal material such as: one or more of tungsten, copper, aluminum, titanium and tantalum.
The material of the work function layer comprises titanium nitride, tantalum nitride or titanium aluminum.
In other embodiments, the material of the gate structure 212 includes polysilicon.
In this embodiment, the material of the sidewall spacers 210 includes a low-k dielectric material or a combination of low-k dielectric materials. The low-k dielectric material comprises SiOC, SiOCN, SiBCN and the like.
In this embodiment, the semiconductor structure further includes: an etch stop layer (not shown) on the sidewalls of the sidewalls 210.
In this embodiment, the material of the etch stop layer includes silicon nitride.
In this embodiment, the semiconductor structure further includes: and a base dielectric layer (not shown) on the surface of the substrate 200, wherein the base dielectric layer is also located on a part of the sidewall surface of the fin structure 201.
In the present embodiment, in a direction perpendicular to the extending direction of the gate structure 212, the second dielectric layer 250 further has a second conductive opening 272 (as shown in fig. 13), and the second conductive opening 272 exposes a portion of the top surface of the gate structure 212.
In this embodiment, the semiconductor structure further includes: a third conductive structure 292 within the second conductive opening 272.
In this embodiment, the semiconductor structure further includes: and a third dielectric layer 270 on the surface of the second dielectric layer 250 and the surface of the conductive protection structure 260.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (32)

1. A semiconductor structure, comprising:
a substrate;
a plurality of source-drain structures located in the substrate;
the first dielectric layers are positioned on the surfaces of the substrate and the source drain structures;
the first conductive structure is positioned in the first dielectric layer and positioned on the surface of the source drain structure, and the top surface of the first conductive structure is flush with the surface of the first dielectric layer;
A conductive protection structure on a top surface of the first conductive structure;
and the second dielectric layer is positioned on the surface of the first dielectric layer and is also positioned on the side wall surface of the conductive protection structure, and the material of the second dielectric layer is different from that of the conductive protection structure.
2. The semiconductor structure of claim 1, wherein a material of the first conductive structure comprises cobalt, ruthenium, or tungsten.
3. The semiconductor structure of claim 1, wherein the conductive protection structure has a thickness in a range from 50 angstroms to 200 angstroms.
4. The semiconductor structure of claim 1, in which a material of the conductive protection structure comprises a dielectric material or a metal compound.
5. The semiconductor structure of claim 1, further comprising a first conductive opening in the second dielectric layer and in the conductive protection structure, the first conductive opening exposing a portion of the top surface of the first conductive structure; the semiconductor structure further includes: a second conductive structure located within the first conductive opening.
6. The semiconductor structure of claim 5, further comprising: the first dielectric layer is also positioned on the side wall surface of the side wall, and the conductive protection structure and the gate protection structure are made of the same material.
7. The semiconductor structure of claim 6, wherein the gate protection structure has a thickness in a range from 50 angstroms to 200 angstroms.
8. The semiconductor structure of claim 6, wherein said second dielectric layer further has a second conductive opening therein in a direction perpendicular to a direction in which said gate structure extends, said second conductive opening exposing a portion of a top surface of said gate structure; a third conductive structure located within the second conductive opening.
9. The semiconductor structure of claim 6, wherein the base comprises a substrate, and a plurality of fin structures on the substrate, the gate structure crossing the fin structures.
10. The semiconductor structure of claim 1, further comprising: and the third dielectric layer is positioned on the surface of the second dielectric layer and the surface of the conductive protection structure.
11. A semiconductor structure, comprising:
a substrate;
a plurality of source-drain structures located in the substrate;
the first dielectric layers are positioned on the surfaces of the substrate and the source drain structures;
the first conductive structure is positioned in the first dielectric layer and positioned on the surface of the source drain structure, and the top surface of the first conductive structure is flush with the surface of the first dielectric layer;
A sacrificial layer on a top surface of the first conductive structure;
and the second dielectric layer is positioned on the surface of the first dielectric layer and is also positioned on the side wall surface of the sacrificial layer, and the material of the second dielectric layer is different from that of the sacrificial layer.
12. The semiconductor structure of claim 11, wherein a material of the first conductive structure comprises cobalt, ruthenium, or tungsten.
13. The semiconductor structure of claim 11, in which a material of the sacrificial layer comprises titanium nitride or a metal material.
14. The semiconductor structure of claim 13, wherein the metal material comprises: tungsten, ruthenium or platinum.
15. The semiconductor structure of claim 11, in which a material of the sacrificial layer comprises a dielectric material.
16. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a plurality of source-drain structures in the substrate;
forming a first dielectric layer on the substrate and the surfaces of the source drain structures;
forming a first conductive structure positioned on the surface of the source drain structure in the first dielectric layer;
after the first conductive structure is formed, a sacrificial layer is formed on the top surface of the first conductive structure by adopting a selective film forming process;
And after the sacrificial layer is formed, forming a second dielectric layer on the surface of the first dielectric layer, wherein the sacrificial layer and the second dielectric layer are made of different materials.
17. The method of forming a semiconductor structure of claim 16, wherein a material of the first conductive structure comprises cobalt, ruthenium, or tungsten.
18. The method of forming a semiconductor structure of claim 16, wherein a material of the second dielectric layer comprises a dielectric material or a metal compound.
19. The method of forming a semiconductor structure of claim 16, wherein the sacrificial layer is a dielectric material; the method for forming the semiconductor structure further comprises the following steps: etching part of the sacrificial layer until a first conductive opening is formed in the second dielectric layer, wherein the first conductive opening exposes part of the top surface of the first conductive structure; and forming a second conductive structure in the first conductive opening.
20. The method of claim 16, wherein the sacrificial layer comprises titanium nitride or a metallic material, and wherein the selective film formation process comprises a selective metal electroless plating process.
21. The method of forming a semiconductor structure of claim 20, wherein the metal material comprises: tungsten, ruthenium or platinum.
22. The method of forming a semiconductor structure of claim 20, wherein the process parameters of the selective metal electroless plating process comprise: the pressure range is 20 Pa to 100 Pa; the gases used included: SiH4、H2、WF6Wherein, WF6The gas flow range of (2) sccm to 50 sccm; the temperature range is 100 ℃ to 400 ℃.
23. The method of forming a semiconductor structure of claim 20, further comprising: after the second dielectric layer is formed, etching back and removing the sacrificial layer, and forming a first opening in the second dielectric layer, wherein the first opening exposes the top surface of the first conductive structure; and forming a conductive protection structure in the first opening, wherein the conductive protection structure is made of a material different from that of the second dielectric layer.
24. The method of forming a semiconductor structure of claim 21, wherein the process of etching back the sacrificial layer comprises a plasma etch process, and process parameters of the plasma etch process comprise: pressure ranges from 40 mTorr to 300 mTorr; the source power range is 500 watts to 1500 watts; the gases used included: SiH 4HBr and SF6One or more of (a).
25. The method of forming a semiconductor structure of claim 21, wherein a material of the conductive protection structure comprises a dielectric material or a metal compound.
26. The method of forming a semiconductor structure of claim 21, further comprising: forming a conductive opening mask layer on the second dielectric layer and the conductive protection structure, wherein the conductive opening mask layer is internally provided with a first conductive mask opening, and the first conductive mask opening exposes part of the surface of the conductive protection structure and part of the surface of the second dielectric layer adjacent to the conductive protection structure; etching part of the conductive protection structure by taking the conductive opening mask layer and the second dielectric layer as masks until a first conductive opening is formed in the second dielectric layer and the conductive protection structure, and the first conductive opening exposes part of the top surface of the first conductive structure; and forming a second conductive structure in the first conductive opening.
27. The method for forming a semiconductor structure of claim 26, wherein in the step of etching a portion of the conductive protection structure, an etch selectivity ratio of the conductive protection structure to the second dielectric layer is greater than 5: 1.
28. The method of forming a semiconductor structure of claim 27, further comprising: and forming a third dielectric layer on the surface of the second dielectric layer and the surface of the conductive protection structure before etching part of the conductive protection structure.
29. The method of forming a semiconductor structure of claim 26, further comprising: before the first conductive structure is formed, a plurality of grid structures, grid protection structures located on the top surfaces of the grid structures and side walls located on the side wall surfaces of the grid structures and the grid protection structures are formed on the surface of the substrate, the first dielectric layer is also located on the side wall surfaces of the side walls, and the conductive protection structures and the grid protection structures are made of the same material.
30. The method of forming a semiconductor structure of claim 29, wherein the gate protection structure has a thickness in a range of 50 angstroms to 200 angstroms.
31. The method of forming a semiconductor structure of claim 29, wherein the conductive opening mask layer further has a plurality of second conductive mask openings therein, the second conductive mask openings exposing portions of the gate protection structure; the method for forming the semiconductor structure further comprises the following steps: etching the gate protection structure while etching the conductive protection structure until a second conductive opening is formed in the second dielectric layer and the gate protection structure, wherein the second conductive opening exposes a part of the top surface of the gate structure; and forming a third conductive structure in the second conductive opening.
32. The method of claim 31, wherein the base comprises a substrate and a plurality of fin structures on the substrate, and the gate structure crosses the fin structures.
CN202011568825.5A 2020-12-25 2020-12-25 Semiconductor structure and forming method thereof Pending CN114678422A (en)

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