CN110349908B - Self-aligned contact structure and method for forming the same - Google Patents
Self-aligned contact structure and method for forming the same Download PDFInfo
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- CN110349908B CN110349908B CN201810303653.5A CN201810303653A CN110349908B CN 110349908 B CN110349908 B CN 110349908B CN 201810303653 A CN201810303653 A CN 201810303653A CN 110349908 B CN110349908 B CN 110349908B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Abstract
The invention provides a self-aligned contact structure and a forming method thereof. The forming method of the self-aligned contact structure comprises the following steps: providing a substrate on which a grid structure is formed; forming a spacer liner on the gate structure and the substrate; forming sacrificial layers between and over the gate structures; forming a dielectric plug through the sacrificial layer above the gate structure; removing the sacrificial layer to form a contact opening between the gate structures; conformally forming an anti-etching layer to cover the side wall and the bottom of the contact opening; and forming a contact plug in the contact opening. The invention avoids the leakage current between the grid structure and the self-aligned contact structure.
Description
Technical Field
The present invention relates generally to semiconductor technology, and more particularly to a self-aligned contact structure and a method for forming the same.
Background
The semiconductor integrated circuit industry is experiencing rapid growth. Technological advances in integrated circuit design and materials have produced generations of integrated circuits where each generation has smaller and more complex circuits than the previous generation. In the process of integrated circuit development, the geometric dimensions are gradually shrinking.
As the size of integrated circuits is reduced, the distance between the self-aligned contact structure and the gate is reduced, and thus the probability of short circuit to generate leakage current is increased. Conventionally, when fabricating a self-aligned contact structure, the sidewall spacers of the gate may be lost when forming the self-aligned contact structure. Such incomplete sidewall spacers may not effectively isolate the self-aligned contact structure from the gate, resulting in gate-to-self-aligned contact structure leakage current after cycling.
While existing self-aligned contact structures are adequate for their intended purposes, they are not satisfactory in every aspect. For example, leakage current between the gate and the self-aligned contact structure still needs to be improved.
Disclosure of Invention
Some embodiments of the present invention provide a method for forming a self-aligned contact structure, including: providing a substrate on which a grid structure is formed; forming a spacer liner on the gate structure and the substrate; forming sacrificial layers between and over the gate structures; forming a dielectric plug through the sacrificial layer above the gate structure; removing the sacrificial layer to form a contact opening between the gate structures; conformally forming an anti-etching layer to cover the side wall and the bottom of the contact opening; and forming a contact plug in the contact opening.
Other embodiments of the present invention provide a self-aligned contact structure, comprising: a gate structure located over the substrate; a spacer liner layer on the gate structure and exposing an upper portion of the gate structure; a dielectric plug located above the gate structure; an anti-etching layer, which is covered on the side wall of the dielectric plug and the side wall of the grid structure in a compliance way, and the anti-etching layer covers the upper part of the grid structure; and a contact plug located on the substrate between the gate structures.
The invention avoids leakage current between the gate structure and the self-aligned contact structure.
Drawings
The embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the embodiments of the present invention.
Fig. 1 is a flow chart illustrating a method of fabricating a self-aligned contact structure according to some embodiments.
Fig. 2-12 are cross-sectional views of various stages of a method for fabricating a self-aligned contact structure, according to some embodiments.
FIG. 13 depicts a layout of a memory having self-aligned contact structures, according to some embodiments.
FIG. 14 is a flow chart illustrating a method of fabricating a self-aligned contact structure according to further embodiments.
FIGS. 15-17 are cross-sectional views of various stages of a method of fabricating a self-aligned contact structure, according to yet other embodiments.
Reference numerals
10 to the Process
12. 14, 16, 18, 20, 22 and 24 to the step
100-self aligned contact structure
102 to substrate
104-grid structure
105-grid
106 spacer
108 spacer liner
110-sacrificial layer
112-dielectric plug
112a dielectric material
114-spacer
115-contact opening
116 resist layer
118-thermal process
120-barrier layer
122-contact plug
124-bit line
200-layout drawing
30 to the method
31 to step
315 contact opening
316-resist layer
W-width
Distance S
H. Hg-height
PWL, PBL-pitch
In the X, Y-directions
Detailed Description
While various embodiments or examples are disclosed below to practice various features of embodiments of the invention, specific embodiments of components and arrangements thereof are described below to illustrate embodiments of the invention. These examples are merely illustrative, and should not be construed as limiting the scope of the embodiments of the present invention. For example, references in the specification to a first feature being formed over a second feature include embodiments in which the first feature is in direct contact with the second feature, and embodiments in which there are additional features between the first and second features, i.e., the first and second features are not in direct contact. Moreover, where specific reference numerals or designations are used in various embodiments, these have been repeated among the various embodiments and/or structures in order to provide a clear and concise description of the embodiments as well as a concise description of the various embodiments.
Furthermore, spatially relative terms, such as "in 8230," "below," "lower," "above," "higher," and the like, may be used herein to describe one element(s) or feature(s) relative to another element(s) or feature(s) of the illustrations and may encompass different orientations of the device in use or operation and orientations of the device in the figures and/or the like. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.
As used herein, the term "about", "about" or "substantially" generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The term "substantially perpendicular" generally means that the included angle is within 90 ° ± 10 °, preferably within 90 ° ± 5 °. A given quantity is an approximate quantity, that is, the meanings of "about", and "about" may still be implied without specifically stating "about", or "about".
Although the steps in some of the embodiments described are performed in a particular order, the steps may be performed in other logical orders. In various embodiments, some of the described steps may be replaced or omitted, and other operations may be performed before, during, and/or after the steps described in embodiments of the invention. Other features may be added to the semiconductor device structure of embodiments of the present invention. Some features may be replaced or omitted in different embodiments.
The embodiment of the invention provides a mode for forming a self-aligned contact structure, wherein an anti-etching layer is formed on the side wall and the bottom of a contact opening, and then the anti-etching layer is densified by a thermal process. The anti-etch layer provides effective electrical isolation to compensate for the damaged spacer liner on the upper sidewall of the gate structure due to removal of the sacrificial layer during formation of the self-aligned contact structure, thereby preventing leakage current between the gate structure and the self-aligned contact structure.
Fig. 1 is a flow chart depicting a method 10 of fabricating a self-aligned contact structure 100, in accordance with some embodiments. Fig. 2-12 are cross-sectional views illustrating various stages of a method for fabricating a self-aligned contact structure 100, according to some embodiments. The flow chart of fig. 1 is combined with the cross-sectional schematic diagrams of fig. 2 to 12 to describe the embodiment of the present invention.
As illustrated in fig. 1 and 2, the method 10 begins with step 12 by providing a substrate 102 having a gate structure 104 formed thereon, the gate structure 104 including a gate 105 and a spacer 106.
In some embodiments, the substrate 102 in fig. 2 may be a semiconductor substrate, which may include an elemental semiconductor, such as silicon (Si), germanium (Ge), etc.; compound semiconductors such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), and the like; an alloy semiconductor such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium phosphide (GaInAsP), or a combination thereof. The substrate 102 may be a semiconductor on insulator (semiconductor on insulator).
Next, a gate structure 104 is formed on the substrate 102, wherein the gate structure 104 includes a gate 105 and spacers 106 formed on opposite sidewalls of the gate 105. In some embodiments, gate 105 includes a gate dielectric layer and a gate electrode layer (not shown). The gate dielectric layer may comprise silicon oxide (silicon nitride), silicon oxynitride (silicon oxynitride), high-k dielectric material (i.e., dielectric constant greater than 3.9), such as HfO 2 、LaO、AlO、ZrO、TiO、Ta 2 O 5 、Y 2 O 3 、SrTiO 3 、BaTiO 3 、BaZrO、HfZrO、HfLaO、HfTaO、HfSiO、HfSiON、HfTiO、LaSiO、AlSiO、(Ba、Sr)TiO 3 、Al 2 O 3 Or a combination of the foregoing. The gate dielectric layer may be formed using a suitable oxidation process (e.g., a dry oxidation process or a wet oxidation process), a deposition process (e.g., a Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD)), other suitable processes, or a combination thereof. In some embodiments, the gate dielectric layer may beBy thermal oxidation processes in the presence of oxygen or nitrogen (e.g. containing NO or N) 2 O) and forming a gate dielectric layer before forming the gate electrode layer.
In some embodiments, a gate electrode layer is formed on the gate dielectric layer. The gate electrode layer may include polysilicon, metal (e.g., tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, the like, or combinations thereof), metal alloy, metal nitride (e.g., tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride, the like, or combinations thereof), metal silicide (e.g., tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, the like, or combinations thereof), metal oxide (e.g., ruthenium oxide, indium tin oxide, the like, or combinations thereof), other suitable material, or combinations thereof. The gate electrode layer may be patterned by forming an electrode material on the substrate 102 using a chemical vapor deposition process (e.g., low Pressure Chemical Vapor Deposition (LPCVD)) or a Plasma Enhanced Chemical Vapor Deposition (PECVD)), a Physical Vapor Deposition (PVD) (e.g., resistance heating evaporation, e-beam evaporation, or sputtering), an electroplating process, an atomic layer deposition (ald) process, other suitable processes, or a combination thereof, and then forming the gate electrode by patterning the electrode material using a photolithography and etching process.
In some embodiments, spacers 106 are formed on opposing sidewalls of gate 105. The spacers 106 may be an oxide, a nitride, an oxynitride, a high-k material, a low-k material, or a combination thereof. The precursor material or reaction gas for forming the spacers 106 may include Triethoxysilane (TRIES), tetraethoxysilane (TEOS), bistriutylamino silane (BTBAS), O 2 、N 2 O, NO, other gases or materials, or combinations of the above. In some embodiments, chemical vapor deposition (e.g., high-density plasma chemical vapor deposition (HDPCVD)), atmospheric pressure chemical vapor deposition (atmospheric pressure chemical vapor deposition), or combinations thereof may be usedon, APCVD), lpcvd, or pecvd), atomic layer deposition, other suitable techniques, or a combination thereof, conformally deposit a spacer material over the gate structure and substrate, followed by anisotropic etch back of the spacer material, leaving spacers 106 on both sides of the gate 105. In some embodiments, the etch-back process may use a dry etch, which may include an oxygen-containing gas, a fluorine-containing gas (e.g., CF) 4 、SF 6 、CH 2 F 2 、CHF 3 And/or C 2 F 6 ) Chlorine-containing gas (e.g., cl) 2 、CHCl 3 、CCl 4 And/or BCl 3 ) Bromine-containing gas (e.g., HBr and/or CHBR) 3 ) Iodine containing gas, other suitable gases and/or plasmas, and/or combinations thereof.
As illustrated in fig. 1 and 3, the method 10 continues with step 14 by forming a spacer liner 108 on the gate structure 104 and the substrate 102. In some embodiments, the spacer liner 108 may be an oxide, a nitride, an oxynitride, a high dielectric constant material, a low dielectric constant material, or a combination thereof. The precursor material or reaction gas for forming spacer liner 108 may include triethoxysilane, tetraethoxysilane, bis-tert-butylaminosilane, O 2 、N 2 O, NO, other gases or materials, or combinations of the above. In some embodiments, the spacer liner 108 may be formed on the gate structure 104 and the substrate 102 using chemical vapor deposition (e.g., high density plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, or plasma assisted chemical vapor deposition), atomic layer deposition, other suitable techniques, or a combination thereof. In some embodiments, the spacer liner 108 is a different material than the spacer 106. In some embodiments, the spacer liner 108 completely covers the gate structure 104 and the substrate 102.
As illustrated in fig. 1 and 4, the method 10 then proceeds to step 16 by forming sacrificial layers 110 between and over the gate structures 104. In some embodiments, the sacrificial layer 110 may comprise polysilicon, silicon-rich oxide, oxynitride, aluminum oxide, or combinations thereof. In some embodiments, the sacrificial layer 110 may be formed between and over the gate structures 104 using chemical vapor deposition (e.g., high density plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, or plasma-assisted chemical vapor deposition), atomic layer deposition, physical vapor deposition process, electroplating, spin-on coating (spin-on coating), other suitable techniques, or a combination thereof.
As illustrated in fig. 1, 5 and 6, the method 10 then proceeds to step 18, where a dielectric plug 112 is formed through the sacrificial layer 110 over the gate structure 104. In some embodiments, a hole (not shown) in the sacrificial layer 110 above the gate structure 104 is formed by a patterning process, such as photolithography and etching, before the dielectric plug 112 is formed. The patterning process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposing a pattern, post-exposure baking, photoresist developing, rinsing and drying (e.g., hard baking), other suitable techniques, or combinations thereof. The etch process may include a dry etch process (e.g., reactive ion etching, anisotropic plasma etching), a wet etch process, or a combination thereof. In some embodiments, after forming the hole over the gate structure 104, spacers 114 are formed on the sidewalls of the hole. In some embodiments, the spacer 114 is the same material as the spacer liner 108. In some embodiments, a deposition process may be used to conformally deposit a spacer material in the hole and over the sacrificial layer 110, followed by anisotropic etch back of the spacer material, leaving the spacers 114 on both sidewalls of the hole. The deposition process and the etching process for forming the spacers 114 may be the same as or similar to those for forming the spacers 106, and the details thereof will not be repeated.
After forming the hole in the sacrificial layer 110 above the gate structure 104 and the spacer 114 on the sidewall thereof, a dielectric plug 112 is formed in the hole in the sacrificial layer 110 above the gate structure 104. First, as shown in fig. 5, a dielectric material 112a is filled in the hole and above the sacrificial layer 110. In some embodiments, the dielectric material 112a includes silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and/or other suitable dielectric materials. The dielectric material 112a may be filled in the hole and over the sacrificial layer 110 using chemical vapor deposition (e.g., high density plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, or plasma assisted chemical vapor deposition), physical vapor deposition, atomic layer deposition, spin-on coating, other suitable techniques, or a combination thereof.
Next, as shown in fig. 6, a planarization process, such as Chemical Mechanical Polishing (CMP) or etch-back process, is performed to remove the excess dielectric material 112a until the sacrificial layer 110 is exposed, so as to form a dielectric plug 112 in the sacrificial layer 110 above the gate structure 104. The dielectric plug 112 can protect the gate structure 104 from mobile ions (mobile ions) affecting the device reliability.
In some embodiments, the sacrificial layer 110 is removed in a subsequent process and a self-aligned contact structure is formed therein. During the process of removing the sacrificial layer 110, the spacer layer 108 may be consumed, reducing the distance between the gate structure 104 and the self-aligned contact structure, and causing a short circuit between the gate structure 104 and the self-aligned contact structure (described in detail later).
In some embodiments, as illustrated in fig. 5, the maximum width W of the sacrificial layer 110 between the gate structures 104 is 40% to 200% of the distance S between the gate structures 104. If the width W is too large, the hole above the gate structure 104 is too small to be filled with dielectric material to form the dielectric plug 112. If the width W is too small, the cross-sectional area of the self-aligned structure formed subsequently is too small, resulting in an increase in the resistance of the contact.
In some embodiments, as illustrated in fig. 5, the height H of the protrusion of the sacrificial layer 110 from the gate structure 104 between the gate structures 104 is 10% to 100% of the gate structure height Hg. If the height H is too large, the etching time for subsequently removing the sacrificial layer 110 is long, and the spacer layer 108 on the upper portion of the gate 104 is easily damaged, thereby causing a short circuit between the subsequently formed contact plug and the gate structure 104. If the height H is too small, the height of the dielectric plug 112 is too small to protect the gate structure 104, and mobile ions (mobility) will affect the device reliability.
As shown in fig. 1 and 7, the method 10 then proceeds to step 20, where the sacrificial layer 110 is removed to form a contact opening 115 between the gate structures 104. In some embodiments, the sacrificial layer 110 is removed with an etching process. The etching process may include dry etching, wet etching, reactive ion etching, and/or other suitable processes. In some embodiments, the dry etch process may include an oxygen-containing gas, a fluorine-containing gas (e.g., CF) 4 、SF 6 、CH 2 F 2 、CHF 3 And/or C 2 F 6 ) Chlorine-containing gas (e.g., cl) 2 、CHCl 3 、CCl 4 And/or BCl 3 ) Bromine-containing gas (e.g., HBr and/or CHBR) 3 ) Iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. In some embodiments, the wet etch process may include etching in dilute hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia (ammonia), hydrofluoric acid (HF) solution, nitric acid (nitroc acid, HNO) 3 ) And/or acetic acid (CH) 3 COOH), or other suitable wet etchant. In some embodiments, as shown in fig. 7, after the sacrificial layer 110 is removed, the spacer liner 108 on the upper sidewalls of the gate 104 is lost, thereby exposing the upper portion of the gate structure 104. In some embodiments, the etch selectivity of the spacer liner 108 is different from that of the spacers 106, for example, the spacer liner 108 is formed of, for example, an oxide and the spacers 106 are formed of, for example, a nitride, such that, when the etch selectivity is adjusted with, for example, a chlorine-containing gas, a bromine-containing gas, a fluorine-containing gas, or other suitable gas to remove the sacrificial layer 110, a portion of the spacer liner 108 is consumed to expose an upper portion of the gate structure 104 (including the spacers 106).
As shown in fig. 1 and 8, the method 10 then proceeds to step 22, where an etch stop layer 116 is conformally formed to cover the sidewalls and bottom of the contact opening 115. In some embodiments, the etch stop layer 116 is formed of the same material as the spacer liner 108, e.g., oxide.The etch stop layer 116 compensates for the removal of the spacer liner 108 from the sacrificial layer 110, and also prevents further loss of the spacer liner 108 on the upper sidewalls of the gate structure 104 during the subsequent etching process. Accordingly, a self-aligned contact structure subsequently formed in the contact opening 115 may be kept at an appropriate distance from the gate structure 104, thereby avoiding a short circuit caused by the self-aligned contact structure being too close to the gate structure 104. In addition, in some embodiments, the etch stop layer 116 may have a high selectivity with respect to a material (e.g., nitride) (not shown) on the substrate 102 during a subsequent etching process. And thus is not readily etched in subsequent processes to expose the gate structure 104. In some embodiments, the etch stop layer 116 comprises an oxide, a nitride, an oxynitride, a high dielectric constant material, or a combination thereof. The precursor material or reaction gas for forming the etch-resistant layer 116 may include triethoxysilane, tetraethoxysilane, ditertiarybutylamine silane, O 2 、N 2 O, NO, other gases or materials, or combinations of the above. In some embodiments, the etch stop layer 116 may be conformally formed on the sidewalls and bottom of the contact opening 115 using atomic layer deposition, chemical vapor deposition (e.g., high density plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, or plasma assisted chemical vapor deposition), other suitable techniques, or a combination thereof.
Next, as shown in fig. 9, a thermal process 118 is performed on the etch-resistant layer 116 to densify the etch-resistant layer 116. In some embodiments, the thermal process 118 may include: rapid Thermal Processing (RTP), laser annealing (laser annealing), furnace annealing (furnace annealing), and/or flash lamp annealing (flash lamp annealing). The thermal process may be performed in an oxidizing environment, a combination of a vapor environment and an oxygen environment, or in an inert gas environment. In some embodiments, the thermal process 118 is at a temperature of 0 ℃ to 1000 ℃ for a time of 0 minutes to 100 minutes. If the thermal process 118 is too high or too long, the contact opening 115 may have an excessive oxide layer remaining, which may result in an insufficient removal of contacts (contact open), and if the thermal process 118 is too low or too short, the densification may be insufficient to effectively reduce the leakage current between the gate structure 104 and the subsequently formed self-aligned contact structure.
As illustrated in fig. 1 and 10-12, the method 10 then proceeds to step 24, where a contact plug 122 is formed in the contact opening 115. In some embodiments, the etch stop layer 116 and the spacer liner 108 between the gate structures 104 are etched to expose the substrate 102, as shown in fig. 10. In some embodiments, the etch process may include anisotropic etch back and/or other suitable processes. In some embodiments, the etch stop layer 116 and the spacer liner 108 between the gate structures 104 are etched, and the substrate 102 is also etched such that the contact openings 115 between the gate structures 104 extend into the substrate 102. In some embodiments, the vertical etch rate of this etching process is greater than the horizontal etch rate, thereby depleting the etch resistant layer 116 above the dielectric plug 112 so as to expose the dielectric plug 112. If the etch stop layer 116 is not formed, the spacer liner 108 may be further consumed to expose more of the gate structure 104, which may cause a short circuit between the subsequently formed self-aligned contact structure and the gate structure 104, thereby generating a leakage current.
Next, as shown in fig. 11, a barrier layer 120 is conformally formed on the sidewalls and bottom of the contact opening 115. The barrier layer 120 may prevent subsequently formed conductive materials from diffusing into the gate structure 104. The material of the barrier layer 120 may be titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), other suitable materials, or combinations thereof. The barrier layer 120 may deposit the barrier layer material using a physical vapor deposition process (e.g., evaporation or sputtering), an atomic layer deposition process, an electroplating process, other suitable processes, or a combination thereof.
Next, as shown in fig. 12, the contact opening 115 is filled with a conductive material to form a contact plug 122. The contact plug 122 comprises a metal material (e.g., tungsten, aluminum, or copper), a metal alloy, polysilicon, other suitable materials, or a combination thereof. The contact plug 122 may be formed by depositing a conductive material using a physical vapor deposition process (e.g., evaporation or sputtering), an atomic layer deposition process, an electroplating process, another suitable process, or a combination thereof, and optionally performing a Chemical Mechanical Polishing (CMP) or an etch-back process to remove the excess conductive material.
In some embodiments, as illustrated in fig. 1 and 2-12, by conformally forming the anti-etching layer 116 on the sidewalls of the gate structure 104 after removing the sacrificial layer 110, the damaged spacer liner 108 on the upper sidewalls of the gate structure 104 caused by removing the sacrificial layer 110 can be compensated, and the contact plug 122 can be prevented from shorting to the gate structure 104, which can result in leakage current. The densification of the anti-etching layer 116 by the thermal process 118 may further improve the quality of the anti-etching layer 116, thereby preventing the leakage current between the subsequently formed contact plug 122 and the gate structure 104.
FIG. 13 depicts a layout 200 of a memory having a self-aligned contact structure, according to some embodiments. The gate structures 104 (i.e., word lines) are arranged to extend along the Y-axis with a pitch (pitch) PWL, and the bit lines 124 are arranged along the X-axis with a pitch PBL. The X axis and the Y axis are perpendicular to each other. Where the contact plug 122 is located between the gate structures 104 and the bit line 124. In some embodiments, pitch PWL is between 0.1 μm to 0.3 μm and pitch PBL is between 0.05 μm to 0.2 μm. If the pitches PWL and PBL are too small, the contact plugs 122 are not easily formed. If the pitches PWL and PBL are too large, the area of the array and the wafer is additionally increased.
Fig. 14 to 17 are modified examples of the above embodiment. Fig. 14 is a flow chart illustrating a method 30 of fabricating a self-aligned contact structure 300, according to some embodiments. Fig. 15-16, which follow fig. 7, illustrate cross-sectional views of various stages of a method of fabricating a self-aligned contact structure 300, according to some embodiments. Wherein, the same or similar processes or elements as those in the previous embodiments will be followed by the same reference numerals, and the detailed description thereof will not be repeated. The difference from the previous embodiment is that after the sacrificial layer 110 is removed, step 31 is performed to completely remove the spacer liner layer 108. As shown in fig. 15, the spacer liner 108 between the gate structures 104 is completely removed, forming a contact opening 315 between the gate structures 104. In some embodiments, the spacer liner 108 is removed with an etch process. The etching process may include wet etching, dry etching, reactive ion etching, and/or other suitable processes. Next, as shown in FIG. 16, an etch stop layer 316 is conformally formed to cover the sidewalls and bottom of the contact opening 315.
Thereafter, the process of fig. 9 is followed by performing the thermal process 118 and performing the subsequent steps, as shown in fig. 17, forming the contact plug 122 in the contact opening 315 to form the self-aligned contact structure 300.
In some embodiments, as shown in fig. 14 and 15-17, by completely removing the spacer liner 108, uniformity and quality of the sidewall film may be improved without affecting the selectivity (aspect ratio) of the contact opening 315, thereby avoiding a reduction in process margin for forming the self-aligned contact structure 300 and further avoiding leakage current between the subsequently formed contact plug 122 and the gate structure 104.
In summary, embodiments of the present invention provide a self-aligned contact (SAC) forming method, after removing a sacrificial layer and before forming a contact plug, an anti-etching layer is conformally formed on a sidewall and a bottom of a contact opening, and the anti-etching layer can provide electrical isolation between the contact plug and a gate structure, thereby preventing short-circuit leakage current caused by loss of spacer liners at two sides of the gate structure. Densification of the etch-resistant layer by a thermal process can further improve the quality of the etch-resistant layer and avoid leakage current through the etch-resistant layer.
The foregoing outlines features of many embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art may readily devise many other varied processes and structures that are equally effective to achieve the same objects and/or achieve the same advantages of the embodiments of the invention without departing from the spirit and scope of the invention. Those skilled in the art should also realize that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments of the invention and that such equivalents are to be found within the spirit and scope of the embodiments of the invention.
Claims (8)
1. A method for forming a self-aligned contact structure, comprising:
providing a substrate on which a plurality of grid structures are formed;
forming a spacer liner layer on the plurality of gate structures and the substrate;
forming a sacrificial layer between and over the plurality of gate structures;
forming a plurality of dielectric plugs through the sacrificial layer above the plurality of gate structures, wherein the spacer liner is between bottom surfaces of the plurality of dielectric plugs and top surfaces of the plurality of gate structures;
removing the sacrificial layer and wearing at least a portion of the spacer liner to form a plurality of contact openings between the plurality of gate structures and leaving the spacer liner between bottom surfaces of the plurality of dielectric plugs and top surfaces of the plurality of gate structures;
conformably forming an etch-resistant layer covering sidewalls and bottoms of the plurality of contact openings and sidewalls of the spacer liner between bottom surfaces of the plurality of dielectric plugs and top surfaces of the plurality of gate structures; and
a plurality of contact plugs are formed in the plurality of contact openings.
2. The method of claim 1, wherein after forming the etch-resistant layer, a thermal process is performed on the etch-resistant layer to densify the etch-resistant layer, wherein the thermal process is performed at a temperature ranging from 0 ℃ to 1000 ℃ for a time ranging from 0 minutes to 100 minutes, wherein the etch-resistant layer comprises an oxide, a nitride, an oxynitride, or combinations thereof, and wherein the spacer liner comprises an oxide, a nitride, an oxynitride, or combinations thereof.
3. The method of claim 1, wherein the forming of the plurality of contact plugs comprises:
etching the spacer liner layer between the gate structures to expose the substrate;
conformally forming a barrier layer to cover the side walls and the bottom of the contact openings; and
the plurality of contact openings are filled with a conductive material.
4. The method of claim 1, further comprising:
after removing the sacrificial layer and before forming the etch-resistant layer, completely removing the spacer liner, wherein a maximum width of the sacrificial layer between the gate structures is 40% to 200% of a distance between the gate structures, and a height of the sacrificial layer between the gate structures protruding from the gate structures is 10% to 100% of a height of the gate structures.
5. The method of claim 1, wherein a pitch of the gate structures in a first direction is between 0.1 μm and 0.3 μm.
6. A self-aligned contact structure, comprising:
a plurality of gate structures on a substrate;
a spacer liner layer on top and side surfaces of the plurality of gate structures and exposing an upper portion of the plurality of gate structures;
a plurality of dielectric plugs over the plurality of gate structures;
an anti-etch layer conformally covering sidewalls of the plurality of dielectric plugs and sidewalls of the plurality of gate structures, the anti-etch layer covering the upper portions of the plurality of gate structures, and the anti-etch layer covering sidewalls of the spacer liner between bottom surfaces of the plurality of dielectric plugs and top surfaces of the plurality of gate structures; and
a plurality of contact plugs on the substrate between the gate structures,
wherein the spacer liner is between bottom surfaces of the plurality of dielectric plugs and top surfaces of the plurality of gate structures.
7. The self-aligned contact structure of claim 6, wherein the etch resistant layer comprises an oxide, a nitride, an oxynitride, or combinations thereof, wherein the spacer liner comprises an oxide, a nitride, an oxynitride, or combinations thereof, wherein the plurality of contact plugs comprises:
a barrier layer conformally covering between the gate structures and directly contacting the substrate; and
a conductive material on the barrier layer between the gate structures.
8. The self-aligned contact structure of claim 6, wherein a pitch of the gate structures in a first direction is between 0.1 μm and 0.3 μm.
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