CN100561712C - Semiconductor device and manufacture method thereof - Google Patents
Semiconductor device and manufacture method thereof Download PDFInfo
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- CN100561712C CN100561712C CNB2006101190579A CN200610119057A CN100561712C CN 100561712 C CN100561712 C CN 100561712C CN B2006101190579 A CNB2006101190579 A CN B2006101190579A CN 200610119057 A CN200610119057 A CN 200610119057A CN 100561712 C CN100561712 C CN 100561712C
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Abstract
The invention discloses a kind of manufacture method of semiconductor device, comprising: form the grid with sidewall spacers on Semiconductor substrate, described sidewall spacers comprises silicon oxide layer and silicon nitride layer; In described Semiconductor substrate, form source region and drain region, and form metal silicide on described grid, source region and surface, drain region; Remove the silicon nitride layer in the described sidewall spacers; Form etching stop layer at the substrate surface that comprises described grid, source region and drain region; At described etching stop layer surface deposition dielectric layer.The present invention can improve the filling quality in the space of pmd layer between grid.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of complementary mos device (CMOS) and manufacture method thereof.
Background technology
Along with the semiconductor device processing technology develop rapidly, the dense degree of device is more and more higher in the integrated circuit, and the critical dimension of device has reached the deep-submicron stage.In this case, for the space fill process between the components and parts new challenge has been proposed.Fig. 1 is the schematic diagram of existing semiconductor device of explanation and forming process thereof.As shown in Figure 1, at processing line back segment (the back end of line that forms interconnection layer, when BEOL) beginning, usually need be at processing line leading portion (front end of line, FEOL) dielectric layer deposited 20 between MOS transistor of Xing Chenging and the orlop in the interconnection layer 18, this dielectric layer 20 be called dielectric layer before the metal (pre-metal dielectric, PMD).In 20 layers of dielectric layers by etching through hole and be filled with metal material and form connecting hole 16.The grid 14 of MOS transistor is connected to metal connecting line 19 in the interconnection layer 18 (source electrode, the also corresponding connection of drain electrode) by connecting hole 16, and connecting line 19 is connected to the upper layer interconnects layer by dual damascene (dual-damascene) structure again.
Application number is a formation method of having introduced a kind of pmd layer in 200510077686.5 the Chinese patent application.Form before the pmd layer, form the CMOS transistor at the processing line leading portion, Semiconductor substrate 10 at first is provided, formation n trap and p trap are used to form NMOS and PMOS in substrate 10.At substrate 10 surface deposition grid oxic horizons, again in grid oxic horizon surface deposition polysilicon layer, described polysilicon layer of patterning and etch polysilicon form the grid 12 and the transistorized grid 14 of PMOS of nmos pass transistor then.Carry out the light dope formation shallow junction that low dose ion injects then in the both sides of grid 12 and 14.Next at substrate 10 and gate surface silicon oxide deposition and silicon nitride, and utilize dry etching to form sidewall spacers (offsetspacer) 15, carry out the heavy doping that high dose ion is injected subsequently in the both sides of grid 12 and 14, form source region 17 and drain region 11.Follow the autoregistration barrier layer on deposit autoregistration barrier layer and etching grid 12 and 14, source region 17 and 11 surfaces, drain region, depositing metal nickel or cobalt, form metal silicide 13 on grid 12 and 14, source region 17 and 11 surfaces, drain region after annealing, the deposit contact hole etching stops layer 21 then.In ensuing processing step, utilize plasma-reinforced chemical vapor deposition (HDP-CVD) or inferior normal pressure chemical vapor deposition (SACVD) technology deposit pmd layer 20, and utilize cmp (CMP) technology pmd layer 20 planarizations.Because pmd layer 20 is filled in the space between grid 14 and 12 with needing tight, the deposit influential effect of pmd layer 20 is to the formation quality of follow-up contact hole 16.After manufacturing process entered the following process node of 90nm, the space length between the grid 12 and 14 was very narrow and small, and similar high aspect ratio trench quite is filled the difficulty further that just becomes for the space between grid 12 and 14 in this case.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor device and manufacture method thereof, can improve the space filling quality of pmd layer between grid.
For achieving the above object, the invention provides a kind of manufacture method of semiconductor device, comprising:
Form the grid with sidewall spacers on Semiconductor substrate, described sidewall spacers comprises silicon oxide layer and silicon nitride layer;
In described Semiconductor substrate, form source region and drain region, and form metal silicide on described grid, source region and surface, drain region;
Remove the silicon nitride layer in the described sidewall spacers;
Form etching stop layer at the substrate surface that comprises described grid, source region and drain region;
At described etching stop layer surface deposition dielectric layer.
Adopt wet etching to remove the silicon nitride layer of described sidewall spacers.
The corrosive liquid of described wet etching is a phosphoric acid, and etching time is 20～600 seconds, and the temperature of described corrosive liquid is 120 ℃～200 ℃.
The material of described etching stop layer is the silicon nitride of silicon nitride, silicon oxynitride or carbon containing.
The thickness of described etching stop layer is
The depositing technics of described etching stop layer is a plasma-reinforced chemical vapor deposition.
Correspondingly, the invention provides a kind of semiconductor device, comprising:
The grid that on Semiconductor substrate, forms, described gate lateral wall has silicon oxide layer;
Source region that in described Semiconductor substrate, forms and drain region, the surface in described grid, source region and drain region has metal silicide; And
The etching stop layer that forms on described grid, source region and surface, drain region;
Dielectric layer in described etching stopping laminar surface formation.
The material of described etching stop layer is the silicon nitride of silicon nitride, silicon oxynitride or carbon containing.
The thickness of described etching stop layer is
Described metal silicide is the silicide of nickel or cobalt.
Compared with prior art, the present invention has the following advantages:
Method, semi-conductor device manufacturing method of the present invention utilizes wet clean process optionally to remove silicon nitride layer in the grid side walls spacer after the processing line leading portion forms metal silicide.Remove silicon nitride layer in the routine wall spacer and increased space length between the cmos device grid.When processing line back segment deposit pmd layer, because the increase of space length between the grid has reduced the difficulty of filling, improved filling effect and the covering power of pmd layer to the space between the grid, relaxed the process window of deposit pmd layer.In addition, remove after the sidewall spacers, method of the present invention stops layer in the device surface deposit silicon nitride as contact hole etching, this etching stop layer covers the NMOS and the PMOS transistor surface of cmos device, etching stop layer effect when it plays the etching contact hole on the one hand, played the effect of stress film on the other hand, it covers NMOS and PMOS transistor surface can adjust NMOS and the PMOS transistor stress along channel direction, thereby improves device performance.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Painstakingly do not draw accompanying drawing in proportion, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, amplified the thickness in layer and zone.
Fig. 1 is the schematic diagram of existing semiconductor device of explanation and forming process thereof;
Fig. 2 to Fig. 9 is the generalized section of explanation according to the method, semi-conductor device manufacturing method of the embodiment of the invention;
Figure 10 is the generalized section according to the semiconductor device of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Fig. 2 to Fig. 9 is the generalized section of explanation according to the method, semi-conductor device manufacturing method of the embodiment of the invention, and described schematic diagram is an example, and it should excessively not limit the scope of protection of the invention at this.As shown in Figure 2, method, semi-conductor device manufacturing method of the present invention at first provides semi-conductive substrate 100, substrate 100 can be the silicon or the SiGe (SiGe) of monocrystalline, polycrystalline or non crystalline structure, it also can be silicon-on-insulator (SOI), the material that perhaps can also comprise other, for example indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide.Though in these several examples of having described the material that can form substrate 100, any material that can be used as Semiconductor substrate all falls into the spirit and scope of the present invention.In substrate 100, pass through doping process for example ion implantation technology formation n trap and p trap (not shown).
Then, form grid oxic horizon 110 on substrate 100 surfaces, grid oxic horizon 110 can be silica (SiO2) or silicon oxynitride (SiNO).At the following process node of 65nm, the material of grid oxic horizon 110 is preferably high dielectric constant material, for example hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc.Particularly preferably be hafnium oxide, zirconia and aluminium oxide.Though in this a few examples of having described the material that can be used for forming grid oxic horizon 110, this layer can be formed by other material that reduces grid leakage current.The growing method of grid oxic horizon 110 can be any conventional vacuum coating technology, such as ald (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) technology, be preferably atom layer deposition process.In such technology, can form smooth atom interface between substrate 100 and the grid oxic horizon 110, can form the gate dielectric layer of ideal thickness.
Then, at grid oxic horizon surface deposition polysilicon layer, can utilize PECVD or high-density plasma chemical vapor deposition (HDP-CVD) technology at substrate surface deposit polysilicon layer.Polysilicon layer surface in deposition also need form a hard mask layer, and for example silicon nitride adopts the pecvd process deposit to form above-mentioned silicon nitride usually.Be coated with photoresist and patterning photoresist position then, utilize photoresist and silicon nitride subsequently, adopt plasma etching method etch polysilicon layer to form the grid 120 and the transistorized grid 130 of PMOS of nmos pass transistor as mask with the definition grid.Remove remaining photoresist and hard mask silicon nitride then, cineration technics is adopted in the removal of photoresist, and hard mask silicon nitride adopts the phosphoric acid wet method to remove.
Next as shown in Figure 3, the damage that the sidewall of grid 120 and 130 is caused in order to repair etching and to remove silicon nitride also needs in gate surface and both sides growth layer of oxide layer 140.Can utilize thermal oxidation or ISSG (generation of original position steam) to form above-mentioned oxide layer 140.Then substrate is carried out the foreign ion injection formation source region of low dosage and the shallow junction in drain region.The n type impurity that adopts for nmos pass transistor is phosphorus (P), arsenic (As); For the PMOS transistor, the p type impurity of employing is boron (B).The atom of impurity is by ionization, separation, acceleration (acquisition kinetic energy), forms ion beam current, inswept polysilicon layer surface, and foreign ion carries out physical bombardment to the polysilicon layer surface, enters the surface and stops below the surface.Ion injects the gaseous source of using impurity, and most of gaseous source adopt fluoride, for example PF
5, AsF
5, BF
3
Then, as shown in Figure 4, in grid 120 and 130 surfaces and substrate 100 surface deposition oxide layers 150, oxide layer 150 can be silica (SiO
2), in reative cell, feed silane (SiH
4) and oxygen O
2, utilize conventional CVD technology deposit to form, the thickness of this layer exists
Between.Adopt plasma-reinforced chemical vapor deposition process (PECVD) at oxide layer 150 surface deposition silicon nitride layers 160, as shown in Figure 5 subsequently.
Adopt dry etching, for example reactive ion etching (RIE) technology etch silicon nitride layer 160 and oxide layer 150 form the sidewall spacers with ON structure, and the ON structure comprises silica 150 ' and silicon nitride 170, as shown in Figure 6.In the present embodiment, feed etchant gas flow 50-400sccm in the reative cell, underlayer temperature is controlled between 20 ℃ and 90 ℃, and chamber pressure is 4-80mTorr, plasma source radio frequency power output 1500W-2000W.Etching agent adopts mist, and mist comprises SF6, CHF3, CF4, chlorine Cl
2, oxygen O
2, nitrogen N
2, helium He and oxygen O
2, and other inert gas, for example hydrogen Ar, neon Ne or the like.Next, utilize high dose ion to inject and carry out heavy doping, form source region and drain region.Form the autoregistration barrier layer on substrate 100, grid 120 and 130, sidewall spacers surface then.The material on autoregistration barrier layer is preferably silicon rich oxide, adopts chemical vapor deposition or thermal oxidation method to form, and thickness is
Subsequently, at autoregistration barrier layer surface coating photoresist and by the described autoregistration of photoetching process composition barrier layers such as development, photographic fixing, define the position that adopted metal silicide forms whereby.Then, utilize the photoresist of patterning to be the described autoregistration of mask etching barrier layer, the position in corresponding grid, source region and drain region forms opening in the autoregistration barrier layer.Then, utilize the method plated metal nickel or the cobalt of physical sputtering at the autoregistration barrier layer surface.Because the effect of mask is played on the autoregistration barrier layer, therefore described metal only can contact with the silicon on grid, source region and surface, drain region.Carry out thermal annealing subsequently, preferred rapid thermal anneal process, so that the silicon generation silicification reaction of metal that contacts with grid, source region and drain region and below, the silicide 180 of formation nickel or cobalt.The typical anneal temperature is between 500～550 ℃.Next adopt wet-cleaned to remove residual metallic and the autoregistration barrier layer that silicification reaction does not take place.
In ensuing processing step, as shown in Figure 7, the silicon nitride layer 170 in the routine wall spacer that method of the present invention will before form removes.Silicon nitride layer 170 adopts the method for wet etching to remove, and the corrosive liquid that uses is phosphoric acid (H
3PO
4), the time of corrosion was controlled between 20～600 seconds, and the temperature of corrosive liquid is 120 ℃～200 ℃.Then, as shown in Figure 8, utilize CVD technology, be preferably PECVD, at the substrate 100 surface deposition etching stop layers 190 that comprise grid 120 and 130, source region and drain region, etching stop layer 190 be silicon nitride (Si3N4), silicon oxynitride (SiON) or carbon containing silicon nitride (nitridedoped carbon, NDC), nitrogen silicon oxide carbide (SiOCN) for example, thickness is
Above-mentioned etching stop layer 190 one side are as the etching stopping layer of subsequent etching connecting hole, played the effect of stress film on the other hand, it covers NMOS and PMOS transistor surface, can adjust the grid 120 of nmos pass transistor and the transistorized grid of PMOS 130 belows stress, thereby improve device performance along channel direction.
Then, in above-mentioned etching stop layer 190 surface in situ dielectric layer deposited 200, as shown in Figure 9.Dielectric layer 200 is the inorganic silicon matrix layers (Inorganicsilicon based layer) by the low-k of CVD (Chemical Vapor Deposition) method deposition, for example silicon oxide carbide (SiCO) or fluorinated silica glass (FSG), being preferably Material Used (Applied Materials) house mark is the silicon dioxide (SiO2) of black diamond (black diamond).In a preferred embodiment of the invention, the method that forms the preceding low K dielectrics layer 200 of metal is used the accurate normal pressure chemical vapor deposition of heating (SACVD) technology high-density plasma chemical vapor deposition (HDP-CVD) technology that comprises carbon containing organic metal or organo-silicon compound, ozone and dopant source.The organic metal of carbon containing or organo-silicon compound can comprise cyclosiloxane for example tetramethyl-ring tetrasiloxane (TMCTS) or octamethylcy-clotetrasiloxane (OMCTS) or other annular siloxane, are preferably OMCTS.In the CVD reative cell, with wafer be placed on reative cell inside, comprising on the platform that heating element is arranged, come controlling platform by the thermo receptor that is used to control the reaction indoor temperature.In reative cell, feed reacting gas flow, comprise the mixture and the helium of OMCTS, oxygen.Forming low-k dielectric layer 200 reaction conditions is: the flow of octamethylcy-clotetrasiloxane OMCTS is 1500～3500mgm; The flow of oxygen O2 is 50～500sccm; Helium He is 0～2000sccm; Radio-frequency power is 300～1000W; Chamber pressure is 2～10Torr.The dielectric constant of the dielectric layer 200 that forms is approximately less than 3.0.Subsequently, utilize CMP technology that above-mentioned dielectric layer 200 is carried out planarization.
Figure 10 is the generalized section according to the semiconductor device of the embodiment of the invention.As shown in figure 10, comprise Semiconductor substrate 100, the grid oxic horizon 110 that forms on substrate 100 surfaces, at the grid 120 and 130 that grid oxic horizon 110 surfaces form, grid 120 and 130 sidewalls have silicon oxide layer 150 ' respectively.The source region and the drain region that in described Semiconductor substrate 100, form, the metal silicide 180 that forms on the surface in grid, source region and drain region; And the etching stop layer 190 that forms on substrate 100, grid 120 and 130, source region and surface, drain region; The dielectric layer 200 that forms on etching stop layer 190 surfaces.Wherein the material of etching stop layer 190 is the silicon nitride of silicon nitride, silicon oxynitride or carbon containing, and thickness is
Described metal silicide is the silicide of nickel or cobalt.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (7)
1, a kind of manufacture method of semiconductor device comprises:
Form the grid with sidewall spacers on Semiconductor substrate, described sidewall spacers comprises silicon oxide layer and silicon nitride layer;
In described Semiconductor substrate, form source region and drain region, and form metal silicide on described grid, source region and surface, drain region;
Remove the silicon nitride layer in the described sidewall spacers;
Form etching stop layer at the substrate surface that comprises described grid, source region and drain region;
In described etching stop layer surface in situ dielectric layer deposited,
Wherein, the reaction condition of the described dielectric layer of deposit is: the flow of octamethylcy-clotetrasiloxane OMCTS is 1500～3500mgm; The flow of oxygen O2 is 50～500sccm; Helium He is 0～2000sccm; Radio-frequency power is 300～1000W; Chamber pressure is 2～10Torr.
2, the method for claim 1 is characterized in that: adopt wet etching to remove the silicon nitride layer of described sidewall spacers.
3, method as claimed in claim 2 is characterized in that: the corrosive liquid of described wet etching is a phosphoric acid, and etching time is 20 seconds～600 seconds, and the temperature of described corrosive liquid is 120 ℃～200 ℃.
4, the method for claim 1 is characterized in that: the material of described etching stop layer is silicon nitride or silicon oxynitride.
5, the method for claim 1 is characterized in that: the material of described etching stop layer is the silicon nitride of carbon containing.
6, as claim 4 or 5 described methods, it is characterized in that: the thickness of described etching stop layer is
7, method as claimed in claim 6 is characterized in that: the depositing technics of described etching stop layer is a plasma-reinforced chemical vapor deposition.
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| CN102779746A (en) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | Method for forming metal grid |
| CN103367164B (en) * | 2013-06-26 | 2015-11-11 | 株洲南车时代电气股份有限公司 | A kind of gate electrode and preparation method thereof |
| CN105448724B (en) * | 2014-08-22 | 2019-03-22 | 无锡华润上华科技有限公司 | A kind of semiconductor devices and its manufacturing method, electronic device |
| CN110211944B (en) * | 2018-02-28 | 2022-04-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method |
| CN110349908B (en) * | 2018-04-03 | 2022-11-04 | 华邦电子股份有限公司 | Self-aligned contact structure and method for forming the same |
| CN117316876A (en) * | 2023-11-28 | 2023-12-29 | 粤芯半导体技术股份有限公司 | Method for preparing semiconductor structure and semiconductor structure |
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Effective date of registration: 20111108 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |