CN102779746A - Method for forming metal grid - Google Patents
Method for forming metal grid Download PDFInfo
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- CN102779746A CN102779746A CN2012102931244A CN201210293124A CN102779746A CN 102779746 A CN102779746 A CN 102779746A CN 2012102931244 A CN2012102931244 A CN 2012102931244A CN 201210293124 A CN201210293124 A CN 201210293124A CN 102779746 A CN102779746 A CN 102779746A
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Abstract
The invention discloses a method for forming a metal grid. The method comprises the steps of: forming a CESL (Contact Etch Stop Layer) stress layer and an interlayer medium layer after forming a metal silicide layer; flattening the intermediate medium layer until the CESL stress layer on the top surface of an amorphous carbon grid is exposed; and then removing the CESL stress layer on the top surface of the amorphous carbon grid. Thus, a stress memory technology is applied to the manufacture process of the metal grid, and the stress memorized in the grid structure is still conducted to a channel, thus the carrier mobility is favorably increased.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of metal gates formation method.
Background technology
Along with the development of cmos semiconductor device technology and dimension shrinks in proportion, stress engineering is playing increasing effect aspect semiconductor technology and the device performance; Introduce stress in the cmos device; Mainly be in order to improve the device carrier mobility; It is useful to the NMOS electron mobility to go up tensile stress at cmos device channel direction (longitudinal); And compression is useful to the PMOS hole mobility; Tensile stress on channel width dimension (transverse) is all useful to the carrier mobility of NMOS and PMOS device, and useful to the nmos device electron mobility in the compression of vertical-channel in-plane (out-of-plane), tensile stress is then useful to PMOS device hole mobility.
Stress memory effect (SMT; Stress memorization technique) be the method for introducing stress in a kind of CMOS technology, its technological process is: after device source/leakage is injected, and deposition one deck silicon nitride film protective layer (cap layer); And then carry out source/leakage annealing; In source/leakage annealing process, can produce thermal stress and internal stress effect between silicon nitride film protective layer, polysilicon gate and the side wall, these stress can be by memory among polysilicon gate; In polysilicon, can produce tensile stress, and channel direction (longitudinal) can produce compression along vertical-channel in-plane (out-of-plane); In ensuing technology; The silicon nitride film protective layer is etched away; But the stress of memory in polysilicon gate; Still can be transmitted among the raceway groove of cmos semiconductor device, the stress that is transmitted in the raceway groove is the compression of vertical-channel in-plane (out-of-plane) and the tensile stress on the channel direction (longitudinal), can be drawn by the influence of above-mentioned stress to the cmos device carrier mobility; Such stress effect is useful to improving the nmos device electron mobility, can improve the nmos device performance.
Along with process node contracts to 45 nanometers and following, for satisfying the new demand that device dimensions shrink causes, metal gates is widely used.How stress technique is applied to and becomes the technical problem that those skilled in the art need to be resolved hurrily in the metal gates manufacture process.
Summary of the invention
The present invention provides a kind of metal gates manufacturing approach of applied stress memory technique.
For solving the problems of the technologies described above, the present invention provides a kind of metal gates formation method, comprising:
One substrate is provided, and the side wall that is formed with the amorphous carbon grid on the said substrate and centers on said amorphous carbon grid is formed with source electrode and drain electrode in the said substrate;
In said source electrode and drain electrode, form metal silicide layer;
On said substrate, form the CESL stressor layers and carry out annealing process;
On said CESL stressor layers, form interlayer dielectric layer;
The said interlayer dielectric layer of planarization is until the CESL stressor layers that exposes said amorphous carbon grid end face;
Remove the CESL stressor layers of said amorphous carbon grid end face;
Remove said amorphous carbon grid, in said interlayer dielectric layer, form groove; And
Form the metal level of filling said groove and covering said interlayer dielectric layer.
Further, said CESL stressor layers is a stressed silicon nitride layers.
Further, adopt wet-etching technology to remove said CESL stressor layers.
Further, the etching liquid of said wet-etching technology employing is phosphoric acid solution.
Further, said annealing process is rapid thermal annealing or laser pulse annealing process.
Further, adopt oxygen ashing process to remove said amorphous carbon grid.
Further, said oxygen ashing process adopts mode long-range or original position to produce oxyanion precursor.
Compared with prior art; Metal gates formation method provided by the invention forms CESL stressor layers and interlayer dielectric layer after forming metal silicide layer; And the said interlayer dielectric layer of planarization is until the CESL stressor layers that exposes amorphous carbon grid end face; Remove the CESL stressor layers of said amorphous carbon grid end face subsequently, so, stress memory technique is applied in the manufacture process of metal gates; The stress of memory in grid structure still can be transmitted among the raceway groove, helps improving carrier mobility.
Description of drawings
Fig. 1 is the schematic flow sheet of the metal gates formation method of one embodiment of the invention;
Fig. 2 to Fig. 8 is that the metal gates of one embodiment of the invention forms the device profile structural representation in the procedure.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that broad to those skilled in the art, and not as limitation of the present invention.
For clear, whole characteristics of practical embodiments are not described.In following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development possibly be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to description and claims advantage of the present invention and characteristic.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
As shown in Figure 1, the metal gates formation method of one embodiment of the invention comprises the steps:
Step S1: a substrate is provided, and the side wall that is formed with the amorphous carbon grid on the said substrate and centers on said amorphous carbon grid is formed with source electrode and drain electrode in the said substrate;
Step S2: in said source electrode and drain electrode, form metal silicide layer;
Step S3: on said substrate, form the CESL stressor layers and carry out annealing process;
Step S4: on said CESL stressor layers, form interlayer dielectric layer;
Step S5: the said interlayer dielectric layer of planarization is until the CESL stressor layers that exposes said amorphous carbon grid end face;
Step S6: the CESL stressor layers of removing said amorphous carbon grid end face;
Step S7: remove said amorphous carbon grid, in said interlayer dielectric layer, form groove;
Step S8: form the metal level of filling said groove and covering said interlayer dielectric layer.
Be example to form the CMOS transistor below, more specify metal gates formation method of the present invention in conjunction with Fig. 2 to Fig. 8.
As shown in Figure 2; At first; The substrate 100 that comprises first area 100a and second area 100b is provided; First side wall 121 that is formed with the first amorphous carbon grid 111 on the said first area 100a and centers on the said first amorphous carbon grid 111, second side wall 122 that is formed with the second amorphous carbon grid 112 on the said second area 100b and centers on the said second amorphous carbon grid 112.
Said substrate 100 comprises but is not limited to comprise the silicon materials of semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).Said first area 100a is in order to form the PMOS transistor, and said second area 100b is in order to form nmos pass transistor, and vice versa.Can also be formed with dopant well in the said substrate 100, wherein, said dopant well ion implantation technology capable of using is accomplished, and the dopant well of said P type or N type is used to form the conducting channel of NMOS or PMOS.With NMOS is example, and said dopant well is the P type, and this dopant well is not shown.Also be formed with first grid dielectric layer 131 on the said first area 100a, also be formed with second gate dielectric layer 132 on the said second area 100b, the said first grid dielectric layer 131 and second gate dielectric layer 132 comprise silicon oxide layer or silicon oxynitride layer.Said first side wall 121 and second side wall 122 comprise silicon oxide layer, silicon oxynitride layer and/or silicon nitride layer.Form source electrode 101 and drain electrode 101 ' in the Semiconductor substrate of the said first amorphous carbon grid 111 both sides, in the Semiconductor substrate of the second amorphous carbon grid, 112 both sides, form source electrode 102 and drain electrode 102 '.In addition, also be formed with fleet plough groove isolation structure 140 in the said substrate 100, in order to isolate active area.
As shown in Figure 3, then, at the said source electrode 101,102 and 101 ', 102 ' the last metal silicide layer 150 that forms that drains.Said metal silicide layer 150 can form through following steps: at first, on first area 100a and second area 100b, form metal barrier layer film (SAB); Then, selective etch falls source electrode 101,102 and the metal barrier layer film on 101 ', 102 ' of draining; Then, nickel deposited (Ni) or cobalt (Co) metal; Next, carry out annealing process forming metal silicide layer 150, said annealing process can be divided into repeatedly and carrying out, and for example, can be divided into twice annealing technology; At last, remove said metal barrier layer film.
As shown in Figure 4; On said first area 100a and second area 100b, form via etch and stop layer (Contact etch stop layer; Be called for short CESL) stressor layers 160, and carry out annealing process, on CESL stressor layers 160, form interlayer dielectric layer 170 subsequently.Said CESL stressor layers 160 covers said first area 100a, second area 100b, the first amorphous carbon grid 111, the second amorphous carbon grid 112, first side wall 121 and second side wall 122, and said interlayer dielectric layer 170 covers said CESL stressor layers 160.
Said CESL stressor layers 160 for example is a stressed silicon nitride layers.Said CESL stressor layers 160 is preferably stressed silicon nitride layers, and it has good stress effect, and the thickness of said CESL stressor layers 160 is the 30-60 nanometer for example, and said annealing process for example is rapid thermal annealing (RTA) or laser pulse annealing (LSA) technology.In annealing process, can produce stress, these stress can be memorized, and the stress of memory in grid structure still can be transmitted among the raceway groove, helps improving carrier mobility.
Said interlayer dielectric layer 170 can adopt PECVD (plasma enhanced CVD), SACVD (inferior normal pressure chemical vapor deposition) or LPCVD technologies such as (low-pressure chemical vapor phase depositions) to form.Said inter-level dielectric layer material comprises but is not limited to phosphorosilicate glass (phosphosilicateglass; PSG), Pyrex (borosilicate; BSG), boron-phosphorosilicate glass (borophosphosilicate, BPSG), fluorine silex glass (FSG) or have a kind of or its combination in the advanced low-k materials.Said have advanced low-k materials include but not limited to black diamond (Black Diamond, BD) or coral etc.
As shown in Figure 5, then, the said interlayer dielectric layer 170 of planarization is until the end face that exposes the said first amorphous carbon grid 111 and the second amorphous carbon grid 112.Preferable, also can carry out extra etching technics to remove the first amorphous carbon grid 111 and the residual interlayer dielectric layer of the second amorphous carbon grid, 112 end faces after the said interlayer dielectric layer 170 of planarization.
As shown in Figure 6, then, adopt wet-etching technology, for example, adopt the CESL stressor layers 160 of said first amorphous carbon grid 111 of hot phosphoric acid (HPO) solution removal and the second amorphous carbon grid, 112 end faces.
As shown in Figure 7; Then; Adopt oxygen ashing process to remove the said first amorphous carbon grid 111 and the second amorphous carbon grid 112; Original position capable of using or remote plasma technology remove the first amorphous carbon grid 111 and the second amorphous carbon grid 112, in said interlayer dielectric layer 170, to form groove 171.
As shown in Figure 8, last, form the metal level 180 of filling said groove 171 and covering said interlayer dielectric layer 170, and planarization makes said metal level 180.Said metal level 180 comprises metal, metal alloy, metal silicide, metal alloy silicide, contain the conductive oxide of metal or contain the conductive silicide of metal, and wherein metal is from by a kind of or its combination Al, Co, Cr, Fe, h, h, Hf, Mg, Mo, Mn, N1Pd, Pt, La, Os, Nb, Rh, Re, Ru, Sn, Ta, Ti, V, W, Y and the Zr.Can adopt galvanoplastic or physical gas-phase deposition to form said metal level.
In sum; Metal gates formation method provided by the invention forms CESL stressor layers and interlayer dielectric layer after forming metal silicide layer, and the said interlayer dielectric layer of planarization is removed the CESL stressor layers of said amorphous carbon grid end face subsequently until the CESL stressor layers that exposes amorphous carbon grid end face; So; Stress memory technique is applied in the manufacture process of metal gates, the stress of memory in grid structure still can be transmitted among the raceway groove, helps improving carrier mobility.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these change and modification.
Claims (7)
1. metal gates formation method comprises:
One substrate is provided, and the side wall that is formed with the amorphous carbon grid on the said substrate and centers on said amorphous carbon grid is formed with source electrode and drain electrode in the said substrate;
In said source electrode and drain electrode, form metal silicide layer;
On said substrate, form the CESL stressor layers and carry out annealing process;
On said CESL stressor layers, form interlayer dielectric layer;
The said interlayer dielectric layer of planarization is until the CESL stressor layers that exposes said amorphous carbon grid end face;
Remove the CESL stressor layers of said amorphous carbon grid end face;
Remove said amorphous carbon grid, in said interlayer dielectric layer, form groove; And
Form the metal level of filling said groove and covering said interlayer dielectric layer.
2. metal gates formation method as claimed in claim 1 is characterized in that, said CESL stressor layers is a stressed silicon nitride layers.
3. metal gates formation method as claimed in claim 2 is characterized in that, adopts wet-etching technology to remove said CESL stressor layers.
4. metal gates formation method as claimed in claim 3 is characterized in that, the etching liquid that said wet-etching technology adopts is phosphoric acid solution.
5. metal gates formation method as claimed in claim 1 is characterized in that, said annealing process is rapid thermal annealing or laser pulse annealing process.
6. metal gates formation method as claimed in claim 1 is characterized in that, adopts oxygen ashing process to remove said amorphous carbon grid.
7. metal gates formation method as claimed in claim 6 is characterized in that, said oxygen ashing process adopts mode long-range or original position to produce oxyanion precursor.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004012256A1 (en) * | 2002-07-31 | 2004-02-05 | Advanced Micro Devices, Inc. | Process for manufacturing mosfets using amorphous carbon replacement gate and structures formed in accordance therewith |
| CN101197323A (en) * | 2006-12-04 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its manufacturing method |
| CN101593686A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Metal gates formation method |
| CN102543696A (en) * | 2010-12-17 | 2012-07-04 | 中国科学院微电子研究所 | Manufacture method for semiconductor device |
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- 2012-08-16 CN CN2012102931244A patent/CN102779746A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004012256A1 (en) * | 2002-07-31 | 2004-02-05 | Advanced Micro Devices, Inc. | Process for manufacturing mosfets using amorphous carbon replacement gate and structures formed in accordance therewith |
| CN101197323A (en) * | 2006-12-04 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its manufacturing method |
| CN101593686A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Metal gates formation method |
| CN102543696A (en) * | 2010-12-17 | 2012-07-04 | 中国科学院微电子研究所 | Manufacture method for semiconductor device |
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Application publication date: 20121114 |