CN101465325B - Method for forming semiconductor structure - Google Patents
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- CN101465325B CN101465325B CN200710160007XA CN200710160007A CN101465325B CN 101465325 B CN101465325 B CN 101465325B CN 200710160007X A CN200710160007X A CN 200710160007XA CN 200710160007 A CN200710160007 A CN 200710160007A CN 101465325 B CN101465325 B CN 101465325B
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Abstract
The semiconductor structure formation method comprises the step of providing a substrate with an array region and a surrounding region; the array region comprises a plurality of first gate stacks; the surrounding region comprises a low-voltage component second gate stack and a high-voltage component third gate stack; a first dielectric layer is formed on the substrate; a second dielectric layer is deposited on the first dielectric layer; part of the second dielectric layer is removed, and only the second dielectric layer on the third gate stack is left; the second dielectric layer is deposited on the substrate once again; the second dielectric layer is etched to expose the first dielectric layer; the second dielectric layer in the array region is removed to expose the first dielectric layer; the first dielectric layer is etched to expose the upper surfaces of all the gate stacks; a first gap wall, a second gap wall and a third gap wall are respectively formed at the sidewall of each gate stack; and the third gap wall is the thickest, while the first gap wall is the thinnest. The method can be used for different component surrounding edges in the semiconductor structure to form the gap walls of different thickness.
Description
Technical field
The invention relates to a kind of semiconductor structure, and particularly relevant for the storage arrangement with at least three kinds of clearance wall thickness.
Background technology
According to transistorized design and intrinsic characteristic thereof, adjust the grid below channel length between transistor source and drain electrode or can influence transistorized usefulness with the resistance that changes channel region by the length that define channel region in grid clearance wall on every side.For example, source/drain regions can define out via ion implantation technology by using grid and clearance wall as mask.Therefore, the width of the clearance wall around the grid can directly influence the size and the position of source/drain regions.When clearance wall was thin more, the source/drain regions of grid below can be approaching more, and short channel region length can make transistorized service speed promote.
For example in the application of memory, be positioned at the clearance wall around the grid in array district, just can do thinly increasing transistorized service speed as much as possible, thereby increase the efficient that memory writes or exports.Being arranged in the surrounding zone needs the thicker clearance wall of transistor needs of higher operation voltage to make it have higher puncture voltage (breakdown voltage) to increase its channel region length, and also needs more than one clearance wall thickness to define the channel region length that is fit to the transistor in individual applications.
Therefore, industry is needed the clearance wall of the zones of different formation different-thickness in integrated circuit badly, the operational requirements that meets individual component to define suitable channel region length, and form in the different-thickness clearance wall process, also want can avoid influencing the yield of subsequent technique.
Summary of the invention
The invention provides a kind of formation method of semiconductor structure, comprise substrate is provided, substrate comprises array district and surrounding zone, and comprise a plurality of first grid storehouses in the array district, and comprise the second grid storehouse of low-voltage assembly and the 3rd stack of high-voltage assembly in the surrounding zone, form first dielectric layer and be covered in the first grid storehouse, the second grid storehouse, and the top and the sidewall of the 3rd stack, deposit second dielectric layer on first dielectric layer, remove second dielectric layer that is positioned on first grid storehouse and the second grid storehouse, and stay second dielectric layer on the 3rd stack, deposit second dielectric layer once more in the first grid storehouse, the second grid storehouse, and on the 3rd stack, etch-back second dielectric layer, to expose first dielectric layer, remove second dielectric layer in the array district to expose first dielectric layer, and etch-back first dielectric layer is to expose the first grid storehouse, the second grid storehouse, and the upper surface of the 3rd stack, and in the first grid storehouse, the second grid storehouse, and the sidewall of the 3rd stack forms first clearance wall respectively, second clearance wall, and third space wall, wherein the thickness of third space wall is greater than second clearance wall, and the thickness of second clearance wall is greater than first clearance wall.
Thus, advantage of the present invention is: different assembly peripheries that can be in semiconductor structure form the clearance wall of different-thickness.Can by the clearance wall of different-thickness form different length channel (source electrode with drain between distance) or light dope source electrode/drain region to meet the demand of different assemblies.And see through the thin dielectric layer of gradation deposition and be combined into thicker clearance wall, the defective that is produced in the time of can avoiding forming thicker dielectric layer is for example because of the defective of the not good hole that produces of step coverage rate or the unfavorable subsequent techniques such as (overhang) of overhanging.And in an embodiment of the present invention, only need the twice mask process just can form the clearance wall of three kinds of thickness, escapable cost.
Description of drawings
Fig. 1 to Figure 10 is the series of process profile, in order to form the making flow process of three kinds of different-thickness clearance walls in explanation one embodiment of the invention.
Symbol description:
10～substrate; 12～array district; 14～surrounding zone; 16～first grid storehouse; 18～second grid storehouse; 20～the 3rd stacks; 11～shallow trench isolation district; 16a～first light dope source electrode/drain region; 18a～second light dope source electrode/drain region; 20a～the 3rd light dope source electrode/drain region; 22～the first dielectric layers; 24a～(depositing for the first time) second dielectric layer; 26～the first photoresist layers; 24b～(depositing for the second time) second dielectric layer; 28～the second photoresist layers; 16b～first source/drain regions; 18b～second source/drain regions; 20b～the 3rd source/drain regions.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below:
Clearance wall structure provided by the present invention and method for making thereof are applicable to many kinds of semiconductor structures, being specially adapted to the depth-to-width ratio (aspect ratio) of opening (or gap) of subregion inter-module in the structure assembly in higher and regional needs thin clearance wall, and needs thicker clearance wall at other regional assembly.For example, in the application of non-volatility memorizer (nonvolatile memory cell), memory can for example be distinguished into array district (array region) and surrounding zone (periphery region).
Fig. 1 to Figure 10 is the series of process profile, in order to form the making flow process of three kinds of different-thickness clearance walls in explanation one embodiment of the invention.
Now please refer to Fig. 1, substrate 10 at first is provided.Substrate 10 comprises array district 12 and surrounding zone 14.Substrate 10 can be the semiconductor-based end, for example silicon base, silicon-Germanium base, other semiconducting compound substrate or silicon-on-insulator (SOI) etc.In array district 12, comprise a plurality of first grid storehouses 16, have the opening (or gap) that a plurality of width differ therebetween, the depth-to-width ratio of at least one opening is higher than 2.6 in these openings.In surrounding zone 14, comprise the second grid storehouse 18 of low-voltage assembly and the 3rd stack 20 of high-voltage assembly.The substrate that second grid storehouse 18 and the 3rd stack are 20 can comprise shallow trench isolation district 11.Above-mentioned stack can be made in known manner.Wherein, first grid storehouse 16, second grid storehouse 18, and the 3rd stack 20 in comprise for example gate electrode, gate dielectric and/or other material layer etc. all respectively, be not shown among the figure for simplified herein.In addition, can be optionally with first grid storehouse 16, second grid storehouse 18, and the 3rd stack 20 be screen, and substrate 10 is carried out the light dope ion implantation technology with respectively at forming first light dope source electrode/drain region 16a, second light dope source electrode/drain region 18a, and the 3rd light dope source electrode/drain region 20a in the substrate 10 of stack both sides.The formation of light dope source electrode/drain region can for example be implanted arsenic ion or phosphonium ion in the substrate 10 with lower energy and doping.The formation of light dope source electrode/drain region can be avoided thermoelectronic effect effectively.
For the service speed and the density of promoting assembly, the clearance wall that will approach on first grid storehouse 16 will be formed in subsequent technique, and need the second grid storehouse 18 of higher operation voltage assembly and the 3rd stack 20 to be formed thick and thicker clearance wall last time respectively, can puncture under the prerequisite of (breakdown) avoiding with the assembly of guaranteeing higher operation voltage, have very fast service speed.
Then, as shown in Figure 1, can be through for example the method or the oxidizing process of chemical vapour deposition (CVD) form first dielectric layer 22 in substrate 10.But be covered in to first dielectric layer, 22 compliances first grid storehouse 16, second grid storehouse 18, and the top and the sidewall of the 3rd stack 20.Wherein, the thickness of first dielectric layer 22 will determine first grid storehouse 16 formed clearance wall thickness in subsequent technique, and the thickness that can optionally adjust first dielectric layer 22 meets the operational requirements of assembly.Because the required clearance wall thinner thickness of first grid storehouse, therefore the thinner thickness of first dielectric layer 22 of required formation is an example with 90 nanometer technologies, approximately
To about
Be preferably approximately
The material of first dielectric layer 22 comprises silica, silicon nitride, silicon oxynitride or other material that is fit to.
Next, in order to make the thick clearance wall at high-voltage assembly, and avoid in the array district 12 to form defectives, the present invention deposits second dielectric layer of thick clearance wall in two stages.The deposition of the second dielectric layer phase I (i.e. the second dielectric layer 24a) please refer to Fig. 2-Fig. 4, after forming the second dielectric layer 24a in the substrate 10, optionally removes, and only stays the second dielectric layer 24a of the 3rd stack 20.
Please refer to Fig. 2, after forming first dielectric layer 22, for example can seeing through, the method for chemical vapour deposition (CVD) deposits the second dielectric layer 24a on first dielectric layer 22.The second dielectric layer 24a will form the clearance wall of the 3rd stack 20 jointly with first dielectric layer 22 and the follow-up second dielectric layer 24b that will deposit once more.The clearance wall thickness of visual required the 3rd stack 20 of the thickness of the second dielectric layer 24a, the thickness of the follow-up second dielectric layer 24b that will deposit once more, and array district 12 in the patient thickness of high-aspect-ratio opening wait and adjust.The thickness of the second dielectric layer 24a is example with the technology of 90 nanometers, approximately
To about
Be preferably approximately
The second dielectric layer 24a need select the material that is different from first dielectric layer 22 for use, is beneficial to optionally remove in the subsequent technique the second dielectric layer 24a.The material of the second dielectric layer 24a can comprise silicon nitride, silica, silicon oxynitride or other material that is fit under the prerequisite that is different from first dielectric layer 22.Such as all optionally remove the combination of materials of one, all can not influence under the assembly operation in order to as first dielectric layer and second dielectric layer.
As shown in Figure 3, formed second the electricity layer 24a after, can form protective material for example first photoresist layer 26 on the 3rd stack 20.When the follow-up second dielectric layer 24a that for example removes with etching method on first grid storehouse 16 and the second grid storehouse 18, first photoresist layer 26 can remove in order to protect the second dielectric layer 24a on the 3rd stack 20 to avoid being subjected to etching.The formation of first photoresist layer 26 can comprise the coating photoresist layer in substrate 10, and then photoresist layer is exposed and developing process to form first photoresist layer 26 that only covers the 3rd stack 20.Yet, also can use other mask layer to substitute first photoresist layer 26.
Then, please refer to Fig. 4, remove and be not subjected to the second dielectric layer 24a that first photoresist layer 26 protects and expose first dielectric layer 22 on first grid storehouse 16 and the second grid storehouse 18.The removing to use of the second dielectric layer 24a comprises dry-etching method or wet etching.Because the material of the second dielectric layer 24a is different with first dielectric layer 22, cooperate the technology that removes again to be fit to, optionally remove the second dielectric layer 24a.For example when the material of first dielectric layer 22 are silica, and the material of the second dielectric layer 24a is when being silicon nitride, suitable dry-etching is preferably the anisotropic reactive ion etching method (anisotropic RIE) of utilizing, the etchant that is fit to comprises CHF
4/ O
2, CF
4/ H
2, C
2F
6, C
3F
8, NF
3, or aforesaid combination etc.The wet etching that is fit to comprises that use hot phosphoric acid solution (between about 150 ℃-Yue 200 ℃) comes the etching second dielectric layer 24a (silicon nitride layer).Then, remove the protective material on the 3rd stack 20, for example be shown in first photoresist layer 26 of Fig. 3.The removing of first photoresist layer 26 can wet type divests method or dry type and divests method and carry out.Wet type divests method and comprises that organic solvents such as using acetone and aromatic series or inorganic solutions such as sulfuric acid and hydrogen peroxide remove photoresistance.Dry type divests method and comprises that use oxygen electricity slurry comes ashing (ashing) photoresistance, makes photoresist be reacted into CO, the CO of gaseous state
2, and H
2O etc. and removing.
Then carry out the deposition (i.e. the second dielectric layer 24b) of the second dielectric layer second stage.As shown in Figure 5, behind the second dielectric layer 24a that removes part and first photoresist layer 26, for example the method for chemical vapour deposition (CVD) forms second dielectric layer (i.e. second dielectric layer 24b) in substrate 10 once more.The second dielectric layer 24b of Xing Chenging and first dielectric layer 22 will be formed the clearance wall of second grid storehouse 18 jointly in subsequent technique once more.The demand of the low-voltage assembly under the visual second grid storehouse 18 of the thickness of the second dielectric layer 24b adjusts, so still should not be blocked up to avoid forming defective in the high depth-width ratio open in array district 12, the thickness of the second dielectric layer 24b is example with the technology of 90 nanometers, about 200
To about 600
, be preferably about 400
Then, as shown in Figure 6, the second dielectric layer 24b that etch-back (etch back) forms once more and the second dielectric layer 24a are to expose first grid storehouse 16, second grid storehouse 18, and first dielectric layer 22 of the top section of the 3rd stack 20.Be similar to removing of the second dielectric layer 24a among Fig. 4,, cooperate again, optionally remove the second dielectric layer 24b with suitable etch back process because the material of the second dielectric layer 24b is different with first dielectric layer 22.Preferable use anisotropic etching comes the etch-back second dielectric layer 24b, for example uses reactive ion etching method (RIE), and the material of the visual second dielectric layer 24b of used etchant is selected for use.In addition; because the 3rd stack 20 before had been subjected to the protection of first photoresist layer 26 and had once deposited twice second dielectric layer 24a and the 24b, therefore the thickness of second dielectric layer (24a and 24b) around the 3rd stack 20 is greater than second dielectric layer (24b) around the second grid storehouse 18.Wherein, second dielectric layer 24a of the 3rd stack 20 peripheries and the gross thickness of 24b are example with the technology of 90 nanometers, about 1000
To about 1400
, be preferably about 1200
Please follow with reference to Fig. 7, can form protective material for example second photoresist layer 28 in substrate 10 with second dielectric layer 24 of protection in the surrounding zone 14.Second photoresist layer 28 can form similar in appearance to the method for first photoresist layer 26.
As shown in Figure 8, after forming the protective material (for example second photoresist layer 28 among Fig. 7) of surrounding zone 14, can use dry-etching method for example or wet etching to remove the second dielectric layer 24b in the array district 12.Similar in appearance to removing of preceding twice second dielectric layer 24a or 24b,, therefore optionally remove the second dielectric layer 24b in the array district 12 because the material of the second dielectric layer 24b is different from first dielectric layer 22.
Please follow with reference to Fig. 9, after removing second photoresist layer 28, first dielectric layer 22 is carried out etch back process exposing first grid storehouse 16, second grid storehouse 18, and the upper surface of the 3rd stack 20, and in first grid storehouse 16, second grid storehouse 18, and the sidewall of the 3rd stack 20 form first clearance wall, second clearance wall, and third space wall respectively.Preferable use anisotropic etching comes etch-back first dielectric layer 22, for example uses reactive ion etching method (RIE), and the material of visual first dielectric layer 22 of used etchant is selected for use.Wherein, on the whole the thickness of first clearance wall determined by the thickness of first dielectric layer 22, and second clearance wall and third space wall are made of jointly first dielectric layer 22 and second dielectric layer (24b or 24a and 24b) respectively.In an embodiment of the present invention, the compound clearance wall (composite spacer) that second clearance wall and third space wall are made of jointly first dielectric layer 22 and second dielectric layer (24b or 24a and 24b), and wherein first dielectric layer 22 is " L " types (as shown in Figure 9).
Then can carry out ion implantation technology to form source/drain regions to substrate 10.As shown in figure 10, with formed first clearance wall, second clearance wall, and the third space wall be mask and ion implantation technology is carried out in substrate 10, respectively at first grid storehouse 16, second grid storehouse 18, and the substrate 10 of the clearance wall both sides of the 3rd stack 20 form the first source/drain regions 16a, the second source/drain regions 18a, and the 3rd source/drain regions 20a respectively.
As mentioned above, the present invention has needs many advantages, and different assembly peripheries that embodiments of the invention can be in semiconductor structure for example form the clearance wall of different-thickness.Can by the clearance wall of different-thickness form different length channel (source electrode with drain between distance) or light dope source electrode/drain region to meet the demand of different assemblies.And see through the thin dielectric layer of gradation deposition and be combined into thicker clearance wall, the defective that is produced in the time of can avoiding forming thicker dielectric layer is for example because of the defective of the not good hole that produces of step coverage rate or the unfavorable subsequent techniques such as (overhang) of overhanging.And in an embodiment of the present invention, only need the twice mask process just can form the clearance wall of three kinds of thickness, escapable cost.
It will be recognized by one skilled in the art that the assembly in the semiconductor structure has many kinds, naturally its best clearance wall thickness differs from one another, embodiments of the invention are described the clearance wall of three kinds of thickness that form energy optimization assembly overall performance.Those skilled in the art work as can be if necessary in not breaking away under the spirit of the present invention, and the clearance wall that forms thickness more than three kinds is to meet the demand of indivedual semiconductor structures.And also can form three kinds of channel region or runnings of coming the optimization semiconductor structure of light dope source electrode/drain region more than the length by the clearance wall of these thickness more than three kinds.
Though the present invention discloses as above with several preferred embodiments; yet be not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can changing arbitrarily and retouching, so protection scope of the present invention is when looking being as the criterion that the claim scope defined.
Claims (6)
1. the formation method of a semiconductor structure, this method may further comprise the steps:
One substrate is provided, and this substrate comprises an array district and a surrounding zone, and comprises a plurality of first grid storehouses in this array district, and comprises the second grid storehouse of a low-voltage assembly and the 3rd stack of a high-voltage assembly in this surrounding zone;
Form top and sidewall that one first dielectric layer is covered in described first grid storehouse, this second grid storehouse, reaches the 3rd stack;
Deposit one second dielectric layer on this first dielectric layer;
Remove this second dielectric layer that is positioned on described first grid storehouse and this second grid storehouse, and stay this second dielectric layer on the 3rd stack;
Deposit once more this second dielectric layer in described first grid storehouse, this second grid storehouse, and the 3rd stack on;
The described first grid storehouse of etch-back, this second grid storehouse, and the 3rd stack on this second dielectric layer, with expose described first grid storehouse, this second grid storehouse, and the 3rd stack on this first dielectric layer of top section;
Remove this second dielectric layer in this array district to expose this first dielectric layer; And
This first dielectric layer of etch-back to be exposing described first grid storehouse, this second grid storehouse, and the upper surface of the 3rd stack, and in described first grid storehouse, this second grid storehouse, and the sidewall of the 3rd stack form one first clearance wall, one second clearance wall, an and third space wall respectively;
Wherein the thickness of this third space wall is greater than this second clearance wall, and the thickness of this second clearance wall is greater than this first clearance wall.
2. the formation method of semiconductor structure as claimed in claim 1, wherein the material of this first dielectric layer and this second dielectric layer is selected from following dissimilar material, comprises silica, silicon nitride or silicon oxynitride.
3. the formation method of semiconductor structure as claimed in claim 1 wherein before removing this second dielectric layer that is positioned on described first grid storehouse and this second grid storehouse, also comprises forming one first photoresist layer earlier to protect the 3rd stack.
4. the formation method of semiconductor structure as claimed in claim 1, wherein this second dielectric layer in removing this array district also comprises before this first dielectric layer and forms one second photoresist layer earlier to protect this second grid storehouse and the 3rd stack to expose.
5. the formation method of semiconductor structure as claimed in claim 1, wherein the etch-back of this first dielectric layer becomes the L type with this first dielectric layer etch in this second clearance wall and this third space wall.
6. the formation method of semiconductor structure as claimed in claim 1 comprises that also with this first clearance wall, this second clearance wall or this third space wall be mask and this substrate is carried out an ion implantation technology to form source at least.
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| CN200710160007XA CN101465325B (en) | 2007-12-20 | 2007-12-20 | Method for forming semiconductor structure |
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|---|---|---|---|
| CN200710160007XA CN101465325B (en) | 2007-12-20 | 2007-12-20 | Method for forming semiconductor structure |
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| CN101465325B true CN101465325B (en) | 2010-07-07 |
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| CN107104050A (en) * | 2016-02-19 | 2017-08-29 | 北大方正集团有限公司 | The preparation method and field-effect transistor of field-effect transistor |
| CN108538788B (en) * | 2017-03-01 | 2020-10-02 | 联华电子股份有限公司 | Method for manufacturing semiconductor memory device |
| CN110349908B (en) * | 2018-04-03 | 2022-11-04 | 华邦电子股份有限公司 | Self-aligned contact structure and method for forming the same |
| CN118055612A (en) * | 2022-11-07 | 2024-05-17 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1131561C (en) * | 1998-05-20 | 2003-12-17 | 三星电子株式会社 | Method for fabricating semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1131561C (en) * | 1998-05-20 | 2003-12-17 | 三星电子株式会社 | Method for fabricating semiconductor device |
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