CN104143528B - The forming method of interconnection structure - Google Patents
The forming method of interconnection structure Download PDFInfo
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- CN104143528B CN104143528B CN201310170457.2A CN201310170457A CN104143528B CN 104143528 B CN104143528 B CN 104143528B CN 201310170457 A CN201310170457 A CN 201310170457A CN 104143528 B CN104143528 B CN 104143528B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
Abstract
A kind of forming method of interconnection structure, including：Semiconductor substrate is provided；Sequentially form interlayer dielectric layer, dielectric hard mask layer and metal hard mask layer from the bottom to top on a semiconductor substrate, the material of interlayer dielectric layer is low-k materials or ultralow-k material film；Form first in metal hard mask layer to be open, metal hard mask layer is run through in the first opening；With remaining metal hard mask layer as mask, etch media hard mask layer and interlayer dielectric layer, until forming etching structure in interlayer dielectric layer, etching structure includes one kind or its combination in through hole and groove；Full sacrifice layer is filled in etching structure；Remaining metal hard mask layer and sacrifice layer are removed successively；Full metal material is filled in etching structure.The present invention forms the pattern of metal interconnecting wires, metal plug or dual-damascene structure preferably, and the performance of the semiconductor devices comprising formed metal interconnecting wires, metal plug or dual-damascene structure is preferable.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of interconnection structure.
Background technology
Gradually increase with to super large-scale integration high integration and high performance demand, semiconductor technology towards
The technology node development of the even more small characteristic sizes of 65nm, and the arithmetic speed of chip is substantially subject to the electricity caused by metallic conduction
Hinder the influence of capacitance delays.
On the one hand, in order to improve the performance of integrated circuit, using having the advantages that low-resistivity, excellent deelectric transferred ability
Copper replace aluminium as the metal interconnecting wires in semiconductor, it is possible to decrease metal interconnecting wires resistance.
On the other hand, by the use of low-k materials or ultralow-k material film as the interlayer dielectric layer of metal interconnecting wires, can be effective
Reduce electric capacity.
The metal interlamination medium layer that copper dual-damascene technology collocation low-k materials are constituted is interconnection structure most popular at present
Process combination, its phenomenon that can be effectively improved RC delays, the standard that will turn into generation semiconductor technique is interconnected
Technology.
A kind of forming method of copper dual-damascene structure includes in existing process：Semiconductor substrate is provided, and is partly led described
Interlayer dielectric layer, dielectric hard mask layer and metal hard mask layer are sequentially formed on body substrate from the bottom to top；Covered in the metallic hard
Formed in film layer through the first opening of its thickness, the location and shape of first opening are respectively with to be subsequently formed copper metal mutual
The location and shape correspondence of line；Photoresist layer is formed in the described first opening, and is formed in the photoresist layer and is run through
Its thickness second opening, it is described second opening location and shape respectively with the location and shape for being subsequently formed copper metal connector
Correspondence；With metal hard mask layer as mask, the photoresist layer comprising the second opening, dielectric hard mask layer and interlayer dielectric layer are entered
Row etching, to the Semiconductor substrate is exposed, groove is formed and positioned at the logical of beneath trenches with the interlayer dielectric layer
Hole；The metal hard mask layer is removed by wet etching；Metal hard mask layer around the through hole, groove and groove
Upper formation copper metal material；The copper metal material and dielectric layer hard mask layer are carried out using chemical mechanical milling tech flat
Change, to the interlayer dielectric layer is exposed, the dual-damascene structure of copper metal interconnection line and copper metal connector is included to be formed.
However, being found when the copper dual-damascene structure formed to above-mentioned technique is checked：Formed copper dual-damascene structure
Pattern it is poor, and the semiconductor devices including formed copper dual-damascene structure poor-performing.
The content of the invention
The problem that the present invention is solved is to provide a kind of forming method of interconnection structure, make the pattern of formed interconnection structure compared with
It is good, improve the performance comprising the semiconductor devices for forming interconnection structure.
To solve the above problems, the present invention provides a kind of forming method of interconnection structure, including：
Semiconductor substrate is provided；
Sequentially form interlayer dielectric layer, dielectric hard mask layer and metal hard mask from the bottom to top on the semiconductor substrate
Layer, the material of the interlayer dielectric layer is low-k materials or ultralow-k material film；
Form first in the metal hard mask layer to be open, the metal hard mask layer is run through in first opening；
With the remaining metal hard mask layer as mask, the dielectric hard mask layer and interlayer dielectric layer are etched, until
Etching structure is formed in the interlayer dielectric layer, the etching structure includes one kind or its combination in through hole and groove；
Full sacrifice layer is filled in the etching structure；
The remaining metal hard mask layer and the sacrifice layer are removed successively；
Full metal material is filled in the etching structure.
Optionally, the material of the metal hard mask layer is titanium nitride, copper nitride or aluminium nitride.
Optionally, the method for removing the metal hard mask layer is wet etching, and the solution of the wet etching is dioxygen
The mixed solution of water and acid solution, the acid solution includes one or more in hydrofluoric acid, hydrochloric acid and sulfuric acid.
Optionally, the material of the sacrifice layer is bottom anti-reflective material.
Optionally, the method for removing the sacrifice layer is dry etching, the gas of the dry etching include nitrogen or
Oxygen-containing gas.
Optionally, the material of the sacrifice layer is siliceous antireflection material.
Optionally, the method for removing the sacrifice layer is wet etching, and the solution of the wet etching is propylene glycol monomethyl ether
With the mixed solution of propylene glycol monomethyl ether acetate, or in propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate and CLK888
A kind of solution.
Optionally, the material of the sacrifice layer is amorphous carbon.
Optionally, the method for removing the sacrifice layer is cineration technics.
Optionally, the material of the sacrifice layer is DOU（DOU is a kind of semi-conducting material of Honeywell companies）, removal
The method of the sacrifice layer is wet etching, and the solution of the wet etching is CLK888（CLK888 is Mallinckrodt
A kind of etching agent of Baker companies）.
Optionally, the etching structure includes through hole and groove；With the remaining metal hard mask layer as mask, etching
The dielectric hard mask layer and interlayer dielectric layer, until etching structure is formed in the interlayer dielectric layer including:Described
Photoresist layer is formed in one opening, the second opening of the photoresist layer thickness is formed through in the photoresist layer；With institute
It is mask to state metal hard mask layer and photoresist layer, and the interlayer dielectric layer is performed etching, remaining pre- to the second opening lower section
Determine the interlayer dielectric layer of thickness；Remove the photoresist layer；With the metal hard mask layer as mask, the inter-level dielectric is etched
Layer, until exposing the Semiconductor substrate.
Compared with prior art, technical scheme has advantages below：
After formation etching structure in interlayer dielectric layer, filling in etching structure is formed in the interlayer dielectric layer full
Sacrifice layer, to protect the interlayer dielectric layer during metal hard mask layer is removed, then removes the metallic hard successively
Mask layer and sacrifice layer, finally fill full metal material, to be formed by metal interconnecting wires and metal in formed etching structure
Dual-damascene structure, metal interconnecting wires or metal plug that connector is constituted.During metal hard mask layer is removed, the sacrifice
Layer can effectively protect the interlayer dielectric layer on the wall of etching structure side, make formed dual-damascene structure, metal interconnecting wires or
The pattern of person's metal plug preferably, improves the semiconductor devices including dual-damascene structure, metal interconnecting wires or metal plug
Performance.
Brief description of the drawings
Fig. 1 to Fig. 8 is the schematic diagram of the forming method first embodiment of interconnection structure of the present invention；
Fig. 9 to Figure 12 is the schematic diagram of the forming method second embodiment of interconnection structure of the present invention.
Specific embodiment
Inventor by research find, existing process formed copper metal connector pattern it is poor, including copper dual-damascene structure
The poor-performing of semiconductor devices mainly caused by following reason：In order to reduce the k values of interlayer dielectric layer, generally using porous
The low-k materials or ultralow-k material film of structure pass through wet etching and remove the metal hard mask layer as interlayer dielectric layer
When, etching solution easily reacts through through hole with interlayer dielectric layer, destroys the interlayer dielectric layer, and make formed through hole with
Groove deforms, and have impact on the pattern of formed copper dual-damascene structure, also have impact on the semiconductor including copper dual-damascene structure
The performance of device.
It is similar, forming copper metal interconnection line or copper metal connector by above-mentioned technique, or by above-mentioned technique
When forming dual-damascene structure, metal interconnecting wires or the metal plug of other materials, above mentioned problem is there is also.
Therefore, the invention provides a kind of forming method of interconnection structure, formed in interlayer dielectric layer etching structure it
Afterwards, the full sacrifice layer of filling in etching structure is formed in the interlayer dielectric layer, the sacrifice layer can be covered in removal metallic hard
The interlayer dielectric layer is protected during film layer, it is to avoid the removal technique of metal hard mask layer causes to damage to interlayer dielectric layer.
After metal hard mask layer is removed, sacrifice layer is removed, full metal material is filled in etching structure, formed by metal interconnecting wires
Dual-damascene structure, metal interconnecting wires or the metal plug constituted with metal plug.During metal hard mask layer is removed, by
It is not damaged in interlayer dielectric layer, forms dual-damascene structure, metal interconnecting wires or metal plug pattern preferably, including
The performance of the semiconductor devices of formed dual-damascene structure, metal interconnecting wires or metal plug is preferable.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
First embodiment
The present embodiment is forming dual-damascene structure（I.e. etching structure includes groove and through hole simultaneously）As a example by, it is mutual to the present invention
The forming method for linking structure is illustrated.
With reference to Fig. 1, there is provided Semiconductor substrate 200, and sequentially form etching from the bottom to top in the Semiconductor substrate 200
Stop-layer 202a, interlayer dielectric layer 204a, dielectric hard mask layer 206a and metal hard mask layer 208.
In the present embodiment, the material of the Semiconductor substrate 200 can for monocrystalline silicon, monocrystalline germanium or monocrystalline germanium silicon, absolutely
Silicon, iii-v element compound, monocrystalline silicon carbide etc. are well known to a person skilled in the art other materials on edge body.
Additionally, may also be formed with device architecture in the Semiconductor substrate 200（It is not shown）, the device architecture can be half
The device architecture formed in conductor FEOL, such as MOS transistor etc..
In the present embodiment, it can be silica, silicon nitride, silicon oxynitride, carbonization that the material of the etching stop layer 202a is
Silicon and containing one or several the combination in carbonitride of silicium, with the stopping formed as etching in groove and via process
Layer, it is to avoid etching technics causes to damage to the Semiconductor substrate 200.The material of the interlayer dielectric layer 204a is low-k materials
Or ultralow-k material film.The method for forming the interlayer dielectric layer 204a can be chemical vapor deposition method.The dielectric hardmask
The material of layer 206a can be silica, silicon nitride, silicon oxynitride, carborundum and containing one or several the group in carbonitride of silicium
Close, be used to improve the adhesiveness between interlayer dielectric layer 204a and the metal hard mask layer 208 that is subsequently formed, and as interlayer
The protective layer of dielectric layer 204a, in preventing metallic atom in metal hard mask layer 208 from diffusing to interlayer dielectric layer 204a, it is to avoid right
The k values of interlayer dielectric layer 204a are impacted, and prevent electric leakage.The method for forming the dielectric hard mask layer 206a can be to change
Learn gas-phase deposition.The material of the metal hard mask layer 208 can be titanium nitride, copper nitride or aluminium nitride.Form described
The method of metal hard mask layer 208 is chemical vapor deposition method.
With continued reference to Fig. 1, the first opening 210, the position of first opening 210 are formed in metal hard mask layer 208
It is corresponding with the location and shape for being subsequently formed metal interconnecting wires in dual-damascene structure respectively with shape.
Specifically, it is mask that can use photoresist layer, the metal hard mask layer 208 is performed etching, form described the
One opening 210.Its specific formation process is well known to those skilled in the art, and will not be repeated here.
With reference to Fig. 2, photoresist layer 212 is formed in first opening 210 in Fig. 1, formed in the photoresist layer 212
Have through the second opening 214 of the thickness of the photoresist layer 212.
In the present embodiment, the location and shape of second opening 214 respectively be subsequently formed metal in dual-damascene structure
The location and shape correspondence of connector.Formation includes that the method for the photoresist layer 212 of the second opening 214 is those skilled in the art institute
Know, will not be repeated here.
With reference to Fig. 3, with metal hard mask layer 208 described in Fig. 2 and photoresist layer 212 as mask, to dielectric hard mask layer
206a, interlayer dielectric layer 204a are performed etching, to the interlayer dielectric layer 204a of the remaining predetermined thickness in the lower section of the second opening 214；So
After remove the photoresist layer 212；Subsequently, with the metal hard mask layer 208 as mask, continue to etch the inter-level dielectric
Layer 204a, until expose the etching stop layer 202a, in the interlayer dielectric layer 204b to form groove 216 and be located at
The through hole 218 of the lower section of groove 216.
In the present embodiment, the method performed etching to dielectric hard mask layer 206a, interlayer dielectric layer 204a is dry etching,
Such as anisotropic dry etch, its specific etching technics is well known to those skilled in the art, will not be repeated here.Removal is described
The method of photoresist layer 212 can be cineration technics.
It should be noted that with metal hard mask layer 208 described in Fig. 2 and photoresist layer 212 as mask, it is hard to medium
When mask layer 206a, interlayer dielectric layer 204a are performed etching, the interlayer dielectric layer of the remaining predetermined thickness in lower section of the second opening 214
The thickness of 204a is corresponding with the depth of follow-up formed groove 216.
Also, it should be noted that during groove 216 and through hole 218 is formed, positioned at the medium of the lower section of hard mask layer 208
Hard mask layer 206b is not removed.
With reference to Fig. 4, full sacrifice layer 220 is filled in the groove 216 and through hole 218 in figure 3.
In the present embodiment, the material of the sacrifice layer 220 can be bottom anti-reflective material, amorphous carbon, siliceous anti-reflective
Penetrate material or DOU.The full sacrifice layer 220 of filling may include following steps in groove 216 and through hole 218：In the groove 216
With in through hole 218, in the opening that is enclosed by dielectric hard mask layer 206b and metal hard mask layer 208 of the top of groove 216 with
And form sacrifice layer on the metal hard mask layer 208 around groove 216；Sacrifice layer of the removal on metal hard mask layer 208.
In the present embodiment, the method that can remove the sacrifice layer on metal hard mask layer 208 is cmp work
Skill, can also be dry etch process.When the sacrifice layer on metal hard mask layer 208 is removed by dry etch process,
The dry etching gas can be nitrogen or oxygen-containing gas.
With reference to Fig. 5, metal hard mask layer 208 described in removal Fig. 4.
In the present embodiment, the method for removing the metal hard mask layer 208 can be wet etching, the wet etching it is molten
Liquid is the mixed solution of hydrogen peroxide and acid solution, the acid solution include one kind in hydrofluoric acid, hydrochloric acid and sulfuric acid or
It is various.By the upper surface of interlayer dielectric layer 204b is covered by the dielectric hard mask layer 206b, and groove 216 and through hole
Interlayer dielectric layer 204b on 218 side walls is sacrificed layer 220 and is covered, and can avoid the solution of wet etching to interlayer dielectric layer
204b causes to damage, and can also avoid the groove 216 caused by interlayer dielectric layer 204b is by the solution consumption of wet etching and lead to
Hole 218 deforms, and the pattern for forming groove 216 and through hole 218 is preferable.
With reference to Fig. 6, sacrifice layer 220 described in removal Fig. 5 exposes the ditch in the interlayer dielectric layer 204b again
Groove 216 and through hole 218.
In the present embodiment, when the material of sacrifice layer 220 is bottom anti-reflective material（BARC）When, removal sacrifice layer 220
Method can be wet etching, dry etching or cineration technics.When the sacrifice layer 220 is removed using wet etching, wet method
The solution of etching can be the mixed solution of propylene glycol monomethyl ether and propylene glycol monomethyl ether acetate, or be propylene glycol monomethyl ether, the third two
A kind of solution in alcohol monomethyl ether acetate and CLK888.When the sacrifice layer 220 is removed using dry etching, the dry method
The gas of etching can be nitrogen or oxygen-containing gas.
When the material of sacrifice layer 220 is amorphous carbon, the method for removing the sacrifice layer 220 can also be cineration technics.
When the material of sacrifice layer 220 is siliceous antireflection material（Si-ARC）When, removing the method for sacrifice layer 220 can be
Wet etching, the solution of the wet etching can be the mixed solution of propylene glycol monomethyl ether and propylene glycol monomethyl ether acetate, or
A kind of solution only in propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate and CLK888.
When the material of the sacrifice layer 220 is DOU, the method for removing the sacrifice layer 220 can be wet etching, described
The solution of wet etching can be CLK888.
During sacrifice layer 220 is removed, due to the solution of the etching gas of dry etching, wet etching in above-mentioned technique
Or the gas of cineration technics will not cause to damage to interlayer dielectric layer 204b, make the pattern of formed groove 216 and through hole 218
Preferably.
With reference to Fig. 7, the etching stop layer 202a of the bottom of through hole 218 is located in removal Fig. 6, is served as a contrast to the semiconductor is exposed
Bottom 200, to form through hole 219, and the remaining etching stop layer 202b around through hole 219.
In the present embodiment, removal can be alternatively positioned at the method for the bottom etching stop layer 202a of through hole 218 for dry etching
Wet etching.The bottom etching stop layer 202a of through hole 218 is such as located at using wet etching removal, the solution of the wet etching can
It is phosphoric acid solution.Because phosphoric acid solution is slow with the reaction of the interlayer dielectric layer 204b, its damage to interlayer dielectric layer 204b
Wound is negligible.
With reference to Fig. 8, full metal material is filled in the groove 216 and through hole 219 in the figure 7, it is mutual to form metal respectively
Line 222 and metal plug 224, the metal interconnecting wires 222 and metal plug 224 collectively form dual-damascene structure.
In the present embodiment, the metal material can be copper, and the method for forming copper metal material can be physical vapour deposition (PVD) work
Skill.Forming metal interconnecting wires 222 and metal plug 224 may include following steps：In the figure 7 in the groove 216 and through hole 219
And copper metal material is formed on the dielectric hard mask layer 206 around groove 216；Using chemical mechanical milling tech to the copper
Metal material and dielectric hard mask layer 206 are planarized, and to the interlayer dielectric layer 204b is exposed, form copper metal interconnection
Line 222 and copper metal connector 224.
In other embodiments, full other metal materials can be also filled in the groove 216 and through hole 219（Such as：Tungsten,
Aluminium etc.）, to form the metal interconnecting wires and metal plug of other materials, the invention is not limited in this regard.
In the present embodiment, before the full metal material of filling in groove 216 and through hole 219, first removal is located at groove 216 weeks
The metal hard mask layer 208 for enclosing, reduces the depth-to-width ratio of groove 216 and the depth-to-width ratio of through hole 219, reduces in groove 216 and leads to
The difficulty of metal material is filled in hole 219, groove 216 and the filling effect of through hole 219 is improve.And, metal hard mask layer 208
Removal technique will not to the interlayer dielectric layer 204b around dual-damascene structure cause damage, make formed groove 216 and through hole
Preferably, and then it is also preferable to form the dual-damascene structure pattern including metal interconnecting wires 222 and metal plug 224 for 219 pattern,
Effectively increase the performance of the semiconductor devices including formed dual-damascene structure.
Second embodiment
The present embodiment is with the metal plug in single mosaic technology（I.e. etching structure only includes through hole）As a example by, it is mutual to the present invention
The forming method for linking structure is illustrated, metal interconnecting wires（Corresponding etching structure only includes groove）Forming method and metal
The forming method of connector is similar to, and is not detailed herein.
With reference to Fig. 9, there is provided Semiconductor substrate 300, etch-stop is sequentially formed from the bottom to top in the Semiconductor substrate 300
Only layer 302a, interlayer dielectric layer 304, dielectric hard mask layer 306 and metal hard mask layer 308, and formed and run through the metallic hard
First opening of mask layer 308（It is not shown）And simultaneously through dielectric hard mask layer 306 and the through hole of interlayer dielectric layer 304
（It is not shown）, full sacrifice layer 312 is then filled in the through hole.
In the present embodiment, the Semiconductor substrate 300, etching stop layer 302a, interlayer dielectric layer 304, dielectric hardmask
The material of layer 306, metal hard mask layer 308 and sacrifice layer 312, formation process refer to first embodiment, be not detailed herein.
In other embodiments, the etching stop layer 302a can be also omitted, the direct shape in the Semiconductor substrate 300
Into the interlayer dielectric layer 304.
With reference to Figure 10, metal hard mask layer 308 described in removal Fig. 9.
In the present embodiment, the method for removing metal hard mask layer 308 refer to first embodiment, will not be repeated here.By
Layer 312 is sacrificed in the interlayer dielectric layer 304 on through-hole side wall to be covered, and be located at interlayer dielectric layer 304 around through hole
On the surface of interlayer dielectric layer 304 covered by the dielectric hard mask layer 306, the removal of metal hard mask layer 308 can be avoided
Technique causes to damage to interlayer dielectric layer 304, improves the performance of formed semiconductor devices.
With reference to Figure 11, sacrifice layer 312 described in Figure 10, the etching stop layer positioned at the lower section of sacrifice layer 312 are removed successively
302a, forms the through hole 314 through the interlayer dielectric layer 304 and etching stop layer 302b.Specifically may include following steps：First
Sacrifice layer 312 described in removal Figure 10；Again with dielectric hard mask layer 306 as mask, etching stop layer 302a described in etching Figure 10,
To exposing the Semiconductor substrate 300.
In the present embodiment, the sacrifice layer 312 and please positioned at the method for the lower section etching stop layer 302a of sacrifice layer 312 is removed
With reference to the corresponding steps of first embodiment.When sacrifice layer 312 is removed, positioned at the etching stop layer 302a of the lower section of sacrifice layer 312
Semiconductor substrate 300 can effectively be protected from damaging.
With reference to Figure 12, full metal material is filled in the through hole 314 in fig. 11, form copper metal connector 316.Its is specific
May include following steps：In Fig. 10 copper is formed on the dielectric hard mask layer 306 in the through hole 314 and around through hole 314
Metal material；Flatening process is carried out to copper metal material and dielectric hard mask layer 306 using chemical mechanical milling tech, to sudden and violent
Expose the interlayer dielectric layer 304, form copper metal connector 316.
In the present embodiment, damage is not caused during removal metal hard mask layer 308 to interlayer dielectric layer 304, and ensureing logical
While 314 filling effect of hole, make the pattern for being formed at through hole 314 in interlayer dielectric layer 304 preferable, and then make formed metal
The pattern of connector 316 preferably, improves the performance of the semiconductor devices including formed metal plug 316.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (12)
1. a kind of forming method of interconnection structure, it is characterised in that including：
Semiconductor substrate is provided；
Sequentially form interlayer dielectric layer, dielectric hard mask layer and metal hard mask layer from the bottom to top on the semiconductor substrate,
The material of the interlayer dielectric layer is low-k materials or ultralow-k material film；
Form first in the metal hard mask layer to be open, the metal hard mask layer is run through in first opening；
With the remaining metal hard mask layer as mask, the dielectric hard mask layer and interlayer dielectric layer are etched, until in institute
State and formed in interlayer dielectric layer etching structure, the etching structure includes one kind or its combination in through hole and groove；
Full sacrifice layer is filled in the etching structure；
The remaining metal hard mask layer and the sacrifice layer are removed successively；
Full metal material is filled in the etching structure；
The material of the sacrifice layer is bottom anti-reflective material, siliceous antireflection material or amorphous carbon.
2. the forming method of interconnection structure as claimed in claim 1, it is characterised in that the material of the metal hard mask layer is
Titanium nitride, copper nitride or aluminium nitride.
3. the forming method of interconnection structure as claimed in claim 2, it is characterised in that the side of the removal metal hard mask layer
Method is wet etching, and the solution of the wet etching is hydrogen peroxide and the mixed solution of acid solution, and the acid solution includes
One or more in hydrofluoric acid, hydrochloric acid and sulfuric acid.
4. the forming method of interconnection structure as claimed in claim 1, it is characterised in that when the material of the sacrifice layer is bottom
During antireflection material, the method for removing the sacrifice layer is dry etching, and the gas of the dry etching includes nitrogen or contains
Carrier of oxygen.
5. the forming method of interconnection structure as claimed in claim 1, it is characterised in that the material of the sacrifice layer is siliceous
Antireflection material.
6. the forming method of interconnection structure as claimed in claim 5, it is characterised in that the method for the removal sacrifice layer is wet
Method is etched, and the solution of the wet etching is propylene glycol monomethyl ether and the mixed solution of propylene glycol monomethyl ether acetate, or is third
A kind of solution in glycol methyl ether, propylene glycol monomethyl ether acetate and CLK888.
7. the forming method of interconnection structure as claimed in claim 1, it is characterised in that when the material of the sacrifice layer is without fixed
During shape carbon, the method for removing the sacrifice layer is cineration technics.
8. the forming method of interconnection structure as claimed in claim 1, it is characterised in that the sacrifice layer is DUO, removal is described
The method of sacrifice layer is wet etching, and the solution of the wet etching is CLK888.
9. the forming method of interconnection structure as claimed in claim 1, it is characterised in that the material of the dielectric hard mask layer is
Silica, silicon nitride, silicon oxynitride, carborundum and containing one or several the combination in carbonitride of silicium.
10. the forming method of interconnection structure as claimed in claim 1, it is characterised in that formed on the semiconductor substrate
Before interlayer dielectric layer, also include：Etching stop layer is formed on the semiconductor substrate, and the material of the etching stop layer is
Silica, silicon nitride, silicon oxynitride, carborundum and containing one or several the combination in carbonitride of silicium.
The forming method of 11. interconnection structures as claimed in claim 1, it is characterised in that the metal material is copper.
The forming method of 12. interconnection structures as claimed in claim 1, it is characterised in that the etching structure include through hole and
Groove；With the remaining metal hard mask layer as mask, the dielectric hard mask layer and interlayer dielectric layer are etched, until in institute
Formation etching structure includes in stating interlayer dielectric layer:Photoresist layer, shape in the photoresist layer are formed in the described first opening
It is open through the second of the photoresist layer thickness into having；With the metal hard mask layer and photoresist layer as mask, to described
Interlayer dielectric layer is performed etching, to the interlayer dielectric layer of the second remaining predetermined thickness in opening lower section；Remove the photoresist layer；
With the metal hard mask layer as mask, the interlayer dielectric layer is etched, until exposing the Semiconductor substrate.
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| CN108155145A (en) * | 2016-12-02 | 2018-06-12 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method |
| CN108281427A (en) * | 2017-01-06 | 2018-07-13 | 中芯国际集成电路制造(上海)有限公司 | Flush memory device and its manufacturing method |
| CN112201620B (en) * | 2020-10-27 | 2024-02-02 | 合肥晶合集成电路股份有限公司 | Forming method of metal interconnection structure |
| CN116598194B (en) * | 2023-07-17 | 2023-09-29 | 致真存储(北京)科技有限公司 | Hard mask manufacturing method and memory |
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| CN102403269A (en) * | 2011-11-30 | 2012-04-04 | 上海华力微电子有限公司 | Method for dry etching of first metal layer |
| CN102437101A (en) * | 2011-09-09 | 2012-05-02 | 上海华力微电子有限公司 | Improved method for integrating hard mask and porous material with low dielectric constant value |
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| CN102437101A (en) * | 2011-09-09 | 2012-05-02 | 上海华力微电子有限公司 | Improved method for integrating hard mask and porous material with low dielectric constant value |
| CN102403269A (en) * | 2011-11-30 | 2012-04-04 | 上海华力微电子有限公司 | Method for dry etching of first metal layer |
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