CN104217991B - Method for forming interconnection structures - Google Patents
Method for forming interconnection structures Download PDFInfo
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- CN104217991B CN104217991B CN201310222161.0A CN201310222161A CN104217991B CN 104217991 B CN104217991 B CN 104217991B CN 201310222161 A CN201310222161 A CN 201310222161A CN 104217991 B CN104217991 B CN 104217991B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
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Abstract
The invention discloses a method for forming interconnection structures. The method includes forming interlayer dielectric layers, adhesion layers, protection layers and hard mask layers on semiconductor substrates from bottom to top; forming first openings in the hard mask layers; carrying out plasma treatment and cleaning processes; using remaining portions of the hard mask layers as masks and sequentially etching the protection layers, the adhesion layers and the interlayer dielectric layers until etch structures are formed in the interlayer dielectric layers; filling metal materials in the etch structures and removing remaining portions of the hard mask layers, the protection layers and the adhesion layers. The first openings are perforated through the hard mask layers. The etch structures comprise through holes or grooves or combinations of the through holes and the grooves. The method has the advantages that the quantities of metal plugs or metal interconnection wires or combinations of the metal plugs and the metal interconnection wires which are formed by the aid of the method are accurate, the metal plugs and the metal interconnection wires are excellent in morphology, and semiconductor devices with the metal plugs or the metal interconnection wires or the combinations of the metal plugs and the metal interconnection wires are excellent in performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of interconnection structure.
Background technology
With gradually increasing super large-scale integration high integration and high performance demand, semiconductor technology is towards more
The technology node development of little characteristic size, and the arithmetic speed of chip is substantially subject to the RC delays caused by metallic conduction
Impact.
On the one hand, in order to improve the performance of integrated circuit, using having the advantages that low-resistivity, excellent deelectric transferred ability
Copper replace aluminum as the metal interconnecting wires in quasiconductor, it is possible to decrease metal interconnecting wires resistance.
On the other hand, by the use of low-k materials or ultralow-k material film as the interlayer dielectric layer of metal interconnecting wires, can be effective
Reduce electric capacity.
The metal interlamination medium layer that copper dual-damascene technology collocation low-k materials are constituted is interconnection structure most popular at present
Process combination, it can be effectively improved the phenomenon of RC delays.
A kind of forming method of copper dual-damascene structure includes in existing process：Semiconductor substrate is provided, and is partly led described
Sequentially form interlayer dielectric layer, adhesion layer, protective layer and hard mask layer on body substrate from the bottom to top；The hard mask layer is carried out
Etching, with formed expose the protective layer first opening, it is described first opening location and shape respectively be subsequently formed
The location and shape correspondence of copper metal interconnection line；Cleaning is carried out, to remove the polymerization remained in the first opening process is formed
Thing；Described first opening in formed include second opening photoresist layer, it is described second be open location and shape respectively with
It is subsequently formed the location and shape correspondence of copper metal connector；With metal hard mask layer and photoresist layer as mask, to protective layer, glue
Attached layer and interlayer dielectric layer are performed etching, to the interlayer dielectric layer of the second open bottom remainder thickness；Remove described second
Photoresist layer；With the hard mask layer as mask, the protective layer, adhesion layer and interlayer dielectric layer are etched, it is described to exposing
Semiconductor substrate, to be formed in the interlayer dielectric layer groove and the etching structure positioned at beneath trenches through hole are included；Institute
The full metal material of filling in etching structure is stated, and removes the hard mask layer, protective layer and adhesion layer.
Wherein, the material of the adhesion layer is silicon oxide, and it is formed by reactant of tetraethyl orthosilicate, to improve interlayer
Adhesiveness between dielectric layer and the protective layer that is subsequently formed, the thickness range of the adhesion layer is 50 angstroms~500 angstroms.The guarantor
The material of sheath be by chemical vapor deposition method formed silicon oxide, for as by etching technics in hard mask layer
The stop-layer of opening is formed, the thickness range of the protective layer is 50 angstroms~1000 angstroms.
However, finding when the copper dual-damascene structure formed to above-mentioned technique is checked：Part copper dual-damascene structure is sent out
Raw disappearance deforms, and has had a strong impact on the performance of the semiconductor device including formed copper dual-damascene structure.
The content of the invention
The problem that the present invention is solved is to provide a kind of forming method of interconnection structure, it is to avoid metal plug, the gold for being formed
Category interconnection line either dual-damascene structure occur disappearance or deform, improve comprising formed metal plug, metal interconnecting wires or
The performance of the semiconductor device of dual-damascene structure.
To solve the above problems, the present invention provides a kind of forming method of interconnection structure, including：
There is provided Semiconductor substrate, and sequentially form from the bottom to top on the semiconductor substrate interlayer dielectric layer, adhesion layer,
Protective layer and hard mask layer；
Form first in the hard mask layer to be open；
Carry out corona treatment and cleaning；
With the remaining hard mask layer as mask, the protective layer, adhesion layer and interlayer dielectric layer are carved successively
Erosion, until form etching structure in the interlayer dielectric layer, the etching structure include the one kind in through hole and groove or its
Combination；
Full metal material is filled in the etching structure, and removes the remaining hard mask layer, protective layer and adhesion
Layer.
Optionally, the material of the adhesion layer is silicon oxide.
Optionally, the corona treatment and cleaning of carrying out includes：First entered using the mixed gas for including ammonia
Row corona treatment；Cleaning is carried out again.
Optionally, the corona treatment and cleaning of carrying out includes：First carry out cleaning；Again using ammonia or
Person's nitrogen carries out corona treatment.
Optionally, the corona treatment and cleaning of carrying out includes：Carried out using the mixed gas including ammonia
First time plasma process；Carry out cleaning；Second plasma process is carried out using ammonia or nitrogen.
Optionally, carrying out cleaning includes：First first time cleaning treatment is carried out using hydrofluoric acid solution, then using dioxygen
The mixed solution of water and EKC carries out second cleaning treatment；Hydrogen peroxide is with EKC's in the mixed solution of the hydrogen peroxide and EKC
Volume range is 1:1~4.
Optionally, the etching structure includes through hole and groove；With the remaining hard mask layer as mask, successively to institute
State protective layer, adhesion layer and interlayer dielectric layer to perform etching, until etching structure is formed in the interlayer dielectric layer including：
Photoresist layer is formed in first opening, the second opening is formed with the photoresist layer；With the hard mask layer and photoetching
Glue-line is mask, and the protective layer, adhesion layer and interlayer dielectric layer are performed etching, to the remaining predetermined thickness in the second opening lower section
Interlayer dielectric layer；Remove the photoresist layer；With the hard mask layer as mask, the protective layer, adhesion layer and layer are etched
Between dielectric layer, until exposing the Semiconductor substrate.
Compared with prior art, technical scheme has advantages below：
After the first opening is formed, plasma treatment and cleaning are carried out, to expose viscous in the first open bottom
During attached layer, it is to avoid the adhesion layer surface modification that cleaning solution is caused in cleaning, or remove molten with cleaning in cleaning
Liquid reacts and the adhesion layer of degeneration, enables to be located at protective layer, adhesion layer and the interlayer dielectric layer below the first opening by follow-up
Etching technics is removed, it is to avoid the etching structure of formation occurs disappearance or deforms, it is ensured that form metal plug, metal interconnecting wires
Or the pattern of dual-damascene structure, and then ensure to include form metal plug, metal interconnecting wires or dual-damascene structure half
The electric property of conductor device.
Further, carrying out plasma treatment and cleaning includes：First using the mixed gas for including ammonia carry out etc. from
Daughter is processed, and removes the hydroxide ion positioned at adhesion layer and protective layer, makes to be located at the first open bottom adhesion layer and guarantor
The surface of sheath is hydrophobicity by hydrophilic conversion；Cleaning is carried out again, and what is remained in removal the first opening process of formation is poly-
Compound.Due to the protective layer after corona treatment and adhesion layer surface be in hydrophobicity, in cleaning cleaning solution be difficult with
Protective layer and adhesion layer surface contact, it is to avoid adhesion layer surface makes to be opened positioned at first because reacting with cleaning solution and degeneration
Protective layer, adhesion layer and interlayer dielectric layer below mouthful can be removed by follow-up etching technics, and then avoid formed etching
There is disappearance or deform in structure, formed metal plug, metal interconnecting wires or dual-damascene structure quantity is accurate and pattern
Preferably, improve the electric property comprising the semiconductor device for forming metal plug, metal interconnecting wires or dual-damascene structure.
Further, carrying out plasma treatment and cleaning includes：Cleaning is first carried out, then using ammonia or nitrogen
Carry out corona treatment.In the polymer remained during the first opening forming process is removed by cleaning, if first opens
Mouth bottom-exposed goes out adhesion layer, and the adhesion layer for exposing easily reacts and degeneration with cleaning solution；Using ammonia or nitrogen
When gas carries out corona treatment, the adhesion layer after degeneration is reduced, make be located at first opening below protective layer, adhesion layer and
Interlayer dielectric layer can be removed by follow-up etching technics, and then avoid formed etching structure from disappearance occurring or deforms, institute
Formed metal plug, metal interconnecting wires or dual-damascene structure quantity it is accurate and pattern is preferable.
Further, carrying out plasma treatment and cleaning includes：First carry out the using the mixed gas for including ammonia
Plasma process；Cleaning is carried out again；Finally second plasma process is carried out using ammonia or nitrogen.It is logical
It is hydrophobicity by hydrophilic conversion to cross first time plasma process and make the adhesion layer surface for exposing, with most in cleaning
Can be avoided that adhesion layer surface occurs degeneration；The adhesion layer for making to be reacted with cleaning solution by second plasma process
Be reduced, it is ensured that the first open bottom without after degeneration adhesion layer remain, and then ensure be located at first opening below protective layer,
Adhesion layer and interlayer dielectric layer can be removed by follow-up etching technics, it is to avoid the etching structure for being formed occurs disappearance or becomes
Shape, the quantity for forming metal plug, metal interconnecting wires or dual-damascene structure is accurate and pattern is preferable.
Description of the drawings
Fig. 1~Fig. 5 is the schematic diagram of the forming method first embodiment of interconnection structure of the present invention；
Fig. 6~Figure 11 is the schematic diagram of the forming method second embodiment of interconnection structure of the present invention.
Specific embodiment
Inventor has found that copper dual-damascene structure is easily lacked or deformed mainly by following in existing process through research
Reason is caused：In order to reduce the depth-to-width ratio of formed groove and through hole, reduce subsequently filling copper metal material in groove and through hole
The difficulty of material, the protective layer being arranged on interlayer dielectric layer is relatively thin, and when performing etching to form opening to hard mask layer, Yi Jiang
Protective layer below opening is removed, and causes part adhesion layer exposure.Cleaning is being carried out, to remove the first opening process is being formed
During the polymer of middle residual, cleaning solution easily reacts with the adhesion layer for exposing, and makes adhesion layer surface modification.And in etching
In forming groove and via process, etching technics is difficult to remove the adhesion layer after degeneration, causes to be located at after degeneration under adhesion layer
The adhesion layer and interlayer dielectric layer of side cannot be removed, and form groove and through hole occurs disappearance or deforms, and then cause institute
The quantity of the copper dual-damascene structure of formation, shape change, and finally have impact on partly leading including formed copper dual-damascene structure
The performance of body device.
Inventor has found after further research, after the first opening can be formed in hard mask layer, carries out plasma
Process and cleaning, to solve the problems, such as that above-mentioned copper dual-damascene structure is easily lacked or deformed.Its at least can be divided into
Lower three kinds of situations：
First, after the first opening is formed, corona treatment is first carried out, then carry out cleaning.By carry out etc.
Gas ions process, removal is attached to the hydroxide ion of protective layer and adhesion layer surface, and then makes protective layer and adhesion layer surface
It is hydrophobicity by hydrophilic conversion.When cleaning is carried out, cleaning solution is difficult to be contacted with adhesion layer, it is to avoid adhesion layer with it is clear
Dilution reacts and degeneration, enables not removed completely by the adhesion layer that hard mask layer is covered.
Second, after the first opening is formed, cleaning is first carried out, then carry out corona treatment.Cleaned
During technique, the adhesion layer that the first open bottom exposes reacts and degeneration with cleaning solution.By carrying out corona treatment, make
Adhesion layer reduction after degeneration, and then enable not removed completely by the adhesion layer that hard mask layer is covered.
3rd, the corona treatment includes first time plasma process and second plasma process.In shape
Into after the first opening, first time plasma process is first carried out, then carry out cleaning, finally carry out second plasma
Technique.By carrying out first time plasma process, protective layer is set to be thin by hydrophilic conversion with the adhesion layer surface for exposing
Aqueouss, make adhesion layer as few as possible react with cleaning solution.Even and if a small amount of adhesion layer still reacts with cleaning solution
And degeneration, it is also possible to second plasma process after by cleaning is reduced, it is ensured that the first open bottom is without change
Property after adhesion layer residual, and then enable by hard mask layer cover adhesion layer do not remove completely.
By carrying out above-mentioned corona treatment and cleaning, make the quantity of formed dual-damascene structure accurate and shape
Looks are preferable.
In addition, above-mentioned technique applies also for the formation process of metal plug and metal interconnecting wires.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
First embodiment
The present embodiment is with the metal interconnecting wires in single mosaic technology（The etching structure formed i.e. in interlayer dielectric layer is logical
Hole）As a example by, the forming method of interconnection structure of the present invention is illustrated, the forming method of metal plug and the shape of metal interconnecting wires
Similar into method, here is not detailed.
With reference to Fig. 1, there is provided Semiconductor substrate 200, and sequentially form interlayer from the bottom to top in the Semiconductor substrate 200
Dielectric layer 202a, adhesion layer 204a, protective layer 206a and hard mask layer 208a.
In the present embodiment, the material of the Semiconductor substrate 200 can for monocrystal silicon, monocrystalline germanium or monocrystalline germanium silicon, absolutely
Silicon, iii-v element compound, monocrystalline silicon carbide etc. are well known to a person skilled in the art semi-conducting material on edge body.
Additionally, may also be formed with device architecture in the Semiconductor substrate 200（It is not shown）, the device architecture can be half
The device architecture formed in conductor FEOL, such as MOS transistor etc.；May also be formed with the Semiconductor substrate 200 with
Metal plug of device architecture connection etc..
In the present embodiment, the material of the interlayer dielectric layer 202a is low-k materials or ultralow-k material film, forms the layer
Between the method for dielectric layer 202a can be chemical vapor deposition method.
The material of the adhesion layer 204a can be silicon oxide, and thickness range is 50 angstroms~500 angstroms, to improve inter-level dielectric
Adhesiveness between layer 202a and the protective layer 206a that is subsequently formed；The reactant for forming the adhesion layer 204a can be positive silicic acid
Ethyl ester and ozone, its concrete formation process is well known to those skilled in the art, and will not be described here.
The material of the protective layer 206a is silicon oxide, and thickness range is 50 angstroms~1000 angstroms；Form the protective layer
The method of 206a can be chemical vapor deposition method.The material of the hard mask layer 208a can be titanium nitride, copper nitride or nitrogen
Change aluminum, the method for forming the hard mask layer 208a can be chemical vapor deposition method.
With reference to Fig. 2, hard mask layer 208a described in Fig. 1 is performed etching, is formed in remaining hard mask layer 208b
One opening 209, first opening 209 runs through the hard mask layer 208b.
In the present embodiment, the method that the first opening 209 is formed in the hard mask layer 208a is dry etching.Its is concrete
May include：The photoresist layer for including the first opening figure is formed on hard mask layer 208a（It is not shown）；With the photoresist layer
For mask, the hard mask layer 208a is performed etching to form first opening 209；Remove the photoresist layer.
It should be noted that in order to ensure formed the first opening 209 through the hard mask layer 208a, the is being formed
During one opening 209, being also pointed to the protective layer 206a of the lower section of the first opening 209 carries out over etching, remains to the first 209 bottoms of opening
The protective layer 206b of remaining segment thickness.And due to the thinner thickness of protective layer 206a in Fig. 1, positioned at the lower section of the first opening 209
Partial protection layer 206a is easily completely removed, and exposes the part adhesion layer 204a.
Then, after the first opening 209 is formed, adopting includes ammonia（NH3）Mixed gas carry out at plasma
Reason.
In the present embodiment, the range of flow of the ammonia is 10sccm~2000sccm, carries out the temperature of corona treatment
Degree scope is 10 DEG C~250 DEG C, and time range is 10s~120s.The mixed gas including ammonia are gone back in addition to including ammonia
May include in nitrogen, helium and argon one or several.
Corona treatment is carried out to silicon oxide surface using the mixed gas including ammonia, can be removed and be attached to oxidation
The hydroxide ion of silicon face.Because the material of adhesion layer 204a and protective layer 206b is silicon oxide, therefore included by adopting
The mixed gas of ammonia carry out corona treatment, eliminate and are attached to bottom protective layer 206b of the first opening 209 and adhesion layer
The hydroxide ion on 204a surfaces, the surface for making protective layer 206b and adhesion layer 204a is hydrophobicity by hydrophilic conversion.
Optionally, using the mixed gas for including ammonia corona treatment is carried out with the shape in the hard mask layer 208a
Carry out in same equipment into the first opening 209, to reduce the step of shifting Semiconductor substrate, simplify the formation work of interconnection structure
Skill, it is cost-effective.
It should be noted that carrying out corona treatment and in the hard mask layer using the mixed gas including ammonia
The first opening 209 is formed in 208a can also be carried out in different equipment, and the present invention is without limitation.
Then, ammonia is included in employing（NH3）Mixed gas carry out after corona treatment, carrying out cleaning.
Specifically, carrying out cleaning includes：First first time cleaning treatment is carried out using hydrofluoric acid solution, then using dioxygen
The mixed solution of water and EKC carries out second cleaning treatment.Hydrogen peroxide is with EKC's in the mixed solution of the hydrogen peroxide and EKC
Volume range is 1:1~4.Wherein, a kind of alkaline solution that EKC is provided by EKC Technology Inc of Du Pont.
The hydrofluoric acid solution can remove to form the polymer remained during the first opening 209；Hydrogen peroxide and EKC's
In mixed solution, EKC can further remove to form the polymer remained during the first opening 209, and hydrogen peroxide can be removed
The micro hard mask layer 208b, beneficial to the removal for being attached to polymer on hard mask layer 208b, and beneficial to follow-up through hole
Formation and metal material filling.
It should be noted that because EKC removes hard mask layer 208b very littles, second cleaning treatment is to the first opening 209
The impact of pattern is negligible.
By carrying out the cleaning, can effectively remove to form the polymer remained during the first opening 209, with
Beneficial to the etching technics of follow-up through hole, it is ensured that form the quality of through hole.
Because the surface of the adhesion layer 204a for being exposed is hydrophobicity, cleaning solution is difficult and adhesion layer in cleaning
204a surfaces contact, it is to avoid adhesion layer 204a surfaces react and degeneration with cleaning solution.
With reference to Fig. 3, with hard mask layer 208b as mask, to remaining protective layer 206b, adhesion layer 204a and interlayer in Fig. 2
Dielectric layer 202a is performed etching, to exposing the Semiconductor substrate 200, remaining protective layer 206c, adhesion layer 204b and interlayer
Dielectric layer 202b, forms the through hole 210 through the interlayer dielectric layer 202b.
In the present embodiment, the side that remaining protective layer 206b, adhesion layer 204a and interlayer dielectric layer 202a are performed etching
Method is dry etching, and its concrete technology is well known to those skilled in the art, and will not be described here.
In the present embodiment, because the adhesion layer 204a surfaces that the first 209 bottom-exposeds of opening go out do not occur degeneration, work is etched
Artistic skill is enough by the adhesion layer 204a not covered by hard mask layer 208b and the interlayer dielectric layer below adhesion layer 204a
202a is removed completely, it is ensured that the first 209 figures of opening can be transferred to interlayer dielectric layer complete and accurate in hard mask layer 208b
In 202b, to form through hole 210 in interlayer dielectric layer 202b, it is to avoid the through hole 210 for being formed deforms or lacks, institute
The formation quantity of through hole 210 is accurate and pattern is preferable.
With reference to Fig. 4, metal material is formed on the hard mask layer 208b in the through hole 210 and around through hole 210 in figure 3
Material 212a.
In the present embodiment, the metal material 212a is copper.The method for forming metal material 212a can be heavy for physical vapor
Product technique, but the invention is not restricted to this.
With reference to Fig. 5, using chemical mechanical milling tech to metal material 212a, remaining hard mask layer 208b, guarantor in Fig. 4
Sheath 206c and adhesion layer 204b are planarized, to the interlayer dielectric layer 202b is exposed, to form metal interconnecting wires
212b。
It should be noted that in the present embodiment metal interconnecting wires 212b also with Semiconductor substrate 200 in metal plug（Figure
Do not show）Connection, so that the semiconductor device in Semiconductor substrate 200 realizes electrical connection.
During this city is implemented, after the first opening 209 is formed in hard mask layer 208a, first using the gaseous mixture for including ammonia
Body carries out corona treatment, removes the hydroxide ion on protective layer 206b and adhesion layer 204a, makes to be opened positioned at first
The surface of 209 bottom adhesion layer 204a of mouth is hydrophobicity by hydrophilic conversion, then carries out cleaning, removes and forms the first opening
The polymer remained during 209.It is clear in cleaning because the adhesion layer 204a surfaces after corona treatment are in hydrophobicity
Dilution is difficult and adhesion layer 204a surface contact properties, it is to avoid adhesion layer 204a surfaces become because reacting with cleaning solution
Property, protective layer 206b, the adhesion layer 204a and interlayer dielectric layer 202a that are located at the lower section of the first opening 209 are enable by follow-up etching
Technique is removed, and then avoids formed through hole 210 from disappearance occurring or deforms, and the quantity for forming metal interconnecting wires 212b is accurate
True and pattern preferably, improves the electric property comprising the semiconductor device for forming metal interconnecting wires 212b.
Second embodiment
The present embodiment is with dual-damascene structure（The etching structure formed i.e. in interlayer dielectric layer includes through hole and groove, institute
State through hole positioned at the groove lower section and with the groove insertion）As a example by, the forming method of interconnection structure of the present invention is carried out
Explanation.
With reference to Fig. 6, there is provided Semiconductor substrate 300, and sequentially form interlayer from the bottom to top in the Semiconductor substrate 300
Dielectric layer 302a, adhesion layer 304a, protective layer 306a and hard mask layer 308a.
In the present embodiment, the Semiconductor substrate 300, interlayer dielectric layer 302a, adhesion layer 304a, protective layer 306a and hard
The material and formation process of mask layer 308a refer to first embodiment, will not be described here.
With reference to Fig. 7, the first opening 310 is formed in the hard mask layer 308a in figure 6, first opening 310 runs through
The hard mask layer 308b.
In the present embodiment, it is described first opening 310 location and shape respectively be subsequently formed metal in dual-damascene structure
The location and shape correspondence of interconnection line.
It should be noted that due to the thinner thickness of protective layer 306b, during the first opening 310 is formed, positioned at the
The part adhesion layer 304a of the lower section of one opening 310 easily exposes.Its concrete reason refer to first embodiment, will not be described here.
Then, after the first opening 310 is formed, cleaning is first carried out.
Specifically, carrying out the cleaning includes：First first time cleaning treatment is carried out using hydrofluoric acid solution, then adopted
The mixed solution of hydrogen peroxide and EKC carries out second cleaning treatment.During cleaning is carried out, the first 310 bottoms of opening
The adhesion layer 304a for exposing reacts and degeneration with cleaning solution.
Then, after cleaning is carried out, corona treatment is carried out using ammonia or nitrogen.
In the present embodiment, when corona treatment is carried out using ammonia or nitrogen, the flow model of ammonia or nitrogen
Enclose for 10sccm~2000sccm, the temperature range for carrying out corona treatment is 100 DEG C~400 DEG C, time range be 10s~
120s.Carried out in plasma treatment procedure using ammonia or nitrogen, the adhesion layer 304a after degeneration is reduced.
Due to can by improve corona treatment temperature to improve degeneration after adhesion layer 304a rate of reduction, therefore will
The temperature setting of corona treatment is more than or equal to 100 DEG C and less than or equal to 400 DEG C, now, at plasma
Manage the rate of reduction to adhesion layer 304a after degeneration very fast, and the performance of formed interconnection structure will not be impacted.And work as
When the temperature of corona treatment is less than 100 DEG C, corona treatment is slower to the rate of reduction of adhesion layer 304a after degeneration, mutually
The make efficiency for linking structure is low, and cost of manufacture is high.When the temperature of corona treatment is more than 400 DEG C, corona treatment meeting
The performance of formed interconnection structure is impacted, impact forms the yield rate of interconnection structure.
With reference to Fig. 8, in the figure 7 photoresist layer 314 is formed in first opening 310, formed in the photoresist layer 314
There is the second opening 312 through the thickness of the photoresist layer 314.
In the present embodiment, it is described second opening 312 location and shape respectively be subsequently formed metal in dual-damascene structure
The location and shape correspondence of connector.Formation includes that the method for the photoresist layer 314 of the second opening 312 is those skilled in the art institute
Know, will not be described here.
With reference to Fig. 9, the hard mask layer 308b with Fig. 8 and photoresist layer 314 to the protective layer 306b, are adhered to as mask
Layer 304a and interlayer dielectric layer 302a is performed etching, to the interlayer dielectric layer 302b of the remaining predetermined thickness in the lower section of the second opening 312,
And remaining adhesion layer 304b and protective layer 306b positioned at hard mask layer 308b and the lower section of photoresist layer 314.
In the present embodiment, the predetermined thickness is corresponding with the thickness for being subsequently formed groove.
With reference to Figure 10, photoresist layer 314 described in Fig. 9 is removed, and with the hard mask layer 308b as mask, etching is described
Protective layer 306b, adhesion layer 304b and interlayer dielectric layer 302b, until the Semiconductor substrate 300 is exposed, with the layer
Between groove 316 and through hole 318, protective layer 306c and adhesion of the residue below hard mask layer 308b are formed in dielectric layer 302c
Layer 304c.The through hole 318 is located at the lower section of the groove 316, and with the insertion of the groove 316.
With reference to Figure 11, in Fig. 10 full metal material is filled in the groove 316 and through hole 318, to form metal interconnection
Line 320 and metal plug 322, and remove remaining hard mask layer 308b, protective layer 306c and adhesion layer 304c.
Specifically, can first in Fig. 10 in the groove 316 and through hole 318, the top of groove 316 by adhesion layer 304c, protect
Fill out to form metal material in the opening that sheath 306c and hard mask layer 308b are enclosed and on hard mask layer 308b, then adopt
Metal material, hard mask layer 308b, protective layer 306c and adhesion layer 304c are planarized with chemical mechanical milling tech, extremely
The interlayer dielectric layer 302c is exposed, metal material of the residue in groove 316 and through hole 318 is tied respectively as dual damascene
Metal interconnecting wires 320 and metal plug 322 in structure.
In the present embodiment, the metal material is copper, and its formation process can be physical gas-phase deposition.
In the present embodiment, cleaning is first carried out, to remove the polymer remained during the first opening 310 is formed, this
When, if the first 310 bottom-exposeds of opening go out part adhesion layer 304a, adhesion layer 304a reacts and degeneration with cleaning solution；
After the cleaning process, then using ammonia or nitrogen corona treatment is carried out, so that the adhesion layer 304a reduction after degeneration.
With hard mask layer 308b as mask, when forming groove 316 and through hole 318 by etching technics, it is ensured that not by hard mask layer
The protective layer 306b and adhesion layer 304a that 308b is covered can be completely removed, and make to be formed at groove 316 in interlayer dielectric layer 202b
And pattern accurate with the quantity of through hole 318 preferably, and then ensures to form the quantity of metal interconnecting wires 320 and metal plug 322
Accurate and pattern is preferable, including the performance of the semiconductor device of metal interconnecting wires 320 and metal plug 322 is good.
In other embodiments, after the first opening 310 can be also formed in the first hard mask layer 308b, first adopting includes
The mixed gas of ammonia carry out first time plasma process；Cleaning is carried out again；Finally carried out using ammonia or nitrogen
Second plasma process.The adhesion layer 304a surfaces for exposing are made by hydrophilic conversion by first time plasma process
For hydrophobicity, to avoid adhesion layer 304a surfaces to react with cleaning solution as far as possible in cleaning.Cleaned
In technical process, the degeneration even if part adhesion layer 304a and cleaning solution react can also pass through second plasma work
Skill reduces the adhesion layer 304a after degeneration.When groove 316 and through hole 318 is formed by etching technics, not by hard mask layer
The protective layer 306b and adhesion layer 304a that 308b is covered can be completely removed, and insert formed metal interconnecting wires 320 and metal
Plug 322 quantity is accurate and pattern preferably, improve semiconductor device including metal interconnecting wires 320 and metal plug 322
Performance.The method for carrying out first time plasma process using the mixed gas including ammonia refer to the phase in first embodiment
Answer step, and the method that second plasma process is carried out using ammonia or nitrogen refer to it is corresponding in second embodiment
Step, here is not detailed.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, without departing from this
In the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (13)
1. a kind of forming method of interconnection structure, it is characterised in that include：
Semiconductor substrate is provided, and sequentially forms interlayer dielectric layer, adhesion layer, protection from the bottom to top on the semiconductor substrate
Layer and hard mask layer；
Form first in the hard mask layer to be open；
Carry out corona treatment and cleaning；
With the remaining hard mask layer as mask, the protective layer, adhesion layer and interlayer dielectric layer are performed etching successively, directly
To etching structure is formed in the interlayer dielectric layer, the etching structure includes the one kind in through hole and groove or its combination；
Full metal material is filled in the etching structure, and removes the remaining hard mask layer, protective layer and adhesion layer.
2. the forming method of interconnection structure as claimed in claim 1, it is characterised in that the material of the adhesion layer is oxidation
Silicon.
3. the forming method of interconnection structure as claimed in claim 2, it is characterised in that the corona treatment and clear of carrying out
Washing technique includes：
First carry out corona treatment using the mixed gas for including ammonia；
Cleaning is carried out again.
4. the forming method of interconnection structure as claimed in claim 2, it is characterised in that the corona treatment and clear of carrying out
Washing technique includes：
First carry out cleaning；
Again corona treatment is carried out using ammonia or nitrogen.
5. the forming method of interconnection structure as claimed in claim 2, it is characterised in that the corona treatment and clear of carrying out
Washing technique includes：
First time plasma process is carried out using the mixed gas including ammonia；
Carry out cleaning；
Second plasma process is carried out using ammonia or nitrogen.
6. the forming method of the interconnection structure as described in claim 3 or 5, it is characterised in that when using the mixing for including ammonia
When gas carries out corona treatment, the range of flow of ammonia is 10sccm~2000sccm, carries out the temperature of corona treatment
Degree scope is 10 DEG C~250 DEG C, and time range is 10s~120s.
7. the forming method of the interconnection structure as described in claim 3 or 5, it is characterised in that using the gaseous mixture for including ammonia
Body carries out corona treatment to be carried out with the first opening is formed in the hard mask layer in same equipment.
8. the forming method of the interconnection structure as described in claim 4 or 5, it is characterised in that when being entered using ammonia or nitrogen
During row corona treatment, the range of flow of ammonia or nitrogen is 10sccm~2000sccm, carries out corona treatment
Temperature range is 100 DEG C~400 DEG C, and time range is 10s~120s.
9. the forming method of the interconnection structure as described in any one of claim 3 to 5, it is characterised in that carry out cleaning bag
Include：First first time cleaning treatment is carried out using hydrofluoric acid solution, then using hydrogen peroxide and EKC mixed solution carry out second it is clear
Wash process；Hydrogen peroxide and the volume range of EKC are 1 in the mixed solution of the hydrogen peroxide and EKC:1~4；Wherein, EKC is
A kind of alkaline solution produced by EKC Technology Inc of Du Pont.
10. the forming method of interconnection structure as claimed in claim 1, it is characterised in that the material of the protective layer is oxidation
Silicon, the method for forming the protective layer is chemical vapor deposition method, and the thickness range of the protective layer is 50 angstroms~1000 angstroms.
The forming method of 11. interconnection structures as claimed in claim 1, it is characterised in that the material of the interlayer dielectric layer is
Low-k materials or ultralow-k material film, the metal material is copper.
The forming method of 12. interconnection structures as claimed in claim 1, it is characterised in that the material of the hard mask layer is nitrogen
Change titanium, copper nitride or aluminium nitride.
The forming method of 13. interconnection structures as claimed in claim 1, it is characterised in that the etching structure include through hole and
Groove；With the remaining hard mask layer as mask, the protective layer, adhesion layer and interlayer dielectric layer are performed etching successively,
Until etching structure is formed in the interlayer dielectric layer including：Photoresist layer, the photoetching are formed in the described first opening
The second opening is formed with glue-line；With the hard mask layer and photoresist layer as mask, to the protective layer, adhesion layer and interlayer
Dielectric layer is performed etching, to the interlayer dielectric layer of the remaining predetermined thickness in the second opening lower section；Remove the photoresist layer；With described
Hard mask layer is mask, the protective layer, adhesion layer and interlayer dielectric layer is etched, until exposing the Semiconductor substrate.
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| CN107119280B (en) * | 2016-02-25 | 2020-02-18 | 东莞新科技术研究开发有限公司 | Pad surface treatment method |
| CN111276456B (en) * | 2020-02-18 | 2020-12-04 | 合肥晶合集成电路有限公司 | Semiconductor device and method for manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6534397B1 (en) * | 2001-07-13 | 2003-03-18 | Advanced Micro Devices, Inc. | Pre-treatment of low-k dielectric for prevention of photoresist poisoning |
| CN102347206A (en) * | 2010-07-29 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102543844A (en) * | 2010-12-30 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device structure and semiconductor device structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6534397B1 (en) * | 2001-07-13 | 2003-03-18 | Advanced Micro Devices, Inc. | Pre-treatment of low-k dielectric for prevention of photoresist poisoning |
| CN102347206A (en) * | 2010-07-29 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102543844A (en) * | 2010-12-30 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device structure and semiconductor device structure |
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