CN104517894B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN104517894B CN104517894B CN201310460183.0A CN201310460183A CN104517894B CN 104517894 B CN104517894 B CN 104517894B CN 201310460183 A CN201310460183 A CN 201310460183A CN 104517894 B CN104517894 B CN 104517894B
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- 238000000034 method Methods 0.000 title claims abstract description 96
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 230000004888 barrier function Effects 0.000 claims abstract description 168
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 239000000463 material Substances 0.000 claims description 74
- 230000008569 process Effects 0.000 claims description 39
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 34
- 229910052802 copper Inorganic materials 0.000 claims description 34
- 239000010949 copper Substances 0.000 claims description 34
- 238000005530 etching Methods 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000005516 engineering process Methods 0.000 claims description 14
- 229910018565 CuAl Inorganic materials 0.000 claims description 13
- 229910016344 CuSi Inorganic materials 0.000 claims description 13
- 238000009713 electroplating Methods 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 229910004541 SiN Inorganic materials 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000010408 film Substances 0.000 claims 19
- 239000002305 electric material Substances 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 512
- 239000004020 conductor Substances 0.000 description 12
- 230000000903 blocking effect Effects 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 230000005611 electricity Effects 0.000 description 6
- 230000007480 spreading Effects 0.000 description 5
- 238000003892 spreading Methods 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- 239000012670 alkaline solution Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910021205 NaH2PO2 Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003638 chemical reducing agent Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- KTVIXTQDYHMGHF-UHFFFAOYSA-L cobalt(2+) sulfate Chemical compound [Co+2].[O-]S([O-])(=O)=O KTVIXTQDYHMGHF-UHFFFAOYSA-L 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, wherein the forming method of semiconductor structure includes：Substrate with interconnecting area is provided；The first block film, conductive film, the second block film and first medium film are formed in substrate surface；Etched portions first medium film, the second block film, conductive film and the first block film are until exposing substrate surface, to form the first barrier layer, the first conductive layer, the second barrier layer and first medium layer on the interconnecting area surface of substrate；Third barrier layer is formed in the sidewall surfaces of the first conductive layer；Second dielectric layer is formed in the sidewall surfaces of substrate surface, third barrier layer surface and first medium layer, the surface of second dielectric layer is flushed with first medium layer surface；Part first medium layer is removed, forms the second opening in second dielectric layer and first medium layer, the second open bottom exposes the first conductive layer surface of part.It is formed by semiconductor structure performance improvement.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
In the art of semiconductor manufacturing, in order to realize the electrical connection between semiconductor devices, various gold have been developed at present
Belong to interconnection structure and formation process, such as copper interconnection structure, and forms the copper electroplating technology of copper interconnection structure（ECP,
electro-coppering plating）.However, with super large-scale integration（ULSI）Development, semiconductor devices
Characteristic size（CD）It constantly reduces, the technique for forming metal interconnection structure is also challenged.
By taking existing copper interconnection structure as an example, Fig. 1 to Fig. 4 is the section of the forming process of the copper interconnection structure of the prior art
Structural schematic diagram.
Referring to FIG. 1, providing substrate 100, there is conductive layer 105, the substrate 100, which exposes, leads in the substrate 100
Electric layer 105；Dielectric layer 101 is formed in the substrate 100 and 105 surface of conductive layer.
Referring to FIG. 2, forming the opening 102 for exposing the conductive layer 105 in substrate 100 in the dielectric layer 101.
Referring to FIG. 3, the surface of the dielectric layer 101 and opening 102（As shown in Figure 2）Side wall and bottom surface formed
The material of seed layer 103, the seed layer is conductive material；It is formed and is filled on 103 surface of the seed layer using electroplating technology
The copper interconnection layer 104 of full gate mouth 102.
Referring to FIG. 4, the copper interconnection layer 104 on etching removal part 101 surface of dielectric layer（As shown in Figure 3）, formed
Copper interconnection structure 104a.
In addition it is also possible to the copper interconnection layer 104 using CMP process removal higher than 101 surface of dielectric layer（Such as
Shown in Fig. 3）, form copper interconnection structure.
However, to be formed by copper interconnection structure performance poor for the prior art.
Invention content
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, and raising is formed by electrical interconnection knot
The performance of structure.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided, it is described
Substrate has interconnecting area；The first block film and conductive film positioned at the first block film surface are formed in substrate surface；
The second block film of formation and the first medium film positioned at the second block film surface on the conductive film surface；It carves
The erosion part first medium film, the second block film, conductive film and the first block film are until expose substrate surface
Until, with the interconnecting area surface of substrate formed the first barrier layer, positioned at the first barrier layer surface the first conductive layer, be located at the
Second barrier layer of one conductive layer surface and first medium layer positioned at the second barrier layer surface；In first conductive layer
Sidewall surfaces form third barrier layer；In the sidewall surfaces of the substrate surface, third barrier layer surface and first medium layer
Second dielectric layer is formed, the surface of the second dielectric layer is flushed with first medium layer surface；Part first medium layer is removed,
The second opening is formed in second dielectric layer and first medium layer, second open bottom exposes part the first conductive layer table
Face.
Optionally, the quantity of the interconnecting area is greater than or equal to 1, has the first opening in the interconnecting area of the substrate.
Optionally, there is the first conductive structure, surface and the substrate table of first conductive structure in first opening
Face flushes or is less than the substrate surface.
Optionally, the forming method of the conductive film includes：Using electroplating technology in the first barrier layer surface shape
At conductive film；Thermal annealing is carried out to the conductive film；After thermal annealing, the thickness of the conductive film is thinned.
Optionally, before thermal annealing, use the thickness of the conductive film of electroplating technology formation for 1500 angstroms~2500 angstroms
Optionally, the technique of the thermal annealing is：Temperature is 200 degrees Celsius~450 degrees Celsius, and the time is 5 minutes~30
Minute.
Optionally, the technique of the thinned conductive film thickness for CMP process or is etched back to technique.
Optionally, the material on first barrier layer is conductive material, including：The combination of Ta and TaN, Ru, CuAl,
CuSi, CuAlSi, CuMn or Co；The material on second barrier layer include the combination of Ta and TaN, Ru, CuAl, CuSi,
CuAlSi, CuMn, SiN, NDC or BN；The material of first conductive layer includes copper.
Optionally, the material of the first medium layer is different from the material of second dielectric layer；The material of the first medium layer
Material includes：NDC、SiN、SiO2, one or more combinations in SiCN, BN, SiCOH and low-k materials；The second dielectric layer
Material includes：SiO2, SiN, SiON, SiCOH or low-k materials.
Optionally, the formation process on the third barrier layer is selective deposition technique, the material on the third barrier layer
Including CoWP, CuAl, CuSi, CuAlSi or CuMn.
Optionally, the formation process of the second dielectric layer includes：Using depositing operation on substrate surface, third barrier layer
The side wall and top surface of surface and first medium layer form second medium film；Using CMP process to described
Second medium film is polished, and until the top surface for exposing first medium layer, forms second dielectric layer.
Optionally, the depositing operation for forming second medium film is plasma enhanced chemical vapor deposition technique.
Optionally, it is formed with gap in the second dielectric layer between adjacent first conductive layer.
Optionally, the formation process of second opening includes：In the first medium layer and second medium layer surface shape
At patterned layer, the patterned layer exposes part first medium layer and second medium layer surface；It is with the patterned layer
Mask, first medium layer described in etched portions simultaneously expose the second barrier layer surface of part, form the second opening；In etching technics
Later, the patterned layer is removed.
Optionally, further include：After forming the second opening, the second conductive structure, institute are formed in second opening
Stating the second conductive structure includes：Positioned at the 4th barrier layer of second opening sidewalls and bottom surface and positioned at described the
Second conductive layer of four barrier layer surfaces and full second opening of filling.
Optionally, second conductive structure is also formed into second medium layer surface and is across the second open top.
Optionally, second conductive structure is also formed into second dielectric layer and first medium layer surface.
Optionally, the material on the 4th barrier layer includes：The combination of Ta and TaN, Ru, CuAl, CuSi, CuAlSi,
CuMn or Co；The material of second conductive layer includes copper.
Correspondingly, semiconductor structure is formed by using the above method the present invention also provides a kind of, including：Substrate, it is described
Substrate has interconnecting area；Positioned at the first barrier layer of the substrate surface of the interconnecting area；Positioned at first barrier layer surface
There is the top surface of first conductive layer, first conductive layer the second barrier layer, second barrier layer surface to have first
The sidewall surfaces of dielectric layer, first conductive layer have third barrier layer；Positioned at the substrate surface, third barrier layer surface
It is flushed with first medium layer surface with the surface of the second dielectric layer of the sidewall surfaces of first medium layer, the second dielectric layer；
Positioned at the second opening of the second barrier layer of part top surface, second opening is located at second dielectric layer and first medium layer
It is interior.
Optionally, further include：The second conductive structure in second opening, second conductive structure include：
Positioned at the 4th barrier layer of second opening sidewalls and bottom surface and positioned at the 4th barrier layer surface and filling it is full
Second conductive layer of second opening.
Compared with prior art, technical scheme of the present invention has the following advantages：
In the forming method of semiconductor structure, after forming the first conductive layer, second medium is formed in substrate surface
Layer, the second dielectric layer are formed in the sidewall surfaces of third barrier layer surface and first medium layer, i.e., the described second dielectric layer
For being electrically isolated first conductive layer.Since the second dielectric layer is formed after forming first conductive layer so that
The second dielectric layer will not be impacted by forming the technique of first conductive layer, therefore be formed by second dielectric layer
Quality it is good, be electrically isolated performance stablize.Secondly, first conductive layer bottom is formed with the first barrier layer, and described first leads
The second barrier layer is formed at the top of electric layer, and the side wall of first conductive layer is formed with third barrier layer, that is, is formed by the
One conductive layer surface is surrounded by the first barrier layer, the second barrier layer and third barrier layer completely；And first barrier layer, second
Barrier layer and third barrier layer can prevent the material of the first conductive layer from spreading, to make the performance of first conductive layer
Stablize.Again, the second dielectric layer is flushed with first medium layer surface, and the first medium layer is formed in the first conductive layer
Top surface can be formed and be led with first thus, it is only required to which the first conductive layer can be exposed by removing part first medium layer
Second opening of electric layer connection, and second opening is used to form conductive structure.It is good due to being formed by the second opening pattern
It is good, and the first conductive layer can be only exposed, therefore, it is possible to keep the electrical connection properties between conductive structure and the first conductive layer good
It is good.
Further, the forming method of the conductive film includes：Conductive film is deposited in first barrier layer surface；It is right
The conductive film carries out thermal annealing.After deposition forms conductive film, the thickness of the conductive film is thicker, is moved back through overheat
After fire, the lattice dimensions in the conductive film can be made to become larger, to make the resistivity of the conductive film reduce, make institute
The electrical property of the first conductive layer formed improves.
In the semiconductor structure, first conductive layer bottom has the first barrier layer, has at the top of first conductive layer
There is the second barrier layer, and the side wall of first conductive layer has third barrier layer, that is, it is complete to be formed by the first conductive layer surface
It is surrounded entirely by the first barrier layer, the second barrier layer and third barrier layer.First barrier layer, the second barrier layer and third blocking
Layer can prevent the material of the first conductive layer from spreading, to make the performance of first conductive layer stablize.
Description of the drawings
Fig. 1 to Fig. 4 is the cross-sectional view of the forming process of the copper interconnection structure of the prior art；
Fig. 5 to Figure 16 is the structural schematic diagram of the forming process of semiconductor structure described in the embodiment of the present invention.
Specific implementation mode
As stated in the background art, it is poor to be formed by conductive interconnecting structure performance for the prior art.
By the study found that please continue to refer to Fig. 1 to Fig. 4, when the prior art forms copper interconnection structure, head is in dielectric layer
Opening 102 is formed in 101, and copper interconnection layer 104 is being formed in opening 102 by electroplating technology.However, with integrated circuit
Integrated level improves, and the size of semiconductor devices reduces therewith, is easy to cause the size contracting of the required copper interconnection structure 104a formed
It is small, it is accordingly used in forming 102 size reduction of opening of copper interconnection structure 104a, makes this deep wide increase of the opening 102, cause
Gap is generated in the copper interconnection layer 104 filled in the opening 102, then is formed by under the electrical property of copper interconnection structure 104a
Drop.
Secondly, as the integrated level of integrated circuit improves, the size of semiconductor devices reduces therewith, the prior art is in order to carry
The performance of high device, using low K（Low-K）Material forms dielectric layer 101, and the low-K material includes porous media material, such as
Porous silica, porous silicon nitride.However, since the prior art forms the copper-connection after forming the dielectric layer 101
Structure 104a, then during forming the copper interconnection structure 104a, the gap being easy to cause in porous media material disappears,
The K values of dielectric layer 101 are caused to rise, then the electric isolution performance of the dielectric layer 101 declines, and then causes to be formed by copper-connection
The performance of structure 104a is unstable.
To solve the above-mentioned problems, the present invention proposes a kind of forming method of semiconductor structure, including：There is provided has interconnection
The substrate in area；The first block film is formed in substrate surface and positioned at the conductive film of the first barrier layer surface；It is led described
Film surface forms the second block film and the first medium film positioned at the second block film surface；Etched portions institute
First medium film, the second block film, conductive film and the first block film are stated until exposing substrate surface, is being served as a contrast
The interconnecting area surface at bottom formed the first barrier layer, positioned at the first barrier layer surface the first conductive layer, be located at the first conductive layer table
Second barrier layer in face and first medium layer positioned at the second barrier layer surface；In the sidewall surfaces of first conductive layer
Form third barrier layer；Second is formed in the sidewall surfaces of the substrate surface, third barrier layer surface and first medium layer to be situated between
The surface of matter layer, the second dielectric layer is flushed with first medium layer surface；Part first medium layer is removed, in second dielectric layer
It is open with forming second in first medium layer, second open bottom exposes the second barrier layer surface of part.
Wherein, after forming the first conductive layer, second dielectric layer is formed in substrate surface, the second dielectric layer is formed
In the sidewall surfaces of third barrier layer surface and first medium layer, i.e., the described second dielectric layer is conductive for being electrically isolated described first
Layer.Since the second dielectric layer is formed after forming first conductive layer so that form the work of first conductive layer
Skill will not impact the second dielectric layer, therefore the quality for being formed by second dielectric layer is good, be electrically isolated performance
Stablize.Secondly, first conductive layer bottom is formed by the first barrier layer, and the first conductive layer top is formed with the second blocking
Layer, and the side wall of first conductive layer is formed with third barrier layer, that is, is formed by the first conductive layer surface completely by first
Barrier layer, the second barrier layer and third barrier layer surround；And first barrier layer, the second barrier layer and third barrier layer can
Prevent the material of the first conductive layer from spreading, to make the performance of first conductive layer stablize.Again, the second medium
Layer is flushed with first medium layer surface, and the first medium layer is formed in the first conductive layer top surface, thus, it is only required to remove
Part first medium layer can expose the first conductive layer, can form the second opening being connected to the first conductive layer, and
Second opening is used to form conductive structure.It is good due to being formed by the second opening pattern, and can only expose first
Conductive layer, therefore, it is possible to keep the electrical connection properties between conductive structure and the first conductive layer good.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 5 to Figure 16 is the structural schematic diagram of the forming process of semiconductor structure described in the embodiment of the present invention.
Referring to FIG. 5, providing substrate 200, the substrate 200 has interconnecting area I.
In the present embodiment, the substrate 200 includes：Semiconductor base, be formed in semiconductor base or surface half
Conductor device, the conductive structure for being electrically connected the semiconductor devices and be formed in semiconductor substrate surface for electricity every
Insulating layer from the semiconductor devices and conductive structure.The semiconductor base includes silicon substrate, silicon-Germanium substrate, silicon carbide lining
Bottom, silicon-on-insulator substrate, germanium substrate on insulator, glass substrate or III-V compound substrate（Such as gallium nitride substrate or
Gallium arsenide substrate etc.）.
The interconnecting area I of the substrate 200 is used to form the first conductive structure 210, and the quantity of the interconnecting area I is more than or waits
In 1, that is, the quantity for being formed in the first conductive structure 210 in substrate 200 is greater than or equal to 1.Fig. 5 show 4 it is adjacent and point
Vertical interconnecting area I is formed with 4 the first adjacent conductive structures 210 in substrate 200.And the interconnecting area I of the substrate 200
Inside there is the first opening（It is not shown）, described first, which is open, is used to form the first conductive structure.
In the present embodiment, the surface of the substrate 200 is insulating layer（It does not indicate）, and the insulating layer of the interconnecting area I
Inside there is the first opening, the first conductive structure 210, the surface of first conductive structure 210 are formed in first opening
It is flushed with the surface of insulating layer；Moreover, in the present embodiment, first conductive structure 210 is conductive plunger.In an embodiment
In, the first conductive structure is not formed in first opening, and first open bottom exposes the first conductive structure.At it
In its embodiment, the first conductive structure is formed in first opening, and the surface of first conductive structure is less than substrate table
Face.
In addition, in another embodiment, the substrate 200 is semiconductor base, in the interconnecting area I of the semiconductor base
It is formed with the first conductive structure, the surface of first conductive structure is flushed with the surface of semiconductor base, and described first is conductive
Structure is conductive plunger, i.e., the described conductive plunger is as through-silicon via structure（TSV, Through Silicon Via）.
Referring to FIG. 6, forming the first block film 201 on 200 surface of substrate；On 201 surface of the first block film
Deposit conductive film 202.
The conductive film 202 is used to form the first conductive layer, in the present embodiment, the first conductive layer for being subsequently formed and
Second conductive structure is copper interconnection structure, therefore the material of the conductive film 202 is copper, forms the conductive film 202
Technique is copper electroplating technology（ECP）.Therefore, the first barrier layer 201 is needed to form before forming conductive film 202；Described
The material on one barrier layer 201 is conductive material, enables first barrier layer 201 as the seed formed in copper electroplating technology
Layer；Secondly, first barrier layer 201, which can also be used as, prevents the follow-up material that be formed by the first conductive layer to substrate 200
Interior diffusion.The material on first barrier layer 201 includes the combination of Ta and TaN, Ru, CuAl, CuSi, CuAlSi, CuMn or Co.
After the conductive film 202 formed using copper electroplating technology, the thickness of the conductive film 202 is 1500 angstroms~
2500 angstroms.Can subsequently in thermal anneal process, be conductive since the thickness for being formed by conductive film 202 is thicker
Lattice dimensions in film 202, which expand, provides enough spaces.And the expansion of the lattice dimensions can reduce the resistance of material
Rate makes the electrical property of the first conductive layer carry because the resistivity for the first conductive layer that can make to be formed by conductive film 202 reduces
It is high.
Referring to FIG. 7, carrying out thermal annealing to the conductive film 202；After thermal annealing, the conductive film is thinned
202 thickness.
The parameter of the thermal anneal process includes：Temperature is 200 degrees Celsius~450 degrees Celsius, and the time is 5 minutes~30 points
Clock.
The material of the conductive film 202 is copper, therefore the material of the conductive film 202 is in polycrystalline state.In the heat
After annealing process, the lattice dimensions of 202 material of the conductive film can expand so that the resistance of the conductive film 202
Rate reduces, then is formed by the resistivity of the first conductive layer by the conductive film 202 and reduces, make subsequently to be formed by first and lead
The electrical property of electric layer is improved.
Since the thickness of the conductive film 202 formed using electroplating technology is thicker, it is therefore desirable to after thermal anneal process
The conductive film 202 is thinned so that the thickness of conductive film 202, which is thinned to, meets required the first conductive layer formed
Size.The technique of the conductive film 202 is thinned as CMP process or is etched back to technique.Wherein, described time quarter
Etching technique can use the plasma of hydrogen, in the environment of less than room temperature, bombarded and reality the conductive film 202
It is existing.
Referring to FIG. 8, forming the second block film 203 on 202 surface of the conductive film and stopping positioned at second thin
The first medium film 204 on 203 surface of film.
Second block film 203 is used to form positioned at the second barrier layer of the first conductive layer top surface, and described
Two barrier layers are used to prevent the material of the first conductive layer from top to external diffusion.The formation process of second block film 203
For chemical vapor deposition method；The material of second block film 203 is conductive material or insulating materials；Wherein, conduction material
Material includes combination, Ru, CuAl, CuSi, CuAlSi or CuMn of Ta and TaN；Insulating materials is SiN, NDC（The silicon nitride of carbon dope）
And BN（The silicon nitride of boron-doping）In one or more combinations；When the material of second block film 203 is conductive material,
The second opening being subsequently formed can expose the second barrier layer；When the material of second block film 203 is insulating materials
When, after the second opening for being subsequently formed exposes the second barrier layer, need to remove the second barrier layer of the second open bottom and sudden and violent
Expose the first conductive layer.
The first medium film 204 is subsequently formed first medium layer, and the first medium layer can be used as etching second
Hard mask when block film 203, conductive film 202 and the first block film 201（Hard Mask）；In addition, described first is situated between
Matter layer can also be as the stop-layer of CMP process when being subsequently formed second dielectric layer.The first medium film
204 formation process is chemical vapor deposition method, and the material of the first medium film 204 includes：NDC、SiN、SiO2、
One or more combinations in SiCN, BN, SiCOH and low-k materials.
Referring to FIG. 9, first medium film 204 described in etched portions, the second block film 203, conductive film 202 and
One block film 201 forms the first barrier layer until exposing 200 surface of substrate, on the surfaces interconnecting area I of substrate 200
201a, the first conductive layer 202a positioned at the first barrier layer surfaces 201a, the second blocking positioned at the first surfaces conductive layer 202a
The layer 203a and first medium layer 204a positioned at the second barrier layer surfaces 203a.
The etching technics is anisotropic dry etch process, etches the first barrier layer 201a of formation, first leads
The side wall of electric layer 202a, the second barrier layer 203a and first medium layer 204a are vertical relative to 200 surface of substrate.The present embodiment
In, due to the material of the first barrier layer 201a, the first conductive layer 202a, the second barrier layer 203a and first medium layer 204a
With it is complicated, the etching technics is：In the environment of less than room temperature, bombarded using the plasma of hydrogen；Due to
In the etching technics, the physical bombardment for relying primarily on hydrogen gas plasma performs etching, and chemistry is anti-between weakening each layer
The speed difference answered, therefore the first barrier layer 201a, the first conductive layer 202a, the second barrier layer 203a that etching can be made to be formed
It is good with the sidewall surfaces pattern of first medium layer 204a.
The etching technics etches the first medium film 204 first, and being formed by first medium layer 204a can make
Hard mask when the second block film 203, conductive film 202 and the first block film 201 is put for subsequent etching；Secondly, institute's shape
At first medium layer 204a can be when being subsequently formed second dielectric layer, the stop-layer as polishing process；Again, described
One dielectric layer 204a is formed in the first surfaces conductive layer 202a, and the second dielectric layer being subsequently formed is located at the first conductive layer
The sidewall surfaces of 202a make have Etch selectivity between the first medium layer 202a and second dielectric layer, then can pass through
Etching technics removal part first medium layer 202a can form the opening for exposing the first conductive layer 202a, the opening energy
It is enough in the conductive structure for being formed in the first conductive layer 202a electrical connections, the technique for forming conductive structure is easy to control, energy
Enough make to be formed by that conductive structure pattern is good, performance is stablized.
It should be noted that the present embodiment is formed by the figure that the first conductive layer 202a is parallel to 200 surface direction of substrate
Shape is bar shaped；And the surfaces interconnecting area I of several adjacent discretes are respectively formed the first conductive layer 202a, i.e., in several interconnecting area I shapes
At several first conductive layer 202a, and the bar pattern of several first conductive layer 202a is arranged in parallel.
It is formed by the first conductive layer 202a and is formed in 200 surface of substrate of interconnecting area I, therefore be formed by the first conduction
Layer 202a can be electrically connected with the first conductive structure 210.And the first conductive layer 202a is conductive by be subsequently formed second
Structure realizes mutual electricity interconnection, to constitute copper interconnection structure.Moreover, the bottom of the first conductive layer 202a has
First barrier layer 201a, the first barrier layer 201a can prevent the material of the first conductive layer 202a from being spread into substrate 200；
Wherein, the material of the first barrier layer 201a is conductive material, therefore, is located at the first conductive structure 210 and the first conductive layer
The first barrier layer 201a between 202a does not interfere with electrical connection properties.The top surface of the first conductive layer 202a has the
Two barrier layer 203a, the second barrier layer 203a can prevent the material of the first conductive layer 202a into first medium layer 202a
Diffusion.Therefore, it is formed by the electric performance stablity of the first conductive layer 202a.
Referring to FIG. 10, the sidewall surfaces in the first conductive layer 202a form third barrier layer 205.
The third barrier layer 205 is used to prevent the material of the first conductive layer 202a into the second dielectric layer being subsequently formed
Diffusion, to make the surface of the first conductive layer 202a by the first barrier layer 201a, the second barrier layer 203a and third barrier layer 205
It surrounds completely, the material of the first conductive layer 202a is difficult to external diffusion, so as to improve the first conductive layer 202a's
Electrical property.
In the present embodiment, the formation process on the third barrier layer 205 is selective deposition technique, the third blocking
The material of layer 205 includes CoWP, CuAl, CuSi, CuAlSi or CuMn.The selective deposition technique can be such that the third hinders
Barrier 205 is selectively formed in conductive material surface, and therefore, in the present embodiment, the third barrier layer 205 is formed in
The sidewall surfaces of one barrier layer 201a and the first conductive layer 202a；It is described when the second barrier layer 203a is conductive material
Third barrier layer 205 is also formed into the second barrier layer surfaces 203a.And in the present embodiment, 200 surface of the substrate is exhausted
Edge layer, the second barrier layer surfaces 203a are first medium layer 204a, therefore 200 surface of the substrate and first medium layer 204a
Side wall and top surface will not form the third barrier layer 205.Third barrier layer 205 is formed using selective deposition technique
Method is simple, and it is uniformly easily controllable to be formed by 205 thickness of third barrier layer.
In one embodiment, the material on the third barrier layer 205 is CoWP, forms the choosing on the third barrier layer 205
Selecting property depositing operation is selective chemical depositing process（Selective Electroless Plating）.The selective chemical
The parameter of depositing process includes：Deposition liquid includes oxidant, reducing agent and alkaline solution, and the pH value of the alkaline solution is 8.9~
9, temperature is 20 degrees Celsius~90 degrees Celsius.In the present embodiment, it is described when the material on the third barrier layer 205 is CoWP
Oxidant includes H3P(W3O10)4And CoSO4·6H2O, the reducing agent include NaH2PO2, the NaH2PO2A concentration of 0.23
The mol/L of mol/L~0.25, the alkaline solution are KOH solution.In another embodiment, the third barrier layer 205
When material is CuAl, CuSi, CuAlSi or CuMn, it is heavy for selective chemical gas phase to form the technique on the third barrier layer 205
Product technique（Selective CVD）.
In another embodiment, the formation process on the third barrier layer 205 is：On substrate 200, the first barrier layer
201a, the first conductive layer 202a, the second barrier layer 203a and the surfaces first medium layer 204a deposit third block film；Using return
Etching technics removes 200 surface of substrate and the side wall of first medium layer 204a and the third block film of top surface, is formed
Third barrier layer 205.
1 and Figure 12 are please referred to Fig.1, Figure 12 is the vertical view of Figure 11, and Figure 11 is that cross-section structures of the Figure 12 along the directions AA ' is illustrated
Figure.Sidewall surfaces on 200 surface of the substrate, 205 surface of third barrier layer and first medium layer 204a form second medium
Layer 206, the surface of the second dielectric layer 206 is flushed with the surfaces first medium layer 204a.
The second dielectric layer 206 is located at the sidewall surfaces on 205 surface of third barrier layer and first medium layer 204a, i.e. institute
Second dielectric layer 206 and first medium layer 204a is stated to be provided commonly for being electrically isolated the first conductive layer 202a.In the present embodiment, several
First conductive layer 202a of shape is arranged in parallel, and the second dielectric layer 206 carries out electricity between adjacent first conductive layer 202a
Isolation.
The material of the second dielectric layer 206 includes：SiO2, SiN, SiON, SiCOH or low-k materials；Especially when described
When 206 material low-k materials of second dielectric layer, be conducive to improve the electric isolution performance between the first conductive layer 202a.It needs to illustrate
, the material of the second dielectric layer 206 is different from the material of first medium layer 204a, make the second dielectric layer 206 with
There is Etch selectivity between first medium layer 204a, then subsequently can remove part first medium layer 204a by etching technics
To form the opening for exposing the first conductive layer 202a, and the second dielectric layer 206 is not damaged.
The formation process of the second dielectric layer 206 includes：Using depositing operation on 200 surface of substrate, third barrier layer
The side wall and top surface of 205 surfaces and first medium layer 204a form second medium film；Using CMP process
The second medium film is polished, until the top surface for exposing first medium layer 204a, second is formed and is situated between
Matter layer 206.
Wherein, the depositing operation for forming the second medium film is plasma enhanced chemical vapor deposition technique
（PECVD, Plasma Enhanced CVD）, the plasma enhanced chemical vapor deposition technique can be used in form
The more sidewall surfaces for being piled up in first medium layer 204a of material of second medium film and the close tops first conductive layer 202a
The sidewall surfaces in portion so that be formed by second medium film and form gap 213.The gap 213 advantageously reduces second
The k values of dielectric layer 206 improve the electric isolution ability of the second dielectric layer 206.
Secondly, the CMP process stops at the top surface of first medium layer 204a, therefore, described first
Dielectric layer 204a defines the stop position of the polishing process, protects the top surface of the first conductive layer 204a, Er Qie
In subsequent technique, the first medium layer 204a can also be electrically isolated the second conductive structure and the first conductive layer without electrical connection
202a。
3 and Figure 14 are please referred to Fig.1, Figure 14 is the vertical view of Figure 13, and Figure 13 is that cross-section structures of the Figure 14 along the directions BB ' is illustrated
Figure.Patterned layer 207 is formed in the first medium layer 204a and 206 surface of second dielectric layer, the patterned layer 207 exposes
Go out 206 surface part first medium layer 204a and second dielectric layer.
The patterned layer 207 defines the position for the part first medium layer 204a for needing to remove.The patterned layer
207 can be formed using photoetching process, nanoimprinting process or molecular self-assembling technique；In the present embodiment, described graphical
Layer 207 is patterned photoresist layer.
Due to the first medium layer 204a being formed at the top of the first conductive layer 202a and it is formed in the second of 200 surface of substrate
There is Etch selectivity between dielectric layer 206, can retain second dielectric layer 206 while etching first medium layer 204a,
Therefore the region that the patterned layer 207 exposes can be more than the top figure of follow-up required the second opening formed.At this
In embodiment, figure that the patterned layer 207 exposes is bar shaped, and the bar pattern of the patterned layer 207 relative to
The bar pattern of first conductive layer 202a is vertical, and at least exposes the two neighboring surfaces first medium layer 204a and part
206 surface of second dielectric layer.Since the area size that the patterned layer 207 exposes is more than the second opening of required formation
Top figure, therefore the figure accuracy of the patterned layer 207 is more easy to control, and be mask with the patterned layer 207
The pattern of the second opening formed is good, then between the second conductive structure and the first conductive layer 202a that are formed in the second opening
Electrical connection properties it is good.
5 are please referred to Fig.1, with the patterned layer 207（As shown in Figures 12 and 13）For mask, first is situated between described in etched portions
Matter layer 204a forms the second opening 208, second opening, 208 bottoms in second dielectric layer 206 and first medium layer 204a
Expose the part surfaces the first conductive layer 202a；After the etching process, the patterned layer 207 is removed.
The second opening 208 is formed by for being subsequently formed the second conductive structure, second conductive structure can be with the
One conductive layer 202a electrical connections, to realize the electrical interconnection between the first conductive layer 202a.In one embodiment, second resistance
When the material of barrier 203a is conductive material, the bottom-exposed of second opening 208 goes out the second barrier layer 203a.
In another embodiment, when the material of the second barrier layer 203a is insulating materials, the first medium layer 204a is being etched
Later, continue the second barrier layer 203a of 208 bottoms of the second opening of etching until exposing the first conductive layer 202a.
The technique of the etching first medium layer 204a be isotropic dry etching, anisotropic dry etching or
Isotropic wet etching.Since the first medium layer 204a has Etch selectivity relative to second dielectric layer 206, because
This described etching technics can retain the figure while removing the first medium layer 204a that the graph layer 207 exposes
The second dielectric layer 206 that shape layer 207 exposes so that the pattern for being formed by the second opening 208 is good.Moreover, because institute
It states first medium layer 204a and is located at the first surfaces conductive layer 202a, therefore after etched portions first medium layer 204a, it can
Only expose part the first conductive layer 202a so that the first conductive layer can be precisely directed to by being formed by the second opening 208
202a, to ensure that the electricity being subsequently formed between the second conductive structure and the first conductive layer 202a in the second opening 208
Switching performance；The deviation because of lithography alignment technique is avoided, causes what position between the second opening and the first conduction deviateed to ask
Topic.
After forming the second opening 208, the patterned layer 207 is removed, the patterned layer 207 of the present embodiment is photoetching
Glue-line, the then technique for removing the patterned layer are cineration technics or wet clean process.Remove the patterned layer 207 it
Afterwards, the second conductive structure can be formed in 206 surface of second dielectric layer and the second opening 208.
6 are please referred to Fig.1, the second opening 208 is being formed（As shown in figure 15）Later, it is formed in second opening 208
Second conductive structure 209.
Second conductive structure 209 with the first conductive layer 202a for being electrically connected, and second conductive structure 209
It is also formed into 206 surface of second dielectric layer and is across 208 top of the second opening, therefore second conductive structure 209 can
Realize the electrical connection between the first conductive layer 202a.In addition, second conductive structure 209 can also be formed in and not be removed
The surfaces first medium layer 204a, the first medium layer 204a can be electrically isolated the first conductive layer 202a and described second and lead
Electric structure 209.
Second conductive structure 209 includes：Positioned at the 4th barrier layer of the second opening 208 side walls and bottom surface
211 and positioned at the 4th barrier layer surface and the second conductive layer of full second opening 208 of filling.
Wherein, the 4th barrier layer 211 is used to prevent the material of the second conductive layer to first medium layer 204a and second
Diffusion in dielectric layer 206, the 4th barrier layer 211 are conductive material, including：The combination of Ta and TaN, Ru, CuAl, CuSi,
CuAlSi, CuMn or Co.
Secondly, the material of second conductive layer is copper, formation process include copper electroplating technology and copper electroplating technology it
Etching technics afterwards；Second conductive layer can also be formed in second dielectric layer 206 and the surfaces first medium layer 204a, make point
It is realized and is electrically interconnected by second conductive layer between the first vertical conductive layer 202a.In the present embodiment, the described second conductive knot
Structure 209 makes electricity interconnection between the first adjacent conductive layer 202a, the first conductive layer 202a and the second conductive structure 209 constitute
Copper interconnection structure.In addition, the material of second conductive layer can also be other conductive materials, such as aluminium, tungsten.
It should be noted that the formation process of second conductive structure 209 can also be walked with technique described in Fig. 5 to Figure 10
It is rapid identical.
In the present embodiment, after forming the first conductive layer, second dielectric layer, the second medium are formed in substrate surface
Layer is formed in the sidewall surfaces of third barrier layer surface and first medium layer, i.e., the described second dielectric layer is for being electrically isolated described the
One conductive layer.Since the second dielectric layer is formed after forming first conductive layer so that it is conductive to form described first
The technique of layer will not impact the second dielectric layer, therefore the quality for being formed by second dielectric layer is good, electricity every
Stablize from performance.Secondly, first conductive layer bottom is formed with the first barrier layer, and the is formed at the top of first conductive layer
Two barrier layers, and the side wall of first conductive layer is formed with third barrier layer, that is, it is complete to be formed by the first conductive layer surface
It is surrounded by the first barrier layer, the second barrier layer and third barrier layer；And first barrier layer, the second barrier layer and third blocking
Layer can prevent the material of the first conductive layer from spreading, to make the performance of first conductive layer stablize.Again, described
Second medium layer is flushed with first medium layer surface, and the first medium layer is formed in the first conductive layer top surface, therefore, only
Part first medium layer, which need to be removed, can expose the first conductive layer, can form second be connected to the first conductive layer and open
Mouthful, and second opening is used to form conductive structure.It is good due to being formed by the second opening pattern, and can only expose
First conductive layer, therefore, it is possible to keep the electrical connection properties between conductive structure and the first conductive layer good.
Correspondingly, the embodiment of the present invention also provides a kind of semiconductor structure, please continue to refer to Figure 16, including：Substrate
200, the substrate 200 has interconnecting area I；The first barrier layer 201 positioned at 200 surface of substrate of the interconnecting area I；Positioned at institute
The top surface for stating first the conductive layer 202a, the first conductive layer 202a on the first barrier layer surfaces 201a has the second blocking
Layer 203a, the second barrier layer surfaces 203a have first medium layer 204a, the sidewall surfaces of the first conductive layer 202a
With third barrier layer 205；Side wall positioned at 200 surface of the substrate, 205 surface of third barrier layer and first medium layer 204a
The surface of the second dielectric layer 206 on surface, the second dielectric layer 206 is flushed with the surfaces first medium layer 204a；Positioned at part
Second opening of the second barrier layer 203a top surfaces（It is not shown）, second opening is positioned at second dielectric layer 206 and first
In dielectric layer 204a, there is the second conductive structure 209 in second opening.
It should be noted that second conductive structure 209 includes：Positioned at second opening sidewalls and bottom surface
4th barrier layer and positioned at the 4th barrier layer surface and the second conductive layer of full second opening of filling.
In the present embodiment, first conductive layer bottom has the first barrier layer, has the at the top of first conductive layer
Two barrier layers, and the side wall of first conductive layer has third barrier layer, that is, is formed by the first conductive layer surface quilt completely
First barrier layer, the second barrier layer and third barrier layer surround.First barrier layer, the second barrier layer and third barrier layer energy
Enough prevent the material of the first conductive layer from spreading, to make the performance of first conductive layer stablize.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (15)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Substrate is provided, the substrate has interconnecting area；
The first block film and conductive film positioned at the first block film surface, the conductive thin are formed in substrate surface
The forming method of film includes：Conductive film is formed in first barrier layer surface using electroplating technology, using electroplating technology shape
At conductive film thickness be 1500 angstroms~2500 angstroms；Thermal annealing, the technique of the thermal annealing are carried out to the conductive film
For：Temperature is 200 degrees Celsius~450 degrees Celsius, and the time is 5 minutes~30 minutes；After thermal annealing, the conductive thin is thinned
The thickness of film；
The second block film is formed on the conductive film surface and first medium positioned at the second block film surface is thin
Film；
First medium film, the second block film, conductive film and the first block film described in etched portions are until expose lining
Until bottom surface, with the interconnecting area surface of substrate formed the first barrier layer, positioned at the first barrier layer surface the first conductive layer,
Positioned at the second barrier layer of the first conductive layer surface and positioned at the first medium layer of the second barrier layer surface；
Third barrier layer is formed in the sidewall surfaces of first conductive layer；
Second dielectric layer is formed in the sidewall surfaces of the substrate surface, third barrier layer surface and first medium layer, described the
The surface of second medium layer is flushed with first medium layer surface；
Part first medium layer is removed, forms the second opening, second open bottom in second dielectric layer and first medium layer
Portion exposes the first conductive layer surface of part.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the quantity of the interconnecting area is more than or waits
There is the first opening in 1, the interconnecting area of the substrate.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that have first to lead in first opening
The surface of electric structure, first conductive structure flushes with substrate surface or is less than the substrate surface.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the work of the thinned conductive film thickness
Skill is CMP process or is etched back to technique.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material on first barrier layer is to lead
Electric material, including：The combination of Ta and TaN, Ru, CuAl, CuSi, CuAlSi, CuMn or Co；The material packet on second barrier layer
Include combination, Ru, CuAl, CuSi, CuAlSi, CuMn, SiN, NDC or BN of Ta and TaN；The material of first conductive layer includes
Copper.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the first medium layer and
The material of second medium layer is different；The material of the first medium layer includes：NDC、SiN、SiO2, SiCN, BN, SiCOH and low k materials
One or more combinations in material；The material of the second dielectric layer includes：SiO2, SiN, SiON, SiCOH or low-k materials.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that the formation process on the third barrier layer
Material for selective deposition technique, the third barrier layer includes CoWP, CuAl, CuSi, CuAlSi or CuMn.
8. the forming method of semiconductor structure as described in claim 1, which is characterized in that the formation process of the second dielectric layer
Including：Using depositing operation the is formed in substrate surface, the side wall of third barrier layer surface and first medium layer and top surface
Second medium film；The second medium film is polished using CMP process, until exposing first medium
Until the top surface of layer, second dielectric layer is formed.
9. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that described to form the heavy of second medium film
Product technique is plasma enhanced chemical vapor deposition technique.
10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that between adjacent first conductive layer
It is formed with gap in second medium layer.
11. the forming method of semiconductor structure as described in claim 1, which is characterized in that the formation process of second opening
Including：Patterned layer is formed in the first medium layer and second medium layer surface, the patterned layer exposes part first
Dielectric layer and second medium layer surface；Using the patterned layer as mask, first medium layer described in etched portions simultaneously exposes portion
Divide the second barrier layer surface, forms the second opening；After the etching process, the patterned layer is removed.
12. the forming method of semiconductor structure as described in claim 1, which is characterized in that further include：Forming the second opening
Afterwards, the second conductive structure is formed in second opening, second conductive structure includes：Positioned at second opening sidewalls
It is led with the 4th barrier layer of bottom surface and positioned at the second of the 4th barrier layer surface and full second opening of filling
Electric layer.
13. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that second conductive structure is also formed
In second medium layer surface and it is across the second open top.
14. the forming method of semiconductor structure as claimed in claim 13, which is characterized in that second conductive structure is also formed
In second dielectric layer and first medium layer surface.
15. the forming method of semiconductor structure as claimed in claim 13, which is characterized in that the material packet on the 4th barrier layer
It includes：The combination of Ta and TaN, Ru, CuAl, CuSi, CuAlSi, CuMn or Co；The material of second conductive layer includes copper.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5382545A (en) * | 1993-11-29 | 1995-01-17 | United Microelectronics Corporation | Interconnection process with self-aligned via plug |
| US6177286B1 (en) * | 1998-09-24 | 2001-01-23 | International Business Machines Corporation | Reducing metal voids during BEOL metallization |
| CN101431047A (en) * | 2007-10-09 | 2009-05-13 | 应用材料股份有限公司 | Method for forming an air gap in multilevel interconnect structure |
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| US5382545A (en) * | 1993-11-29 | 1995-01-17 | United Microelectronics Corporation | Interconnection process with self-aligned via plug |
| US6177286B1 (en) * | 1998-09-24 | 2001-01-23 | International Business Machines Corporation | Reducing metal voids during BEOL metallization |
| CN101431047A (en) * | 2007-10-09 | 2009-05-13 | 应用材料股份有限公司 | Method for forming an air gap in multilevel interconnect structure |
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