CN104217991A - Method for forming interconnection structures - Google Patents
Method for forming interconnection structures Download PDFInfo
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- CN104217991A CN104217991A CN201310222161.0A CN201310222161A CN104217991A CN 104217991 A CN104217991 A CN 104217991A CN 201310222161 A CN201310222161 A CN 201310222161A CN 104217991 A CN104217991 A CN 104217991A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
Abstract
The invention discloses a method for forming interconnection structures. The method includes forming interlayer dielectric layers, adhesion layers, protection layers and hard mask layers on semiconductor substrates from bottom to top; forming first openings in the hard mask layers; carrying out plasma treatment and cleaning processes; using remaining portions of the hard mask layers as masks and sequentially etching the protection layers, the adhesion layers and the interlayer dielectric layers until etch structures are formed in the interlayer dielectric layers; filling metal materials in the etch structures and removing remaining portions of the hard mask layers, the protection layers and the adhesion layers. The first openings are perforated through the hard mask layers. The etch structures comprise through holes or grooves or combinations of the through holes and the grooves. The method has the advantages that the quantities of metal plugs or metal interconnection wires or combinations of the metal plugs and the metal interconnection wires which are formed by the aid of the method are accurate, the metal plugs and the metal interconnection wires are excellent in morphology, and semiconductor devices with the metal plugs or the metal interconnection wires or the combinations of the metal plugs and the metal interconnection wires are excellent in performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of formation method of interconnection structure.
Background technology
Increase gradually along with to very lagre scale integrated circuit (VLSIC) high integration and high performance demand, semiconductor technology is towards the technology node development of more small-feature-size, and the arithmetic speed of chip is obviously subject to the impact of the RC delays that metallic conduction causes.
On the one hand, in order to improve the performance of integrated circuit, utilizing the copper with the advantage such as low-resistivity, excellent deelectric transferred ability to replace aluminium as the metal interconnecting wires in semiconductor, metal interconnected line resistance can be reduced.
On the other hand, utilize low-k materials or ultralow-k material film as the interlayer dielectric layer of metal interconnecting wires, effectively can reduce electric capacity.
The metal interlamination medium layer that copper dual-damascene technology collocation low-k materials is formed is interconnection structure process combination most popular at present, and it effectively can improve the phenomenon of RC delays.
In existing technique, a kind of formation method of copper dual-damascene structure comprises: provide Semiconductor substrate, and forms interlayer dielectric layer, adhesion layer, protective layer and hard mask layer successively from the bottom to top on the semiconductor substrate; Etch described hard mask layer, to form the first opening exposing described protective layer, the position of described first opening and shape are corresponding with the position of follow-up formation copper metal interconnecting wires and shape respectively; Carry out cleaning, to remove polymer residual in formation first opening process; Formed in described first opening and comprise the photoresist layer of the second opening, the position of described second opening and shape are corresponding with the position of follow-up formation copper metal plug and shape respectively; With metal hard mask layer and photoresist layer for mask, protective layer, adhesion layer and interlayer dielectric layer are etched, to the interlayer dielectric layer of the second open bottom remainder thickness; Remove described second photoresist layer; With described hard mask layer for mask, etch described protective layer, adhesion layer and interlayer dielectric layer, to exposing described Semiconductor substrate, to form the etching structure comprising groove and be positioned at beneath trenches through hole in described interlayer dielectric layer; In described etching structure, fill full metal material, and remove described hard mask layer, protective layer and adhesion layer.
Wherein, the material of described adhesion layer is silica, and it is that reactant is formed with tetraethoxysilane, in order to improve interlayer dielectric layer and follow-up formation protective layer between adhesiveness, the thickness range of described adhesion layer is 50 dust ~ 500 dusts.The material of described protective layer is the silica formed by chemical vapor deposition method, and for as the stop-layer being formed opening by etching technics in hard mask layer, the thickness range of described protective layer is 50 dust ~ 1000 dusts.
But, find when the copper dual-damascene structure formed above-mentioned technique checks: disappearance or distortion occur part copper dual-damascene structure, have had a strong impact on the performance of the semiconductor device comprising formed copper dual-damascene structure.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of interconnection structure, avoid formed metal plug, metal interconnecting wires or dual-damascene structure that disappearance or distortion occur, improve the performance comprising the semiconductor device of formed metal plug, metal interconnecting wires or dual-damascene structure.
For solving the problem, the invention provides a kind of formation method of interconnection structure, comprising:
Semiconductor substrate is provided, and forms interlayer dielectric layer, adhesion layer, protective layer and hard mask layer successively from the bottom to top on the semiconductor substrate;
The first opening is formed in described hard mask layer;
Carry out plasma treatment and cleaning;
With remaining described hard mask layer for mask, etch successively to described protective layer, adhesion layer and interlayer dielectric layer, until form etching structure in described interlayer dielectric layer, described etching structure comprises one in through hole and groove or its combination;
In described etching structure, fill full metal material, and remove remaining described hard mask layer, protective layer and adhesion layer.
Optionally, the material of described adhesion layer is silica.
Optionally, plasma treatment is carried out described in and cleaning comprises: first adopt the mist comprising ammonia to carry out plasma treatment; Carry out cleaning again.
Optionally, plasma treatment is carried out described in and cleaning comprises: first carry out cleaning; Ammonia or nitrogen is adopted to carry out plasma treatment again.
Optionally, plasma treatment is carried out described in and cleaning comprises: adopt the mist comprising ammonia to carry out first time plasma process; Carry out cleaning; Ammonia or nitrogen is adopted to carry out second time plasma process.
Optionally, carry out cleaning and comprise: first adopt hydrofluoric acid solution to carry out first time clean, then adopt the mixed solution of hydrogen peroxide and EKC to carry out second time clean; In the mixed solution of described hydrogen peroxide and EKC, the volume range of hydrogen peroxide and EKC is 1:1 ~ 4.
Optionally, described etching structure comprises through hole and groove; With remaining described hard mask layer for mask, successively described protective layer, adhesion layer and interlayer dielectric layer are etched, comprise until form etching structure in described interlayer dielectric layer: in described first opening, form photoresist layer, in described photoresist layer, be formed with the second opening; With described hard mask layer and photoresist layer for mask, described protective layer, adhesion layer and interlayer dielectric layer are etched, to the second opening, remains the interlayer dielectric layer of predetermined thickness; Remove described photoresist layer; With described hard mask layer for mask, etch described protective layer, adhesion layer and interlayer dielectric layer, until expose described Semiconductor substrate.
Compared with prior art, technical scheme of the present invention has the following advantages:
After the first opening is formed, carry out plasma treatment and cleaning, with when the first open bottom exposes adhesion layer, avoid the adhesion layer surface modification that cleaning solution in cleaning causes, or react and the adhesion layer of sex change with cleaning solution in removal cleaning, make to be positioned at the protective layer below the first opening, adhesion layer and interlayer dielectric layer can be removed by follow-up etching technics, there is disappearance or distortion in the etching structure avoided the formation of, ensure form metal plug, the pattern of metal interconnecting wires or dual-damascene structure, and then ensure to comprise formed metal plug, the electric property of the semiconductor device of metal interconnecting wires or dual-damascene structure.
Further, carry out plasma treatment and cleaning comprises: first adopt the mist comprising ammonia to carry out plasma treatment, remove the hydroxide ion being positioned at adhesion layer and protective layer, make the surface being positioned at the first open bottom adhesion layer and protective layer be hydrophobicity by hydrophilic conversion; Carry out cleaning again, remove polymer residual in formation first opening process.Due to the protective layer after plasma treatment and adhesion layer surfaces hydrophobic, in cleaning cleaning solution not easily with protective layer and adhesion layer surface contact, avoid adhesion layer surface because reacting and sex change with cleaning solution, make to be positioned at the protective layer below the first opening, adhesion layer and interlayer dielectric layer can be removed by follow-up etching technics, and then avoid formed etching structure that disappearance or distortion occur, form metal plug, the quantity of metal interconnecting wires or dual-damascene structure is accurate and pattern is better, improve and comprise formed metal plug, the electric property of the semiconductor device of metal interconnecting wires or dual-damascene structure.
Further, plasma treatment is carried out and cleaning comprises: first carry out cleaning, then adopt ammonia or nitrogen to carry out plasma treatment.When to be removed in the first opening forming process residual polymer by cleaning, if the first open bottom exposes adhesion layer, the adhesion layer exposed easily and cleaning solution react and sex change; When adopting ammonia or nitrogen to carry out plasma treatment; adhesion layer after sex change is reduced; protective layer, adhesion layer and the interlayer dielectric layer be positioned at below the first opening can be removed by follow-up etching technics; and then avoiding formed etching structure that disappearance or distortion occur, institute forms that the quantity of metal plug, metal interconnecting wires or dual-damascene structure is accurate and pattern is better.
Further, plasma treatment is carried out and cleaning comprises: first adopt the mist comprising ammonia to carry out first time plasma process; Carry out cleaning again; Ammonia or nitrogen is finally adopted to carry out second time plasma process.The adhesion layer surface making to expose by first time plasma process is hydrophobicity by hydrophilic conversion, to avoid adhesion layer surface in cleaning as far as possible, sex change occurs; By second time plasma process, the adhesion layer reacted with cleaning solution is reduced; ensure that the first open bottom remains without the adhesion layer after sex change; and then ensure that protective layer, adhesion layer and the interlayer dielectric layer be positioned at below the first opening can be removed by follow-up etching technics; avoid formed etching structure that disappearance or distortion occur, institute forms that the quantity of metal plug, metal interconnecting wires or dual-damascene structure is accurate and pattern is better.
Accompanying drawing explanation
Fig. 1 ~ Fig. 5 is the schematic diagram of formation method first embodiment of interconnection structure of the present invention;
Fig. 6 ~ Figure 11 is the schematic diagram of formation method second embodiment of interconnection structure of the present invention.
Embodiment
Inventor finds through research; in existing technique easily there is disappearance or be out of shape to cause primarily of following reason in copper dual-damascene structure: in order to reduce the depth-to-width ratio of formed groove and through hole; reduce follow-up difficulty of filling copper metal material in groove and through hole; the protective layer be arranged on interlayer dielectric layer is thinner; and when carrying out etching to hard mask layer and forming opening; easily the protective layer below opening is removed, cause part adheres layer to expose.Carrying out cleaning, during to remove polymer residual in formation first opening process, cleaning solution easily reacts with the adhesion layer exposed, and makes adhesion layer surface modification.And formed in groove and via process in etching, etching technics is difficult to the adhesion layer after by sex change and removes, adhesion layer after causing being positioned at sex change below adhesion layer and interlayer dielectric layer cannot be removed, form groove and through hole disappearance or distortion occur, and then cause the quantity of formed copper dual-damascene structure, shape changes, and finally have impact on the performance of the semiconductor device comprising formed copper dual-damascene structure.
Inventor finds after further research, after can forming the first opening, carries out plasma treatment and cleaning in hard mask layer, to solve the problem that above-mentioned copper dual-damascene structure easily occurs to lack or be out of shape.It at least can be divided into following three kinds of situations:
The first, after formation first opening, first carry out plasma treatment, then carry out cleaning.By carrying out plasma treatment, remove the hydroxide ion being attached to protective layer and adhesion layer surface, and then make protective layer and adhesion layer surface be hydrophobicity by hydrophilic conversion.When carrying out cleaning, cleaning solution not easily contacts with adhesion layer, avoids adhesion layer and cleaning solution to react and sex change, enables not removed completely by the adhesion layer that hard mask layer covers.
The second, after formation first opening, first carry out cleaning, then carry out plasma treatment.When carrying out cleaning, the adhesion layer that the first open bottom exposes and cleaning solution react and sex change.By carrying out plasma treatment, the adhesion layer after sex change is reduced, and then enable not removed completely by the adhesion layer that hard mask layer covers.
3rd, described plasma treatment comprises plasma process and second time plasma process for the first time.After formation first opening, first carry out first time plasma process, then carry out cleaning, finally carry out second time plasma process.By carrying out first time plasma process, making protective layer and the adhesion layer surface exposed be hydrophobicity by hydrophilic conversion, the least possible adhesion layer and cleaning solution are reacted.Even and if a small amount of adhesion layer still reacts and sex change with cleaning solution, also can be reduced by the second time plasma process after cleaning, ensure that the first open bottom remains without the adhesion layer after sex change, and then enable not removed completely by the adhesion layer that hard mask layer covers.
By carrying out above-mentioned plasma treatment and cleaning, the quantity making formed dual-damascene structure accurately and pattern is better.
In addition, above-mentioned technique is also applicable to the formation process of metal plug and metal interconnecting wires.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
First embodiment
The present embodiment is for the metal interconnecting wires (etching structure namely formed in interlayer dielectric layer is for through hole) in single mosaic technology, the formation method of interconnection structure of the present invention is described, the formation method of metal plug and the formation method of metal interconnecting wires similar, do not describe in detail at this.
With reference to figure 1, provide Semiconductor substrate 200, and form interlayer dielectric layer 202a, adhesion layer 204a, protective layer 206a and hard mask layer 208a successively from the bottom to top in described Semiconductor substrate 200.
In the present embodiment, the material of described Semiconductor substrate 200 can well known to a person skilled in the art semi-conducting material for monocrystalline silicon, monocrystalline germanium or monocrystalline germanium silicon, silicon-on-insulator, iii-v element compound, monocrystalline silicon carbide etc.
In addition, also can be formed with device architecture (not shown) in described Semiconductor substrate 200, described device architecture can be the device architecture formed in semiconductor FEOL, such as MOS transistor etc.; The metal plug etc. be connected with device architecture also can be formed in described Semiconductor substrate 200.
In the present embodiment, the material of described interlayer dielectric layer 202a is low-k materials or ultralow-k material film, and the method forming described interlayer dielectric layer 202a can be chemical vapor deposition method.
The material of described adhesion layer 204a can be silica, and thickness range is 50 dust ~ 500 dusts, in order to improve interlayer dielectric layer 202a and follow-up formation protective layer 206a between adhesiveness; The reactant forming described adhesion layer 204a can be tetraethoxysilane and ozone, and its concrete formation process is well known to those skilled in the art, and does not repeat them here.
The material of described protective layer 206a is silica, and thickness range is 50 dust ~ 1000 dusts; The method forming described protective layer 206a can be chemical vapor deposition method.The material of described hard mask layer 208a can be titanium nitride, copper nitride or aluminium nitride, and the method forming described hard mask layer 208a can be chemical vapor deposition method.
With reference to figure 2, etch the 208a of hard mask layer described in Fig. 1, form the first opening 209 in remaining hard mask layer 208b, described first opening 209 runs through described hard mask layer 208b.
In the present embodiment, the method forming the first opening 209 in described hard mask layer 208a is dry etching.It specifically can comprise: on hard mask layer 208a, form the photoresist layer (not shown) comprising the first opening figure; With described photoresist layer for mask, etching is carried out to described hard mask layer 208a and forms described first opening 209; Remove described photoresist layer.
It should be noted that; in order to ensure that the first formed opening 209 runs through described hard mask layer 208a; when formation the first opening 209, also over etching is carried out to the protective layer 206a be positioned at below the first opening 209, to the protective layer 206b of the first opening 209 root remaining portion thickness.And due to the thinner thickness of protective layer 206a in Fig. 1, the partial protection layer 206a be positioned at below the first opening 209 is easily completely removed, and exposes the described adhesion layer 204a of part.
Then, after formation first opening 209, adopt and comprise ammonia (NH
3) mist carry out plasma treatment.
In the present embodiment, the range of flow of described ammonia is 10sccm ~ 2000sccm, and the temperature range of carrying out plasma treatment is 10 DEG C ~ 250 DEG C, and time range is 10s ~ 120s.The described mist comprising ammonia except comprising ammonia, also can comprise in nitrogen, helium and argon gas one or several.
Adopt the mist comprising ammonia to carry out plasma treatment to silicon oxide surface, the hydroxide ion being attached to silicon oxide surface can be removed.Because the material of adhesion layer 204a and protective layer 206b is silica; therefore by adopting the mist comprising ammonia to carry out plasma treatment; eliminate the hydroxide ion being attached to the first opening 209 bottom protective layer 206b and adhesion layer 204a surface, make the surface of protective layer 206b and adhesion layer 204a be hydrophobicity by hydrophilic conversion.
Optionally, adopt the mist comprising ammonia to carry out plasma treatment and in described hard mask layer 208a, form the first opening 209 carrying out in same equipment, to reduce the step of transfer of semiconductor substrate, simplify the formation process of interconnection structure, cost-saving.
It should be noted that, adopt the mist comprising ammonia to carry out plasma treatment and in described hard mask layer 208a, form the first opening 209 also can carry out in different equipment, the present invention does not limit this.
Then, ammonia (NH is comprised in employing
3) mist carry out plasma treatment after, carry out cleaning.
Concrete, carry out cleaning and comprise: first adopt hydrofluoric acid solution to carry out first time clean, then adopt the mixed solution of hydrogen peroxide and EKC to carry out second time clean.In the mixed solution of described hydrogen peroxide and EKC, the volume range of hydrogen peroxide and EKC is 1:1 ~ 4.Wherein, a kind of alkaline solution of being provided by EKC Technology Inc of Du Pont of EKC.
Described hydrofluoric acid solution can remove polymer residual in formation first opening 209 process; In the mixed solution of hydrogen peroxide and EKC, EKC can remove polymer residual in formation first opening 209 process further, hydrogen peroxide can remove the described hard mask layer 208b of trace, be beneficial to the removal being attached to polymer on hard mask layer 208b, and be beneficial to the formation of follow-up through hole and the filling of metal material.
It should be noted that, because EKC removal hard mask layer 208b is very little, the impact of second time clean on the first opening 209 pattern is negligible.
By carrying out described cleaning, effectively can to remove in formation first opening 209 process residual polymer, being beneficial to the etching technics of follow-up through hole, ensure form the quality of through hole.
Because the surface of exposed adhesion layer 204a is hydrophobicity, in cleaning, cleaning solution is difficult to and adhesion layer 204a surface contact, avoids adhesion layer 204a surface to react and sex change with cleaning solution.
With reference to figure 3; with hard mask layer 208b for mask; protective layer 206b remaining in Fig. 2, adhesion layer 204a and interlayer dielectric layer 202a are etched; to exposing described Semiconductor substrate 200; residue protective layer 206c, adhesion layer 204b and interlayer dielectric layer 202b, form the through hole 210 running through described interlayer dielectric layer 202b.
In the present embodiment, the method etched remaining protective layer 206b, adhesion layer 204a and interlayer dielectric layer 202a is dry etching, and its concrete technology is well known to those skilled in the art, and does not repeat them here.
In the present embodiment, there is not sex change in the adhesion layer 204a surface gone out due to the first opening 209 bottom-exposed, the adhesion layer 204a do not covered by hard mask layer 208b and the interlayer dielectric layer 202a be positioned at below adhesion layer 204a can remove by etching technics completely, ensure that in hard mask layer 208b, the first opening 209 figure can be transferred in interlayer dielectric layer 202b complete and accurate, to form through hole 210 in interlayer dielectric layer 202b, avoid formed through hole 210 deform or lack, form through hole 210 quantity accurately and pattern is better.
With reference to figure 4, the hard mask layer 208b in figure 3 in described through hole 210 and around through hole 210 forms metal material 212a.
In the present embodiment, described metal material 212a is copper.The method forming metal material 212a can be physical gas-phase deposition, but the present invention is not limited thereto.
With reference to figure 5, chemical mechanical milling tech is adopted to carry out planarization, to exposing described interlayer dielectric layer 202b, to form metal interconnecting wires 212b to metal material 212a, remaining hard mask layer 208b, protective layer 206c and adhesion layer 204b in Fig. 4.
It should be noted that, in the present embodiment, metal interconnecting wires 212b is also connected with the metal plug (not shown) in Semiconductor substrate 200, realizes electrical connection to make the semiconductor device in Semiconductor substrate 200.
During this city is implemented; form the first opening 209 in hard mask layer 208a after; the mist comprising ammonia is first adopted to carry out plasma treatment; remove the hydroxide ion be positioned on protective layer 206b and adhesion layer 204a; the surface being positioned at adhesion layer 204a bottom the first opening 209 is made to be hydrophobicity by hydrophilic conversion; carry out cleaning again, remove polymer residual in formation first opening 209 process.Due to the adhesion layer 204a surfaces hydrophobic after plasma treatment, in cleaning cleaning solution not easily with adhesion layer 204a surface contact properties, avoid adhesion layer 204a surface because reacting and sex change with cleaning solution, make to be positioned at the protective layer 206b below the first opening 209, adhesion layer 204a and interlayer dielectric layer 202a can be removed by follow-up etching technics, and then avoid formed through hole 210 that disappearance or distortion occur, form metal interconnecting wires 212b quantity accurately and pattern is better, improve the electric property of the semiconductor device comprising formed metal interconnecting wires 212b.
Second embodiment
The present embodiment with dual-damascene structure (etching structure namely formed in interlayer dielectric layer comprises through hole and groove, described through hole be positioned at described groove below and with described grooves extend) be example, the formation method of interconnection structure of the present invention is described.
With reference to figure 6, provide Semiconductor substrate 300, and form interlayer dielectric layer 302a, adhesion layer 304a, protective layer 306a and hard mask layer 308a successively from the bottom to top in described Semiconductor substrate 300.
In the present embodiment, material and the formation process of described Semiconductor substrate 300, interlayer dielectric layer 302a, adhesion layer 304a, protective layer 306a and hard mask layer 308a please refer to the first embodiment, do not repeat them here.
With reference to figure 7, form the first opening 310 in figure 6 in described hard mask layer 308a, described first opening 310 runs through described hard mask layer 308b.
In the present embodiment, the position of described first opening 310 and shape are corresponding with the position of metal interconnecting wires in follow-up formation dual-damascene structure and shape respectively.
It should be noted that, due to the thinner thickness of protective layer 306b, in formation first opening 310 process, the part adheres layer 304a be positioned at below the first opening 310 easily exposes.Its concrete reason please refer to the first embodiment, does not repeat at this.
Then, after formation first opening 310, first cleaning is carried out.
Concrete, carry out described cleaning and comprise: first adopt hydrofluoric acid solution to carry out first time clean, then adopt the mixed solution of hydrogen peroxide and EKC to carry out second time clean.Carrying out in cleaning process, the adhesion layer 304a that the first opening 310 bottom-exposed goes out and cleaning solution react and sex change.
Then, after carrying out cleaning, ammonia or nitrogen is adopted to carry out plasma treatment.
In the present embodiment, when adopting ammonia or nitrogen to carry out plasma treatment, the range of flow of ammonia or nitrogen is 10sccm ~ 2000sccm, and the temperature range of carrying out plasma treatment is 100 DEG C ~ 400 DEG C, and time range is 10s ~ 120s.Carry out in plasma treatment procedure at employing ammonia or nitrogen, the adhesion layer 304a after sex change is reduced.
Owing to improving the rate of reduction of adhesion layer 304a after sex change by improving the temperature of plasma treatment, therefore the temperature of plasma treatment is set to be greater than or equal to 100 DEG C and is less than or equal to 400 DEG C, now, plasma treatment is very fast to the rate of reduction of adhesion layer 304a after sex change, and can not impact the performance of formed interconnection structure.And when the temperature of plasma treatment is less than 100 DEG C, plasma treatment is comparatively slow to the rate of reduction of adhesion layer 304a after sex change, the make efficiency of interconnection structure is low, and cost of manufacture is high.When the temperature of plasma treatment is greater than 400 DEG C, plasma treatment can impact the performance of formed interconnection structure, impact form the rate of finished products of interconnection structure.
With reference to figure 8, form photoresist layer 314 in described first opening 310 in the figure 7, in described photoresist layer 314, be formed with the second opening 312 running through described photoresist layer 314 thickness.
In the present embodiment, the position of described second opening 312 and shape are corresponding with the position of metal plug in follow-up formation dual-damascene structure and shape respectively.Form the method comprising the photoresist layer 314 of the second opening 312 to be well known to those skilled in the art, do not repeat them here.
With reference to figure 9; with hard mask layer 308b in Fig. 8 and photoresist layer 314 for mask; described protective layer 306b, adhesion layer 304a and interlayer dielectric layer 302a are etched; to the second opening 312, remain the interlayer dielectric layer 302b of predetermined thickness, and remain the adhesion layer 304b and protective layer 306b that are positioned at below hard mask layer 308b and photoresist layer 314.
In the present embodiment, described predetermined thickness is corresponding with the thickness of follow-up formation groove.
With reference to Figure 10; remove photoresist layer 314 described in Fig. 9; and with described hard mask layer 308b for mask; etch described protective layer 306b, adhesion layer 304b and interlayer dielectric layer 302b; until expose described Semiconductor substrate 300; to form groove 316 and through hole 318 in described interlayer dielectric layer 302c, remain the protective layer 306c and adhesion layer 304c that are positioned at below hard mask layer 308b.Described through hole 318 is positioned at below described groove 316, and through with described groove 316.
With reference to Figure 11, fill full metal material in described groove 316 and through hole 318 in Fig. 10, to form metal interconnecting wires 320 and metal plug 322, and remove remaining hard mask layer 308b, protective layer 306c and adhesion layer 304c.
Concrete; can first in Fig. 10 in described groove 316 and through hole 318, in the opening that enclosed by adhesion layer 304c, protective layer 306c and hard mask layer 308b above groove 316 and hard mask layer 308b fills out form metal material; then chemical mechanical milling tech is adopted to carry out planarization to metal material, hard mask layer 308b, protective layer 306c and adhesion layer 304c; to exposing described interlayer dielectric layer 302c, the metal material that residue is arranged in groove 316 and through hole 318 is respectively as the metal interconnecting wires 320 of dual-damascene structure and metal plug 322.
In the present embodiment, described metal material is copper, and its formation process can be physical gas-phase deposition.
In the present embodiment, first carry out cleaning, to remove polymer residual in formation first opening 310 process, now, if the first opening 310 bottom-exposed goes out part adheres layer 304a, adhesion layer 304a and cleaning solution react and sex change; After the cleaning process, then adopt ammonia or nitrogen to carry out plasma treatment, reduce to make the adhesion layer 304a after sex change.With hard mask layer 308b for mask; when forming groove 316 and through hole 318 by etching technics; ensure that the protective layer 306b that do not covered by hard mask layer 308b and adhesion layer 304a can be completely removed; the quantity making to be formed at groove 316 and through hole 318 in interlayer dielectric layer 202b accurately and pattern is better; and then ensureing that institute forms that the quantity of metal interconnecting wires 320 and metal plug 322 is accurate and pattern is better, the performance comprising the semiconductor device of metal interconnecting wires 320 and metal plug 322 is good.
In other embodiments, after also can forming the first opening 310 in the first hard mask layer 308b, the mist comprising ammonia is first adopted to carry out first time plasma process; Carry out cleaning again; Ammonia or nitrogen is finally adopted to carry out second time plasma process.The adhesion layer 304a surface making to expose by first time plasma process is hydrophobicity by hydrophilic conversion, reacts with cleaning solution to avoid adhesion layer 304a surface in cleaning as far as possible.Carrying out in cleaning process, the sex change even if part adheres layer 304a and cleaning solution react, also by second time plasma process, the adhesion layer 304a after sex change is being reduced.When forming groove 316 and through hole 318 by etching technics; the protective layer 306b do not covered by hard mask layer 308b and adhesion layer 304a can be completely removed; the quantity making formed metal interconnecting wires 320 and metal plug 322 accurately and pattern is better, improves the performance of the semiconductor device comprising metal interconnecting wires 320 and metal plug 322.The method adopting the mist comprising ammonia to carry out first time plasma process please refer to the corresponding steps in the first embodiment, and the method adopting ammonia or nitrogen to carry out second time plasma process please refer to the corresponding steps in the second embodiment, do not describe in detail at this.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (13)
1. a formation method for interconnection structure, is characterized in that, comprising:
Semiconductor substrate is provided, and forms interlayer dielectric layer, adhesion layer, protective layer and hard mask layer successively from the bottom to top on the semiconductor substrate;
The first opening is formed in described hard mask layer;
Carry out plasma treatment and cleaning;
With remaining described hard mask layer for mask, etch successively to described protective layer, adhesion layer and interlayer dielectric layer, until form etching structure in described interlayer dielectric layer, described etching structure comprises one in through hole and groove or its combination;
In described etching structure, fill full metal material, and remove remaining described hard mask layer, protective layer and adhesion layer.
2. the formation method of interconnection structure as claimed in claim 1, it is characterized in that, the material of described adhesion layer is silica.
3. the formation method of interconnection structure as claimed in claim 2, is characterized in that, described in carry out plasma treatment and cleaning comprises:
The mist comprising ammonia is first adopted to carry out plasma treatment;
Carry out cleaning again.
4. the formation method of interconnection structure as claimed in claim 2, is characterized in that, described in carry out plasma treatment and cleaning comprises:
First carry out cleaning;
Ammonia or nitrogen is adopted to carry out plasma treatment again.
5. the formation method of interconnection structure as claimed in claim 2, is characterized in that, described in carry out plasma treatment and cleaning comprises:
The mist comprising ammonia is adopted to carry out first time plasma process;
Carry out cleaning;
Ammonia or nitrogen is adopted to carry out second time plasma process.
6. the formation method of the interconnection structure as described in claim 3 or 5, it is characterized in that, when adopting the mist comprising ammonia to carry out plasma treatment, the range of flow of ammonia is 10sccm ~ 2000sccm, the temperature range of carrying out plasma treatment is 10 DEG C ~ 250 DEG C, and time range is 10s ~ 120s.
7. the formation method of the interconnection structure as described in claim 3 or 5, is characterized in that, adopts the mist comprising ammonia to carry out plasma treatment and in described hard mask layer, form the first opening carrying out in same equipment.
8. the formation method of the interconnection structure as described in claim 4 or 5, it is characterized in that, when adopting ammonia or nitrogen to carry out plasma treatment, the range of flow of ammonia or nitrogen is 10sccm ~ 2000sccm, the temperature range of carrying out plasma treatment is 100 DEG C ~ 400 DEG C, and time range is 10s ~ 120s.
9. the formation method of the interconnection structure as described in any one of claim 3 to 5, is characterized in that, carries out cleaning and comprises: first adopt hydrofluoric acid solution to carry out first time clean, then adopt the mixed solution of hydrogen peroxide and EKC to carry out second time clean; In the mixed solution of described hydrogen peroxide and EKC, the volume range of hydrogen peroxide and EKC is 1:1 ~ 4.
10. the formation method of interconnection structure as claimed in claim 1, it is characterized in that, the material of described protective layer is silica, and the method forming described protective layer is chemical vapor deposition method, and the thickness range of described protective layer is 50 dust ~ 1000 dusts.
The formation method of 11. interconnection structures as claimed in claim 1, is characterized in that, the material of described interlayer dielectric layer is low-k materials or ultralow-k material film, and described metal material is copper.
The formation method of 12. interconnection structures as claimed in claim 1, is characterized in that, the material of described hard mask layer is titanium nitride, copper nitride or aluminium nitride.
The formation method of 13. interconnection structures as claimed in claim 1, it is characterized in that, described etching structure comprises through hole and groove; With remaining described hard mask layer for mask, successively described protective layer, adhesion layer and interlayer dielectric layer are etched, comprise until form etching structure in described interlayer dielectric layer: in described first opening, form photoresist layer, in described photoresist layer, be formed with the second opening; With described hard mask layer and photoresist layer for mask, described protective layer, adhesion layer and interlayer dielectric layer are etched, to the second opening, remains the interlayer dielectric layer of predetermined thickness; Remove described photoresist layer; With described hard mask layer for mask, etch described protective layer, adhesion layer and interlayer dielectric layer, until expose described Semiconductor substrate.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107119280A (en) * | 2016-02-25 | 2017-09-01 | 东莞新科技术研究开发有限公司 | Bond pad surface processing method |
| CN108012561A (en) * | 2015-06-22 | 2018-05-08 | 英特尔公司 | For backend process（BEOL）Interconnection piece is inverted by using bottom-up crosslinked dielectric picture tone |
| CN111276456A (en) * | 2020-02-18 | 2020-06-12 | 合肥晶合集成电路有限公司 | Semiconductor device and method for manufacturing the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6534397B1 (en) * | 2001-07-13 | 2003-03-18 | Advanced Micro Devices, Inc. | Pre-treatment of low-k dielectric for prevention of photoresist poisoning |
| CN102347206B (en) * | 2010-07-29 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102543844B (en) * | 2010-12-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device structure and semiconductor device structure |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108012561A (en) * | 2015-06-22 | 2018-05-08 | 英特尔公司 | For backend process（BEOL）Interconnection piece is inverted by using bottom-up crosslinked dielectric picture tone |
| CN108012561B (en) * | 2015-06-22 | 2022-03-04 | 英特尔公司 | Image tone reversal with use of bottom-up cross-linked dielectrics for back-end-of-line (BEOL) interconnects |
| CN107119280A (en) * | 2016-02-25 | 2017-09-01 | 东莞新科技术研究开发有限公司 | Bond pad surface processing method |
| CN107119280B (en) * | 2016-02-25 | 2020-02-18 | 东莞新科技术研究开发有限公司 | Pad surface treatment method |
| CN111276456A (en) * | 2020-02-18 | 2020-06-12 | 合肥晶合集成电路有限公司 | Semiconductor device and method for manufacturing the same |
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