CN111276456A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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CN111276456A
CN111276456A CN202010099798.5A CN202010099798A CN111276456A CN 111276456 A CN111276456 A CN 111276456A CN 202010099798 A CN202010099798 A CN 202010099798A CN 111276456 A CN111276456 A CN 111276456A
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dielectric layer
hole
semiconductor device
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CN111276456B (en
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翁文杰
王恒
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Nexchip Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions

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  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the semiconductor device comprises the following steps: providing a substrate, wherein a dielectric layer is formed on the substrate; forming a through hole in the dielectric layer; forming an incompletely cured protective layer in the through hole, wherein the protective layer buries the dielectric layer inside; removing a partial thickness of the protective layer by using a solvent so that the top surface of the protective layer does not exceed the top surface of the dielectric layer; forming a groove in the medium layer with partial thickness, wherein the bottom of the groove is communicated with the through hole; and removing the residual protective layer to re-expose the through hole below the bottom of the groove. The technical scheme of the invention shortens the production time of the semiconductor device, thereby reducing the production cost and improving the yield.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to the field of integrated circuit manufacturing, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
In a semiconductor manufacturing process, interconnected vias (Via) and trenches (Trench) are typically formed in a dielectric layer, and then the interconnected vias and trenches are filled with a conductive material to form a conductive interconnect structure. After the through hole is formed and before the groove is formed, in order to avoid that the structure of the through hole is damaged in the process of etching to form the groove, a protective material is filled in the through hole to protect the through hole, and after filling, baking is continuously carried out at the temperature of at least 205 ℃ to completely harden the filled protective material, so that the effect of protecting the through hole is achieved.
When the protective material is filled, in order to ensure that the through hole is completely filled, the height of the filled protective material exceeds the height of the through hole and buries the dielectric layer around the through hole; in addition, in order to avoid the influence of the protective material on the consistency and the flatness of the subsequently formed trench, after the protective material is baked, the protective material with a part of thickness is removed by adopting dry etching, so that the height of the protective material does not exceed the through hole. However, the dry etching of the protective material requires the transfer of the semiconductor product from the process station for filling and baking the protective material to the process station for dry etching, and the etching process is complicated in operation, resulting in a time of at least 44min for the process of removing the protective material of a partial thickness after baking, which in turn results in an increase in the production time of the semiconductor product, an increase in the production cost, and a decrease in the yield.
Therefore, how to improve the production process of the conventional conductive interconnection structure to shorten the production time, thereby reducing the production cost and improving the yield is a problem to be solved.
Disclosure of Invention
The present invention provides a semiconductor device and a method for manufacturing the same, which can shorten the production time of the semiconductor device, and further reduce the production cost and improve the yield.
To achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein a dielectric layer is formed on the substrate;
forming a through hole in the dielectric layer;
forming an incompletely cured protective layer in the through hole, wherein the protective layer buries the dielectric layer inside;
removing a partial thickness of the protective layer by using a solvent so that the top surface of the protective layer does not exceed the top surface of the dielectric layer;
forming a groove in the medium layer with partial thickness, wherein the bottom of the groove is communicated with the through hole; and the number of the first and second groups,
and removing the residual protective layer to re-expose the through hole below the bottom of the groove.
Optionally, an etching barrier layer is further formed between the dielectric layer and the substrate; the dielectric layer comprises a first dielectric layer, a first hard mask layer, a second dielectric layer and a second hard mask layer which are sequentially formed from bottom to top; the step of forming the through hole in the dielectric layer comprises: and etching the second hard mask layer, the second dielectric layer, the first hard mask layer and the first dielectric layer in sequence, and stopping in the etching barrier layer with partial thickness so as to form the through hole in the dielectric layer and the etching barrier layer with partial thickness.
Optionally, the step of forming the incompletely cured protective layer in the through hole includes: firstly, filling a protective material in the through hole, wherein the protective material buries the dielectric layer inside; then, the protective material is baked so that the protective material is partially cured to form the protective layer that is not completely cured.
Optionally, the protective material comprises a polymer.
Optionally, the polymer includes at least one of a methacrylic resin, a silicone-modified acrylate resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester acrylate resin, and a polyether acrylate resin.
Optionally, the baking temperature is 190 ℃ ± 3 ℃.
Optionally, the solvent comprises an organic solvent.
Optionally, the organic solvent includes at least one of propylene glycol, ethylene glycol monoethyl ether, diethylene glycol monoethyl ether, ethylene glycol monoethyl ether acetate, propylene glycol methyl ether, and propylene glycol methyl ether acetate.
Optionally, the step of forming the trench in the partial thickness of the dielectric layer includes: and etching the second hard mask layer, the second dielectric layer and the first hard mask layer on the side wall of the through hole and the protective layer filled in the through hole in part of thickness in sequence so as to form the groove with the bottom communicated with the through hole in the second hard mask layer, the second dielectric layer and the first hard mask layer, and the protective layer protects the through hole below the bottom of the groove from being etched.
Optionally, after removing the remaining protective layer, the method for manufacturing a semiconductor device further includes:
removing the etching barrier layer at the bottom of the through hole; and the number of the first and second groups,
and filling a conductive material in the through hole and the groove to form a conductive interconnection structure.
Optionally, the substrate has an interlayer dielectric layer and a metal line formed in the interlayer dielectric layer, and the conductive interconnection structure is electrically connected to the metal line.
The invention also provides a semiconductor device manufactured by the manufacturing method of the semiconductor device.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. the manufacturing method of the semiconductor device of the invention, through forming the via hole in the dielectric layer on the substrate; forming an incompletely cured protective layer in the through hole, wherein the protective layer buries the dielectric layer inside; removing a partial thickness of the protective layer by using a solvent so that the top surface of the protective layer does not exceed the top surface of the dielectric layer; forming a groove in the medium layer with partial thickness, wherein the bottom of the groove is communicated with the through hole; and removing the remaining protective layer to re-expose the through hole below the bottom of the trench, so that the production time is shortened, the production cost is reduced, and the yield is improved.
2. According to the semiconductor device, the manufacturing method of the semiconductor device provided by the invention is adopted to manufacture the semiconductor device, so that the production time is shortened, the production cost is reduced, and the yield is improved.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2a to 2h are device diagrams in the method of manufacturing the semiconductor device shown in fig. 1.
Wherein, the reference numbers of the attached drawings 1-2 h are explained as follows:
10-a substrate; 11-an interlayer dielectric layer; 12-a metal wire; 13-etching the barrier layer; 14-a dielectric layer; 141-a first dielectric layer; 142-a first hard mask layer; 143-a second dielectric layer; 144-second hard mask layer; 15-a through hole; 16-a protective layer; 17-a trench; 18-conductive interconnect structure.
Detailed Description
In order to make the objects, advantages and features of the present invention more clear, the semiconductor device and the method for manufacturing the same according to the present invention will be further described in detail with reference to the accompanying drawings 1-2 h. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, and referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, the method for manufacturing a semiconductor device including:
step S1, providing a substrate, wherein a dielectric layer is formed on the substrate;
step S2, forming a through hole in the dielectric layer;
step S3, forming a protective layer which is not completely solidified in the through hole, wherein the protective layer buries the dielectric layer inside;
step S4, removing a part of the protective layer with a solvent to ensure that the top surface of the protective layer does not exceed the top surface of the dielectric layer;
step S5, forming a groove in the dielectric layer with partial thickness, wherein the bottom of the groove is communicated with the through hole;
and step S6, removing the residual protective layer to re-expose the through hole below the bottom of the groove.
The method for manufacturing the semiconductor device according to the present embodiment is described in more detail with reference to fig. 2a to 2h, where fig. 2a to 2h are schematic device diagrams in the method for manufacturing the semiconductor device shown in fig. 1, and fig. 2a to 2h are schematic longitudinal cross-sectional views of the device.
Referring to fig. 2a, a substrate 10 is provided, wherein a dielectric layer 14 is formed on the substrate 10, according to step S1. The substrate 10 is provided with an interlayer dielectric layer 11 and a metal wire 12 formed in the interlayer dielectric layer 11, the interlayer dielectric layer 11 plays a role of electric isolation, and the metal wire 12 can be used as a connecting wire of the substrate 10. The substrate 10 also has a structure (not shown) such as a gate, a source region, and a drain region.
An etching barrier layer 13 is further formed between the dielectric layer 14 and the substrate 10, and the etching barrier layer 13 is used for preventing a subsequent etching process from damaging the metal line 12. The material of the etching barrier layer 13 may be nitrogen-doped carbon (NDC) and/or silicon carbide, and the thickness of the etching barrier layer 13 may be
Figure BDA0002386567240000051
It should be noted that the material and the thickness of the etching stop layer 13 are not limited to the above range, and other suitable materials and suitable thicknesses may be selected and adjusted according to the process requirements.
The dielectric layer 14 includes a first dielectric layer 141, a first hard mask layer 142, a second dielectric layer 143, and a second hard mask layer 144 formed in sequence from bottom to top. The first dielectric layer 141 and the second dielectric layer 143 both play a role in electrical isolation, and the first hard mask layer 142 and the second hard mask layer 144 are both mask layers during etching, so that the influence of an etching process on parts, which do not need to be etched, in the first dielectric layer 141 and the second dielectric layer 143 is avoided. The first dielectric layer 141, the first hard mask layer 142, the second dielectric layer 143, and the second hard mask layer 144 may all be formed by a chemical vapor deposition process. The first dielectric layer 141 and the second dielectric layer 143 may be made of at least one of Tetraethylorthosilicate (TEOS), silicon oxide, borosilicate glass (BSG), phosphosilicate glass (PSG), and borophosphosilicate glass (BPSG)The first hard mask layer 142 and the second hard mask layer 144 may be made of silicon nitride and/or silicon oxynitride. The thickness of the first dielectric layer 141 may be
Figure BDA0002386567240000052
The first hard mask layer 142 may have a thickness of
Figure BDA0002386567240000053
The thickness of the second dielectric layer 143 may be
Figure BDA0002386567240000054
The second hard mask layer 144 may have a thickness of
Figure BDA0002386567240000055
It should be noted that the materials and thicknesses of the first dielectric layer 141, the first hard mask layer 142, the second dielectric layer 143, and the second hard mask layer 144 are not limited to the above ranges, and other suitable materials and suitable thicknesses may be selected and adjusted according to the process requirements.
Referring to fig. 2b, a via 15 is formed in the dielectric layer 14, according to step S2. The step of forming the through hole 15 in the dielectric layer 14 includes: and etching the second hard mask layer 144, the second dielectric layer 143, the first hard mask layer 142 and the first dielectric layer 141 in sequence, and stopping in the etching barrier layer 13 with a part of thickness, so as to form the through hole 15 in the dielectric layer 14 and the etching barrier layer 13 with a part of thickness. The etching method can be dry etching; the thickness of the etch stopper layer 13 remaining after the etching process may be
Figure BDA0002386567240000061
The through hole 15 is formed above the metal line 12, and due to the existence of the remaining etching barrier layer 13, the metal line 12 below the through hole 15 is prevented from being influenced by an etching process.
Referring to fig. 2c, according to step S3, a protective layer 16 that is not completely cured is formed in the via hole 15, and the protective layer 16 buries the dielectric layer 14 therein. The step of forming the incompletely cured protective layer 16 in the through hole 15 includes: firstly, filling a protective material in the through hole 15, and burying the dielectric layer 14 by the protective material to ensure that the through hole 15 is filled by the protective material; the protective material is then baked such that the protective material partially cures to form the protective layer 16 that is not fully cured. The incomplete curing of the protective layer 16 enables the protective layer 16 to protect the structure of the through hole 15 below the bottom of the trench 17 from the influence of the etching process when the trench 17 is formed by subsequent etching, and enables the protective layer 16 with a part of thickness to be removed simply and quickly by using a solvent.
The protective material may include a polymer, and the protective material has no photosensitivity; the protective material is in a liquid state at normal temperature, and can be filled in the through hole 15 in a coating manner and can be gradually cured by baking. The polymer may include at least one of a methacrylic resin, a silicone-modified acrylate resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester acrylate resin, and a polyether acrylate resin. The temperature of the baking may be 190 ℃ ± 3 ℃ to partially cure the protective material. It should be noted that the type of the protective material and the baking temperature are not limited to the above ranges, the protective material may be selected according to the process requirements, and the baking temperature may be selected according to the type of the protective material.
Referring to fig. 2d, a portion of the thickness of the protective layer 16 is removed using a solvent so that the top surface of the protective layer 16 does not extend beyond the top surface of the dielectric layer 14, as per step S4. Since the protective layer 16 formed in step S3 buries the dielectric layer 14 therein, that is, the height of the protective layer 16 is higher than that of the through hole 15, which results in unevenness of the surface of the trench 17 formed by subsequent etching and non-uniformity between the trenches 17, it is necessary to remove a part of the thickness of the protective layer 16 so that the top surface of the protective layer 16 does not exceed the top surface of the dielectric layer 14 and the height of the protective layer 16 in each trench 17 is uniform; moreover, when the protective layer 16 needs to be etched to form the trench 17 subsequently, the structure of the through hole 15 below the bottom of the trench 17 is protected from the etching process, and therefore, the top surface of the protective layer 16 is higher than the height of the through hole 15 below the bottom of the trench 17.
The protective layer 16 with partial thickness is removed by the solvent, so that the operation is simple, and a complex dry etching process is not required; moreover, the steps of filling and baking the protective material and removing a portion of the thickness of the protective layer 16 with the solvent can be performed in a tool at the same process station (e.g., using a Track tool), without moving to a different process station for operation. Therefore, the time required for removing a portion of the thickness of the protection layer 16 is greatly reduced, for example, can be reduced to less than 5min, so that the production time of the semiconductor device is shortened, the cost is reduced, and the yield is improved.
The solvent may include an organic solvent, and the organic solvent may include at least one of propylene glycol, ethylene glycol monoethyl ether, diethylene glycol monoethyl ether, ethylene glycol monoethyl ether acetate, propylene glycol methyl ether, and propylene glycol methyl ether acetate. When the organic solvent comprises a mixture of propylene glycol methyl ether and propylene glycol methyl ether acetate, the volume ratio of the propylene glycol methyl ether to the propylene glycol methyl ether acetate can be 5: 3-10: 3. The kind and the ratio of the solvent are not limited to the above ranges, and the kind and the ratio of the solvent may be appropriately selected according to the kind of the protective material.
Referring to fig. 2e, according to step S5, a trench 17 is formed in a partial thickness of the dielectric layer 14, and the bottom of the trench 17 is communicated with the via 15. The step of forming the trench 17 in a partial thickness of the dielectric layer 14 includes: sequentially etching the second hard mask layer 144, the second dielectric layer 143 and the first hard mask layer 142 on the sidewall of the through hole 15 and the protective layer 16 with a partial thickness filled in the through hole 15, so as to form the trench 17 with the bottom communicated with the through hole 15 in the second hard mask layer 144, the second dielectric layer 143 and the first hard mask layer 142, and the protective layer 16 protects the through hole 15 below the bottom of the trench 17 from being etched; the cross-sectional width of the trench 17 is greater than the cross-sectional width of the via 15 below the bottom of the trench 17.
In the process of forming the trench 17, the etching speed of the second hard mask layer 144, the second dielectric layer 143, and the first hard mask layer 142 on the sidewall of the through hole 15 is greater than the etching speed of the protective layer 16 filled in the through hole 15, so that after the trench 17 is formed by etching, the height of the protective layer 16 is not lower than the height of the through hole 15 below the bottom of the trench 17, and the protective layer 16 can protect the through hole 15 below the bottom of the trench 17 from being etched.
In addition, in the process of forming the trench 17, the first dielectric layer 141 with a partial thickness may also be etched, so as to form the trench 17 with a bottom communicated with the through hole 15 in the second hard mask layer 144, the second dielectric layer 143, the first hard mask layer 142, and the first dielectric layer 141 with a partial thickness. That is, the depth of the trench 17 and the via 15 under the bottom of the trench 17 can be controlled by controlling the etching depth of the dielectric layer 14, and the trench 17 and the via 15 under the bottom of the trench 17 can be manufactured to have a proper depth according to the performance requirement of the semiconductor device.
Referring to fig. 2f, in step S6, the remaining protection layer 16 is removed to re-expose the via 15 under the bottom of the trench 17. The remaining protective layer 16 may be removed using the solvent wash; the remaining protective layer 16 may also be removed by using a dry etching process, and since the protective layer 16 and the dielectric layer 14 are made of different materials, the dry etching process for removing the remaining protective layer 16 is different from the etching gas used for forming the trench 17, and the dry etching process for removing the remaining protective layer 16 does not affect the structure of the through hole 15 below the bottom of the trench 17.
In addition, referring to fig. 2g to 2h, after removing the remaining protective layer 16, the method for manufacturing a semiconductor device further includes: as shown in fig. 2g, removing the etching barrier layer 13 at the bottom of the via hole 15; and, as shown in fig. 2h, filling a conductive material in the via 15 and the trench 17 to form a conductive interconnection structure 18, wherein the conductive interconnection structure 18 is electrically connected to the metal line 12.
In summary, the method for manufacturing a semiconductor device provided by the present invention includes: providing a substrate, wherein a dielectric layer is formed on the substrate; forming a through hole in the dielectric layer; forming an incompletely cured protective layer in the through hole, wherein the protective layer buries the dielectric layer inside; removing a partial thickness of the protective layer by using a solvent so that the top surface of the protective layer does not exceed the top surface of the dielectric layer; forming a groove in the medium layer with partial thickness, wherein the bottom of the groove is communicated with the through hole; and removing the residual protective layer to re-expose the through hole below the bottom of the groove. The manufacturing method of the semiconductor device provided by the invention shortens the production time, further reduces the production cost and improves the yield.
An embodiment of the invention provides a semiconductor device, which is manufactured by adopting the manufacturing method of the semiconductor device provided by the invention. According to the above description of steps S1 to S6, since the semiconductor device is manufactured by using the method for manufacturing a semiconductor device provided by the present invention, the production time of the semiconductor device is shortened, and thus the production cost is reduced and the yield is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (12)

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein a dielectric layer is formed on the substrate;
forming a through hole in the dielectric layer;
forming an incompletely cured protective layer in the through hole, wherein the protective layer buries the dielectric layer inside;
removing a partial thickness of the protective layer by using a solvent so that the top surface of the protective layer does not exceed the top surface of the dielectric layer;
forming a groove in the medium layer with partial thickness, wherein the bottom of the groove is communicated with the through hole; and the number of the first and second groups,
and removing the residual protective layer to re-expose the through hole below the bottom of the groove.
2. The method for manufacturing a semiconductor device according to claim 1, wherein an etching stopper layer is further formed between the dielectric layer and the substrate; the dielectric layer comprises a first dielectric layer, a first hard mask layer, a second dielectric layer and a second hard mask layer which are sequentially formed from bottom to top; the step of forming the through hole in the dielectric layer comprises: and etching the second hard mask layer, the second dielectric layer, the first hard mask layer and the first dielectric layer in sequence, and stopping in the etching barrier layer with partial thickness so as to form the through hole in the dielectric layer and the etching barrier layer with partial thickness.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the protective layer that is not completely cured in the through hole includes: firstly, filling a protective material in the through hole, wherein the protective material buries the dielectric layer inside; then, the protective material is baked so that the protective material is partially cured to form the protective layer that is not completely cured.
4. A method for manufacturing a semiconductor device according to claim 3, wherein the protective material comprises a polymer.
5. The method for manufacturing a semiconductor device according to claim 4, wherein the polymer comprises at least one of a methacrylic resin, a silicone-modified acrylate resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester acrylate resin, and a polyether acrylate resin.
6. The manufacturing method of a semiconductor device according to claim 3, wherein the temperature of the baking is 190 ℃ ± 3 ℃.
7. The method for manufacturing a semiconductor device according to claim 1, wherein the solvent comprises an organic solvent.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the organic solvent includes at least one of propylene glycol, ethylene glycol monoethyl ether, diethylene glycol monoethyl ether, ethylene glycol monoethyl ether acetate, propylene glycol methyl ether, and propylene glycol methyl ether acetate.
9. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the trench in a partial thickness of the dielectric layer comprises: and etching the second hard mask layer, the second dielectric layer and the first hard mask layer on the side wall of the through hole and the protective layer filled in the through hole in part of thickness in sequence so as to form the groove with the bottom communicated with the through hole in the second hard mask layer, the second dielectric layer and the first hard mask layer, and the protective layer protects the through hole below the bottom of the groove from being etched.
10. The method for manufacturing a semiconductor device according to claim 2, further comprising, after removing the remaining protective layer:
removing the etching barrier layer at the bottom of the through hole; and the number of the first and second groups,
and filling a conductive material in the through hole and the groove to form a conductive interconnection structure.
11. The method for manufacturing a semiconductor device according to claim 10, wherein the substrate has an interlayer dielectric layer and a metal line formed in the interlayer dielectric layer, and the conductive interconnection structure is electrically connected to the metal line.
12. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 11.
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CN112255884A (en) * 2020-09-27 2021-01-22 合肥晶合集成电路股份有限公司 Method and system for manufacturing photoetching pattern
CN112255884B (en) * 2020-09-27 2024-04-12 合肥晶合集成电路股份有限公司 Method and system for manufacturing photoetching patterns
CN112885778A (en) * 2021-01-19 2021-06-01 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof

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