TW465033B - Dual damascene process of low dielectric constant - Google Patents

Abstract

A dual damascene process of low dielectric constant comprises the following steps. Provide a substrate, deposit a copper diffusion barrier layer on the substrate, and then deposit a first inter-metal dielectric layer on the diffusion barrier layer. Subsequently, cover the first inter-metal dielectric layer sequentially to form an etching stop layer, a second dielectric layer, and a hard mask layer. Then, a first photoresist layer is formed above the hard mask, followed by defining the first photoresist layer. Using the first photoresist layer as the mask and performing a dry etching process. Sequentially etch through the hard mask layer, the second dielectric layer, stop layer, and the first dielectric layer to form an interlayer hole, and then remove the first photoresist layer and the hard mask layer. Above the second dielectric layer and within interlayer hole, a conventional partial solidification or non-solidification spin-on glass is filled as the filler material. Subsequently, perform etch back for the filler material to expose the surfaces of the second inter-metal dielectric layer and the filler material, and deposit an anti-reflection layer thereon. Then, a second photoresist layer is formed above the anti-reflection layer, followed by defining the second photoresist layer. Using the second photoresist layer as the mask to perform a dry etch process, and use the etch stop layer as the etching end to remove partial portion of the surface exposed from the anti-reflection layer and form a groove. Subsequently, remove the second photoresist layer to form an opening of the damascene. Then, along the contour of the damascene opening, forms a barrier layer made of tantalum nitride in conformal fashion that extends to cover the surface of the inter-metal dielectric layer. Lastly, perform a process of manufacturing interconnects.

Description

4 6 5 0 3 3 Five 'invention description (i) 5 _ 1 Field of invention: The present invention relates to a method for manufacturing a semiconductor device with multiple level interconnects (Multi level Interconnects), and more particularly to a low dielectric constant. Method of dual metal inlay (Dual Damascene) process. 5-2 Background of the Invention: Due to the increasing accumulation of semiconductor elements in integrated circuits, the surface of the wafer cannot provide enough area to make the required interconnects in order to match the Metal Oxide Semiconductor M0S) The increased interconnect requirements after the transistor has shrunk. The design of two or more metal layers has gradually become a necessary method for many integrated circuits. In addition, in the deep sub-micron process, due to the increasing enthusiasm of integrated circuits, most of the current use of multi-level interconnects (Multi-level interconnects) three-dimensional structure, and often within the metal dielectric layer (Inter-Metal Dielectric IMD) as a dielectric material to isolate the interconnections of various metals. The wires used to connect the upper and lower metal layers are called Via Plugs in the semiconductor industry. The opening usually formed in the dielectric layer is called a dielectric window (V i a) if the base element in the interconnect is exposed. Therefore, the electrical connections between the two layers of interconnects are made through the metal plugs of the contact window or via window.

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V. Description of the invention (2) Hole and inner two steps The upper element forms a dielectric layer and a dielectric layer. Steps to use as interlayers One of the following 'cause methods' is to form a dielectric (Photoresist; PR) over a metal layer. A deposition method is used on this interlayer window, and then the metal-metal interconnect process is deposited and defined. The internal wiring, so it needs to be tedious in the deep sub-process (Sub-process, because of the multilayer wiring layout (metal interconnection pattern). Learn about the submarine window and layer, then use the deposition conductive layer, and finally use two Sub-micron deposition and quarter Layout) Interlayer interconnections are manufactured at the dielectric layer. The material is engraved with technical materials to complete the redeposition of the dielectric film. The pattern is defined by micron) More complex interconnections are completed, that is, the photoresist layer window. The traditional window and metal are made of the double window. However, it ’s difficult to define a semiconductor system.

Damascene interconnect structure). According to the characteristics of the process, can it be single type, dual type, and self-aligned type. The Damascene method is a method of etching the trenches of the metal interconnects in the dielectric layer, and then filling the metal as the interconnects. This method can make the process of metal interconnects unnecessary. Step, and can introduce metals such as copper that are not easily engraved into semiconductor components. Therefore, this method is the best way to make interconnects in deep sub-microns. The traditional dual metal damascene process includes two pattern definitions. One is the definition of deep patterns, that is, the definition of forming a via hole; the other is

Page 6 46 50. V. Description of the invention (3) Whether it is a shallow pattern definition or a line pattern definition, that is, a definition of forming a groove. Referring to the first figure a, a dielectric layer 12 is first formed on a substrate 10, and then an etch stop layer 14 (Etching stop layer) and a dielectric layer 1 6 are sequentially formed on the dielectric layer 12 » A photoresist layer 18 is formed on the electrical layer 16, and then the photoresist layer 18 defines a region where a deep pattern is to be formed. As shown in FIG. 1B, a deep pattern dry etching process is performed with the photoresist layer 18 as a mask, and the dielectric layer 16, the termination layer 14 and the dielectric layer 12 are sequentially etched through, and a dielectric is formed. Layer hole 20, and then remove the photoresist layer 18. As shown in FIG. 1C, a photoresist layer 2 2 ′ is deposited and formed on the dielectric layer 16, and a portion to be formed with a shallow pattern is defined, so that the photoresist layer 22 exposes the via hole 20 and the dielectric layer. A part of the surface of the electrical layer 16 has a horizontal pattern with a shallow pattern larger than a horizontal pattern with a deep pattern. As shown in the first figure D, a dry pattern dry etching process is performed by using the photoresist layer 22 as a mask, and the etching stop layer 14 is used as an etching end point to remove the exposed portion of the dielectric layer 16 Surface and form another trench 24 with a larger horizontal dimension. As shown in the first E diagram, the photoresist layer 2 2 ′ is removed and the metal mosaic openings 20 and 24 are formed. A process of internal connection can be performed next 'because this process is known to those skilled in the art and does not affect the key points of the present invention, so it will not be described in detail here. The technique of double metal damascene is a technique for forming interlayer windows and interconnects. For the application of the dual metal damascene process, the design of the first integrated circuit of the via is not as sensitive as the self-aligned (S e 1 f-a 1 igned) design. ).

46 50 33 V. Explanation of the invention (4) In addition, when the second photoresist layer is formed, the photoresist will remain in the via hole, and when the second photoresist layer is removed or the photoresist residue is removed, It can also damage the surface of materials with low dielectric constant. In view of the above reasons, we need a new method of dual metal damascene with a low dielectric constant. In order to improve the yield and yield of subsequent processes. 5-3 Objects and Summary of the Invention: In view of the above-mentioned background of the invention, the traditional double metal damascene process has many disadvantages. The present invention provides a method to overcome the problems of the traditional process. The purpose of the present invention is to provide a new integration technology of a dual metal damascene process with low dielectric constant. The present invention utilizes Siloxane or Methyl siloxane as a trench. Fill in (G apfi 1 1) material. Another object of the present invention is to provide a new integration technology of a low-k dielectric double heavy metal damascene process. The present invention can avoid the formation of some photoresist residues on the vias by forming trench filling materials. The formation of trench filling materials can also be used to avoid damage to the low dielectric when removing the photoresist layer and photoresist residues.

46 50 3 3 V. Description of the invention (5) Dielectric layer with coefficient. Therefore, the present invention can effectively improve the yield in the process. A further object of the present invention is to fill the interlayer window with a trench filling material to avoid the bottom of the interlayer window from being over-etched to destroy the region to be conductive. And after the trench is etched, it can be easily performed by dry or wet method. The trench filling material is removed by etching. Therefore, the method of the present invention is simple and economical, and can be applied to deep sub-micron technology. A further object of the present invention is to fill the filler material in the medium by the traditional partial-cured or uncured spin-on g 1 ass (S 0 G) method. In the layer window, to prevent the photoresist layer from contacting the material with low dielectric constant. According to the above-mentioned object, the present invention discloses a new integration technology of a dual metal damascene process with a low dielectric constant. In this embodiment, a substrate is provided, in which a copper conductive layer and a dielectric layer are mixed. First, a copper diffusion barrier layer (Diffusion barrier layer) is deposited on the substrate, and then a first dielectric layer (Inter-metal dielectric) is deposited on the diffusion barrier layer. Then, an etching stop layer (Etching stop layer) and a second dielectric layer are sequentially formed on the first dielectric layer. Secondly, a hard mask is formed on the second dielectric layer. A first photoresist layer is then formed over the hard mask layer, and this first photoresist layer is then used to define a region where a deep pattern is to be formed. Then use the first photoresist layer as a mask to perform a deep pattern dry etching process ’to sequentially etch through the hard mask layer, the second dielectric layer, the termination layer and the first dielectric layer’

Page 9 46503: V. Description of the invention (6) Form a via hole and then remove the first photoresist layer and hard mask layer. A trench filling material is filled above the second dielectric layer and in the dielectric hole. The trench filling material is Si loxane or Methy i si 10 oxane, and It is filled with traditional partially-cured or non-cured spin-on glass (p_s0G), and then the trench filling material is etched back to expose the surface of the second dielectric layer and the trench filling material. In order to prevent the reflection of the surface from affecting the accuracy of the exposure, the anti-reflection coating (ARC) must be covered on the second dielectric layer to facilitate the formation of a primary antibody. Anti-reflective layer (ARL). Generally speaking, those who deposit an anti-reflection layer on a photoresist layer are called top anti-reflection coatings (TARC); those who deposit an anti-reflection layer under a photoresist layer are called bottom anti-reflection coatings. Reflective layer

Bottom anti-reflection coating; TARC). A second photoresist layer is then formed over the anti-reflection layer. Then define this second photoresist layer-the area where the shallow pattern is to be formed, so that the second photoresist layer exposes part of the surface of the via hole and the bottom antireflection layer 'And the horizontal size of the light pattern is larger than the horizontal size of the dark pattern. Then use the second photoresist layer as a mask to perform a dry pattern dry etching process' and use the etch stop layer as the end point of the etching to remove the exposed part of the surface of the anti-reflection layer and form another trench with a larger horizontal size. groove. Then, the groove filling material is removed by wet etching. Wet etching can use an organic organoamine solution or a buffered oxide etching solution. Then, the second photoresist layer is removed, and a damascene opening is formed. A tantalum nitride (TaN) barrier layer is then conformally formed along the contour of the damascene opening.

Page 10 465033 V. Description of the invention (7) '^ and extended to cover the surface of the second dielectric layer β followed by the production of interconnections' First, a copper seed layer (Seed layer) is deposited on tantalum nitride A copper conductive metal layer is formed on the copper seed layer by electro-chemical deposition (ECD) on the barrier layer of (TaN). The existence of the layer, so the metal layer is selectively formed in the opening of the metal insert, and only partially extends to the surface of the dielectric layer. After that, a chemical mechanical polishing (CMP) method is used to perform a planarization process to remove the conductive metal on the second dielectric layer. Next, the barrier layer of nitride nitride is removed, and then the anti-reflection layer is removed. Finally, a copper barrier layer is deposited. 5-4 Detailed description of the invention: A preferred embodiment of the present invention will be described in detail as follows. However, in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments' and the scope of the present invention is not limited. , Which is subject to the scope of subsequent patents. Referring to FIG. 2A, a substrate 200 is provided, in which a dielectric layer 205 and a copper conductive layer 210 are mixed. First, a diffusion barrier layer 22 (diffusion barrier layer) is deposited on the substrate 2000, and then a first dielectric layer (Inter-metal dielectic c) 230 is deposited on the diffusion barrier layer 220. In this embodiment, the preferred composition material of the diffusion barrier layer 220 is

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Any dielectric material that has a barrier ability to copper diffusion, such as gasification broken SiN), silicon carbide (SiC), etc., the preferred composition of the first dielectric layer 23 is a dielectric material with a low dielectric constant, 5。 The material dielectric coefficient of this first dielectric layer 23〇 is less than about 3.5. 1 With reference to FIG. 2B, an etching stop layer (235) and a second dielectric layer (24) are sequentially formed on the first dielectric layer (23). Secondly, a hard mask layer 250 is formed on the second dielectric layer 240. Then, a first photoresist layer 26 is formed over the hard mask layer 250, and then this first photoresist layer 260 is defined as a region to be formed with a deep pattern 'as shown in the second c diagram. Among them, the preferred composition material of the etch stop layer 235 is any material that has a higher etch selection ratio than the material of the second dielectric layer 24, for example, silicon dioxide (S102), silicon nitride (si N ), Silicon carbide (si C), etc., the preferred composition material of the second dielectric layer 240 is a low dielectric constant material '"and the preferred composition material of the hard mask layer 250 is any Compared with the material of the second dielectric layer 240, the material having a higher etching selectivity ratio, for example, silicon dioxide (SiO2), silicon nitride (SiN), silicon carbide (Sic), and the like. The dielectric coefficient of the material of the first " electrical layer 2 4 0 is less than about 3.5. Referring to the second figure D, the first photoresist layer 26o is used as a mask to perform a deep dry etching process, and the hard masking layer 25o, the second dielectric layer 24o, and the termination layer 235 are sequentially etched. And the first dielectric layer 23G, and a dielectric hole 27 is formed. Referring to the second figure E, the first photoresist layer 26 and the hard mask layer 25 are moved.

Page 12 ^ 65033 V. Description of Invention (9) Except. A trench filling material 280 is filled over the second dielectric layer 240 and the dielectric hole 270. The trench filling material is si 10 xane or Methyl sioxane. loxane), and filled with β by conventional partially-cured or non-cured spin-on glass (P-S0G), and then engraved the groove filling material 28, and exposed the second dielectric layer 24 0 and The surface of the trench filling material 280 is shown in FIG. 1F. In order to prevent the reflection of the surface from affecting the precision of the exposure, the anti-reflection coating (ARC) must be covered first. An anti-reflection layer (ARL) 290 is formed on the second dielectric layer 24o to facilitate deposition. In this embodiment, a first photoresist is formed on the anti-reflection layer 29o. Layer 300, and then define the second photoresist layer 300 as a region to be formed with a shallow pattern, so that the second photoresist layer 300 exposes a part of the via 27a and the anti-reflection layer 29G. The horizontal size of the light pattern is larger than the horizontal size of the deep 'Jai. The second photoresist layer 29 is a dry etching process performed on the mask, and the etching stop layer 235 is used as an etching green dot to remove the exposed part of the surface position of the anti-reflection layer 290, and another trench with a larger horizontal size is formed. Then 'remove the trench fill 280 by wet etching. Wet etching can use organic amine aqueous solution (Aque〇us, rganoannne solution) or buffered oxide etching solution (Buffered oxide etching solution) =

Page 13 465033 V. Description of the invention (ίο) Referring to the second figure, the second photoresist layer 300 is removed, and a metal mosaic opening is formed. Then, a barrier layer 310 of a gasification boat (TaN) is conformally deposited along the outline of the metal inlaid opening, and extends to cover the surface of the second dielectric layer 240. Referring to the second figure I, the interconnection process is performed. First, a copper seed layer is deposited on the barrier layer 310 of TaN, which is not shown in the figure. A copper conductive metal layer mo is then formed on the copper seed layer by electrochemical deposition (ECD). The metal layer is selected because of the presence of a seed layer on the sidewall and the bottom of the opening contour of the metal mosaic. It is formed in the opening of the metal inlay, and only partially extends to the surface of the dielectric layer 240. Referring to the second figure J, a planarization process is performed by using a chemical mechanical polish (CMP) method, and the conductive metal layer 320 and the nitride nitride barrier layer 31 on the first dielectric layer 240 are removed. With the anti-reflection layer 290 »Finally, a copper diffusion barrier layer 33 is deposited. In the embodiment of the present invention, 'providing a new integration technology of a low-dielectric double metal inlay process', the present invention avoids the generation of some photoresist residues on the vias of the vias by forming the trench filling material. The formation of the trench filling material can also be used to avoid damaging the low dielectric constant dielectric layer when the photoresist layer and the photoresist residue are removed. Gap filling material (Gap f i 11) can be traditionally partially fixed

Page 14 46 50 3 3 V. Description of the invention (11) Partial-cured or uncured spin-on glass CSpin-glass glass method is filled in the interlayer window. On the other hand, trench filling materials can also be used to fill the interlayer window to prevent the bottom of the interlayer window from being over-etched to destroy the area to be conductive, and the trench filling material can be easily removed by dry or wet etching. ◊ Therefore, the present invention can effectively improve the yield rate in the manufacturing process, so the method of the present invention is simple and economical. For the deep sub-micron process, the integration process of the double metal inlay of the fire ancient soil substrate coefficient. Obviously, according to the description in the above embodiment, the present invention may have many modifications and differences. For this purpose, it is to be understood within the scope of the appended claims. In addition to the foregoing detailed description, the invention is expressly implemented in other embodiments. In broad terms, it is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent; all other equivalent changes or modifications that do not depart from the scope of this disclosure should be included in the following application scope β Yuegegangan 4 6 5 0 3 3 The diagrams briefly illustrate the first A to the first E 圊 are the integration techniques of the traditional traditional low dielectric constant double metal damascene process; and the second A to the second Figure J is a cross-sectional view illustrating a dual-metal damascene process with a low dielectric constant in a preferred embodiment of the present invention. Representative symbols of the main parts: 10 semiconductor substrate 0 12 first dielectric layer 〇 14 contact termination layer 〇 16 second dielectric layer 〇 18 first photoresist layer 〇 20 via hole. 22second photoresist layer 0 24 trench. 200 Semiconductor substrate 0 205 Dielectric layer. 210 metal conductive layer 〇 220 copper diffusion barrier layer. 230 first dielectric layer 〇 235 etch stop layer 0 240 second dielectric layer 〇 250 hard mask layer 260 first photoresist layer 0

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Claims (1)

465033 _ Case No. 89116911_ Amendment Date 6. Application scope 1 _ A dual metal damascene process with low dielectric constant, at least includes the following steps: providing a substrate; forming a barrier layer to cover the substrate; forming a A first dielectric layer covers the barrier layer; a one-stop layer is formed to cover the first dielectric layer; a second dielectric layer is formed to cover the remaining stop layer; a hard mask layer is formed to cover Forming a first photoresist layer on the hard mask layer on the second dielectric layer; defining the first photoresist layer, and performing a dry etching process of the first pattern using the first photoresist layer as a mask, Etch through the hard mask layer, the second dielectric layer, the termination layer and the first dielectric layer in order to form a via hole; remove the first photoresist layer and the hard mask layer; on the second A trench filling material is filled above the dielectric layer and the cavity of the dielectric layer; the trench filling material is etched back to expose the surfaces of the second dielectric layer and the trench filling material; an anti-reflection layer is formed to cover the trench filling material; The second dielectric layer and the surface of the trench filling material are formed on the surface; A second photoresist layer is above the antireflection layer; the second photoresist layer is defined, and a part of the surface of the antireflection layer is exposed, and is larger than the horizontal size of the first pattern; the second photoresist layer Perform a second pattern dry etching process for the mask, and use the etch stop layer as an etching end point to remove the anti-reflection layer. A portion of the surface position of the exposed portion is formed into a trench; d β 5 G 3 3 Case No. 89116911_Year_Month__ VI. Patent application scope Remove the trench filling material; and remove the second photoresist layer, and form a metal inlaid opening. 2. The dual-metal-embedding process with a low dielectric constant as described in item 1 of the scope of the patent application, wherein the dielectric constant of the first dielectric layer is less than about 3.5. 3. The dual-metal-embedding process with a low dielectric constant as described in item 1 of the scope of the patent application, wherein the dielectric constant of the second dielectric layer is less than about 3.5. 4. The dual-metal-embedding process with low dielectric constant as described in item 1 of the scope of the patent application, wherein the trench filling material includes at least Si ioxane or Methyl siloxane. 5. The low-dielectric-constant double metal damascene process as described in item 1 of the scope of the patent application, wherein the filling of the trench filling material is performed by conventional partially-cured or non-cured spin-on glass (P-S0G )law. 6. The dual-metal-embedding process with low dielectric constant as described in item 1 of the scope of patent application, wherein the above-mentioned trench filling material is removed by a wet etching method. 7. Double metal inlay with low dielectric constant as described in item 6 of the scope of patent application Page 19 L Case No. 89116911_ Amendment Date 6. Application for the patented embedded process, where the above wet etching method includes at least an organic amine aqueous solution (Aqueous organoam i ne solution) or a buffered oxide etching solution (Buffered oxide etching) solution). 8. A dual-metal damascene process with a low dielectric constant, including at least the following steps: providing a substrate; forming a first barrier layer overlying the substrate; forming a first dielectric layer overlying the first barrier Layer; forming an etch stop layer to cover the first dielectric layer; forming a second dielectric layer to cover the truncated stop layer; forming a hard masking layer to cover the second dielectric layer; forming A first photoresist layer on the hard mask layer; defining the first photoresist layer, and using the first photoresist layer as a mask to perform a dry etching process of a first pattern, and sequentially etch through the hard mask layer, The second dielectric layer, the termination layer, and the first dielectric layer to form a dielectric hole; removing the first photoresist layer and the hard mask layer; above the second dielectric layer and the dielectric hole A trench filling material is filled therein; the trench filling material is etched back, and the material filling the trench with the second dielectric layer and the trench filling layer is exposed, and the layer frg1 is secondly covered; The material is filled into a trench. The surface is divided into β- Λ ° layers. The upper resistance layer should emit anti-exposure, anti-exposure, and in addition, the layers should block light and light first; the first form surface should be defined. Page 20 46 _'Case No.89116911_Amended in January of the year _ 6. The scope of the patent application is larger than the horizontal size of the first pattern; dry etching of a second pattern is performed using the second photoresist layer as a mask Process, and use the etch stop layer as an etch end point to remove a part of the surface position exposed by the anti-reflection layer and form a trench; remove the trench filling material, remove the second photoresist layer, and form A metal inlaid opening; conformally generating a second barrier layer along the outline of the metal inlaid opening, and extending to cover the surface of the second dielectric layer; forming a seed layer on the second barrier layer Forming a conductive metal layer on the seed layer; performing a planarization process to remove the conductive metal layer on the second dielectric layer; removing the second barrier layer on the second dielectric layer Removing the anti-reflection layer on the second dielectric layer; and forming a third barrier layer on the second dielectric layer and the conductive metal layer 9. The low dielectric as described in item 8 of the scope of patent application Double metal damascene process of electrical coefficient 5。 The dielectric coefficient of the electrical layer is less than about 3.5. 10. The dual-metal-embedding process with a low dielectric constant as described in item 8 of the scope of the patent application, wherein the dielectric constant of the second dielectric layer is less than about 3.5. Page 21 46 5 _Case No. 89H6911_Year Month Amendment_ VI. Patent Application Range 1 1 · Double metal inlaying process with low dielectric constant as described in item 8 of the patent application range, where the above-mentioned groove filling material is at least Contains 5 Xi Xuan (S i 1 ο X ane) or Methyl siloxane. 1 2. The low-dielectric-constant double metal damascene process as described in item 11 of the scope of patent application, wherein the filling of the trench filling material is performed by a conventional partially-cured or non-cured spin-on glass method. 1 3. The dual-metal-embedding process with low dielectric constant as described in item 8 of the scope of the patent application, wherein the above-mentioned trench filling material is removed by a wet etching method. 1 4. The low-dielectric-constant double metal inlaying process as described in item 8 of the scope of the patent application, wherein the above-mentioned wet etching method includes at least an organic amine aqueous solution (Aqueous organoamine solution) or a buffered oxygen solution. Solution (Buffered oxide etching solution) ° Shen Rucheng system inlay. Μ) Ν gold 3 ml heavy C double giant of the number of nitrogen is a layer containing a small amount of dielectric and low barriers to obstructed items 1 6. The dual-metal-embedding process with low dielectric constant as described in item 8 of the scope of the patent application, wherein the seed layer described above includes at least copper (Cu). Page 22_ Case No. 89116911 ± _η Amendment VI. Patent application scope 1 7. The low-dielectric constant double metal damascene process described in item 8 of the patent application scope, wherein the above-mentioned conductive metal layer contains at least copper (Cu ). 18 • The dual-metal-embedding process with low dielectric constant as described in item 8 of the scope of the patent application, wherein the above-mentioned conductive metal layer is formed on the seed layer by an electrochemical deposition method. 1 9. The dual-metal-embedding process with low dielectric constant as described in item 8 of the scope of patent application, wherein the above-mentioned planarization process is performed by a chemical mechanical polishing method. Page 23