A7 B7 ^_I___ 經濟部智慧財產局員工消費合作社印製 565908 7448twf.doc/006 發明說明（I ) 本發明是有關於一種半導體元件之多重內連線（MulU-Level Interconnects)的製造方法，且特別是有關於一種雙 重鑲嵌結構（Dual Damascene)之製造方法。 在半導體製程中，各個元件之連結主要是靠導線，而 導線與積體電路元件之連結部分一般稱爲接觸窗 (Contact)，導線和導線間之連結則稱爲介層窗（Via)。導線 本身的阻値以及導線間的寄生電容大小係爲影響元件速度 的決定性關鍵之一。因此，在半導體製程進入深次微米領 域後，常利用銅取代鋁製作內連線，並配合使用低介電常 數（Low K)材料之金屬間介電層（Inter-Metal Dielectrics， IMD)，以有效降低電阻電容延遲效應（RC Delay)並提升抵 抗電致遷移（Electromigration)之能力。這是由於銅之電致 遷移阻抗値爲鋁之30至100倍，介層窗阻抗値降低10至 20倍，且電阻値降低30%。再者，因爲蝕刻銅是非常不容 易的，所以一般係利用鑲嵌製程取代傳統之導線直接定義 方式來製作銅金屬內連線。 一般的雙重鑲嵌製程包括介層窗自行對準雙重鑲嵌 (Self-Aligned Dual Damascene，SADD)、導線溝渠先定義 雙重鑲嵌（Trench First Dual Damascene，TFDD)、介層窗 先定義雙重鑲嵌（Via First Dual Damascene，VFDD)等方 式。 請參照第1A圖至第IE圖，其係爲習知一種介層窗先 定義雙重鑲嵌結構的製造流程剖面圖。首先，請參照第1A 圖，在已形成有導線102的基底100上依序形成保護層 3 本紙張尺度適用中國國家標準（CNSM4規恪（21〇χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) ·!1 訂—!---•線. A7 B7 565908 74 4 8twf. doc/006 五、發明說明（2) 104、介電層106、蝕刻中止層108、介電層110、頂蓋層 112以及底層抗反射層114。接著，再於底層抗反射層114 上形成正光阻層116,並以微影成像技術圖案化正光阻層 116，以形成開口 117，其係定義出介層窗開口的位置。之 後，以正光阻層116爲罩幕移除部分底層抗反射層114、 頂蓋層112、介電層110、蝕刻中止層108以及介電層106， 以形成暴露保護層104之一介層窗開口 118。 接著，請參照第1B圖，在移除正光阻層116與底層 抗反射層114後，於基底100上形成一層溝塡材料層120 以塡滿介層窗開口 118。之後進行一回蝕製程，移除介層 窗開口 118以外之溝塡材料層120。然後，依序於基底100 上形成底層抗反射層122以及正光阻層124，再以微影成 像技術將正光阻層124圖案化以形成開口 125，用以定義 稍後將形成之溝渠的位置。 接著，請參照第1C圖，以正光阻層124爲罩幕，移 除部分底層抗反射層122、请蓋層112以及介電層110以 形成一溝渠126,同時也會移除部分溝塡材料層120。然 後，再去除正光阻層124以及底層抗反射層122。 接著，請參照第1D圖，在移除溝塡材料層120後， 移除開口 126所裸露之部分蝕刻中止層108以及介層窗開 口 118所裸露之部分保護層104，並暴露出基底.100中之 導線102之表面。 接著，請參照第1E圖，在基底100上先形成一層共 形的阻障層128，再於基底100上形成一層導體層130， 4 _ 本紙張尺度適用中國國家標準（CNS)A4規恪（210 x 297公釐) ~一 " (請先閱讀背面之注意事項再填寫本頁) -·1111111 ^ ·1111111. 經濟部智慧財產局員工消費合作社印製 A7 B7 565908 7448twf.doc/006 五、發明說明（>) 以塡滿介層窗開口 118與溝渠126。之後，再以化學機械 硏磨法進行平坦化，以去除介層窗開口 118與溝渠126以 外之多餘的導體層130與阻障層128。 . 在上述介層窗先定義雙重金屬鑲嵌製程中，需要在介 層窗開口 118中形成一溝塡材料層120以防止正光阻層124 殘留於介層窗開口 118中，進而防止介層窗插塞之阻値與 元件之電阻電容延遲效應因殘留之正光阻而升高。但是， 在線寬緊縮至0.13微米或更小時，塡溝物質即難以塡入高 寬比(Aspect Ratio)大於5的開口。而且，在移除溝塡材料 後，會有部分溝塡材料殘留在介層窗開口 Π8與溝渠126 間之轉角（Corner)上而形成包圍介層窗開口 118之一栅狀 (Fence)結構132，所以在沈積阻障層128時，阻障層128 會被柵狀(Fence)結構截斷而降低其阻障功能，並造成金屬 連線間不當之橋接，甚至使元件失效。 此外，習知技術中定義介層窗開口 118時是以正光阻 層116爲罩幕，直接移除底層抗反射層114、頂蓋層112、 介電層110、蝕刻中止層108以及介電層1〇6直到暴露保 護層104爲止。然而，由於連續蝕刻兩層介電層所需之蝕 刻深度很大，因此正光阻層Π6需要有相當之厚度才能用 來定義介層窗開口 118,而造成光阻之成本增加，且較厚 之正光阻層116也會產生微影製程品質變差以及剝落或掉 落之問題。 此外，習知技術使用之低介電常數材料必須有低於3 之介電常數’例如是氣相沈積尚分子（Vapor-Phase 5 本紙張尺^適用中國國家標準（CNSM4規烙（210 x 297公釐） ------------Aw ---丨！丨訂--------·線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 B7 565908 7 4 4 8twf·doc/006 五、發明說明（Lf )A7 B7 ^ _I ___ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 565908 7448twf.doc / 006 Description of the Invention (I) The present invention relates to a method for manufacturing multiple interconnects (MulU-Level Interconnects) of a semiconductor device, and is particularly It is a manufacturing method of a dual damascene structure. In the semiconductor manufacturing process, the connection of various components is mainly by wires, and the connection between the wires and the integrated circuit components is generally called a contact window, and the connection between the wires and the wires is called a via window. The resistance of the wire itself and the size of the parasitic capacitance between the wires are one of the decisive keys affecting the speed of the component. Therefore, after the semiconductor process enters the deep sub-micron field, copper is often used instead of aluminum to make interconnects, and it is used in conjunction with low-k materials (Inter-Metal Dielectrics, IMD) to Effectively reduce the RC delay effect and improve the ability to resist electromigration. This is because the electrical migration resistance 铜 of copper is 30 to 100 times that of aluminum, the interlayer window resistance 介 is reduced by 10 to 20 times, and the resistance 値 is reduced by 30%. Furthermore, because copper is very difficult to etch, it is common to use a damascene process instead of the traditional direct wire definition method to make copper metal interconnects. A typical dual-damascene process includes Self-Aligned Dual Damascene (SADD), Trench First Dual Damascene (TFDD), and Via First Dual. Damascene, VFDD). Please refer to FIGS. 1A to IE, which are cross-sectional views of a manufacturing process for defining a double-mosaic structure for a conventional interlayer window. First, please refer to Figure 1A, and sequentially form a protective layer 3 on the substrate 100 on which the wires 102 have been formed. This paper size applies Chinese national standards (CNSM4 regulations (21〇χ 297 mm). (Please read the note on the back first) Please fill in this page for more details) ·! 1 Order —! --- • Line. A7 B7 565908 74 4 8twf. Doc / 006 V. Description of the invention (2) 104, dielectric layer 106, etching stop layer 108, dielectric layer 110, the capping layer 112 and the bottom anti-reflection layer 114. Next, a positive photoresist layer 116 is formed on the bottom antireflection layer 114, and the positive photoresist layer 116 is patterned by lithography imaging technology to form an opening 117, which is defined The position of the opening of the dielectric window is then removed. Then, using the positive photoresist layer 116 as a mask, a part of the bottom anti-reflection layer 114, the cap layer 112, the dielectric layer 110, the etching stop layer 108 and the dielectric layer 106 are removed to form an exposure One of the interlayer window openings 118 of the protective layer 104. Next, referring to FIG. 1B, after removing the positive photoresist layer 116 and the bottom anti-reflection layer 114, a trench material layer 120 is formed on the substrate 100 to fill the interlayer window. Opening 118. After that, an etch-back process is performed to remove the interlayer window opening 118 to Trench material layer 120. Then, a bottom anti-reflection layer 122 and a positive photoresist layer 124 are sequentially formed on the substrate 100, and the positive photoresist layer 124 is patterned by lithography imaging technology to form an opening 125, which is used to define later The position of the trench to be formed. Next, referring to FIG. 1C, using the positive photoresist layer 124 as a mask, remove part of the bottom anti-reflection layer 122, the capping layer 112, and the dielectric layer 110 to form a trench 126. Part of the gully material layer 120 will be removed. Then, the positive photoresist layer 124 and the bottom anti-reflection layer 122 are removed. Next, referring to FIG. 1D, after removing the gully material layer 120, remove the exposed part of the opening 126. Part of the etch stop layer 108 and the exposed part of the protective layer 104 exposed through the opening 118 of the via window, and expose the surface of the wire 102 in the substrate 100. Then, referring to FIG. 1E, a conformal layer is first formed on the substrate 100 Barrier layer 128, and then a conductor layer 130 is formed on the substrate 100, 4 _ This paper size applies the Chinese National Standard (CNS) A4 (210 x 297 mm) ~ one " (Please read the precautions on the back first (Fill in this page again)-· 1111111 ^ 1111111. Printed by A7 B7 565908 7448twf.doc / 006 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (>) Filling the interstitial window openings 118 and trenches 126. After that, the chemical mechanical honing method is used The planarization is performed to remove the excess conductive layer 130 and the barrier layer 128 outside the via window 118 and the trench 126. In the above-mentioned interlayer window first-defining dual metal damascene process, a trench material layer 120 needs to be formed in the via window opening 118 to prevent the positive photoresist layer 124 from remaining in the via window opening 118, thereby preventing the via window from being inserted. The resistance of the plug and the delay effect of the resistance and capacitance of the device increase due to the residual positive photoresistance. However, when the line width is narrowed to 0.13 micrometers or less, it is difficult for the trench material to penetrate into the opening having an aspect ratio greater than 5. In addition, after the gully material is removed, a part of the gully material remains on the corner between the interlayer window opening Π8 and the trench 126 to form a fence structure 132 that surrounds the interlayer window opening 118. Therefore, when the barrier layer 128 is deposited, the barrier layer 128 will be truncated by a fence structure to reduce its barrier function, and cause improper bridging between metal connections, and even cause component failure. In addition, in the conventional technology, the opening of the dielectric window 118 is defined by using the positive photoresist layer 116 as a mask, and the bottom anti-reflection layer 114, the capping layer 112, the dielectric layer 110, the etching stop layer 108, and the dielectric layer are directly removed. 106 until the protective layer 104 is exposed. However, due to the large etching depth required to continuously etch the two dielectric layers, the positive photoresist layer Π6 needs to have a considerable thickness to define the opening 118 of the interlayer window, which increases the cost of the photoresist and is thicker. The positive photoresist layer 116 also causes problems such as deterioration in the quality of the lithography process and peeling or dropping. In addition, the low dielectric constant materials used in the conventional technology must have a dielectric constant lower than 3 ', such as Vapor-Phase 5 paper ruler ^ Applicable to Chinese national standards (CNSM4 regulations (210 x 297) Mm) ------------ Aw --- 丨! 丨 Order -------- · Line (Please read the precautions on the back before filling this page) Ministry of Economic Affairs Intellectual Property Printed by the Bureau's Consumer Cooperatives A7 B7 565908 7 4 4 8twf · doc / 006 V. Description of Invention (Lf)
Deposition Polymers，VPDP )、旋塗式介電質（Spin-on Dielectric，SOD)或旋塗式玻璃（Spin-on Glass，SOG)等’ 其緻密性、硬度與機械強度（Mechanical Strength)都較小， 所以在受到應力作用時，容易因爲介層窗開口之存在而造 成介層窗結構之變形(Deformadon)，進而形成薄弱點(Weak Pomt)並造成缺陷，且影響元件良率。 因此，本發明之一目的爲提出一種雙重鑲嵌結構之製 造方法，可以維持可接受的電阻電容延遲(RC Delay)特性， 提升元件效能。 本發明之另一目的爲提出一種雙重鑲嵌結構之製造方 法，可以增加關鍵尺寸（Critical Dimension，CD)的一致性， 並減少光阻之成本及增加製程裕度。 本發明之再一目的爲提出一種雙重鑲嵌結構之製造方 法，可防止介層窗開口之變形。 根據上述目的，本發明提出一種雙重鑲嵌結構之製造 方法，此方法係在已形成一導電層之基底上依序形成一保 護層、一第一介電層、一蝕刻中止層、一第二介電層與作 爲底層抗反射層之一頂蓋層。接著定義頂蓋層與第二介電 層，以形成暴露蝕刻中止層之第一開口，用以定義一介層 窗開口之位置。然後，於頂蓋層上形成具有一第二開口之 一圖案化負光阻層，用以定義一溝渠的位置。接著移除第 二開口所暴露之頂蓋層，並移除第一開口所暴露之蝕刻中 止層，再移除第二開口所暴露之第二介電層以形成一溝 渠，同時移除第一開口所暴露之第一介電層以形成-介層 __ 6 本紙張尺度適用中國國家標準（CNS)A4規恪（210 X 297公堃） ----------------I---訂---------•線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 B7 565908 744 8twf. doc/0 06 五、發明說明（) 窗開口。之後’移除介層窗開口所暴露之保護層。然後移 除負光阻層’再依序於溝渠與介層窗開口內形成一共形的 阻障層以及一導體層，且導體層塡滿溝渠與介層窗開口。 另外，本發明尙可採用先定義介層窗開口之方式，在 已形成導電層之基底上依序形成一第一介電層、一第二介 電層與一底層抗反射層。接著定義底層抗反射層、第二介 电層與弟力笔層以形成暴露導電層之一*介層窗開口。於 底層抗反射層上形成一負光阻層，圖案化該負光阻層以形 成一開口。之後，以負光阻層爲罩幕，移除開口所暴露之 抗反射層與第一介電層以形成暴露第一介電層之一溝渠。 然後移除負光阻層，再於溝渠與介層窗開口內形成共形之 一阻障層及其上之一導體層，且導體層塡滿溝渠與介層窗 開口。 由於本發明係利用負光阻定義溝渠圖案，而在溝渠區 域之未曝光負光阻層可以顯影液移除，所以不會造成光阻 殘留。因此，採用本方法時不需要在介層窗開口中形成溝 塡材料層，即可維持可接受的電阻電容延遲（RC Delay)特 性’同時也因爲不形成溝塡材料層，故不會在介層窗開口 與溝渠之轉角上形成柵狀結構，而可防止金屬連線間不當 之橋接及元件失效。 此外，本發明所提方法之一係利用局部蝕刻製程定義 複合低介電常數材料之雙重鑲嵌結構，並使用抗餓刻能力 比習知技術所使用之正光阻強的負光阻，因此負光阻層之 厚度不需要太厚，而可以增加關鍵尺寸的一致性，並可減 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -· 1 1_1 1 I ·ϋ 1 ϋ 心：04· i-i ϋ ϋ βι ·ϋ ϋ ϋ I · 經濟部智慧財產局員工消費合作社印製 A7 B7 565908 7448twf.doc/006 五、發明說明（€ ) 少成本以及增加製程裕度。而且使用結構較爲緻密之低介 電常數材料作爲雙重金屬鑲嵌結構之介電層，以防止介層 窗開口結構之變形。 另外，直接利用頂蓋層作爲定義介層窗開口以及溝渠 之底層抗反射層，因此不需要另外於頂蓋層上形成底層抗 反射層，可以減少成本。 爲讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A圖至第1E圖爲習知之一種雙重鑲嵌結構之製造 流程剖面圖。 第2A圖與第2F圖是依照本發明一較佳實施例之雙蔞 鑲嵌結構之製造流程剖面圖。 圖式標號之簡單說明： 100、200 :基底 102、202 :導線 104、204 :保護層 108、208 :蝕刻中止層 106、110、206、210 :介電層 112、212 :頂蓋層 114、122 :底層抗反射層 116、 124 ··正光阻層 117、 125、216、218、222、223 :開口 8 本紙張尺度適用中國國家標準（CNS)A4規烙（210 x 297公釐） (請先閱讀背面之注意事項再填寫本頁> 經濟部智慧財產局員工消費合作社印製 -________^----1 — - — ·線 — I-------------- A7 B7 565908 7448twf·doc/006 五、發明說明（η ) 118、219 :介層窗開口 126、223 :溝渠 120 :溝塡材料層 128、224 :阻障層 130、226 ··導體層 132 :柵狀結構 214 :光阻層 220:負光阻層 實施例 本發明較佳實施例之一種雙重鑲嵌結構之製造流程係 以第2A圖至第2F圖來說明。 請參照第2A圖，首先提供一基底200(爲簡化起見， 基底200內之元件並未繪出）。此基底200具有一導線202。 然後，在基底200上依序形成保護層204、介電層206、 蝕刻中止層208、介電層210以及頂蓋層212。 其中，保護層204與蝕刻中止層208之材質例如是氮 化较，其形成方法例如是化學氣相沈積法（Chemical Vapor Deposition，CVD) 〇 介電層206與介電層210之材質例如是低介電常數(介 電常數小於2.6左右）之材質，例如是聚亞芳香基醚（(p〇ly (Arylene Ether)，SiLK)、氟化聚亞芳香基醚（Fiuonirated P〇ly (Arylene Ether)，FLARE)、氫化矽倍半氧化物（HydrogenDeposition Polymers (VPDP), Spin-on Dielectric (SOD), or Spin-on Glass (SOG), etc. 'The density, hardness, and mechanical strength (Mechanical Strength) are small Therefore, when the stress is applied, it is easy to cause the formation of the interlayer window structure due to the existence of the interlayer window opening, thereby forming a weak point (Weak Pomt) and causing defects, and affecting the yield of the device. Therefore, an object of the present invention is to provide a method for manufacturing a dual damascene structure, which can maintain acceptable RC Delay characteristics and improve device performance. Another object of the present invention is to propose a manufacturing method of a dual damascene structure, which can increase the consistency of critical dimensions (CD), reduce the cost of photoresist and increase the process margin. Another object of the present invention is to provide a method for manufacturing a dual mosaic structure, which can prevent the deformation of the opening of the interlayer window. According to the above purpose, the present invention proposes a manufacturing method of a dual damascene structure. This method sequentially forms a protective layer, a first dielectric layer, an etching stop layer, and a second dielectric on a substrate on which a conductive layer has been formed. An electrical layer and a cap layer as one of the underlying anti-reflection layers. Next, a cap layer and a second dielectric layer are defined to form a first opening exposing the etch stop layer, and used to define a position of a dielectric window opening. Then, a patterned negative photoresist layer having a second opening is formed on the top cover layer to define the position of a trench. Then, the cap layer exposed by the second opening is removed, and the etch stop layer exposed by the first opening is removed. Then the second dielectric layer exposed by the second opening is removed to form a trench, and the first is also removed. The first dielectric layer exposed by the opening to form the -dielectric layer__ 6 This paper size applies the Chinese National Standard (CNS) A4 (210 X 297 cm) ------------- --- I --- Order --------- • Line (Please read the precautions on the back before filling out this page) Printed by A7 B7 565908 744 8twf.doc / 0 06 V. Description of the invention () Window opening. After that, the protective layer exposed by the opening of the via is removed. Then, the negative photoresist layer is removed, and a conformal barrier layer and a conductor layer are sequentially formed in the trench and the opening of the via, and the conductive layer fills the trench and the opening of the via. In addition, the present invention can first define a dielectric window opening, and sequentially form a first dielectric layer, a second dielectric layer, and a bottom anti-reflection layer on a substrate on which a conductive layer has been formed. Then define the bottom anti-reflection layer, the second dielectric layer, and the pen layer to form one of the exposed conductive layers * the dielectric window opening. A negative photoresist layer is formed on the bottom anti-reflection layer, and the negative photoresist layer is patterned to form an opening. Then, using the negative photoresist layer as a mask, the anti-reflection layer and the first dielectric layer exposed by the openings are removed to form a trench exposing the first dielectric layer. Then, the negative photoresist layer is removed, and a conformal barrier layer and a conductive layer thereon are formed in the trench and the opening of the via, and the conductive layer fills the trench and the opening of the via. Since the present invention uses a negative photoresist to define the trench pattern, the unexposed negative photoresist layer in the trench area can be removed by the developing solution, so no photoresist will remain. Therefore, when using this method, it is not necessary to form a trench material layer in the opening of the interlayer window, and the acceptable resistance-capacitance delay (RC Delay) characteristic can be maintained. A grid structure is formed on the corner of the window opening and the trench, which can prevent improper bridging between the metal connections and component failure. In addition, one of the methods mentioned in the present invention is to define a dual damascene structure of a composite low-dielectric constant material by using a local etching process, and use a negative photoresistance that is stronger than the positive photoresistance used in the conventional technology. The thickness of the barrier layer does not need to be too thick, but it can increase the consistency of key dimensions, and can be reduced by 7 This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before (Fill in this page)-· 1 1_1 1 I · ϋ 1 ϋ Heart: 04 · ii ϋ ϋ βι · ϋ ϋ ϋ I · Printed by A7 B7 565908 7448twf.doc / 006 of the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs (€) Reduce costs and increase process margin. Furthermore, a low-dielectric constant material with a relatively dense structure is used as the dielectric layer of the double metal damascene structure to prevent the deformation of the dielectric window structure. In addition, the top cap layer is directly used as the bottom anti-reflection layer defining the opening of the via window and the trench. Therefore, there is no need to separately form a bottom anti-reflection layer on the top cap layer, which can reduce costs. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: Figure 1A to FIG. 1E is a cross-sectional view of a conventional manufacturing process of a dual mosaic structure. FIG. 2A and FIG. 2F are cross-sectional views of a manufacturing process of a dual- 蒌 mosaic structure according to a preferred embodiment of the present invention. Brief description of the drawing numbers: 100, 200: substrates 102, 202: wires 104, 204: protective layers 108, 208: etching stop layers 106, 110, 206, 210: dielectric layers 112, 212: cap layers 114, 122: bottom anti-reflection layer 116, 124. · positive photoresist layer 117, 125, 216, 218, 222, 223: opening 8 This paper size applies Chinese National Standard (CNS) A4 (210 x 297 mm) (please Please read the notes on the back before filling in this page> Printed by the Consumer Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs -________ ^ ---- 1 —-— · Line — I ------------- -A7 B7 565908 7448twf · doc / 006 V. Description of the Invention (η) 118, 219: Intermediate window openings 126, 223: Ditch 120: Gully material layer 128, 224: Barrier layer 130, 226 · Conductor layer 132 : Grid structure 214: Photoresist layer 220: Negative photoresist layer Embodiment The manufacturing process of a dual damascene structure according to a preferred embodiment of the present invention is described with reference to Figures 2A to 2F. Please refer to Figure 2A, first A substrate 200 is provided (for simplicity, the components in the substrate 200 are not shown). The substrate 200 has a wire 202. Then, on the substrate 200, The protective layer 204, the dielectric layer 206, the etching stop layer 208, the dielectric layer 210, and the cap layer 212 are sequentially formed. The material of the protective layer 204 and the etching stop layer 208 is, for example, nitride, and the formation method is, for example, chemical Vapor Deposition (CVD). The material of the dielectric layer 206 and the dielectric layer 210 is, for example, a material with a low dielectric constant (dielectric constant less than about 2.6), such as polyarylene ether ((p 〇ly (Arylene Ether), SiLK), fluorinated poly (arylene Ether), FLARE, hydrogenated silicon sesquioxide (Hydrogen
Silsesquioxane，HSQ)等。形成介電層206與介電層210 之方法例如是旋轉塗佈法或化學氣相沈積法。當然，介電 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公窆） ------------Aw ---i — 訂----- - --線 Aw. (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 B7 565908 7448twf·d〇c/006 五、發明說明（§ ) 層206與介電層210之材質也可以是緻密性較上述低介電 常數材質（介電常數小於2·6左右）爲高之低介電常數材料 (介電常數爲3.2至3.6左右)例如是含氟矽玻璃(FluorinatedSilsesquioxane, HSQ) and so on. The method of forming the dielectric layer 206 and the dielectric layer 210 is, for example, a spin coating method or a chemical vapor deposition method. Of course, the paper size of the dielectric paper is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 cm) ------------ Aw --- i — Order ------- -Line Aw. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 565908 7448twf · doc / 006 5. Description of the invention (§) Layer 206 and dielectric layer The material of 210 may also be a low-dielectric constant material (dielectric constant of about 3.2 to 3.6) that is denser than the low-dielectric constant material (dielectric constant less than about 2 · 6), such as fluorine-containing silicon glass ( Fluorinated
Silicate Glass，FSG)或未摻雜矽玻璃（Undoped Silicate Glass，FSG)，形成介電層206與介電層210之方法例如 是電紫增進化學氣相沈積法（Plasma enhanced Chemical Vapor Deposition，PECVD)或高密度電漿化學氣相沈積法 (High Density Plasma Chemical Vapor Deposition > HDPCVD)。上述介電層206與介電層210之材質可爲相同 材質也可爲不同材質，較佳是介電層206之材質的緻密性 較介電層210之材質高，亦即介電層206之機械強度大於 介電層210之機械強度。 另外’頂蓋層212之材質是可作爲光阻層之底層抗反 射材料者，其例如是氮氧化矽（SiON)，而形成頂蓋層212 之方法例如是化學氣相沈積法。 然後，再於頂蓋層212上形成一層光阻層214。此光 阻層214之材質可爲正光阻或負光阻。之後，圖案化光阻 層214以形成一開口 216，用以定義介層窗開口的位置。 接著以光阻層214爲罩幕，移除開口 216所暴露之頂蓋層 212與介電層210以形成暴露部分蝕刻中止層208之一開 □ 218。 請參照第2B圖，之後完全移除掉光阻層214，再於 頂蓋層212上形成一層負光阻層220。之後，圖案化負光 阻層220以形成一開口 222，用以定義溝渠的位置。此處 _____ 10 本紙張尺度適用中國國家標準（CNS)A4規恪（21〇 (請先閱讀背面之注意事項再填寫本頁) • · ϋ ϋ I ϋ I 1 ϋ 一：口- ( ·1 I ϋ n ϋ ϋ n I - 經濟部智慧財產局員工消費合作社印製 297公釐） 565908 A7 B7 7448twf. doc/006 五、發明說明（y) (請先閲讀背面之注意事項再填寫本頁) 之所以使用負光阻的原因如下：因爲正光阻是照光部分產 生分解反應’負先阻是k先P卩分產生鍵結反應，所以使用 正光阻定義溝渠時，在溝渠底部之正光阻可能無法照光分 解，而殘留在介層窗開口底部，因此需要在定義溝渠之前 形成一溝塡材質層塡滿介層窗開Q以防止光阻層殘留。反 之，使用負光阻定義溝渠時，位於溝渠部分之未曝光負光 阻並未鏈結，故可以輕易的以顯影液移除，而不會有部分 負光阻殘留於在介層窗開口中，因此不需要在定義溝渠之 前形成一溝塡材質層塡滿介層窗開口以防止光阻層殘留。 接著，請參照第2C圖，以負光阻層220爲罩幕，移 除開口 222所暴露之部分頂蓋層212以暴露出部分介電層 210，並移除開口 218所暴露之部分蝕刻中止層208以暴 露出部分介電層206。移除部分頂蓋層212以及蝕刻中止 層208之方法例如是非等向蝕刻法。 接著，請參照第2D圖，以負光阻層220爲罩幕，移 除開口 222所暴露之介電層210以形成暴露部分蝕刻中止 層208之溝渠223，並移除開口 218 (第2C圖）所暴露之介 電層206以形成暴露部分保護層204之介層窗開口 219。 經濟部智慧財產局員工消費合作社印製 接著，請參照第2E圖，以負光阻層220爲罩幕，移 除溝渠223所暴露蝕刻中止層208以暴露出部分介電層 2〇6，並移除介層窗開口 219所暴露之保護層204以暴露 出部分導線202。移除部分蝕刻中止層208以及保護層204 之方法例如是非等向飽刻法。 接著，請參照第2F圖，在移除負光阻層220之後， ______11___ 本紙張尺度適用中國國家標準（CNS)A4規烙（2ι〇χ 297公釐） A7 B7 565908 744 8twf. doc/006 五、發明說明（丨D) 在基底200上先形成共形之一層阻障層224。阻障層224 之材質例如是氮化鉅（TaN)、氮化鈦或者鈦矽氮化物。接 著，形成一導體層226於阻障層224上，並塡滿開口 218 與開口 222。形成導體層226之方法例如是物理氣相沈積 法（Physical Vapor Deposition，PVD)、化學氣相沈積法或 濺鍍法。此導體層226例如是銅金屬。 接著，進行化學機械硏磨製程，移除溝渠223以外之 部分金屬層226與阻障層224，直至頂蓋層212暴露出來 爲止，而形成雙重鑲嵌結構。 上述實施例是說明採用局部蝕刻(Partial Etching)製程 定義雙重金屬鑲嵌結構之方式。 另外，本發明尙可採用直接定義介層窗開口之方式， 直接定義底層抗反射層212、介電層210與介電層206以 形成暴露導線202之一介層窗開口 219。然後於底層抗反 射層212上形成一負光阻層220，圖案化負光阻層220以 形成一開口 222。之後，以負光阻層220爲罩幕，移除開 口 222所暴露之底層抗反射層212與介電層210以形成暴 露介電層206之一溝渠223。然後移除負光阻層220，再 於溝渠223與介層窗開口 219內形成共形之一阻障層224 及其上之一導體層226，且導體層226塡滿溝渠223與介 •層窗開口 219。 上述本發明較佳實施例之雙重鑲嵌製程具有下列優 點： (1)利用負光阻定義溝渠圖案，而在溝渠區域之未曝光 12 本紙張尺度適用中國國家標準（CNS)A4規恪（210 x 297公釐） ---- ·!丨丨丨丨訂-丨丨丨丨丨！ · *5^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 B7 565908 7448twf.d〇c/006 五、發明說明（/ /) 負光阻層可以很輕易地以顯影液移除，所以不會有光阻殘 留於介層窗開口中。因此，不需要在介層窗開口中形成溝 塡材料層，即可以維持可接受的電阻電容延遲（RC Delay) 性能，同時也因爲不形成溝塡材料層，故不會在介層窗開 口與溝渠之轉角上形成柵狀結構，而可防止阻障層被柵狀 結構截斷，進而防止金屬連線間不當之橋接及其所導致之 元件失效。 (2) 利用局部蝕刻製程定義複合低介電常數材料之雙重 金屬鑲嵌結構，並使用抗蝕刻能力比正光阻強的負光阻， 因此光阻層之厚度不需要太厚，而可以增加關鍵尺寸的一 致性，同時可減少光阻之成本以及增加製程產能。 (3) 使用結構較爲緻密之低介電常數材料作爲雙重金屬 鑲嵌結構之介電層，以防止介層窗開口結構之變形及損 壞。 (4) 利用頂蓋層作爲定義介層窗開口以及溝渠之抗反射 層，因此不需要另外形成底部抗反射層，可以減少成本。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 13 ------------------ ---訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本纸張尺度適用中國國家標準（CNS)A:1規烙（210 X 297公釐） - ^Silicate Glass (FSG) or Undoped Silicate Glass (FSG) to form the dielectric layer 206 and the dielectric layer 210 is, for example, the Plasma enhanced Chemical Vapor Deposition (PECVD) method. Or high density plasma chemical vapor deposition (High Density Plasma Chemical Vapor Deposition > HDPCVD). The material of the dielectric layer 206 and the dielectric layer 210 may be the same material or different materials. It is preferable that the density of the material of the dielectric layer 206 is higher than that of the dielectric layer 210, that is, the material of the dielectric layer 206 is higher. The mechanical strength is greater than the mechanical strength of the dielectric layer 210. In addition, the material of the top cap layer 212 can be used as a bottom anti-reflective material of the photoresist layer, for example, silicon oxynitride (SiON), and the method of forming the top cap layer 212 is, for example, a chemical vapor deposition method. Then, a photoresist layer 214 is formed on the top cap layer 212. The material of the photoresist layer 214 can be a positive photoresist or a negative photoresist. Thereafter, the photoresist layer 214 is patterned to form an opening 216 for defining the position of the opening of the via window. Next, using the photoresist layer 214 as a mask, the top cap layer 212 and the dielectric layer 210 exposed by the openings 216 are removed to form one of the etching stop layers 208, which are exposed portions 218. Referring to FIG. 2B, the photoresist layer 214 is completely removed, and then a negative photoresist layer 220 is formed on the top cover layer 212. After that, the negative photoresist layer 220 is patterned to form an opening 222 for defining the position of the trench. Here _____ 10 This paper size applies the Chinese National Standard (CNS) A4 (21〇 (Please read the notes on the back before filling out this page) • · · ϋ I ϋ I 1 ϋ One: Mouth-(· 1 I ϋ n ϋ ϋ n I-297 mm printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 565908 A7 B7 7448twf. Doc / 006 V. Description of the invention (y) (Please read the precautions on the back before filling this page) The reason for using negative photoresistors is as follows: because positive photoresistives cause decomposition reactions in the illuminated part, 'negative first resistance is k first and P 卩 components produce bonding reactions, so when using a positive photoresistor to define a trench, the positive photoresistance at the bottom of the trench may not be The light is decomposed and remains at the bottom of the opening of the via. Therefore, a trench material layer needs to be formed before the trench is defined to fill the via window Q to prevent the photoresist layer from remaining. On the other hand, when using a negative photoresistor to define a trench, it is located in the trench. Part of the unexposed negative photoresist is not linked, so it can be easily removed with the developer, and there will be no part of the negative photoresist remaining in the opening of the interlayer window, so there is no need to form a trench before defining the trench. Texture layer The layer window is opened to prevent the photoresist layer from remaining. Next, referring to FIG. 2C, using the negative photoresist layer 220 as a mask, remove a portion of the top cover layer 212 exposed by the opening 222 to expose a portion of the dielectric layer 210, and The portion of the etch stop layer 208 exposed by the opening 218 is removed to expose a portion of the dielectric layer 206. The method of removing a portion of the cap layer 212 and the etch stop layer 208 is, for example, an anisotropic etching method. Next, referring to FIG. 2D, With the negative photoresist layer 220 as a mask, the dielectric layer 210 exposed by the opening 222 is removed to form a trench 223 that exposes the etching stop layer 208, and the dielectric layer 206 exposed by the opening 218 (FIG. 2C) is removed. To form the interstitial window opening 219 that exposes the protective layer 204. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Then, please refer to Figure 2E, using the negative photoresist layer 220 as a mask, and remove the etching stoppage exposed by the trench 223 Layer 208 to expose part of the dielectric layer 206 and remove the protective layer 204 exposed by the dielectric window opening 219 to expose part of the wire 202. The method of removing part of the etch stop layer 208 and the protective layer 204 is, for example, yes or no. Xiang full carved method. Please refer to Figure 2F. After the negative photoresist layer 220 is removed, ______11___ This paper size applies Chinese National Standard (CNS) A4 (2ι〇χ 297 mm) A7 B7 565908 744 8twf. Doc / 006 V. Invention Explanation (丨 D) A conformal barrier layer 224 is first formed on the substrate 200. The material of the barrier layer 224 is, for example, TaN, titanium nitride, or titanium silicon nitride. Next, a conductor layer is formed. 226 is on the barrier layer 224 and fills the openings 218 and 222. The method for forming the conductive layer 226 is, for example, a physical vapor deposition (PVD) method, a chemical vapor deposition method, or a sputtering method. The conductive layer 226 is, for example, copper metal. Then, a chemical mechanical honing process is performed to remove a part of the metal layer 226 and the barrier layer 224 outside the trench 223 until the cap layer 212 is exposed to form a dual damascene structure. The above embodiment is a method for defining a dual metal damascene structure using a partial etch process. In addition, the present invention can directly define the dielectric window opening, and directly define the bottom anti-reflection layer 212, the dielectric layer 210, and the dielectric layer 206 to form a dielectric window opening 219 that is one of the exposed wires 202. A negative photoresist layer 220 is then formed on the bottom anti-reflection layer 212, and the negative photoresist layer 220 is patterned to form an opening 222. After that, using the negative photoresist layer 220 as a mask, the bottom anti-reflection layer 212 and the dielectric layer 210 exposed by the opening 222 are removed to form a trench 223 that exposes the dielectric layer 206. Then, the negative photoresist layer 220 is removed, and a conformal barrier layer 224 and a conductive layer 226 thereon are formed in the trench 223 and the via 219, and the conductive layer 226 covers the trench 223 and the dielectric layer. Window opening 219. The dual inlaying process of the above-mentioned preferred embodiment of the present invention has the following advantages: (1) The trench pattern is defined by using negative photoresistance, and the unexposed in the trench area 12 This paper size applies Chinese National Standard (CNS) A4 (210 x 297 mm) ---- ·! 丨 丨 丨 丨 Order- 丨 丨 丨 丨 丨! * 5 ^ (Please read the notes on the back before filling out this page) Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 565908 7448twf.d〇c / 006 V. Description of the invention (//) The negative photoresist layer can It is easily removed with a developer, so no photoresist will remain in the opening of the via. Therefore, there is no need to form a trench material layer in the opening of the interlayer window, and the acceptable resistance-capacitance delay (RC Delay) performance can be maintained. At the same time, since the trench material layer is not formed, the interlayer window opening and the A grid-like structure is formed on the corner of the trench, which can prevent the barrier layer from being intercepted by the grid-like structure, thereby preventing improper bridging between metal connections and the failure of components caused by it. (2) Use a local etching process to define the dual metal damascene structure of the composite low dielectric constant material, and use a negative photoresistance that is stronger than the positive photoresistance. Therefore, the thickness of the photoresist layer does not need to be too thick, but it can increase the critical size Consistency, while reducing the cost of photoresist and increasing process capacity. (3) Use a relatively low-dielectric constant material with a dense structure as the dielectric layer of the double metal mosaic structure to prevent deformation and damage of the opening structure of the dielectric window. (4) The top cover layer is used as an anti-reflection layer defining the openings of the vias and trenches, so there is no need to form an additional bottom anti-reflection layer, which can reduce costs. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 13 ------------------ --- Order --------- Line (Please read the precautions on the back before filling this page) Ministry of Economic Affairs Intellectual Property The paper size printed by the Bureau's Consumer Cooperatives applies the Chinese National Standard (CNS) A: 1 (210 X 297 mm)-^