510020 7446twf.doc/006 Λ7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（/ ) 本發明是有關於一種半導體元件多重內連線（Multi-Level Interconnects) 的製造方法 ，且特別是有關於一種雙 重鑲嵌結構（Dual Damascene)之製造方法。 在半導體製程中，各個元件之連結主要是靠導線。而 導線與積體電路元件之連結部分一般稱爲接觸窗 (Contact)，導線和導線間之連結部分則稱爲介層窗（via)。 導線本身的阻値以及導線間的寄生電容大小係爲影響元件 速度的決定性關鍵之一。因此，在半導體製程進入深次微 米領域後，常利用銅取代鋁製作內連線，並配合使用低介 電吊數（Low K)材料之金屬間介電層（Inter-Metal Dielectrics)，以有效降低電阻電容延遲效應(RC Delay)並 提升抵抗電致遷移（Electromigration)之能力。這是由於銅 之電致遷移阻抗値爲鋁之30至100倍，介層窗阻抗値降 低10至2 0倍’且電阻値降低3 0 %。再者，因爲触刻銅是 非常不容易的，所以一般係利用鑲嵌製程取代傳統之導線 直接定義方式製作銅金屬內連線。 一般習知的雙重鑲嵌製程包括介層窗自行對準雙重鑲 嵌（Self-Aligned Dual Damascene，SADD)、導線溝渠先定 義雙重鑲嵌（Trench First Dual Damascene，TFDD)、介層 窗先定義雙重鑲嵌(Via First Dual Damascene，VFDD)等方 式。 不論何種方式，在隨著元件集積度增加之趨勢，線寬^ 緊縮至0.13微米或更低時，在維持元件之效能而不改變介 電層厚度之情況下，會使光阻圖案之高寬比(ASpect RatlQ) 3 (請先閱讀背面之注意事項再填寫本頁) · a — — — !— — — — — IIIIIII— — — —--I—--I--1 — 本紙張尺度適用中國國家標準（CNS)A4規恪（210 χ 297公楚） 510020 A7 B7 7 4 4 6twf. doc/0 0 6 五、發明說明（之） 變的很高。高寬比高之光阻圖案則會限制光阻之解析度以 及蝕刻製程。 而且，對於介層窗先定義雙重鑲嵌製程而言，需要在 介層窗開口中形成一溝塡材料層以防止光阻殘留於介層窗 開口中，但是在線寬緊縮至更小時，塡溝物質即難以塡入 高寬比(Aspect Ratio)大於5的開口。而且，在移除溝塡材 料後，也會有部分溝塡材料殘留在介層窗開口與溝渠之轉 角（Corner)並形成包圍介層窗開口之一柵狀（Fence)結構， 而造成金屬連線間不當之橋接，甚至造成元件失效。 此外，想要成功的連續蝕刻兩層很厚的介電層實非易 事，且光阻層之厚度需要有相當之厚度才能完整的定義出 介層窗開口，因而會有使製造成本增加之虞。而較厚之光 阻層也會產生微影蝕刻製程品質變差以及剝落或掉落之問 題。 因此，通常在欲形成雙重鑲嵌結構之介電層上形成一 層氧化矽層作爲罩幕以減低光阻層之厚度。但是，氧化矽 層具有較高的反射率會導致關鍵尺寸（Critical Dimension， CD)値超出範圍。稻此，必須使用一層底層防反射塗佈層 (Bottom Anti-Reflectivity Coating，BARC)降低氧化砂層之 反射率。而且使用厚度越厚之底層防反射塗佈層可越有效 的降低氧化矽層之反射率。由於底層防反射塗佈層在開口 密集區與疏鬆區之厚度會產生落差，而底層防反射塗佈層 之厚度越大，此落差會越大，進而增加顯影後監視以及触 刻後監視（After Etching Inspection，AEI)之偏差，同時也 4 本紙張尺度適用中Θ國家標準（CNS)A4規烙（210 x 297公餐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ------- — 訂---------線----------------------- 510020 經濟部智慧財產局員工消費合作社印製 7446twf.d〇c/〇〇6 五、發明說明（/ 會增強圖案密集區與疏鬆區之間的承載效應（LoacUng510020 7446twf.doc / 006 Λ7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (/) The present invention relates to a method for manufacturing multi-level interconnects of semiconductor devices, and in particular It relates to a method for manufacturing a dual damascene structure. In the semiconductor process, the connection of various components is mainly by wires. The connecting part between the lead and the integrated circuit component is generally called a contact, and the connecting part between the lead and the lead is called a via. The resistance of the wire itself and the size of the parasitic capacitance between the wires are one of the decisive keys affecting the speed of the component. Therefore, after the semiconductor process enters the deep sub-micron field, copper is often used instead of aluminum to make interconnects, and in conjunction with the use of low-k materials (Inter-Metal Dielectrics), to effectively Reduce the RC Delay effect and improve the resistance to Electromigration. This is because the electromigration resistance of copper is 30 to 100 times that of aluminum, the resistance of the interlayer window is reduced by 10 to 20 times' and the resistance is reduced by 30%. Furthermore, because it is not easy to etch copper, it is common to use a damascene process instead of traditional wires to directly define copper metal interconnects. Generally known dual-damascene processes include Self-Aligned Dual Damascene (SADD), Trench First Dual Damascene (TFDD), and Via (via) First Dual Damascene (VFDD). Either way, as the line density of the device increases, the line width ^ shrinks to 0.13 micrometers or less, while maintaining the performance of the device without changing the thickness of the dielectric layer, the photoresist pattern will be high. Aspect Ratio (ASpect RatlQ) 3 (Please read the notes on the back before filling out this page) · a — — —! — — — — — IIIIIII — — — —I — --I--1 — Size of this paper Applicable to China National Standard (CNS) A4 (210 χ 297), 510020 A7 B7 7 4 4 6twf. Doc / 0 0 6 V. The description of the invention (the) has become very high. High aspect ratio photoresist patterns will limit the resolution of the photoresist and the etching process. Moreover, for the first definition of the dual damascene process of the via window, a trench material layer needs to be formed in the via window opening to prevent photoresist from remaining in the via window opening, but the line width is tightened to a smaller value, and the trench material That is, it is difficult to penetrate an opening having an aspect ratio greater than 5. In addition, after the gully material is removed, a part of the gully material will remain at the corner of the interstitial window opening and the trench and form a fence structure surrounding the interstitial window opening, resulting in metal connection. Improper bridging between lines can even cause component failure. In addition, it is not easy to successfully etch two thick dielectric layers in succession, and the thickness of the photoresist layer needs to be considerable to fully define the opening of the dielectric layer window, which will increase the manufacturing cost. Yu. The thicker photoresist layer also causes problems such as deterioration in the quality of the lithography process and peeling or dropping. Therefore, a silicon oxide layer is usually formed on the dielectric layer to form a dual damascene structure as a mask to reduce the thickness of the photoresist layer. However, the high reflectivity of the silicon oxide layer can cause the critical dimension (CD) 値 to be out of range. Therefore, a bottom anti-reflective coating (BARC) must be used to reduce the reflectivity of the oxidized sand layer. Moreover, the thicker the anti-reflection coating, the more effectively the reflectivity of the silicon oxide layer can be reduced. Because the thickness of the bottom anti-reflection coating layer in the open dense area and the loose area will produce a gap, and the larger the thickness of the bottom anti-reflection coating layer, the larger the gap will be, which will increase the monitoring after development and monitoring after etching (After Etching Inspection (AEI), and 4 paper sizes are applicable to Θ National Standard (CNS) A4 Regulation (210 x 297 meals) (Please read the notes on the back before filling this page) Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Employee Consumer Cooperatives --------Order --------- Line ----------------------- 510020 Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Cooperatives 7446twf.d〇c / 〇〇6 V. Description of the invention (/ will enhance the bearing effect between densely patterned areas and loose areas (LoacUng
Effect) ’而使蝕刻效能變差，影響光阻圖案之解析度與聚 焦深度。 ^ 因此’本發明之一目的爲提出一種雙重鑲嵌結構之製 坦$法’於介電層上依序形成一底層防反射塗佈層上與一 層旋塗式介電層作爲蝕刻罩幕，以定義出良好的雙重鑲嵌 結構。 、 本發明之另一目的爲提出一種雙重鑲嵌結構之製造方 法’不需要在介層窗開口中形成一溝塡材料層，可以維持 可接受的電阻電容延遲(RC Delay)性能。 本發明之再一目的爲提出一種雙重鑲嵌結構之製造方 法’可以增加關鍵尺寸的一致性，且光阻層之厚度不需要 太厚’可增加光阻圖案之解析度以及增加製程預度。 根據上述目的’本發明提出一種雙重鑲嵌結構之製造 方法’此方法之步驟如下：首先，在已形成導線之基底上 依序形成一第一介電層、一第二介電層與一底層防反射塗 佈層與一旋塗式介電層。然後，定義旋塗式介電層、底層 防反射塗佈層與第二介電層，以於第二介電層中形成爲一 孔洞’於該旋塗式介電層與該底層防反射塗佈層中形成爲 第溝渠。以旋塗式介電層與底層防反射塗佈層爲罩 幕，移除孔洞所暴露之第一介電層，以形成暴露基底之一 介層窗開口，同時移除第一溝渠所暴露之第二介電層，以 形成暴露第一介電層之一第二溝渠。之後，移除旋塗式介 電層與該底層防反射塗佈層，以及依序於第二溝渠與介層 (請先閱讀背面之注意事項再填寫本頁} 訂----- -----線 —0.-----------------------Effect) ’, which deteriorates the etching performance and affects the resolution and focal depth of the photoresist pattern. ^ Therefore, one of the objectives of the present invention is to propose a method for manufacturing a double-mosaic structure. A bottom anti-reflection coating layer and a spin-on dielectric layer are sequentially formed on the dielectric layer as an etching mask. Define a good dual mosaic structure. Another object of the present invention is to propose a method for manufacturing a dual damascene structure, which does not need to form a trench material layer in the opening of the interlayer window, and can maintain acceptable RC Delay performance. Another object of the present invention is to propose a manufacturing method of a dual damascene structure, which can increase the consistency of key dimensions, and the thickness of the photoresist layer does not need to be too thick. According to the above purpose, the present invention proposes a method for manufacturing a dual damascene structure. The steps of this method are as follows: First, a first dielectric layer, a second dielectric layer, and a bottom layer are sequentially formed on a substrate on which a wire has been formed. A reflective coating layer and a spin-on dielectric layer. Then, a spin-on dielectric layer, a bottom anti-reflection coating layer and a second dielectric layer are defined so as to form a hole in the second dielectric layer. The spin-on dielectric layer and the bottom anti-reflection coating are formed. Formed as a ditch in the distribution layer. Using the spin-on dielectric layer and the bottom anti-reflection coating layer as a mask, the first dielectric layer exposed by the holes is removed to form an opening of a dielectric window that exposes the substrate, and the first exposed by the first trench is removed at the same time. Two dielectric layers to form a second trench exposing one of the first dielectric layers. After that, remove the spin-on dielectric layer and the underlying anti-reflection coating layer, and sequentially on the second trench and the dielectric layer (please read the precautions on the back before filling this page). Order ------ --- line—0 .-----------------------
^ ^ 4 6twf. doc/0 0 6 A7 五、發明說明（Zf ) 窗開口內形成一共形的阻障層以及一導體層，且導體層塡 滿第二溝渠與介層窗開口。 本發明利用於介電層上依序形成一底層防反射塗佈層 上與一層旋塗式介電層。其中，旋塗式介電層可作爲蝕刻 罩幕，而底層防反射塗佈層不但可作爲防反射塗佈層以控 制關鍵尺寸之一致性還可作爲有效的蝕刻罩幕。因此，可 以容易的定義出線寬小於0.1微米以及高寬比大之介層窗 開口或溝渠。 而且，底層防反射塗佈層不會與光阻層混雜 (Intermixed)，可直接先蝕刻旋塗式介電層。雖然底層防反 射塗佈層是形成於旋塗式介電層之下方，當底層防反射塗 佈層具有相當之厚度時，即可有效的降低反射，抑制關鍵 尺寸之變動。 此外，不需要在介層窗開口中形成一溝塡材料層，即 可維持可接受的電阻電容延遲(RC Delay)特性，且光阻層 之厚度不需要太厚，可增加光阻圖案之解析度以及聚焦深 度。 爲讓本發明之：，上述和其他目的、特徵和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第圖至第1H圖爲揭示本發明第一實施例一種雙 重鑲嵌製造流程剖面圖。 第2乂::^_第2H圖爲揭示本發明第二實施例一種雙 (請先閱讀背面之注意事項再填寫本頁) ·---- 經濟部智慧財產局員工消費合作社印製 * I 1 I I I I I I H ϋ I n n ϋ n I I I «I I — — — — —— — — — I.^ ^ 4 6twf. Doc / 0 0 6 A7 V. Description of the Invention (Zf) A conformal barrier layer and a conductor layer are formed in the window opening, and the conductor layer fills the second trench and the interlayer window opening. The present invention utilizes sequentially forming a bottom anti-reflection coating layer and a spin-on dielectric layer on the dielectric layer. Among them, the spin-on dielectric layer can be used as an etching mask, and the bottom anti-reflection coating layer can be used not only as an anti-reflection coating layer to control the consistency of key dimensions, but also as an effective etching mask. Therefore, it is easy to define interstitial window openings or trenches with line widths less than 0.1 micron and large aspect ratios. In addition, the bottom anti-reflection coating layer is not intermixed with the photoresist layer, and the spin-on dielectric layer can be directly etched first. Although the bottom anti-reflection coating layer is formed below the spin-on dielectric layer, when the bottom anti-reflection coating layer has a considerable thickness, the reflection can be effectively reduced, and the change in key dimensions can be suppressed. In addition, it is not necessary to form a trench material layer in the opening of the interlayer window to maintain acceptable RC Delay characteristics, and the thickness of the photoresist layer does not need to be too thick, which can increase the resolution of the photoresist pattern. Degrees and depth of focus. In order to make the present invention: the above and other objects, features, and advantages more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings, as follows: Brief description of the drawings: FIG. FIG. 1 to FIG. 1H are cross-sectional views illustrating a dual damascene manufacturing process according to the first embodiment of the present invention. Chapter 2 :: ^ _ Figure 2H is a pair of revealing a double embodiment of the second embodiment of the present invention (please read the notes on the back before filling out this page) · ---- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * I 1 IIIIIIH ϋ I nn ϋ n III «II — — — — — — — — — I.
本紙張尺度適用中國國家標準（CNS)A:1規恪（210 X 297公餐） 510020 Λ7 B7 7446twf.doc/006 五、發明說明（r) 重鑲嵌結構之製造流程剖面圖。 圖式標號之簡單說明： (請先閱讀背面之注意事項再填寫本頁) 100、200 :基底 102、202 :導線 104、204 :保護層 108、208 :蝕刻中止層 106、110、206、210 :介電層 112、212 :頂蓋層 114、214 :底層防反射塗佈層 116、216 :旋塗式介電層 118、122、218、222 :光阻層 120 、 120a 、 120b 、 120c 、 120d 、 124 、 124a 、 124b 、 220、220a、220b、220c、224a、224b、224c ··開口 126、226 :阻障層 128、228 :導體層 實施例 第一實施例 經濟部智慧財產局員工消費合作社印製 本發明第一實施例之一種雙重鑲嵌結構之製造方法之 示意圖分別以第1A圖至第1H圖來說明。 請參照第1A圖，提供一基底100(爲簡化起見，基底 100內之元件並未繪出）。此基底100具有一導線102。然 後，在基底1〇〇上依序形成保護層104、介電層106、蝕 刻中止層108、介電層110、頂蓋層112、底層防反射塗佈 層114以及旋塗式介電層116。 7 ^紙張尺度適用中國國家標準（CNS)A4規恪（210 x 297公釐) " " " 510020 7446twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（G) 其中，保護層104、蝕刻中止層108與頂蓋層112之 材質例如是氮化矽，形成方法例如是化學氣相沈積法 (Chemical Vapor Deposition，CVD) 〇 介電層106與介電層110之材質例如是低介電常數材 料包括含氟砂玻璃(Fluorinated Silicate Glass ’ FSG)、未摻 雜矽玻璃（Undoped Silicate Glass，USG)、聚亞芳香基醚 ((Poly (Arylene Ether)，SiLK)、氟化聚亞芳香基醚 (Fluonirated Poly (Arylene Ether)，FLARE)與氫化砂倍半 氧化物（Hydrogen Silsesquioxane，HSQ)等。形成介電層 206 與介電層210之方法例如是旋轉塗佈法或化學氣相沈積 法。 底層防反射塗佈層114之材質例如是有機底層防反射 塗膜材質包括聚醯亞胺（Polynmde)。形成底層防反射塗佈 層114之方法例如是旋轉塗佈法。底層防反射塗佈層114 之厚度至少爲1300埃以上。當然，也可以利用不含感光 劑且具有防反射塗膜功用之光阻材料取代底層防反射塗佈 層，例如是I-Line光阻。 旋塗式介電層116之材質例如是旋塗式玻璃（Spin On Glass，SOG)或含矽高分子（矽含量爲丨5%至40%左右）。 形成旋塗式介電層116之方法例如是旋轉塗佈法。旋塗式 介電層116之厚度爲700埃至1600埃左右。 然後’於旋塗式介電層116上形成一層光阻層118。 此光阻層118之材質可爲正光阻或負光阻，厚度爲ι〇〇〇 埃至2500埃左右。之後，圖案化此光阻層118，以形成一 8 (請先閱讀背面之注意事項再填寫本頁) .·—— ϋ 11 ϋ ϋ I n I ϋ I n 11 — — — — — — — — — — — — — — — — — 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公餐） 經濟部智慧財產局員工消費合作社印製 510020 A7 7446twf·d〇c/0〇6 07 五、發明說明（/"/) 開口 120，用以定義介層窗開口的位置。圖案化光阻層118 之方法例如是光微影蝕刻技術。 接著請參照第1B圖，以光阻層11 8爲罩幕，移除開 口 120所暴露之部分旋塗式介電層Η6以形成至少暴露底 層防反射塗佈層114表面之一開口 12〇a。然後移除光阻層 118，以暴露旋塗式介電層116之表面。移除部分旋塗式 介電層116之方法例如是乾式蝕刻法包括反應性離子蝕刻 法。 接著請參照第1C圖，於旋塗式介電層116上形成另 一層光阻層122。此光阻層122之材質可爲正光阻或負光 阻，厚度爲1〇〇〇埃至2500埃左右。之後，圖案化此光阻 層122，以形成至少暴露底層防反射塗佈層114表面之一 開口 124，用以定義溝渠的位置。圖案化光阻層122之方 法例如是光微影蝕刻技術。 接著請參照第1D圖，以光阻層122爲罩幕，移除開 口 120a所暴露之底層防反射塗佈層114與頂蓋層112以 形成暴露出部分介電層110表面之開口 120b。同時’也使 開口 124所暴露之部分旋塗式介電層116厚度變薄。移除 底層防反射塗佈層114以及頂蓋層112之方法例如是乾式 蝕刻法包括反應性離子蝕刻法。 接著請參照第1E圖，以光阻層122爲罩幕，利用頂 蓋112與蝕刻中止層108爲蝕刻終點，移除開口 120b所 暴露之介電層110以形成暴露出部分蝕刻終止層108表面 之開口 120c，以及移除開口 124所暴露之部分旋塗式介電 _______ 9 本紙張尺度適用中國國家標準（CNS)A4規^ (21〇 X 297公餐） -------------·------- 丨訂---------線 (請先閱讀背面之注意事項再填寫本頁) 510020 A7 B7 7446twf.doc/006 五、發明說明（V) 層116與底層防反射塗佈層114以形成暴露出部分頂蓋層 112表面之開口 124c。移除部分旋塗式介電層116、底層 防反射塗佈層Π4與介電層110之方法例如是乾式蝕刻法 包括反應性離子蝕刻法。 接著請參照第1F圖，以光阻層122爲罩幕，移除頂 蓋層112與蝕刻中止層108以暴露出部分介電層110之表 面與部分介電層106之表面。之後，移除光阻層122。 然後以旋塗式介電層116與底層防反射塗膜114爲罩 幕，利用蝕刻中止層108與保護層104爲蝕刻終點，移除 開口 120c所暴露之部分介電層106以形成暴露保護層104 之開口 120d，以及移除開口 124a所暴露之部分介電層110 以形成暴露蝕刻終止層108之開口 124b。其中，開口 120d 是作爲介層窗開口，開口 124b是作爲溝渠。移除介電層110 與介電層106之方法例如是乾式蝕刻法包括反應性離子蝕 刻法。在移除介電層110與介電層106時，也會移除旋塗 式介電層116。 接著，請參照第1G圖，以底層防反射塗佈層114爲 罩幕，移除開口 120d所暴露之保護層104，以及開口 124b 所暴露之蝕刻中止層108。之後移除底層防反射塗佈層 114 〇 然後，在基底100上先形成一層阻障層126，此阻障 層126共形於開口 120d與開口 124b的表面並覆蓋於頂蓋 層112之上。阻障層126之材質例如是氮化钽(TaN)、氮 化鈦或者鈦矽氮化物。接著，形成一導體層128於阻障層 10 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 φί ϋ ·1 ϋ 1 ϋ · ·1 ·1 ·1 ϋ ϋ ϋ 11 線----------------------- 本紙張尺度適用中國國家標準（CNS)Al規格（21〇χ 297公坌） 經濟部智慧財產局員工消費合作社印製 510020 A7 7446twf·d〇c/006 五、發明說明（1) 126上，並塡滿開口 12〇d與開口 124b。形成導體層128 之方法例如是物理氣相沈積法（Physicai Vap〇r Dep〇sitlon， PVD)、化學氣相沈積法或濺鍍法。此導體層128例如是銅 金屬。 接著，請參照第1H圖’進行化學機械硏磨製程，移 除開口 120d與開口 124b以外之部分金屬層128與阻障層 126之化學機械硏磨製程’以去除阻障層126，並暴露出 頂蓋層112之表面，而形成雙重鑲嵌結構。 第二實施例 本發明第二實施例之一種雙重鑲嵌結構之製造方法之 示意圖分別以第2A圖至第2H圖來說明。 請參照第2A圖，提供一基底200(爲簡化起見，基底 200內之元件並未繪出）。此基底200內具有一導線202。 然後，在基底200上依序形成保護層204、介電層206、 蝕刻中止層208、介電層210、頂蓋層212、底層防反射塗 佈層214以及旋塗式介電層216。 其中，保護層204、蝕刻中止層208與頂蓋層212之 材質例如是氮化:砂，形成方法例如是化學氣相沈積法 (Chemical Vapor Deposition，CVD) ° 介電層2〇6與介電層210之材質例如是低介電常數材 料包括含氟矽玻璃、未摻雜矽玻璃、聚亞芳香基醚、氟化 聚亞芳香基醚與氫化矽倍半氧化物等。形成介電層2〇6與 介電層210之方法例如是旋轉塗佈法或化學氣相沈積法。 底層防反射塗佈層214之材質例如是有機底層防反射 11 (請先閱讀背面之注意事項再填寫本頁) ------- —訂---------線- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公餐） 510020 A7 B7 74 46twf. doc/006 五、發明說明UP ) 塗膜材質包括聚醯亞胺。形成底層防反射塗佈層214之方 法例如是旋轉塗佈法。底層防反射塗佈層214之厚度至少 爲1300埃以上。當然，也可以利用不含感光劑且具有防 反射塗膜功用之光阻材質取代底層防反射塗佈層’例如是 I-Line 光阻。 旋塗式介電層216之材質例如是旋塗式玻璃或含矽高 分子，其中含矽高分子之矽含量爲15%至40%左右。形 成旋塗式介電層216之方法例如是旋轉塗佈法。旋塗式介 電層216之厚度爲700埃至1600埃左右。 然後，於旋塗式介電層216上形成一層光阻層218。 此光阻層218之材質可爲正光阻或負光阻，厚度爲1000 埃至2500埃左右。之後，圖案化此光阻層218，以形成一 開口 220，用以定義溝渠的位置。圖案化光阻層218之方 法例如是光微影蝕刻技術。 接著請參照第2B圖，以光阻層218爲罩幕，移除開 口 220所暴露之部分旋塗式介電層216以形成至少暴露底 層防反射塗佈層214表面之一開口 220a。然後移除光阻層 218，以暴露旋塗式介電層216之表面。移除部分旋塗式 介電層216之方法例如是乾式蝕刻法包括反應性離子蝕刻 法。 接著請參照第2C圖，於整個基底200上形成另一層 光阻層222。此光阻層222之材質可爲正光阻或負光阻， 厚度爲1〇〇〇埃至2500埃左右。之後，圖案化此光阻層222， 以形成至少暴露底層防反射塗佈層214表面之一開口 12 本紙張尺度適用中國國家標準（CNS)A4規恪（210 x 297公餐） (請先閱讀背面之注意事項再填寫本頁) -· n ϋ I n ϋ ϋ I 一 δ, I ϋ 1 ϋ n H ϋ ϋ I . 經濟部智慧財產局員工消費合作社印製 510020 7 4 4 6twf·doc/0 0 6 Λ7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（i I) 224，用以定義介層窗開口的位置。圖案化光阻層222之 方法例如是光微影餓刻技術。 接著請參照第2D圖，以光阻層222爲罩幕，移除開 口 224所暴露之底層防反射塗佈層214以及頂蓋層212以 形成暴露出部分介電層210表面之開口 224a。移除部分底 層防反射塗佈層214以及頂蓋層212之方法例如是乾式蝕 刻法包括反應性離子蝕刻法。 接著請參照第2E圖，移除光阻層222後，利用旋塗 式介電層216與底層防反射塗佈層214爲罩幕，以頂蓋層 212與蝕刻中止層208爲蝕刻終點，移除開口 224a所暴露 之介電層210以形成暴露蝕刻中止層208表面之開口 224b，以及移除開口 220a所暴露之底層防反射塗佈層214 以形成暴露頂蓋層212表面之開口 220b。移除部分底層防 反射塗佈層214與介電層210之方法例如是乾式蝕刻法包 括反應性離子蝕刻法。 接著請參照第2F圖，以旋塗式介電層216與底層防 反射塗佈層214爲罩幕，移除頂蓋層212以暴露介電層210 之表面以及移除蝕刻中止層208以暴露介電層206之表 面。 然後’以旋塗式介電層216與底層防反射塗膜214爲 罩幕，利用蝕刻中止層208與保層層204爲蝕刻終點，移 除開口 224b所暴露之介電層206以形成暴露保護層204 之開口 224c，以及移除開口 220b所暴露之介電層210以 形成暴露蝕刻中止層208之開口 220c。其中，開口 224c 13 (請先閱讀背面之注意事項再填寫本頁) · 線· 本紙張尺埂過用宁國國豕標準（CNS)A4規烙（21〇x297公堃） 五 經濟部智慧財產局員工消費合作社印製 510020 A7 7446twf.doc/006 B7 、發明說明（丨之） 是作爲介層窗開口，開口 220c是作爲溝渠。移除介電層210 與介電層206之方法例如是乾式蝕刻法。在移除介電層210 與介電層206時，也會移除旋塗式介電層216。 接著請參照第2G圖，以底層防反射塗佈層114爲罩 幕，移除開口 220c所暴露之蝕刻中止層208與開口 224c 所暴露之保護層204。之後移除底層防反射塗佈層214。 然後在基底200上先形成一層阻障層226，此阻障層 226共形於開口 220c與開口 224c的表面並覆蓋於頂蓋層 212之上。阻障層226之材質例如是氮化鉅(TaN)、氮化鈦 或者鈦矽氮化物。接著，形成一導體層228於阻障層226 上，並塡滿開口 220c與開口 224c。形成導體層228之方 法例如是物理氣相沈積法（Physical Vapor Deposition， PVD)、化學氣相沈積法或濺鍍法。此導體層228例如是銅 金屬。 - 接著，請參照第2H圖，進行化學機械硏磨製程，移 除開口 220c與開口 224c以外之部分金屬層228與阻障層 226，並暴露出頂蓋層212之表面，而形成雙重鑲嵌結構。 根據本發明之較佳實施例，本發明具有下述之優點： (1)於介電層上依序形成一底層防反射塗佈層上與一層 旋塗式介電層。其中，旋塗式介電層作爲蝕刻罩幕，底層 防反射塗佈層不但可作爲防反射塗佈層以控制關鍵尺寸之 一致性還可作爲有效的触刻罩幕。因此，可以容易的定義 出線寬小於0.1微米以及高縱橫尺寸比之介層窗開口或溝 渠0 (請先閱讀背面之注意事項再填寫本頁) .·------- I ^----------------------- 14 510020 A7 —7446tw£·!!!^!_B7___ 五、發明說明（G) (2) 底層防反射塗佈層是形成於旋塗式介電層之下方， 當底層防反射塗佈層具有相當之厚度時，即可有效的降低 反射，抑制關鍵尺寸之變動。且底層防反射塗佈層不會與 光阻層混雜（Intermixed)，可先蝕刻旋塗式介電層。 (3) 不需要在介層窗開口中形成一溝塡材料層，即可維 持可接受的電阻電容延遲（RC Delay)性能。 (4) 底層防反射塗佈層與旋塗式介電層可作爲罩幕，因 此光阻層之厚度不需要太厚，可增加光阻圖案之解析度以 及聚焦深度，進而減少成本以及增加製程產能。 (5) 底層防反射塗佈層、旋塗式介電層以及光阻層是利 用旋轉塗佈的方式形成，可以在同一機台上製作，可增加 之底層防反射塗佈層平坦度，而降低底層防反射塗佈層在 圖案密集區與疏鬆區之間的承載效應。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製This paper size applies the Chinese National Standard (CNS) A: 1 (210 X 297 meals) 510020 Λ7 B7 7446twf.doc / 006 V. Description of the invention (r) Cross-section view of the manufacturing process of the mosaic structure. Brief description of the drawing numbers: (Please read the precautions on the back before filling in this page) 100, 200: Substrate 102, 202: Wire 104, 204: Protective layer 108, 208: Etching stop layer 106, 110, 206, 210 : Dielectric layers 112, 212: Top cap layers 114, 214: Bottom anti-reflection coating layers 116, 216: Spin-on dielectric layers 118, 122, 218, 222: Photoresist layers 120, 120a, 120b, 120c, 120d, 124,124a, 124b, 220,220a, 220b, 220c, 224a, 224b, 224c A schematic diagram of a manufacturing method of a dual-embedded structure printed by a cooperative according to the first embodiment of the present invention is illustrated by FIGS. 1A to 1H, respectively. Referring to FIG. 1A, a substrate 100 is provided (for simplicity, components in the substrate 100 are not shown). The substrate 100 has a conductive line 102. Then, a protective layer 104, a dielectric layer 106, an etching stop layer 108, a dielectric layer 110, a cap layer 112, a bottom anti-reflection coating layer 114, and a spin-on dielectric layer 116 are sequentially formed on the substrate 100. . 7 ^ Paper size applies Chinese National Standard (CNS) A4 (210 x 297 mm) " " " 510020 7446twf.doc / 006 A7 B7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs G) Among them, the material of the protective layer 104, the etching stop layer 108, and the cap layer 112 is, for example, silicon nitride, and the formation method is, for example, Chemical Vapor Deposition (CVD). The dielectric layer 106 and the dielectric layer The material of 110 is, for example, a low-dielectric constant material including Fluorinated Silicate Glass' FSG, Undoped Silicate Glass (USG), Poly (Arylene Ether), SiLK ), Fluorinated Poly (Arylene Ether), FLARE and Hydrogen Silsesquioxane (HSQ), etc. The method of forming the dielectric layer 206 and the dielectric layer 210 is, for example, spin coating Cloth method or chemical vapor deposition method. The material of the bottom anti-reflection coating layer 114 is, for example, an organic bottom anti-reflection coating film material including polyimide. The method of forming the bottom anti-reflection coating layer 114 is, for example, spin coating. Transfer coating method. The thickness of the bottom anti-reflection coating layer 114 is at least 1300 angstroms. Of course, a photoresist material that does not contain a photosensitizer and has an anti-reflection coating function can be used instead of the bottom anti-reflection coating layer. For example, I-Line photoresist. The material of the spin-on dielectric layer 116 is, for example, Spin On Glass (SOG) or a silicon-containing polymer (silicon content is about 5% to 40%). The method of the dielectric layer 116 is, for example, a spin coating method. The thickness of the spin-coated dielectric layer 116 is about 700 to 1600 angstroms. Then, a photoresist layer 118 is formed on the spin-coated dielectric layer 116. This light The material of the resist layer 118 may be a positive or negative photoresistor, and the thickness is about 2500 angstroms to about 2500 angstroms. Then, the photoresist layer 118 is patterned to form an 8 (please read the precautions on the back before filling (This page). · —— ϋ 11 ϋ ϋ I n I ϋ I n 11 — — — — — — — — — — — — — — — This paper size applies the Chinese National Standard (CNS) A4 specification (21〇 X 297 Meal) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 510020 A7 7446twf · d〇 c / 0〇6 07 V. Description of the Invention (" /) The opening 120 is used to define the position of the opening of the via. A method of patterning the photoresist layer 118 is, for example, a photolithography technique. Next, referring to FIG. 1B, using the photoresist layer 118 as a mask, the part of the spin-on dielectric layer Η6 exposed by the opening 120 is removed to form at least one opening 12a that exposes the surface of the bottom anti-reflective coating layer 114. . The photoresist layer 118 is then removed to expose the surface of the spin-on dielectric layer 116. A method of removing a part of the spin-on-type dielectric layer 116 is, for example, a dry etching method including a reactive ion etching method. Next, referring to FIG. 1C, another photoresist layer 122 is formed on the spin-on dielectric layer 116. The material of the photoresist layer 122 can be a positive photoresist or a negative photoresist, and the thickness is about 1000 Angstroms to about 2500 Angstroms. Thereafter, the photoresist layer 122 is patterned to form at least one opening 124 that exposes the surface of the bottom anti-reflection coating layer 114 to define the location of the trench. The method of patterning the photoresist layer 122 is, for example, a photolithography technique. Next, referring to FIG. 1D, using the photoresist layer 122 as a mask, the bottom anti-reflection coating layer 114 and the cap layer 112 exposed by the opening 120a are removed to form an opening 120b that exposes part of the surface of the dielectric layer 110. At the same time, the thickness of the spin-on dielectric layer 116 exposed by the opening 124 is also reduced. The method of removing the bottom anti-reflection coating layer 114 and the cap layer 112 is, for example, a dry etching method including a reactive ion etching method. Next, referring to FIG. 1E, the photoresist layer 122 is used as the cover, the top cover 112 and the etching stop layer 108 are used as the end point of the etching, and the dielectric layer 110 exposed by the opening 120b is removed to form an exposed part of the surface of the etching stop layer 108. The opening 120c of the opening, and the part of the spin-coated dielectric exposed by removing the opening 124 _______ 9 This paper size applies the Chinese National Standard (CNS) A4 ^ (21〇X 297 meals) -------- ----- · ------- 丨 Order --------- Line (Please read the precautions on the back before filling this page) 510020 A7 B7 7446twf.doc / 006 V. Description of the invention The (V) layer 116 and the bottom anti-reflection coating layer 114 form an opening 124 c that exposes a part of the surface of the top cover layer 112. The method of removing part of the spin-on dielectric layer 116, the underlying anti-reflection coating layer Π4, and the dielectric layer 110 is, for example, a dry etching method including a reactive ion etching method. Next, referring to FIG. 1F, with the photoresist layer 122 as a mask, the top cover layer 112 and the etching stop layer 108 are removed to expose a portion of the surface of the dielectric layer 110 and a portion of the surface of the dielectric layer 106. After that, the photoresist layer 122 is removed. Then, the spin-on dielectric layer 116 and the bottom anti-reflection coating film 114 are used as a mask, and the etching stop layer 108 and the protective layer 104 are used as the end point of the etching. Then, a part of the dielectric layer 106 exposed by the opening 120c is removed to form an exposed protective layer The opening 120d of 104 and the portion of the dielectric layer 110 exposed by the opening 124a are removed to form an opening 124b that exposes the etch stop layer 108. Among them, the opening 120d is used as an interlayer window opening, and the opening 124b is used as a trench. The method of removing the dielectric layer 110 and the dielectric layer 106 is, for example, a dry etching method including a reactive ion etching method. When the dielectric layer 110 and the dielectric layer 106 are removed, the spin-on dielectric layer 116 is also removed. Next, referring to FIG. 1G, using the bottom anti-reflection coating layer 114 as a mask, the protective layer 104 exposed by the opening 120d and the etching stop layer 108 exposed by the opening 124b are removed. After that, the bottom anti-reflection coating layer 114 is removed. Then, a barrier layer 126 is formed on the substrate 100. The barrier layer 126 is conformally formed on the surfaces of the opening 120d and the opening 124b and covers the top cover layer 112. The material of the barrier layer 126 is, for example, tantalum nitride (TaN), titanium nitride, or titanium silicon nitride. Next, a conductor layer 128 is formed on the barrier layer 10 (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ϋ ϋ 11 lines ----------------------- This paper size applies to China National Standard (CNS) Al specification (21〇χ 297 cm) Wisdom of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Property Bureau 510020 A7 7446twf · doc / 006 V. Description of the invention (1) 126, and filled the opening 120d and 124b. The method for forming the conductive layer 128 is, for example, a physical vapor deposition method (Physicai Vapor Dep Sitlon (PVD)), a chemical vapor deposition method, or a sputtering method. This conductive layer 128 is, for example, copper metal. Next, please refer to FIG. 1H 'Chemical mechanical honing process, remove part of metal layer 128 and barrier layer 126 except for opening 120d and opening 124b by chemical mechanical honing process' to remove barrier layer 126 and expose The surface of the top cover layer 112 forms a double mosaic structure. Second Embodiment A schematic diagram of a method for manufacturing a dual inlaid structure according to a second embodiment of the present invention will be described with reference to Figs. 2A to 2H, respectively. Referring to FIG. 2A, a substrate 200 is provided (for simplicity, components in the substrate 200 are not shown). The substrate 200 has a conductive wire 202 therein. Then, a protective layer 204, a dielectric layer 206, an etching stop layer 208, a dielectric layer 210, a cap layer 212, a bottom anti-reflection coating layer 214, and a spin-on dielectric layer 216 are sequentially formed on the substrate 200. Among them, the material of the protective layer 204, the etching stop layer 208, and the cap layer 212 is, for example, nitride: sand, and the formation method is, for example, Chemical Vapor Deposition (CVD) ° Dielectric layer 206 and dielectric The material of the layer 210 is, for example, a low-dielectric constant material including fluorine-containing silica glass, undoped silica glass, polyarylene ether, fluorinated polyarylene ether, and hydrogenated silicon sesquioxide. A method of forming the dielectric layer 206 and the dielectric layer 210 is, for example, a spin coating method or a chemical vapor deposition method. The material of the bottom anti-reflection coating layer 214 is, for example, an organic bottom anti-reflection 11 (Please read the precautions on the back before filling in this page) ------- --Order --------- Line-This The paper size applies the Chinese National Standard (CNS) A4 specification (21 × X 297 meals) 510020 A7 B7 74 46twf. Doc / 006 5. Description of the invention UP) The material of the coating film includes polyimide. A method of forming the bottom anti-reflection coating layer 214 is, for example, a spin coating method. The thickness of the bottom anti-reflection coating layer 214 is at least 1300 angstroms or more. Of course, a photoresist material that does not contain a photosensitizer and has an anti-reflection coating function can be used instead of the bottom anti-reflection coating layer, such as an I-Line photoresist. The material of the spin-on dielectric layer 216 is, for example, spin-on glass or a silicon-containing polymer, and the silicon content of the silicon-containing polymer is about 15% to 40%. A method of forming the spin-on dielectric layer 216 is, for example, a spin coating method. The spin-on dielectric layer 216 has a thickness of about 700 Angstroms to about 1600 Angstroms. Then, a photoresist layer 218 is formed on the spin-on dielectric layer 216. The material of the photoresist layer 218 can be a positive photoresist or a negative photoresist, and the thickness is about 1000 Angstroms to 2500 Angstroms. After that, the photoresist layer 218 is patterned to form an opening 220 for defining the position of the trench. A method of patterning the photoresist layer 218 is, for example, a photolithography technique. Next, referring to FIG. 2B, using the photoresist layer 218 as a mask, a part of the spin-on dielectric layer 216 exposed by the opening 220 is removed to form at least one opening 220a that exposes the surface of the bottom anti-reflection coating layer 214. The photoresist layer 218 is then removed to expose the surface of the spin-on dielectric layer 216. A method of removing a part of the spin-on-type dielectric layer 216 is, for example, a dry etching method including a reactive ion etching method. Referring to FIG. 2C, another photoresist layer 222 is formed on the entire substrate 200. The material of the photoresist layer 222 can be a positive photoresist or a negative photoresist, and the thickness is about 1000 Angstroms to about 2500 Angstroms. Afterwards, the photoresist layer 222 is patterned to form an opening that exposes at least one of the surfaces of the bottom anti-reflection coating layer 214. 12 This paper size is in compliance with Chinese National Standard (CNS) A4 (210 x 297 meals) (Please read first Note on the back page, please fill in this page)-· n ϋ I n ϋ ϋ I-δ, I ϋ 1 ϋ n H ϋ ϋ I. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 520020 7 4 4 6twf · doc / 0 0 6 Λ7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of Invention (i I) 224, which is used to define the position of the interstitial window opening. The method of patterning the photoresist layer 222 is, for example, a photolithography technique. Referring to FIG. 2D, the photoresist layer 222 is used as a mask, and the bottom anti-reflection coating layer 214 and the cap layer 212 exposed by the opening 224 are removed to form an opening 224a that exposes part of the surface of the dielectric layer 210. A method of removing a part of the bottom anti-reflection coating layer 214 and the cap layer 212 is, for example, a dry etching method including a reactive ion etching method. Referring to FIG. 2E, after the photoresist layer 222 is removed, the spin-on dielectric layer 216 and the bottom anti-reflection coating layer 214 are used as a mask, and the top cap layer 212 and the etching stop layer 208 are used as the etching end point. The dielectric layer 210 exposed by the opening 224a is removed to form an opening 224b that exposes the surface of the etch stop layer 208, and the bottom anti-reflection coating layer 214 exposed by the opening 220a is formed to form an opening 220b that exposes the surface of the cap layer 212. A method of removing a part of the underlying anti-reflection coating layer 214 and the dielectric layer 210 is, for example, a dry etching method including a reactive ion etching method. Referring to FIG. 2F, using the spin-on dielectric layer 216 and the bottom anti-reflection coating layer 214 as a mask, the top cover layer 212 is removed to expose the surface of the dielectric layer 210 and the etching stop layer 208 is removed to expose The surface of the dielectric layer 206. Then, using the spin-on dielectric layer 216 and the bottom anti-reflection coating film 214 as the mask, the etching stop layer 208 and the protective layer 204 are used as the etching end point, and the dielectric layer 206 exposed by the opening 224b is removed to form an exposure protection. The opening 224c of the layer 204 and the dielectric layer 210 exposed by the opening 220b are removed to form an opening 220c that exposes the etch stop layer 208. Among them, the opening 224c 13 (please read the precautions on the back before filling in this page) · Thread · This paper has been sized using the Ning Guoguo Standard (CNS) A4 Standard (21〇x297 cm) Five Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperative, 512020 A7 7446twf.doc / 006 B7, the description of the invention (丨 zhi) is used as an interlayer window opening, and the opening 220c is used as a trench. A method of removing the dielectric layer 210 and the dielectric layer 206 is, for example, a dry etching method. When the dielectric layer 210 and the dielectric layer 206 are removed, the spin-on dielectric layer 216 is also removed. Next, referring to FIG. 2G, using the bottom anti-reflection coating layer 114 as a mask, the etching stop layer 208 exposed by the opening 220c and the protective layer 204 exposed by the opening 224c are removed. The bottom anti-reflection coating layer 214 is then removed. Then, a barrier layer 226 is formed on the substrate 200, and the barrier layer 226 is conformally formed on the surfaces of the openings 220c and 224c and covers the top cover layer 212. The material of the barrier layer 226 is, for example, TaN, titanium nitride, or titanium silicon nitride. Next, a conductive layer 228 is formed on the barrier layer 226 and fills the openings 220c and 224c. The method for forming the conductor layer 228 is, for example, a physical vapor deposition (PVD) method, a chemical vapor deposition method, or a sputtering method. This conductive layer 228 is, for example, copper metal. -Next, please refer to Figure 2H, perform a chemical mechanical honing process, remove part of the metal layer 228 and the barrier layer 226 outside the openings 220c and 224c, and expose the surface of the top cover layer 212 to form a dual mosaic structure . According to a preferred embodiment of the present invention, the present invention has the following advantages: (1) A bottom anti-reflection coating layer and a spin-on dielectric layer are sequentially formed on the dielectric layer. Among them, the spin-on dielectric layer is used as an etching mask, and the bottom anti-reflection coating layer can be used not only as an anti-reflection coating layer to control the consistency of key dimensions, but also as an effective touch-etching mask. Therefore, it is easy to define interstitial window openings or trenches with a line width of less than 0.1 micron and a high aspect ratio 0 (please read the precautions on the back before filling this page). · ------- I ^- ---------------------- 14 510020 A7 —7446tw £ · !!! ^! _ B7___ V. Description of the invention (G) (2) Anti-reflection coating on the bottom layer The layer is formed below the spin-coating dielectric layer. When the underlying anti-reflection coating layer has a considerable thickness, it can effectively reduce reflections and suppress changes in key dimensions. In addition, the bottom anti-reflection coating layer is not intermixed with the photoresist layer, and a spin-on dielectric layer may be etched first. (3) It is not necessary to form a trench material layer in the opening of the interlayer window to maintain acceptable RC Delay performance. (4) The bottom anti-reflection coating layer and spin-on dielectric layer can be used as a mask, so the thickness of the photoresist layer does not need to be too thick, which can increase the resolution and focus depth of the photoresist pattern, thereby reducing costs and increasing the manufacturing process. Capacity. (5) The bottom anti-reflection coating layer, spin-coating dielectric layer and photoresist layer are formed by spin coating, which can be made on the same machine, which can increase the flatness of the bottom anti-reflection coating layer, and Reduce the bearing effect of the bottom anti-reflection coating layer between the dense pattern area and the loose area. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
····丨丨 I I ϋ n n .^β ϋ 1 n ϋ ·1 I 1 · -I .1 ϋ n n 1· ϋ n ϋ ϋ H -ϋ n ϋ 1 ί I 本紙張尺度適用中國國家標準（CNS)A4規烙（210 X 297公餐)···· 丨 丨 II ϋ nn. ^ Β ϋ 1 n ϋ · 1 I 1 · -I .1 nn nn 1 · ϋ n ϋ ϋ H -ϋ n ϋ 1 ί I This paper standard applies to the Chinese National Standard (CNS ) A4 gauge (210 X 297 meals)