CN102543844B - Method for manufacturing semiconductor device structure and semiconductor device structure - Google Patents
Method for manufacturing semiconductor device structure and semiconductor device structure Download PDFInfo
- Publication number
- CN102543844B CN102543844B CN201010615184.4A CN201010615184A CN102543844B CN 102543844 B CN102543844 B CN 102543844B CN 201010615184 A CN201010615184 A CN 201010615184A CN 102543844 B CN102543844 B CN 102543844B
- Authority
- CN
- China
- Prior art keywords
- layer
- mask layer
- semiconductor device
- reative cell
- interlayer dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a method for manufacturing a semiconductor device structure. The method comprises the following steps of: a) providing a front end device layer structure; b) forming an interlayer dielectric layer with an ultralow dielectric constant on the surface of the front end device layer structure in a first reaction chamber, wherein the interlayer dielectric layer with the ultralow dielectric constant is formed by reaction gas containing methyldiethoxysilane; and c) forming a methyldiethoxysilane mask layer on the surface of the interlayer dielectric layer with the ultralow dielectric constant by a plasma enhanced chemical vapor deposition method in a second reaction chamber. By the method, the conventional process is simplified, mass production of the semiconductor device structure is facilitated, the manufacturing time of the semiconductor device structure is shortened, and the production efficiency of the semiconductor device structure is improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly, the present invention relates to a kind of method and semiconductor device structure of manufacturing semiconductor device structure.
Background technology
Along with the development of integrated circuit technique, interconnected resistance capacitance (RC) postpones progressively to increase.Postpone and improve the performance of semiconductor device in order to reduce RC, conventionally in the dielectric materials layer between semiconductor, extensively adopt low-k (k) material.But, along with constantly reducing and the continuous increase of metal connecting line depth-width ratio of characteristic size, and the increasing of the interlayer parasitic capacitance that causes of number of plies increase, often cause the fast rise of interconnection capacitance and produce extra interconnect delay, affect the raising of circuit speed.Therefore, adopt at present extensively super low-k materials replacement low-k materials as interlayer dielectric layer to improve the performance of semiconductor device.
28 or 32nm semiconductor technology in, to make through hole or contact hole as example on semiconductor device structure.First,, in the first reative cell, there is the interlayer dielectric layer of ultralow dielectric constant layer in the superficial growth of front end device layer structure; Then, above-mentioned front end device layer structure is shifted out from the first reative cell, deliver in the second reative cell with the superficial growth mask layer at above-mentioned interlayer dielectric layer, for improving the critical size after adhesion and the etching between thin layer, the material of described mask layer typically is prestox cyclisation tetrasiloxane (OMCTS, [(CH
3)
2-Si-O]
4); Finally, etching forms through hole or contact hole.
But, because the formation material of interlayer dielectric layer and mask layer is different, if therefore will grow interlayer dielectric layer and mask layer in same reative cell, just need to, after the interlayer dielectric layer of having grown, reative cell be cleaned, so not only increased the process time, make to produce complicated, also can affect the speed of batch production, and the effect of cleaning is likely undesirable, thereby cause respectively structure layer by layer of contaminate subsequent, and then affect wafer quality.Therefore, the most frequently used method is in the above-mentioned layer of different reaction indoor growings structure at present, but need between different reative cells, transport wafer so again, this just may pollute wafer, cause the decline of electric property, and may cause increasing flow time, the increase production cost of whole technique and reduce production efficiency.
Therefore, be necessary the method for existing manufacture semiconductor device structure to improve, with in the situation that not increasing whole process complexity, can avoid wafer contamination, can shorten the process time again, enhance productivity.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to address the above problem, make to shorten the process time and enhance productivity, the invention provides a kind of method of manufacturing semiconductor device structure, comprising:
A) provide front end device layer structure;
B) in the first reative cell, form the interlayer dielectric layer with ultralow dielectric on the surface of described front end device layer structure, wherein, described in there is ultralow dielectric interlayer dielectric layer formed by the reacting gas that comprises methyldiethoxysilane; And
C), in the second reative cell, form methyldiethoxysilane mask layer on the surface of the described interlayer dielectric layer with ultralow dielectric by plasma enhanced chemical vapor deposition method.
Further, described reacting gas also comprises terpinene or bicycloheptadiene.
Further, described the first reative cell and described the second reative cell are same reative cell.
Further, the thickness of described methyldiethoxysilane mask layer is 100 ~ 500 dusts.
Further, the pressure of step c) is 2 ~ 8Torr.
Further, the power of step c) is 300 ~ 1000W.
Further, the temperature of step c) is 200 ~ 300 degrees Celsius.
Further, the intake of the described methyldiethoxysilane of step c) is 500 ~ 3000mg/min.
Further, described method also comprises:
D) form tetraethoxysilane mask layer on the surface of described methyldiethoxysilane mask layer; With
E) form titanium nitride mask layer on the surface of described tetraethoxysilane mask layer.
Further, described method also comprises:
D) in the 3rd reative cell, pass into oxygen, form silicon dioxide layer with the surface at described methyldiethoxysilane mask layer;
E) form tetraethoxysilane mask layer on the surface of described silicon dioxide layer; With
F) form titanium nitride mask layer on the surface of described tetraethoxysilane mask layer.
Further, the flow of described oxygen is 100 ~ 500sccm.
The present invention also provides a kind of semiconductor device structure, and described semiconductor device structure is made up of above-mentioned arbitrary described method.
In sum, the invention provides a kind of method and semiconductor device structure obtained by this method of new manufacture semiconductor device structure, this device architecture has function and the effect suitable with existing device architecture; Secondly, manufacture method of the present invention can form in same reative cell has the interlayer dielectric layer of ultralow dielectric and the mask layer being located thereon, therefore, simplify existing technique, be conducive to the batch production of semiconductor device structure, and, the Production Time of having reduced semiconductor device structure, improve the production efficiency of semiconductor device structure, can also avoid transporting wafer and the wafer contamination that causes.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1 shows that the flow chart of the method for manufacturing according to the preferred embodiment of the present invention semiconductor device structure;
Figure 2 shows that the schematic diagram of the semiconductor device structure that the method according to this invention obtains.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it will be apparent to one skilled in the art that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, will detailed step and structure be proposed in following description, so that explanation the present invention.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
It should be noted that the term that used is only in order to describe specific embodiment here, but not intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative is also intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, entirety, step, operation, element and/or assembly, exists or additional one or more other features, entirety, step, operation, element, assembly and/or their combination but do not get rid of.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skills.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and region, and used the identical Reference numeral to represent identical element, thereby will omit description of them.
Below with reference to Fig. 1, describe the method for manufacturing according to the preferred embodiment of the present invention semiconductor device structure in detail.
Method of the present invention can be for the manufacture of various semiconductor device structures, the various semiconductor device structures that especially form in the interlayer dielectric layer with ultralow dielectric in 28nm or 32nm technique, such as through hole or contact hole etc.Below take form layer structure before through hole or contact hole as example illustrates principle of the present invention.
First,, in step S101, provide front end device layer structure.
As example, described front end device layer structure comprises the device architecture layer forming in preorder technique, the device architecture layer for example forming on substrate etc., wherein substrate can be chosen as silicon or the SiGe (SiGe) of monocrystalline, polycrystalline or non crystalline structure, also can be silicon-on-insulator (SOI), can also comprise other material, such as indium antimonide, lead telluride, indium arsenide, GaAs or gallium antimonide etc.
Wherein, the surface of this front end device layer structure can also be formed with etching stop layer.This etching stop layer is for example copper barrier structure (copper barrier) or other structures.
In addition, it should be noted that front end device layer structure as herein described is not restrictive, but can also there are other structures.
Then,, in step S102, in the first reative cell, form the interlayer dielectric layer with ultralow dielectric on the surface of front end device layer structure.Wherein, the interlayer dielectric layer that has ultralow dielectric is by comprising methyldiethoxysilane (C
5h
14o
2si, is abbreviated as DEMS) reacting gas form.Except DEMS, reacting gas can also comprise terpinene (ATRP) or bicycloheptadiene (BCHD) etc.For example, in one embodiment, described reacting gas is the mist being made up of DEMS and ATRP; In another embodiment, described reacting gas is the mist being made up of DEMS and BCHD.The method that formation has the interlayer dielectric layer of ultralow dielectric can be for example plasma enhanced chemical vapor deposition method, but the method is not restrictive, can also have additive method.
More specifically, the pressure in the first reative cell is 2 ~ 8Torr, for example, can be 3Torr, 4Torr, 6Torr etc.; Power in reative cell is 300 ~ 1000W, for example, can be 500W, 700W, 800W etc.; Temperature in reative cell is 200 ~ 300 degrees Celsius, for example, can be 220 degrees Celsius, 260 degrees Celsius, and 280 degrees Celsius etc.The thickness with the interlayer dielectric layer of ultralow dielectric is 100 ~ 300 dusts, for example, can be 200 dusts, 240 dusts etc.The k value of the described interlayer dielectric layer with ultralow dielectric is less than 2.55.
Then,, in step S103, in the second reative cell, form DEMS mask layer on the surface of the described interlayer dielectric layer with ultralow dielectric by plasma enhanced chemical vapor deposition method.
The formation method of DEMS mask layer and formation condition are should be preferably same or similar with formation method and the condition of interlayer dielectric layer with ultralow dielectric.For example, the formation method of DEMS mask layer can be plasma enhanced chemical vapor deposition method.But its formation method is also nonrestrictive, can also have additive method.Pressure in reative cell is 2 ~ 8Torr, for example, can be 3Torr, 4Torr, 6Torr etc.; Power in reative cell is 300 ~ 1000W, for example, can be 500W, 700W, 800W etc.; Temperature in reative cell is 200 ~ 300 degrees Celsius, for example, can be 220 degrees Celsius, 260 degrees Celsius, and 280 degrees Celsius etc.; The intake of DEMS is 500 ~ 3000mg/min, for example, can be 1000mg/min, 1500mg/min, 2000mg/min etc.
In order to produce enough adhesions, the thickness of DEMS mask layer is 100 ~ 500 dusts, for example, can be 200 dusts, 300 dusts, 350 dusts, 400 dusts etc.
Because DEMS has the character of mask layer, therefore it can be used as the material that forms mask layer, but the more important thing is, it is one of raw material forming the interlayer dielectric layer with ultralow dielectric, therefore can also in same reative cell, generate with the interlayer dielectric layer with ultralow dielectric, described the first reative cell and described the second reative cell are same reative cell.Like this, not only can simplify existing technique, can also avoid transporting the wafer that wafer causes and be polluted, and can reduce the Production Time of semiconductor device structure, and improve the production efficiency of semiconductor device structure.
It will be understood by those skilled in the art that, because working condition and production technology etc. between different production lines there are differences, therefore, it is also different that formation has the raw material of interlayer dielectric layer of ultralow dielectric, although present embodiment is take DEMS mask layer as example, but in order to realize object of the present invention, except DEMS, can also select the other materials with the character that approaches very much super low-k materials to form mask layer according to the formation raw material of interlayer dielectric layer.Preferably, these materials should have the character of improving adhesion between layer structure.
Then,, in step S104, form tetraethoxysilane (TEOS) mask layer on the surface of described DEMS mask layer.
In situation preferably, in order to strengthen the adhesion between DEMS mask layer and TEOS mask layer, can also, before TEOS mask layer forms, first form SiO on the surface of DEMS mask layer
2thin layer, formation method for example for to pass into O in the 3rd reative cell
2.As example, pass into O
2flow be 100 ~ 500sccm, can be for example 200sccm, 300sccm, 400sccm etc.But it will be appreciated by persons skilled in the art that and generate SiO
2step not necessarily.
Then,, in step S105, form titanium nitride (TiN) mask layer on the surface of described TEOS mask layer.
More specifically, described TEOS mask layer is mainly used in strengthening the adhesion between DEMS mask layer and TiN mask layer, and described TiN mask layer is mainly used in improving the critical size after etching.
In sum, the invention provides a kind of method of new manufacture semiconductor device structure, the method can form in same reative cell has the interlayer dielectric layer of ultralow dielectric and the mask layer being located thereon, therefore, simplify existing technique, be conducive to the batch production of semiconductor device structure, and, reduce the Production Time of semiconductor device structure, improved the production efficiency of semiconductor device structure, can also avoid transporting wafer and the wafer contamination that causes.
Describe semiconductor device structure made according to the method for the present invention in detail below with reference to Fig. 2.
Under normal conditions, front end device layer structure 201 comprises the device architecture layer forming in preorder technique.
For example, described front end device layer structure 201 comprises the device architecture layer forming in preorder technique, the device architecture layer for example forming on substrate etc., wherein substrate can be chosen as silicon or the SiGe (SiGe) of monocrystalline, polycrystalline or non crystalline structure, also can be silicon-on-insulator (SOI), can also comprise other material, such as indium antimonide, lead telluride, indium arsenide, GaAs or gallium antimonide etc.
Wherein, the surface of this front end device layer structure 201 can also be formed with etching stop layer 201a.This etching stop layer 201a can be copper barrier structure (copper barrier), can be also other structures.
In addition, need to it should be noted that front end device layer structure 201 as herein described is not restrictive, but can also there are other structures.
The surface of front end device layer structure 201 is formed with the interlayer dielectric layer 202 with ultralow dielectric.
The described interlayer dielectric layer 202 with ultralow dielectric is by comprising methyldiethoxysilane (C
5h
14o
2si, is abbreviated as DEMS) reacting gas form.Except DEMS, reacting gas can also comprise terpinene (ATRP) or bicycloheptadiene (BCHD) etc.For example, in one embodiment, described reacting gas is the mist being made up of DEMS and ATRP; In another embodiment, described reacting gas is the mist being made up of DEMS and BCHD.The thickness with the interlayer dielectric layer 202 of ultralow dielectric is 100 ~ 300 dusts, for example, can be 200 dusts, 240 dusts etc.The k value of the described interlayer dielectric layer with ultralow dielectric is less than 2.55.
The surface with the interlayer dielectric layer 202 of ultralow dielectric is formed with DEMS mask layer 203.Wherein, the thickness of DEMS mask layer is 100 ~ 500 dusts, for example, can be 200 dusts, 300 dusts, 350 dusts, 400 dusts etc.
Because DEMS has the character of mask layer, therefore it can be used as the material that forms mask layer, but the more important thing is, it is one of raw material forming the interlayer dielectric layer with ultralow dielectric, therefore can also in same reative cell, generate with the interlayer dielectric layer with ultralow dielectric, described the first reative cell and described the second reative cell are same reative cell.Like this, not only can simplify existing technique, can also avoid transporting the wafer that wafer causes and be polluted, and can reduce the Production Time of semiconductor device structure, and improve the production efficiency of semiconductor device structure.
It will be understood by those skilled in the art that, because working condition and production technology etc. between different production lines there are differences, therefore, it is also different that formation has the raw material of interlayer dielectric layer of ultralow dielectric, although present embodiment is take DEMS mask layer as example, but in order to realize object of the present invention, except DEMS, the other materials that can also select to have the character that approaches very much super low-k materials forms mask layer.Preferably, these materials should have the character of improving adhesion between layer structure.
The surface of DEMS mask layer 203 is also formed with tetraethoxysilane (TEOS) mask layer 204.
Preferably, in order to strengthen the adhesion between DEMS mask layer 203 and TEOS mask layer 204, between DEMS mask layer 203 and TEOS mask layer 204, can also be formed with SiO
2thin layer (not shown).
The surface of TEOS mask layer 204 is also formed with titanium nitride (TiN) mask layer 205.
Wherein, described TEOS mask layer 204 is for strengthening the adhesion between DEMS mask layer 203 and TiN mask layer 205, and described TiN mask layer 205 is for improving the critical size after etching.
[beneficial effect of the present invention]
In sum, the invention provides a kind of method and semiconductor device structure obtained by this method of new manufacture semiconductor device structure, this device architecture has function and the effect suitable with existing device architecture; Secondly, manufacture method of the present invention can form in same reative cell has the interlayer dielectric layer of ultralow dielectric and the mask layer being located thereon, therefore, simplify existing technique, be conducive to the batch production of semiconductor device structure, and, the Production Time of having reduced semiconductor device structure, improve the production efficiency of semiconductor device structure, can also avoid transporting wafer and the wafer contamination that causes.
[industrial applicibility of the present invention]
Can be applicable in multiple integrated circuit (IC) according to the semiconductor device of execution mode manufacture as above.For example memory circuitry according to IC of the present invention, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in radio frequency products.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (13)
1. a method of manufacturing semiconductor device structure, is characterized in that, comprising:
A) provide front end device layer structure;
B) in the first reative cell, surface in described front end device layer structure forms the interlayer dielectric layer with ultralow dielectric, wherein, the k value of the described interlayer dielectric layer with ultralow dielectric is less than 2.55, described in there is ultralow dielectric interlayer dielectric layer formed by the reacting gas that comprises methyldiethoxysilane; And
C), in the second reative cell, form methyldiethoxysilane mask layer on the surface of the described interlayer dielectric layer with ultralow dielectric by plasma enhanced chemical vapor deposition method.
2. method according to claim 1, is characterized in that, described reacting gas also comprises terpinene or bicycloheptadiene.
3. method according to claim 1, is characterized in that, described the first reative cell and described the second reative cell are same reative cell.
4. method according to claim 1, is characterized in that, the thickness of described methyldiethoxysilane mask layer is 100～500 dusts.
5. method according to claim 1, is characterized in that, the pressure of step c) is 2～8Torr.
6. method according to claim 1 or 5, is characterized in that, the temperature of step c) is 200～300 degrees Celsius.
7. method according to claim 1 or 5, is characterized in that, the power of step c) is 300～1000W.
8. method according to claim 7, is characterized in that, the temperature of step c) is 200～300 degrees Celsius.
9. method according to claim 1, is characterized in that, the intake of the described methyldiethoxysilane of step c) is 500～3000mg/min.
10. method according to claim 1, is characterized in that, described method also comprises:
D) form tetraethoxysilane mask layer on the surface of described methyldiethoxysilane mask layer; With
E) form titanium nitride mask layer on the surface of described tetraethoxysilane mask layer.
11. methods according to claim 1, is characterized in that, described method also comprises:
D) in the 3rd reative cell, pass into oxygen, form silicon dioxide layer with the surface at described methyldiethoxysilane mask layer;
E) form tetraethoxysilane mask layer on the surface of described silicon dioxide layer; With
F) form titanium nitride mask layer on the surface of described tetraethoxysilane mask layer.
12. methods according to claim 11, is characterized in that, the flow of described oxygen is 100～500sccm.
13. 1 kinds of semiconductor device structures, is characterized in that, described semiconductor device structure is made up of the method described in above-mentioned arbitrary claim.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010615184.4A CN102543844B (en) | 2010-12-30 | 2010-12-30 | Method for manufacturing semiconductor device structure and semiconductor device structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010615184.4A CN102543844B (en) | 2010-12-30 | 2010-12-30 | Method for manufacturing semiconductor device structure and semiconductor device structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102543844A CN102543844A (en) | 2012-07-04 |
| CN102543844B true CN102543844B (en) | 2014-05-14 |
Family
ID=46350392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010615184.4A Active CN102543844B (en) | 2010-12-30 | 2010-12-30 | Method for manufacturing semiconductor device structure and semiconductor device structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102543844B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104217991B (en) * | 2013-06-05 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | Method for forming interconnection structures |
| CN105206562B (en) * | 2014-06-18 | 2018-06-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1950932A (en) * | 2004-05-03 | 2007-04-18 | 国际商业机器公司 | An improved method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made |
| CN101316945A (en) * | 2005-12-13 | 2008-12-03 | 应用材料股份有限公司 | A method to improve the ashing/wet etch damage resistance and integration stability of low dielectric constant films |
| CN101378850A (en) * | 2006-02-21 | 2009-03-04 | 应用材料股份有限公司 | Enhanced remote plasma source cleaning for dielectric film layers |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7335980B2 (en) * | 2004-11-04 | 2008-02-26 | International Business Machines Corporation | Hardmask for reliability of silicon based dielectrics |
-
2010
- 2010-12-30 CN CN201010615184.4A patent/CN102543844B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1950932A (en) * | 2004-05-03 | 2007-04-18 | 国际商业机器公司 | An improved method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made |
| CN101316945A (en) * | 2005-12-13 | 2008-12-03 | 应用材料股份有限公司 | A method to improve the ashing/wet etch damage resistance and integration stability of low dielectric constant films |
| CN101378850A (en) * | 2006-02-21 | 2009-03-04 | 应用材料股份有限公司 | Enhanced remote plasma source cleaning for dielectric film layers |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102543844A (en) | 2012-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI631602B (en) | Semiconductor structure and device and methods of forming same using selective epitaxial process | |
| TWI694547B (en) | Insulation layer structure for semiconductor products and preparation method thereof | |
| KR101573205B1 (en) | Methods for manufacturing high dielectric constant film | |
| US9224691B2 (en) | Semiconductor device contact structures | |
| CN101736314B (en) | Formation method of silicon oxide film and metal-insulator-metal capacitor | |
| CN102543844B (en) | Method for manufacturing semiconductor device structure and semiconductor device structure | |
| CN103579006B (en) | There is semiconductor element and the manufacture method thereof of vertical gate | |
| TW200414360A (en) | Manufacturing method for semiconductor integrated circuit device | |
| CN103928391A (en) | Forming method of semiconductor structure | |
| CN104103573A (en) | Semiconductor structure and formation method thereof | |
| CN103489821B (en) | A kind of fill method of high aspect ratio trench quite | |
| CN105336596A (en) | Preparation method for high-dielectric-constant interface layer | |
| CN106601679B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN102693958A (en) | Copper interconnection structure adopting novel diffusion impervious layer and preparation method thereof | |
| CN103137538B (en) | Si/NiSi2 backing material and preparation method thereof on a kind of pattern dielectric body | |
| CN110942984B (en) | Preparation method of cobalt silicide film | |
| CN102492932B (en) | In-situ surface passivation method in ALD (atomic layer deposition) production of GaAs-based MOS (Metal Oxide Semiconductor) devices | |
| CN102024788B (en) | Semiconductor device for interconnection process and manufacturing method thereof | |
| CN107785304B (en) | SOI material with nitride film as insulating buried layer and preparation method thereof | |
| CN103928440A (en) | Copper interconnection diffusion impervious layer and preparation method thereof | |
| CN110379710A (en) | The manufacturing method and semiconductor devices of metal gates | |
| CN105655398A (en) | Semiconductor structure and forming method thereof | |
| JP2003258243A (en) | Semiconductor device and its manufacturing method | |
| CN103681478A (en) | Copper-connection structure and manufacturing method of copper-connection structure | |
| WO2022221986A1 (en) | Semiconductor apparatus and fabrication method therefor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20130106 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20130106 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |