CN103681478A - Copper-connection structure and manufacturing method of copper-connection structure - Google Patents
Copper-connection structure and manufacturing method of copper-connection structure Download PDFInfo
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- CN103681478A CN103681478A CN201310700297.8A CN201310700297A CN103681478A CN 103681478 A CN103681478 A CN 103681478A CN 201310700297 A CN201310700297 A CN 201310700297A CN 103681478 A CN103681478 A CN 103681478A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
Abstract
The invention belongs to the technical field of semiconductors, and particularly relates to a copper-connection structure and a manufacturing method of the copper-connection structure. Based on an original copper-connection structure, a double-layer Ru/TiAlN structure is used as a diffusion impervious layer/adhesion layer/seed crystal layer structure. The manufacturing method includes the particular steps that an atomic layer deposition method is adopted, a TiAlN thin film is firstly deposited on an insulating medium layer, a Ru thin film is then deposited, and finally electrocoppering is directly carried out to obtain the copper-connection structure. As Al is added in the TiAlN thin film, the amorphous TiAlN thin film can be obtained, and the Cu diffusion impervious performance better than that of a TiN thin film can be obtained. According to the copper-connection structure, the amorphous TiAlN thin film with high density is used, channels, such as crystal boundaries, for rapid diffusion do not exist, the ideal diffusion impervious performance and the ideal heat stability are provided, and a practical and reliable scheme is provided for the copper-connection technology of 22nm and smaller-than-22nm technological nodes.
Description
Technical field
The invention belongs to technical field of semiconductors, be specifically related to a kind of integrated circuit copper interconnection structure and preparation method thereof.
Background technology
Development along with integrated circuit processing technique, the characteristic size of semiconductor device and circuit continues to dwindle, interconnect delay replaces device gate delay becomes the principal element that restriction IC speed further improves, and the electric conducting material that searching resistivity is lower and the lower dielectric material of dielectric constant become a great development direction of very lagre scale integrated circuit (VLSIC) technique.Because Cu has the resistivity lower than Al, higher deelectric transferred ability and the coefficient of heat conduction of Geng Gao, become gradually current employing interconnection material the most widely.But, Cu diffusion phase in Si and oxide is worked as fast, and once Cu enters and wherein forms deep-level impurity, charge carrier in device is had to very strong trap effect, device performance degeneration was even lost efficacy, therefore the effective diffusion impervious layer of one deck be need between Cu and Si substrate, form, to play isolated Cu and Si, Cu and the adhering effect of Si substrate improved simultaneously.The barrier material the most often using in semiconductor manufacturing industry is at present TiN, although TiN and Cu, Si are stable on thermodynamics, but its maximum shortcoming is exactly polycrystalline and columnar microstructure, these are least ready to see as barrier layer, because the more crystal boundary existing will become the path of Cu rapid diffusion.The TiN of non crystalline structure can eliminate this defect, but amorphous TiN is very unsettled.The nitride of other transition metal and Cu are also Thermodynamically stables and can prepare amorphous state by the method for reactive sputtering, but it also will start crystallization at the temperature losing efficacy as barrier layer at TiN.So find and a kind ofly there is the more barrier material of high thermal stability and chase after at the eyebrows and eyelashes.
Lasting propelling along with semiconductor process techniques, traditional thin film deposition technology has been difficult to effectively accurately control film characteristics and meet day by day harsh technology requirement, and atomic layer deposition (ALD) technology is owing to can completing the technique that precision is higher, become just gradually the key technology that microelectronic component is manufactured field.It has lower deposition temperature, the advantage such as deposition rate, manageable doping content and high film quality faster, the more important thing is, on to through hole and groove, during deposit diffusion impervious layer, it has better conformality than methods such as sputters.
In various diffusion barrier material, Ru is a kind of very promising copper diffusion barrier layer material, and this is that its resistivity is more much lower than TaN and Ta because it is a kind of inert metal; And have extraordinary adhesiveness with Cu, guaranteed the reliability of device.Yet simple Ru film is the uncomfortable incompatible diffusion impervious layer of doing, because pure Ru film is Columnar structure, the short-range diffusion that its crystal boundary is Cu provides path.Meanwhile, Ru film is also poor at the surface adhesive of silicon dioxide and advanced low-k materials.
Consider requirement higher to diffusion impervious layer under deep-submicron level, we propose to utilize double-deck Ru/TiAlN structure as diffusion impervious layer.Ru layer provides the required adhesiveness of next step copper facing and the possibility of nucleation; TiAlN layer has made up the bad shortcoming of Ru layer barrier properties, and the introducing of AlN has not only changed TiN polycrystalline structure originally, and has strengthened film compactness and thermal stability, makes this structure reach a kind of perfect diffusion barrier effect.
Summary of the invention
The object of the present invention is to provide a kind of novel copper interconnection structure and preparation method thereof, to tackle integrated circuit characteristic size, constantly dwindle difficulty and the requirement higher to diffusion barrier performance of the copper interconnect wiring that brings.
The copper interconnection structure that the present invention proposes, adopts Ru/TiAlN double-decker as copper diffusion barrier layer and inculating crystal layer.
The present invention also provides the preparation method of the copper interconnection structure that uses above-mentioned Ru/TiAlN bilayer, and concrete steps comprise:
(1) adopt RCA standard cleaning technique to clean silicon-based substrate;
(2) on silicon chip, form successively etching barrier layer, insulating medium layer;
(3) by photoetching, etching technics, define interconnect location, form metal valley, contact hole or through hole;
(4) in the structure forming in above-mentioned steps, utilize atomic layer deposition method alternating growth TiN layer and AlN layer, obtain TiAlN film, then the Ru film of then growing, thereby Ru/TiAlN bilayer diffusion barrier formed;
(5) Direct Electroplating copper on said structure, obtains copper interconnection structure;
(6) finally use CMP (Chemical Mechanical Polishing) process leveling wafer surface.
Further, described dielectric layer material is the SiCOH of SiO2, SiOF, SiCOH or porous, and described etching barrier layer material is silicon nitride.
The growth of described bilayer diffusion barrier adopts PEALD method, and its concrete steps comprise two stages, first stage alternating growth n
1layer TiN and n
2layer AlN film, constantly repeats said process, forms TiAlN film; Second stage growth n
3layer Ru, thus double-deck Ru/TiAlN film, wherein n formed
1, n
2and n
3for being more than or equal to 1 integer.
Described Ru/TiAlN bilayer film, first deposit TiAlN of first stage film, the Ti presoma of use is four dimethyl amido titaniums (TDMAT), (diethylamino) titanium (TDEAT) or TiCl
4, gas source is NH
3or N
2/ H
2, the Al presoma of use for trimethyl aluminium (TMA), liquid source be H
2o; Second stage deposit Ru film, the Ru presoma of use is Ru (Cp)
2, Ru (EtCp)
2or Ru (OD)
3, use gas source is O
2, NH
3or H
2.Plasma power is 50 ~ 100W, carrier gas flux 300-400 sccm, and the temperature of reaction cavity is 250 ~ 350
oc, the operating pressure of reaction cavity is 1 ~ 4 Torr.
In the described first stage, first carry out n
1individual TiN growth cycle circulation and n
2the circulation of individual AlN growth cycle, then carry out the above process of repetition and complete growth.The growth cycle of a TiN comprises: toward reaction chamber, pass into Ti presoma, the burst length is 2 ~ 4 s, uses high-purity N
2purge 8 ~ 16s, then pass into gas source plasma, the burst length is 4 ~ 6s, with high pure nitrogen, purges 8 ~ 12s; The growth cycle of an AlN comprises that past reaction chamber passes into Al presoma, and the burst length is 1 ~ 2 s, uses high-purity N
2purge 4 ~ 8s, then pass into liquid source, the burst length is 2 ~ 4s, with high pure nitrogen, purges 4 ~ 8s.Described second stage comprises n
3individual Ru growth cycle circulation (n
1, n
2, n
3for being greater than 1 integer).The growth cycle of a Ru comprises: toward reaction chamber, pass into Ru presoma, the burst length is 1 ~ 5s, uses high-purity N
2purge 2 ~ 10s, then pass into gas source plasma, the burst length is 0.3 ~ 2s, with high pure nitrogen, purges 1 ~ 5s.By changing the number of plies n of TiN and AlN
1, n
2can optimize Cu blocking capability, compactness and the conductivity of TiAlN film.
The present invention uses double-deck Ru/TiAlN as diffusion impervious layer and inculating crystal layer, utilized the adhesive capacity that Cu diffusion barrier effect that TiN is good and Ru are outstanding simultaneously, and make TiN layer change non crystalline structure into from polycrystalline structure by mix Al element in TiN film, thereby diffusion barrier capability and thermal stability have further been improved; Adopt in addition ALD technology can when high aspect ratio structure thin film deposition, there is 100% step coverage, deposit film composition and thickness are had to outstanding control ability, thereby obtain the very good film of high-quality of purity, this has just overcome the deficiency of the traditional thin film deposition technology such as PVD interconnection wiring under sub-micro environment, thereby has effectively improved the Performance And Reliability of copper interconnection structure.Advantage of the present invention is to use the high amorphous state TiAlN film of density, there is not the passage of such Gong the rapid diffusion of crystal boundary, provide desirable diffusion barrier and thermal stability, for the copper interconnection technology of 22nm and following technology node thereof provides a kind of more solid scheme.
Accompanying drawing explanation
Fig. 1-Fig. 6 is the integrated technique flow chart according to a kind of novel C u diffusion impervious layer of the invention process and copper-connection.
Number in the figure: 101 is Semiconductor substrate wafer, 102 is etching barrier layer, and 103 is insulating medium layer, and 104 is diffusion impervious layer TiAlN, and 105 is inculating crystal layer Ru, 106 is electroplated copper film.
Embodiment
Below in conjunction with accompanying drawing and embodiment, be described in further detail, in the drawings, for convenience of description, amplify and dwindled the thickness in layer and region, shown in size do not represent actual size, identical Reference numeral represents identical assembly, and it is repeated in this description omission.
Ru/TiAlN diffusion impervious layer proposed by the invention and preparation method thereof is applicable to the copper interconnection technology of various semiconductor integrated circuit, and below what narrate is to adopt the present invention to prepare the technological process of an embodiment of Ru/TiAlN diffusion impervious layer.
First, on Si (100) substrate 101, adopt standard CMOS process, complete the cleaning of silicon chip, concrete technology mainly comprises: with hydrofluoric acid and the deionized water of sulfuric acid and hydrogen peroxide mixed solution, standard cleaning SC-1, SC-2, dilution, sequentially clean respectively Si substrate, remove various impurity and natural oxidizing layer, and use high-purity N
2dry up.On cleaned Si (100) substrate 101, sequentially deposit one deck etching barrier layer silicon nitride 102, for the dielectric layer 103(of layer insulation as SiO
2film).Then utilize photoetching and the etching technics of standard to form groove or the through hole 201 that interconnection structure is used, as Fig. 1.
After groove or through hole form, utilize the PEALD technology TiAlN film 104 of growing.Ti presoma is TDMAT, and gas source is NH
3; Al presoma is trimethyl aluminium (TMA), and liquid source is H
2o, growth temperature is 200-350
oc, the pressure of reaction chamber is 1 ~ 4 Torr, plasma power is 80W.First the grow TiN of 3 growth cycles and the AlN of 2 growth cycles, constantly repeat this process to form TiAlN film, as shown in Figure 2.The growth cycle of a TiN comprises: toward reaction chamber, pass into TDMAT, the burst length is 2 s, uses high-purity N
2purge 8s, then pass into NH
3plasma, the burst length is 4s, with high pure nitrogen, purges 8s.The growth cycle of an AlN comprises that past reaction chamber passes into TMA, and the burst length is 1 s, uses high-purity N
2purge 4s, then pass into H
2o, the burst length is 4s, with high pure nitrogen, purges 8s.Structure as shown in Figure 3.
Next regrowth Ru film 105, the Ru presoma of use is Ru (EtCp)
2, gas source is O
2, other conditions are constant.First, in reflection chamber, pass into Ru source, the burst length is 1s; Use high-purity N
2purge reaction chamber 2s; Pass into O
2, the time is 0.5 s, uses high-purity N
2purge reflection chamber 2s; Repeat 50 growth cycles, finally obtain Ru/TiAlN barrier layer structure, as shown in Figure 4.
Then, adopt the mode of electroplating, in groove or through-hole structure, electro-coppering wire 106, forms copper interconnection structure, as shown in Figure 5.
Finally, by chemico-mechanical polishing (CMP) technology leveling wafer surface, complete the interconnection structure of one deck, as shown in Figure 6, for lower one deck interconnection structure is prepared.
Below by reference to the accompanying drawings the specific embodiment of the present invention is described; but these explanations can not be understood to limit scope of the present invention; protection scope of the present invention is limited by the claims of enclosing, and any change on the claims in the present invention basis is all protection scope of the present invention.
Claims (8)
1. a copper interconnection structure, is characterized in that adopting double-deck Ru/TiAlN structure as copper diffusion barrier layer and inculating crystal layer.
2. as a preparation method for copper interconnection structure according to claim 1, it is characterized in that concrete steps are:
(1) adopt RCA standard cleaning technique to clean silicon-based substrate;
(2) on silicon substrate, form successively one deck etching barrier layer, insulating medium layer;
(3) by photoetching, etching technics, define interconnect location, form metal valley, contact hole or through hole;
(4), in the structure forming in above-mentioned steps, utilize atomic layer deposition method alternating growth TiN layer and AlN layer to obtain TiAlN film, then the Ru film of then growing, thereby Ru/TiAlN bilayer diffusion barrier formed;
(5), in the structure forming in above-mentioned steps, Direct Electroplating copper, obtains copper interconnection structure;
(6) finally use CMP (Chemical Mechanical Polishing) process leveling wafer surface.
3. according to the preparation method described in claim 2, it is characterized in that, the described dielectric layer material of step (2) is SiO
2, SiOF, SiCOH or porous SiCOH.
4. according to the preparation method described in claim 2, it is characterized in that, the described etching barrier layer material of step (2) is silicon nitride.
5. according to the preparation method described in claim 2, it is characterized in that, the growth of the described bilayer diffusion barrier of step (4) adopts plasma to help ald (PEALD) method, and its detailed process is divided into two stages, first stage alternating growth n
1layer TiN and n
2layer AlN film, constantly repeats said process, forms TiAlN film; Second stage growth n
3layer Ru, thus double-deck Ru/TiAlN film, wherein n formed
1, n
2and n
3for being more than or equal to 1 integer, by controlling n
1, n
2and n
3numerical value, finally obtain the barrier film of desired thickness.
6. according to the preparation method described in claim 2, it is characterized in that, the described PEALD growth of step (4) the required Ti of TiN source is four dimethyl amido titaniums, diethylamino titanium or TiCl
4, gas source is NH
3or N
2/ H
2; The required Al of growing AIN source is trimethyl aluminium, and liquid source is H
2o; The growth required Ru of Ru source is Ru (Cp)
2, Ru (EtCp)
2or Ru (OD)
3, gas source is O
2, NH
3or H
2, plasma power is 50 ~ 100W, carrier gas flux 300-400 sccm, and the temperature of reaction cavity is 250 ~ 350
oc, the operating pressure of reaction cavity is 1 ~ 4 Torr.
7. preparation method according to claim 6, is characterized in that, the growth cycle of a TiN comprises: toward reaction chamber, pass into Ti presoma, the burst length is 2 ~ 4 s, uses high-purity N
2purge 8 ~ 16s, then pass into gas source plasma, the burst length is 4 ~ 6s, with high pure nitrogen, purges 8 ~ 12s; The growth cycle of an AlN comprises that past reaction chamber passes into Al presoma, and the burst length is 1 ~ 2 s, uses high-purity N
2purge 4 ~ 8s, then pass into liquid source, the burst length is 2 ~ 4s, with high pure nitrogen, purges 4 ~ 8s; The growth cycle of a Ru comprises: toward reaction chamber, pass into Ru presoma, the burst length is 1 ~ 5s, uses high-purity N
2purge 2 ~ 10s, then pass into gas source plasma, the burst length is 0.3 ~ 2s, with high pure nitrogen, purges 1 ~ 5s.
8. preparation method according to claim 2, is characterized in that, it is 0.5A/dm that the described copper interconnection structure of step (5) is used the current density of electroplating
2-3.0A/dm
2.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106910709A (en) * | 2015-12-22 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN109267025A (en) * | 2018-11-16 | 2019-01-25 | 江苏科技大学 | The method for preparing Ti-Al-Ru-N nano-hard film based on ceramic substrate surface |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6181012B1 (en) * | 1998-04-27 | 2001-01-30 | International Business Machines Corporation | Copper interconnection structure incorporating a metal seed layer |
| CN101710577A (en) * | 2009-11-19 | 2010-05-19 | 复旦大学 | Method for inhibiting oxidization of copper in copper interconnect structure |
| CN101819944A (en) * | 2010-04-28 | 2010-09-01 | 复旦大学 | Method for forming copper contact interconnection structure |
-
2013
- 2013-12-19 CN CN201310700297.8A patent/CN103681478B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6181012B1 (en) * | 1998-04-27 | 2001-01-30 | International Business Machines Corporation | Copper interconnection structure incorporating a metal seed layer |
| CN101710577A (en) * | 2009-11-19 | 2010-05-19 | 复旦大学 | Method for inhibiting oxidization of copper in copper interconnect structure |
| CN101819944A (en) * | 2010-04-28 | 2010-09-01 | 复旦大学 | Method for forming copper contact interconnection structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106910709A (en) * | 2015-12-22 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN106910709B (en) * | 2015-12-22 | 2020-04-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method thereof and electronic device |
| CN109267025A (en) * | 2018-11-16 | 2019-01-25 | 江苏科技大学 | The method for preparing Ti-Al-Ru-N nano-hard film based on ceramic substrate surface |
| CN109267025B (en) * | 2018-11-16 | 2020-10-09 | 江苏科技大学 | Method for preparing Ti-Al-Ru-N nano hard film based on ceramic substrate surface |
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