CN102693958A - Copper interconnection structure adopting novel diffusion impervious layer and preparation method thereof - Google Patents

Abstract

The invention belongs to the technical field of semiconductor integrated circuit manufacturing, in particular to a copper interconnection structure and a preparation method thereof. Based on the existing copper interconnection structure, the invention adopts manganese silicate film as the copper diffusion barrier layer of the copper interconnection structure. The present invention uses the atomic layer deposition method to grow a 5-20nm manganese silicate film in the trench and through-hole structure of copper interconnection, and the deposited film can achieve good step coverage and can greatly reduce holes and gaps, etc. The occurrence of defects. In addition, by adjusting the ratio of Si and Mn in the manganese silicate film, better copper diffusion barrier ability and adhesion characteristics can be obtained. The invention has the advantages of being able to improve the anti-electromigration characteristics of copper interconnection lines, and maintain its reliability in the application of copper interconnection in integrated circuits, and provide an ideal interconnection process technology for 45nm and below process technology nodes solution.

Description

A copper interconnection structure using a novel diffusion barrier layer and its preparation method

technical field

The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a copper interconnection structure and a preparation method thereof.

Background technique

Integrated circuit technology has always followed Moore's Law, increasing transistor density by continuously reducing device size and increasing wafer size, thereby reducing costs and making it develop at a high speed. However, when the feature size of the device is reduced to the nanometer scale, the interconnection delay gradually replaces the chip delay as the key factor affecting the chip performance, which greatly reduces the chip performance. In order to reduce the RC delay caused by interconnection, Cu interconnection has gradually replaced Al interconnection to become the mainstream technology in the semiconductor industry.

As the interconnection material of integrated circuits, metal Cu has the following advantages compared with traditional Al: (1) The resistivity of Cu is small. The resistivity of Al of the general bulk material is 2.7 μΩ.cm, while the resistivity of Cu is 1.7 μΩ.cm; (2) The parasitic capacitance caused by Cu interconnection is smaller than that of aluminum interconnection; (3) The resistivity of Cu The electromigration ability is much better than that of Al. At high current density, the anti-electromigration ability of Cu can be improved by nearly four orders of magnitude compared with that of Al, so it can greatly reduce the holes or gaps caused by the electromigration effect, reduce the leakage current, and greatly improve the reliability of the device. (4) Cu also has good anti-stress hole characteristics, etc.; (5) Cu has better thermal conductivity than Al, which can make the silicon chip dissipate heat quickly through the external packaging structure, and can also improve the reliability of the chip , to prolong the life of the chip. Therefore, the use of Cu interconnection technology can meet the requirements of advanced integrated circuits with high frequency, high integration, high power, large capacity and long life, so that the nano-sized process technology node, Al interconnection process is gradually replaced by copper interconnection process .

However, although the process of using Cu material as the interconnection line of the integrated circuit can overcome the innate deficiency of the Al metal material, there are still many problems to be overcome and solved. For example, metal Cu is easily oxidized and corroded by moisture in the atmospheric environment, and Cu does not form its own protective layer like Al, thus affecting the stability and life of the metal interconnection. Furthermore, Cu has a certain solubility at low temperature, and when Cu reacts with the Si substrate, a Cu silicide will be formed and the device will fail. In addition, Cu atoms have rapid diffusion. When accelerated by the electric field, Cu will easily penetrate the insulating dielectric layer and quickly reach the Si substrate. Once Cu diffuses into the silicon substrate, it will interact with Si and This causes Cu to penetrate the interface of the transistor and short circuit the device. the

At present, the problem of high diffusivity between Cu and the insulating dielectric layer or Si is generally overcome by using the double-layer structure of TaN/Ta as the diffusion barrier layer. However, if the diffusion barrier layer of the TaN/Ta double-layer structure is prepared, if the degree of crystallization is high, Cu diffusion channels will be formed at the grain boundaries, which will intensify the Cu diffusion effect. Moreover, the adhesion of the TaN/Ta double-layer structure is poor, and reliability problems are prone to occur. the

In addition, the traditional preparation method of the TaN/Ta double-layer diffusion barrier layer mainly adopts physical vapor deposition (PVD) technology. However, PVD technology cannot meet the requirements of metal oxide semiconductor (MOS) transistor devices down to 45/32nm process nodes and below due to poor step coverage and poor filling ability of trenches and vias, which may easily lead to reliability changes. Bad question. In order to reduce interconnect resistance, reduce capacitance between interconnects and improve reliability, ALD technology is used to grow a layer of nano-manganese silicate, which can have good shape retention during the filling process of trenches and vias , improve the reliability of the device, and can effectively reduce the interconnection RC delay.

Contents of the invention

The object of the present invention is to provide a copper interconnection structure with excellent Cu diffusion resistance and its preparation method, so as to improve the shortcoming of large RC delay caused by the continuous reduction of integrated circuit feature size, and improve the performance of semiconductor chips. the

The copper interconnection structure provided by the present invention is based on the existing copper interconnection structure, and its improvement is that the manganese silicate film is used as the diffusion barrier layer of the copper interconnection structure, and the thickness of the manganese silicate film is 5-20 nm. the

By introducing the above-mentioned new diffusion barrier layer than using ALD to fabricate the diffusion barrier layer applied to nanoscale trench and via interconnection, not only the step coverage characteristics can be improved, but also the adhesion of the diffusion barrier layer and the interlayer insulating dielectric layer can be enhanced. , can form a barrier layer with better physical appearance, as few holes or gap defects as possible, and excellent resistance to Cu diffusion, so as to improve the shortcoming of large RC delay caused by the continuous reduction of integrated circuit feature size, and improve the performance of semiconductor chips. the

The preparation method of the copper interconnection structure provided by the present invention, concrete steps are as follows:

Chemically cleaned silicon-based substrates;

Forming a layer of etching barrier layer and insulating dielectric layer in sequence on the silicon wafer;

Through photolithography and etching processes, the interconnection position is defined at the insulating dielectric layer and the underlying etching barrier layer to form metal trenches or via holes;

Using the atomic layer deposition (ALD) method to grow a manganese silicate film on the trench or via hole as an anti-copper diffusion barrier layer;

growing a copper seed layer on the diffusion barrier layer;

Then directly electroplate copper to obtain a copper interconnection structure;

Finally, the wafer surface is planarized by a chemical mechanical polishing process.

Further, the material of the etch stop layer in the above method is silicon nitride. The material of the insulating medium layer is SiO ₂ , SiOF, SiCOH or porous SiCOH.

The manganese silicate thin film adopts ALD growth technology, the Mn reaction precursor used is Mn(EtCp) ₂ , the Si reaction precursor used is tris(dimethylaminosilane) (TDMAS), and the oxygen source used is H ₂ O, H ₂ O ₂ or O ₃ , the growth temperature is 200~300 ^o C, and the base pressure of the reaction is 1~4 Torr.

The copper seed layer on the diffusion barrier layer is also grown by ALD. The Cu reaction precursor used is Cu(acac) ₂ , or Cu(thd) ₂ , or [Cu( ^s Bu-amd)] ₂ , another reactant used is H ₂ , and the growth temperature is 150~250 ^o C, the base pressure of the reaction is 1~4 Torr.

Compared with the traditional copper diffusion barrier layer adopting TaN/Ta double-layer structure and the PVD preparation method used, the manganese silicate anti-copper diffusion barrier material used in the present invention can well block Diffusion of Cu, O and H ₂ O while maintaining good electrical properties. Moreover, using ALD to grow manganese silicate film, with its self-limiting growth characteristics and low process temperature, only a film with a thickness of about 0.03~0.1nm is formed in each growth cycle, which can achieve nanoscale width and high depth. In the higher ratio structure, the high conformal preparation of the Cu diffusion barrier layer avoids the generation of defects such as holes or gaps in the subsequent process, and reduces the contact resistance in the trench or through hole, thereby effectively improving the performance and reliability of the chip.

Description of drawings

Fig. 1-Fig. 5 is the sectional view of the integrated process of a kind of novel Cu diffusion barrier layer and copper interconnection implemented according to the present invention.

Numbers in the figure: 101 is a semiconductor substrate wafer, 102 is an etching barrier layer, 103 is an insulating dielectric layer, 104 is a diffusion barrier copper silicate film, 105 is a seed layer copper film, and 106 is an electroplated copper film.

Detailed ways

Embodiments of the present invention are described below with reference to the drawings. In the following description, the same reference numerals denote the same components, and repeated description thereof will be omitted.

The anti-Cu diffusion barrier layer manganese silicate and its preparation method proposed by the present invention can be applied to the subsequent copper interconnection structures of different integrated circuit technologies. The following describes the preparation of the copper interconnection diffusion barrier layer manganese silicate film Be the technological process of embodiment.

First, on the semiconductor wafer Si (100) substrate 101, the standard CMOS process is used to complete the cleaning of the silicon wafer, which mainly includes: using a mixed solution containing sulfuric acid and hydrogen peroxide, standard cleaning SC-1, SC-2 solution, diluting Hydrofluoric acid and deionized water were used to clean the Si substrate in sequence to remove various impurities and natural oxide layers, and dry it with high-purity _N2 . On the cleaned Si (100) substrate 101, a layer of etching stopper layer silicon nitride 102 and a dielectric layer 103 (such as SiO ₂ film) for interlayer insulation are deposited in sequence. Next, trenches or vias 201 for interconnect structures are formed using standard photolithography and etching processes.

Then, after the trench or via hole 201 is formed, the ALD is used to grow the manganese silicate diffusion barrier film 104 . The Mn reaction precursor used is Mn(EtCp) ₂ , the Si reaction precursor used is tris(dimethylaminosilane) (TDMAS), the oxygen source used is H ₂ O, H ₂ O ₂ or O ₃ , the growth temperature The temperature is 200~300 ^o C, and the base pressure of the reaction is 1~4 Torr. First, the Mn(EtCp) ₂ source was introduced into the reaction chamber for 1-5 s; the reaction chamber was purged with high-purity N ₂ for 1-10 s; then the oxygen source was introduced for 1-5 s; The reaction chamber was purged with high-purity N2 for 1-10 s, thus completing an ALD growth cycle of manganese oxide. According to the nature of the film, this cycle is repeated n times (n=1~20). Then, the TDMAS source was introduced into the reaction chamber for 1-5 s; the reaction chamber was purged with high-purity N2 for 1-10 s; the _oxygen source was introduced again for 1-5 s; Wash the reaction chamber for 1-10 s to complete a silicon oxide ALD growth cycle. Through the number of cycles of ALD growth of SiO ₂ , the content of Si in the entire manganese silicate film can be controlled, and the corresponding process parameters can be optimized to make the entire interconnection barrier layer have the best electrical and mechanical properties. Then repeat the ALD growth of manganese oxide and _SiO2 thin films with the same number of growth cycles before, until an ideal diffusion barrier layer thickness of 5-20 nm is obtained, as shown in FIG. 3 is the prepared manganese silicate diffusion barrier layer 103.

Next, after the manganese silicate diffusion barrier layer 104 is formed, a Cu seed layer 105 of about 10-30 nm is grown by ALD. The Cu reaction precursor used is Cu(acac) ₂ , or Cu(thd) ₂ , or [Cu( ^s Bu-amd)] ₂ , another reactant used is H ₂ , and the growth temperature is 150~250 ^o C, the base pressure of the reaction is 1~4 Torr. First, the Cu reaction precursor was introduced into the reaction chamber for 1-10 s; the reaction chamber was purged with high-purity N ₂ for 1-10 s; H2 was then introduced for 1-5 s; _2. Purge the reaction chamber for 1~10 s, thus completing an ALD growth cycle of the Cu seed layer. By repeating the above reaction cycle of growing Cu by ALD, a Cu seed layer 105 with a certain thickness can be obtained.

Then, copper wires 106 are electroplated in the trench or through-hole structure by electroless plating to form a copper interconnection structure, as shown in FIG. 4 .

Finally, chemical mechanical polishing (CMP) technology is used to planarize the wafer surface to complete the interconnection structure of one layer, as shown in FIG. 5, to prepare for the interconnection structure of the next layer.

The foregoing embodiment is only an example of the present invention, although the best embodiment of the present invention and the accompanying drawings are disclosed for the purpose of illustration, those skilled in the art can understand that: without departing from the spirit and scope of the present invention and the appended claims Inside, various substitutions, changes and modifications are possible. Therefore, the present invention should not be limited to what is disclosed in the preferred embodiments and drawings.

Claims (6)

1. a copper interconnection structure is the basis with the existing copper interconnection structure, it is characterized in that adopting the diffusion impervious layer of manganous silicate film as copper interconnection structure, and the thickness of manganous silicate film is 5 ~ 20 nm.

2. the preparation method of a copper interconnection structure is characterized in that concrete steps are:

The silicon-based substrate of chemical cleaning;

On silicon chip, form one deck etching barrier layer, insulating medium layer successively;

Through photoetching, etching technics, the etching barrier layer place below insulating medium layer reaches defines interconnect location, forms metal valley or through hole;

Utilize the atomic layer deposition method manganous silicate film of on groove or through hole, growing, as anti-copper diffusion barrier layer;

Growth layer of copper inculating crystal layer on diffusion impervious layer;

Direct Electroplating copper obtains copper interconnection structure again;

Use CMP process leveling wafer surface at last.

3. preparation method according to claim 2 is characterized in that, described dielectric layer material is SiO ₂, SiOF, SiCOH or porous SiCOH.

4. preparation method according to claim 2 is characterized in that, described etching barrier layer material is a silicon nitride.

5. preparation method according to claim 2 is characterized in that, when said ALD method was grown the silicic acid manganese film, the Mn reaction precursor body that uses was Mn (EtCp) ₂, the Si reaction precursor body of use is three (dimethylamino silane), the oxygen source that uses is H ₂O, H ₂O ₂Or O ₃, the temperature of reaction cavity is 200 ~ 300 ^oC, the base of reaction is pressed in 1 ~ 4 Torr.

6. preparation method according to claim 2 is characterized in that, described copper seed layer adopts the growth of ALD method, and the Cu reaction precursor body that uses is Cu (acac) ₂, Cu (thd) ₂Or [Cu ( ^sBu-amd)] ₂, the other a kind of reactant that uses is H ₂, growth temperature is 150 ~ 250 ^oC, the base of reaction is pressed in 1 ~ 4 Torr.

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