CN102693958A - Copper interconnection structure adopting novel diffusion impervious layer and preparation method thereof - Google Patents
Copper interconnection structure adopting novel diffusion impervious layer and preparation method thereof Download PDFInfo
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- CN102693958A CN102693958A CN2012102069163A CN201210206916A CN102693958A CN 102693958 A CN102693958 A CN 102693958A CN 2012102069163 A CN2012102069163 A CN 2012102069163A CN 201210206916 A CN201210206916 A CN 201210206916A CN 102693958 A CN102693958 A CN 102693958A
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Abstract
The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and specifically relates to a copper interconnection structure and a preparation method thereof. According to the invention, based on the existing copper interconnection structure, a manganese silicate film is used as a diffusion impervious layer of the copper interconnection structure. According to the invention, a manganese silicate film (5-20 nm) grows in a copper-interconnected groove and through hole structure by using an atomic layer deposition method, and the deposited film can achieve a good step coverage effect, therefore, the occurrence of defects such as holes and gaps can be significantly reduced. In addition, through adjusting the ratio of Si to Mn in the manganese silicate film, a better diffusion impervious capacity and a better adhesion property can be achieved. The structure and method disclosed by the invention have the advantages that the electromigration resistance of a copper-interconnected line can be increased, and the reliability of the copper-interconnected line in the copper interconnection applications of integrated circuits can be kept, so that an ideal interconnection process technology solution is provided for 45nm-and-below process technology nodes.
Description
Technical field
The invention belongs to semiconductor integrated circuit manufacturing technology field, be specifically related to a kind of copper interconnection structure and preparation method thereof.
Background technology
Integrated circuit technique is followed Moore's Law always, improves transistor density through continuous reduction of device size and increase wafer size, thereby reduces cost, and make its high speed development.But, after device feature size narrowed down to nanoscale, interconnect delay replaced the key factor that chip delays becomes influences chip performance gradually, made chip performance significantly reduce.In order to reduce the RC delay that interconnection line causes, the Cu interconnection has replaced the mainstream technology that the Al interconnection becomes inventionthe semiconductor industry circle gradually.
Metal Cu compares with traditional Al as the interconnect material of integrated circuit, mainly contains following advantage: the resistivity of (1) Cu is less.The resistivity of the Al of general body material is 2.7 μ Ω .cm, and the resistivity of Cu is 1.7 μ Ω .cm; (2) parasitic capacitance that causes of Cu interconnection line is come for a short time than aluminum interconnecting; What (3) the deelectric transferred ability force rate Al of Cu will be good is many.Under high current density, Cu deelectric transferred can force rate Al improve four one magnitude nearly, therefore can significantly reduce hole or the slit that produces owing to electromigration effect, can reduce leakage current, and greatly improve the reliability of device; (4) Cu also has hole characteristic that good anti-stress causes etc.; (5) thermal conductivity of Cu is better than Al, and silicon wafer is dispelled the heat through the encapsulating structure of outside faster, also can improve the reliability of wafer, prolongs the life-span of wafer.Therefore, adopt the Cu interconnection technique can satisfy the requirement of high frequency, high integration, high-power, big capacity and long-life advanced integrated circuit, make the technology node of nano-scale, the Al interconnection process is replaced by copper wiring technique gradually.
But, though adopt the Cu material can overcome Al metal material deficiency in the sky earlier, also exist a lot of problems need overcome solution as the technology of integrated circuit interconnection line.For example, metal Cu is easy to take place oxidation and makes moist and corrode under atmospheric environment, and Cu equally can form self protective layer unlike Al, therefore can influence the stability and the life-span of metal interconnecting wires.Moreover Cu has certain solubility when low temperature, and Cu and Si substrate react, and can form the silicide of Cu and makes component failure.In addition; The Cu atom has diffusivity fast; Under the acceleration at electric field, Cu will be easy to penetrate insulating medium layer and enter inside promptly arriving the Si substrate, in case Cu is diffused into and will causes Cu to penetrate transistorized interface with the Si effect in the silicon substrate and make the device phenomenon that is short-circuited.
At present, the high diffusibility problem between Cu and insulating medium layer or the Si generally adopts the double-decker of TaN/Ta to overcome as diffusion impervious layer.But the double-deck diffusion impervious layer of preparation TaN/Ta if crystallization degree is higher, can form the diffusion admittance of Cu at the crystal boundary place, the diffusion effect of aggravation Cu.And the double-deck adhesion of TaN/Ta is relatively poor, is prone to take place integrity problem.
In addition, the traditional preparation process method of TaN/Ta double-decker diffusion impervious layer mainly adopts physical vapor deposition (PVD) technology.But the PVD technology is because the step covering power is relatively poor; Groove and through hole filling capacity are not good; Can not satisfy metal-oxide semiconductor (MOS) (MOS) transistor device dimensions shrink to 45/32nm process node and following requirement, cause problems such as reliability variation easily.In order to reduce interconnection resistance, reduce the electric capacity between the interconnection and to improve reliability; Adopt the ALD technology nano level manganous silicate of one deck of growing, can in the filling process of groove and through hole, have good conformality; Improve the reliability of device, and can reduce interconnection RC delay effectively.
Summary of the invention
The object of the present invention is to provide excellent copper interconnection structure of a kind of anti-Cu diffusion and preparation method thereof, cause RC to postpone big shortcoming, promote the performance of semiconductor chip to improve continuous minimizing of integrated circuit characteristic size.
Copper interconnection structure provided by the invention is to be the basis with the existing copper interconnection structure, and its improvements are to adopt the diffusion impervious layer of manganous silicate film as copper interconnection structure, and the thickness of manganous silicate film is 5 ~ 20 nm.
Make the diffusion impervious layer that is applied to nano-scale trenches and through-hole interconnection through introducing above-mentioned novel diffusion impervious layer than adopting ALD; Can not only improve the step coverage property; And can strengthen the adhesion of diffusion impervious layer and layer insulation dielectric layer; Can form have the preferred physical pattern, the least possible hole or slit defective; Barrier layer with excellent anti Cu diffusion causes RC to postpone big shortcoming to improve continuous minimizing of integrated circuit characteristic size, promotes the performance of semiconductor chip.
The preparation method of copper interconnection structure provided by the invention, concrete steps are following:
The silicon-based substrate of chemical cleaning;
On silicon chip, form one deck etching barrier layer, insulating medium layer successively;
Through photoetching, etching technics, the etching barrier layer place below insulating medium layer reaches defines interconnect location, forms metal valley or through hole;
Utilize atomic layer deposition (ALD) the method manganous silicate film of on groove or through hole, growing, as anti-copper diffusion barrier layer;
Growth layer of copper inculating crystal layer on diffusion impervious layer;
Direct Electroplating copper obtains copper interconnection structure again;
Use CMP process leveling wafer surface at last.
Further, the etching barrier layer material described in the said method is a silicon nitride.Described dielectric layer material is SiO
2, SiOF, SiCOH or porous SiCOH.
Described manganous silicate film adopts the ALD growing technology, and the Mn reaction precursor body that uses is Mn (EtCp)
2, the Si reaction precursor body of use be three (dimethylamino silane) (TDMAS), the oxygen source that uses is H
2O, H
2O
2Or O
3, growth temperature is 200 ~ 300
oC, the base of reaction is pressed in 1 ~ 4 Torr.
Copper seed layer on the said diffusion impervious layer also adopts the ALD growing technology.The Cu reaction precursor body that uses is Cu (acac)
2, or Cu (thd)
2, or [Cu (
sBu-amd)]
2, the other a kind of reactant that uses is H
2, growth temperature is 150 ~ 250
oC, the base of reaction is pressed in 1 ~ 4 Torr.
Adopt the double-decker of TaN/Ta with traditional copper diffusion barrier layer, and the PVD preparation method who uses compares, the anti-copper diffusion barrier layer material of manganous silicate that the present invention uses, 5 ~ 20 nm are thick just can to stop Cu, O and H well
2The diffusion of O can keep good electrology characteristic simultaneously.And utilize the ALD manganous silicate film of growing, rely on its growth characteristics, lower technological temperature from restriction; Each growth cycle only forms the film that is about 0.03 ~ 0.1nm left and right thickness, and it is wide to can be implemented in nanoscale, in the structure of high depth ratio; High conformal prepares the Cu diffusion impervious layer; Avoid generation of defects such as hole or slit in the subsequent technique, reduced the contact resistance in groove or the through hole, thereby improved the Performance And Reliability of chip effectively.
Description of drawings
Fig. 1 – Fig. 5 is according to a kind of novel C u diffusion impervious layer of the present invention's enforcement and the integrated technique profile of copper-connection.
Label among the figure: 101 is the Semiconductor substrate wafer, and 102 is etching barrier layer, and 103 is insulating medium layer, and 104 is diffusion impervious layer cupric silicate film, and 105 is the inculating crystal layer copper film, and 106 is electroplated copper film.
Embodiment
Execution mode of the present invention is described with reference to the drawings below.In the description of back, identical Reference numeral is represented identical assembly, and it is repeated in this description omission.
Anti-Cu diffusion impervious layer manganous silicate proposed by the invention and preparation method thereof goes in the back road copper interconnection structure of different integrated circuit techniques, and below what narrated is the technological process of preparation copper interconnecting line diffusion impervious layer manganous silicate film for embodiment.
At first; On semiconductor wafer Si (100) substrate 101; Adopt standard CMOS process, accomplish the cleaning of silicon chip, mainly comprise: hydrofluoric acid and deionized water with the mixed solution that contains sulfuric acid and hydrogen peroxide solution, standard cleaning SC-1, SC-2 solution, dilution clean the Si substrate respectively in regular turn; Remove various impurity and natural oxidizing layer, and use high-purity N
2Dry up.On cleaned Si (100) substrate 101, in regular turn deposit one deck etching barrier layer silicon nitride 102, be used for layer insulation dielectric layer 103 (like SiO
2Film).Then, utilize the photoetching of standard and etching technics to form groove or the through hole 201 that interconnection structure is used.
Then, after groove or through hole 201 forms, begin to utilize the ALD manganous silicate diffusion barrier film 104 of growing.The Mn reaction precursor body that uses is Mn (EtCp)
2, the Si reaction precursor body of use be three (dimethylamino silane) (TDMAS), the oxygen source that uses is H
2O, H
2O
2Or O
3, growth temperature is 200 ~ 300
oC, the base of reaction is pressed in 1 ~ 4 Torr.At first, in reaction chamber, feed Mn (EtCp)
2The source, the time is 1 ~ 5 s; Use high-purity N
2Purge reaction chamber 1 ~ 10 s; Feed oxygen source again, the time is 1 ~ 5 s; With high-purity N 2 purge reaction chambers 1 ~ 10 s, accomplish the ALD growth cycle of a manganese oxide like this.According to the character of film, repeat such cycle n time (n=1 ~ 20).Then, in reaction chamber, feed the TDMAS source, the time is 1 ~ 5 s; With high-purity N 2 purge reaction chambers 1 ~ 10 s; Feed oxygen source again, the time is 1 ~ 5 s; Use high-purity N
2Purge reaction chamber 1 ~ 10 s accomplishes the ALD growth cycle of a silica like this.Through ALD growth SiO
2Periodicity, can be controlled at the content of Si in the whole manganous silicate film, optimize corresponding technological parameter, can be so that whole interconnect barrier has best electricity and mechanical performance.Then repeat manganese oxide, the SiO of ALD growth front isometric growth periodicity more respectively
2Film up to obtaining desirable diffusion barrier layer thickness 5 ~ 20 nm, is illustrated in figure 3 as the manganous silicate diffusion impervious layer 103 that preparation is accomplished.
Then, after forming manganous silicate diffusion impervious layer 104, again with the inculating crystal layer 105 of the Cu about ALD growth one deck 10 ~ 30 nm.The Cu reaction precursor body that uses is Cu (acac)
2, or Cu (thd)
2, or [Cu (
sBu-amd)]
2, the other a kind of reactant that uses is H
2, growth temperature is 150 ~ 250
oC, the base of reaction is pressed in 1 ~ 4 Torr.At first, in reaction chamber, feed Cu reaction precursor body, the time is 1 ~ 10 s; Use high-purity N
2Purge reaction chamber 1 ~ 10 s; Feed H2 again, the time is 1 ~ 5 s; Use high-purity N
2Purge reaction chamber 1 ~ 10 s accomplishes the ALD growth cycle of a Cu inculating crystal layer like this.Repeat the reaction time of above-mentioned ALD growth Cu, can obtain certain thickness Cu inculating crystal layer 105.
Then, use the electroless plating method, in groove or through-hole structure, electro-coppering lead 106 forms the copper interconnecting line structure, and is as shown in Figure 4.
At last,, accomplish the interconnection structure of one deck with the technological leveling wafer surface of chemico-mechanical polishing (CMP), as shown in Figure 5, for following one deck interconnection structure is prepared.
The foregoing description is of the present invention giving an example; Although disclose most preferred embodiment of the present invention and accompanying drawing for the purpose of illustration; But it will be appreciated by those skilled in the art that: in the spirit and scope that do not break away from the present invention and appended claim, various replacements, variation and modification all are possible.Therefore, the present invention should not be limited to most preferred embodiment and the disclosed content of accompanying drawing.
Claims (6)
1. a copper interconnection structure is the basis with the existing copper interconnection structure, it is characterized in that adopting the diffusion impervious layer of manganous silicate film as copper interconnection structure, and the thickness of manganous silicate film is 5 ~ 20 nm.
2. the preparation method of a copper interconnection structure is characterized in that concrete steps are:
The silicon-based substrate of chemical cleaning;
On silicon chip, form one deck etching barrier layer, insulating medium layer successively;
Through photoetching, etching technics, the etching barrier layer place below insulating medium layer reaches defines interconnect location, forms metal valley or through hole;
Utilize the atomic layer deposition method manganous silicate film of on groove or through hole, growing, as anti-copper diffusion barrier layer;
Growth layer of copper inculating crystal layer on diffusion impervious layer;
Direct Electroplating copper obtains copper interconnection structure again;
Use CMP process leveling wafer surface at last.
3. preparation method according to claim 2 is characterized in that, described dielectric layer material is SiO
2, SiOF, SiCOH or porous SiCOH.
4. preparation method according to claim 2 is characterized in that, described etching barrier layer material is a silicon nitride.
5. preparation method according to claim 2 is characterized in that, when said ALD method was grown the silicic acid manganese film, the Mn reaction precursor body that uses was Mn (EtCp)
2, the Si reaction precursor body of use is three (dimethylamino silane), the oxygen source that uses is H
2O, H
2O
2Or O
3, the temperature of reaction cavity is 200 ~ 300
oC, the base of reaction is pressed in 1 ~ 4 Torr.
6. preparation method according to claim 2 is characterized in that, described copper seed layer adopts the growth of ALD method, and the Cu reaction precursor body that uses is Cu (acac)
2, Cu (thd)
2Or [Cu (
sBu-amd)]
2, the other a kind of reactant that uses is H
2, growth temperature is 150 ~ 250
oC, the base of reaction is pressed in 1 ~ 4 Torr.
?
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017001953A1 (en) * | 2015-06-30 | 2017-01-05 | International Business Machines Corporation | Structure and fabrication method for electromigration immortal nanoscale interconnects |
| CN108047274A (en) * | 2017-12-15 | 2018-05-18 | 江南大学 | A kind of copper interconnection barrier layer material pyridyl group Mn（Ⅱ）Compound |
| CN112151504A (en) * | 2020-08-17 | 2020-12-29 | 复旦大学 | Copper interconnection structure with hole sealing layer and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6475913B1 (en) * | 1999-06-24 | 2002-11-05 | Hyundai Electronics Industries Co., Ltd. | Method for forming damascene type of metal wires in semiconductor devices |
| US20020192948A1 (en) * | 2001-06-15 | 2002-12-19 | Applied Materials, Inc. | Integrated barrier layer structure for copper contact level metallization |
| CN1697175A (en) * | 2004-02-27 | 2005-11-16 | 半导体理工学研究中心股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN101521175A (en) * | 2008-02-29 | 2009-09-02 | 台湾积体电路制造股份有限公司 | Semiconductor device and a manufacturing method therefor |
| CN102222641A (en) * | 2010-04-16 | 2011-10-19 | 台湾积体电路制造股份有限公司 | Method for forming a metal oxidation barrier layer of a copper interconnect |
-
2012
- 2012-06-21 CN CN2012102069163A patent/CN102693958A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6475913B1 (en) * | 1999-06-24 | 2002-11-05 | Hyundai Electronics Industries Co., Ltd. | Method for forming damascene type of metal wires in semiconductor devices |
| US20020192948A1 (en) * | 2001-06-15 | 2002-12-19 | Applied Materials, Inc. | Integrated barrier layer structure for copper contact level metallization |
| CN1697175A (en) * | 2004-02-27 | 2005-11-16 | 半导体理工学研究中心股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN101521175A (en) * | 2008-02-29 | 2009-09-02 | 台湾积体电路制造股份有限公司 | Semiconductor device and a manufacturing method therefor |
| CN102222641A (en) * | 2010-04-16 | 2011-10-19 | 台湾积体电路制造股份有限公司 | Method for forming a metal oxidation barrier layer of a copper interconnect |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017001953A1 (en) * | 2015-06-30 | 2017-01-05 | International Business Machines Corporation | Structure and fabrication method for electromigration immortal nanoscale interconnects |
| GB2555269A (en) * | 2015-06-30 | 2018-04-25 | Ibm | Structure and fabrication method for electromigration immortal nanoscale interconnects |
| GB2555269B (en) * | 2015-06-30 | 2020-10-07 | Tessera Inc | Structure and fabrication method for electromigration immortal nanoscale interconnects |
| CN108047274A (en) * | 2017-12-15 | 2018-05-18 | 江南大学 | A kind of copper interconnection barrier layer material pyridyl group Mn（Ⅱ）Compound |
| CN108047274B (en) * | 2017-12-15 | 2019-08-20 | 江南大学 | A kind of copper interconnection barrier layer material pyridyl group Mn (II) compound |
| CN112151504A (en) * | 2020-08-17 | 2020-12-29 | 复旦大学 | Copper interconnection structure with hole sealing layer and preparation method thereof |
| CN112151504B (en) * | 2020-08-17 | 2022-04-29 | 复旦大学 | Copper interconnection structure with hole sealing layer and preparation method thereof |
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Application publication date: 20120926 |