CN102024788B - Semiconductor device for interconnection process and manufacturing method thereof - Google Patents
Semiconductor device for interconnection process and manufacturing method thereof Download PDFInfo
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- CN102024788B CN102024788B CN 200910195811 CN200910195811A CN102024788B CN 102024788 B CN102024788 B CN 102024788B CN 200910195811 CN200910195811 CN 200910195811 CN 200910195811 A CN200910195811 A CN 200910195811A CN 102024788 B CN102024788 B CN 102024788B
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Abstract
The invention provides a semiconductor device for interconnection process, comprising a front-end device layer, a first barrier layer deposited on the front-end device layer, a first dielectric layer deposited on the first barrier layer and made of plasma enhanced tetraethoxysilane (PETEOS), a through hole penetrating through the first barrier layer and the first dielectric layer, a second barrier layer deposited on a metal layer and the first dielectric layer and a second dielectric layer deposited on the second barrier layer and made of PETEOS, wherein the through hole is filled with the metal layer. The invention solves the problem of wafer warpage in the copper interconnection process, especially the ultra thickness metal (UTM) process.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly copper interconnection wiring manufacture process.
Background technology
Along with improving constantly of chip integration, copper has replaced aluminium becomes the main flow interconnection technique of very lagre scale integrated circuit (VLSIC) in making.As the substitute of aluminium, copper conductor can reduce interconnection impedance, reduces power consumption and cost, improves integrated level, device density and the clock frequency of chip.The technique that copper interconnection structure forms deep trench is called as super thick metal (UTM) interconnection process, is generally used for making in the technique of radio frequency products inductor.
Figure 1A to 1D shows the schematic diagram of interconnection structure in traditional UTM technique.Shown in Figure 1A, on front end device layer 101, deposit the first barrier layer 102 with chemical vapour deposition (CVD) (CVD) method, material can be chosen as SiN, and thickness is 900～1100 dusts.The effect on this first barrier layer 102 is to prevent that the copper ion in the wiring layer of rear end from infiltrating and polluting adjacent layer and active area, and as the etching stopping layer of subsequent.Then deposit a layer thickness as the first dielectric layer 103 of 25000-35000 dust take the CVD method on the first barrier layer 102, material can be chosen as PEOX, for example silicon dioxide.Then, deposit the second barrier layer 104 with the CVD method on the first dielectric layer 103, material can be chosen as SiON, and thickness is 600～800 dusts.Then as shown in Figure 1B, etching through hole 110 on the first barrier layer 102, the first dielectric layer 103 and the second barrier layer 104.Then, shown in Fig. 1 C, fill metal level 111 with physical vapour deposition (PVD) (PVD) or plating mode, metal can be chosen as copper, removes part and whole the second barrier layer 104 that metal level 111 exceeds the first dielectric layer 103 in chemico-mechanical polishing (CMP) mode again.Next, shown in Fig. 1 D, the 3rd barrier layer 105 take CVD method deposition a layer thickness as 600～800 dusts on metal level 111 and the first dielectric layer 103, material can be chosen as SiN.Then, the second dielectric layer 106 take CVD method deposition a layer thickness as the 3000-4000 dust on the 3rd barrier layer 105, material can be chosen as PEOX, for example silicon dioxide.
In the process of making semiconductor device, can produce a large amount of heat in the CVD process, and in semiconductor device, be used to provide the thick copper layer of low-resistance interconnection current path or similar conductive layer, and the difference that thermal coefficient of expansion is arranged between its accompanying bottom silicon body wafer material, thereby the generation wafer distortion is the cave in arc attitude of peripheral perk of center wafer, makes chip warpage, this warpage that thicker metal level produces is more obvious, shown in Fig. 2 A.Shown in Fig. 2 B, after the CVD step, the angularity of wafer significantly increases, and reaches about about 250 microns.The warpage of wafer may be with badly influencing other processing technology of integrated circuit, such as ensuing lithography step, need the vacuum suction substrate to base station, if wafer distortion is serious, will affect adsoptivity, perhaps also can cause owing to absorption is not firm the photoetching process failure.In addition, the appearance of stress is so that wafer cracky more in subsequent step, and is particularly particularly evident when cutting in order to before encapsulating wafer being carried out attenuate.
The method of traditional solution metal warpage has three kinds.First method is to change the process conditions of filling metal level, such as filling speed, technological temperature etc.; Second method is the heat treatment step between filling metal level and the CMP metal level to be put into the CMP metal level carry out afterwards; The third method is the sedimentary condition that changes the second dielectric layer, such as deposition velocity, depositing temperature, deposition frequency etc.For first method and second method method, only carried out certain improvement to depositing the second dielectric layer chip warpage problem before, and the chip warpage problem after the second dielectric layer deposition is not done any solution.As for the third method, only the technique that deposits the second dielectric layer is made certain improvements, because the warpage of wafer just forms when forming the first metal layer, the method has little effect to the problem that solves chip warpage.So these three kinds of methods all do not reach better effect, can not solve preferably the problem of chip warpage, and probably change the characteristic of metal in the implementation process.
Therefore, need a kind ofly can to reduce copper wiring technique, particularly chip warpage degree and the method easily implemented in the UTM technique are for the smooth of wafer surface laid a good foundation.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to overcome copper wiring technique, particularly the problem of chip warpage in the UTM technique the invention provides a kind of semiconductor device for interconnection process, and described semiconductor device comprises: the front end device layer; On the first barrier layer that described front end device layer deposits; The material that deposits on described the first barrier layer is the first dielectric layer that plasma strengthens tetraethoxysilane; Pass the through hole that described the first barrier layer and described the first dielectric layer form, be filled with metal level in the described through hole; On the second barrier layer that described the first metal layer and described the first dielectric layer deposit; The material that deposits on described the second barrier layer is the second dielectric layer that plasma strengthens tetraethoxysilane.
According to a further aspect in the invention, also provide a kind of method, semi-conductor device manufacturing method for interconnection process, described manufacture method comprises: on front end device layer deposition the first barrier layer; Deposition materials is the first dielectric layer that plasma strengthens tetraethoxysilane on described the first barrier layer; On described the first dielectric layer deposition the second barrier layer; Pass described the first barrier layer, the second barrier layer and described the first dielectric layer and form through hole, in described through hole, fill metal level; Carry out chemico-mechanical polishing, remove part and the second barrier layer that metal level exceeds the first dielectric layer; On described metal level and described the first dielectric layer deposition the 3rd barrier layer; Deposition materials is the second dielectric layer that plasma strengthens tetraethoxysilane on described the 3rd barrier layer.
Adopt the angularity of the primary sample that the chip warpage degree of the interconnection layer of technique manufacturing of the present invention makes than traditional handicraft significantly to reduce, and technique is simple, easy to implement.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A to Fig. 1 D is the generalized section of traditional UTM interconnection structure;
Fig. 2 A and 2B are that chip warpage degree schematic diagram and chip warpage degree are with the changing trend diagram of processing step;
Fig. 3 A to Fig. 3 D is the generalized section that has heavily stressed dielectric layer structure according to of the present invention;
Fig. 4 be the chip warpage degree of traditional UTM interconnection structure with according to the chip warpage degree comparison diagram with UTM interconnection structure of heavily stressed dielectric layer structure of the present invention;
Fig. 5 is the manufacturing process flow diagram that has heavily stressed dielectric layer structure according to of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, detailed step will be proposed, so that how explanation the present invention utilizes heavily stressed dielectric layer structure in order to solve the problem of chip warpage in following description.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
, the present invention proposes and a kind ofly in copper interconnect wiring technique, use heavily stressed dielectric layer and overcome this problem because the warpage that effect of stress causes in order to overcome wafer in the UTM technique.With reference to Fig. 3 A to Fig. 3 D, the cutaway view according to each step in the fabrication processing of the UTM interconnection structure with heavily stressed dielectric layer structure of the present invention is shown.
At first, as shown in Figure 3A, deposit the first barrier layer 202 with chemical vapour deposition (CVD) (CVD) method on front end device layer 201, material is preferably SiN, and thickness is for being preferably 900～1100 dusts.The effect on this first barrier layer 202 is to prevent that the copper ion in the wiring layer of rear end from infiltrating and polluting adjacent layer and active area, and as the etching stopping layer of subsequent.Then on the first barrier layer 202, deposit a layer thickness as the first dielectric layer 203 of 25000-35000 dust take plasma reinforced chemical vapour deposition (PECVD) method, material is preferably plasma and strengthens tetraethoxysilane (PETEOS), the low frequency power of implementing the device of PECVD is preferably 150～190 watts, high frequency power is preferably 710～810 watts, depositing temperature is preferably 395～405 degrees centigrade, the PETEOS ply stress is-180～-80 MPas, and negative sign represents compression.Then, deposit the second barrier layer 204 with the CVD method on the first dielectric layer 203, material can be chosen as SiON, and thickness is 600～800 dusts.
Then, shown in Fig. 3 B, the second barrier layer 204 surperficial resist coatings, and finish the etching of through hole 210.Concrete technology is as follows: use N
2And O
2Mix gas-bearing formation body etching the second barrier layer 204 and the first dielectric layer 203, after running into the first barrier layer 202, use the CF gas etching instead, until penetrate the first barrier layer 202, form through hole 210.
Then, shown in Fig. 3 C, fill metal level 211 with physical vapour deposition (PVD) (PVD) or plating mode, described metal is copper preferably, removes part and whole the second barrier layer 204 that metal level 211 exceeds the first dielectric layer 203 in chemico-mechanical polishing (CMP) mode again.
Then, shown in Fig. 3 D, deposit the 3rd barrier layer 205 with the CVD method on metal level 211 and the first dielectric layer 203, material can be chosen as SiN, and thickness is 600～800 dusts.The second dielectric layer 206 take plasma reinforced chemical vapour deposition (PECVD) method deposition a layer thickness as 3600～4400 dusts on the 3rd barrier layer 205, material is preferably PETEOS, the low frequency power of implementing the device of PECVD is preferably 230～290 watts, high frequency power is preferably 780～940 watts, depositing temperature is preferably 395～405 degrees centigrade, and the PETEOS ply stress is-180～-80 MPas.
In the present invention, in conjunction with heavily stressed dielectric layer structure, the material of the first dielectric layer 103 in the traditional handicraft and the second dielectric layer 106 (shown in Fig. 1 D) has been carried out special selection, in order to effectively solve the warpage issues of wafer.Selected PETEOS dielectric layer and metal level have rightabout deformation.
To adopt measuring method according to the made sample with heavily stressed dielectric layer structure of above-mentioned technique, measure the chip warpage degree, i.e. the difference in height of Waffer edge point and its central point.As seen from Figure 4, the chip warpage degree that adopts technique of the present invention significantly reduces than the angularity of the primary sample that traditional handicraft is made.After whole technique was finished, the angularity of the wafer of employing technique of the present invention reduced general 100 microns than the angularity of primary sample, has reached thus the splendid effect that overcomes chip warpage.
The flow chart of Fig. 5 shows the UTM interconnection structure technological process with heavily stressed dielectric layer structure of making according to the embodiment of the invention.In step 501, on front end device layer deposition the first barrier layer, the effect of this layer is to prevent that the copper ion in the wiring layer of rear end from infiltrating and polluting adjacent layer and active area, and as the etching stopping layer of subsequent.Deposition the first dielectric layer on the first barrier layer, thickness is the 25000-35000 dust, material is preferably plasma and strengthens tetraethoxysilane (PETEOS), then deposits the second barrier layer with the CVD method on the first dielectric layer.In step 502, etching through hole on the first barrier layer, the second barrier layer and the first dielectric layer.In step 503, fill metal level with physical vapour deposition (PVD) or plating mode, remove part and whole the second barrier layer that metal level exceeds the first dielectric layer in the CMP mode again.In step 504, on metal level and the first dielectric layer deposition the 3rd barrier layer, on the 3rd barrier layer, deposit the second dielectric layer with the CVD method, thickness is 3600～4400 dusts, material is preferably PETEOS.
Also can be applicable to random layer in the multilayer interconnection wiring according to heavily stressed dielectric layer structure of the present invention, but be preferably applied to last one deck Wiring technique.Therefore, term front end device layer described here can refer to the front end active device, also can refer to front end interconnection wiring layer.
Semiconductor device according to the heavily stressed dielectric layer structure of aforesaid embodiment manufacturing can be applicable in the multiple integrated circuit (IC).For example be memory circuitry according to IC of the present invention, such as random access memory (RAM), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, such as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio frequency (RF) device or any other circuit devcies.IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (22)
1. a semiconductor device that is used for interconnection process is characterized in that, described semiconductor device comprises:
The front end device layer;
On the first barrier layer that described front end device layer deposits, described the first barrier layer is SiN;
The material that deposits on described the first barrier layer is the first dielectric layer that plasma strengthens tetraethoxysilane;
Pass the through hole that described the first barrier layer and described the first dielectric layer form, be filled with metal level in the described through hole;
On the second barrier layer that described metal level and described the first dielectric layer deposit;
The material that deposits on described the second barrier layer is the second dielectric layer that plasma strengthens tetraethoxysilane; Described the first dielectric layer and the second dielectric layer all have compression.
2. semiconductor device as claimed in claim 1 is characterized in that, the thickness of described the first dielectric layer is the 25000-35000 dust.
3. semiconductor device as claimed in claim 1, it is characterized in that, described the first dielectric layer is by plasma reinforced chemical vapour deposition method deposition, and the low frequency power of the radio-frequency unit of selecting is 150～190 watts, high frequency power is 710～810 watts, and depositing temperature is 395～405 degrees centigrade.
4. semiconductor device as claimed in claim 1 is characterized in that, the stress of described the first dielectric layer is-180～-80 MPas.
5. semiconductor device as claimed in claim 1, the thickness that it is characterized in that described the second dielectric layer is 3600～4400 dusts.
6. semiconductor device as claimed in claim 1, it is characterized in that, described the second dielectric layer is by plasma reinforced chemical vapour deposition method deposition, and the low frequency power of precipitation equipment is 230～290 watts, high frequency power is 780～940 watts, and depositing temperature is 395～405 degrees centigrade.
7. semiconductor device as claimed in claim 1 is characterized in that, the stress of described the second dielectric layer is-180～-80 MPas.
8. semiconductor device as claimed in claim 1 is characterized in that described metal level is copper.
9. semiconductor device as claimed in claim 1 is characterized in that described metal level is with physical vapour deposition (PVD) or plating mode filling.
10. semiconductor device as claimed in claim 1 is characterized in that, described front end device layer is front end active device or front end interconnection layer.
11. an integrated circuit that comprises semiconductor device as claimed in claim 1, wherein said integrated circuit is selected from dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC) and radio-frequency devices.
12. an electronic equipment that comprises semiconductor device as claimed in claim 1, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
13. a method, semi-conductor device manufacturing method that is used for interconnection process is characterized in that, described manufacture method comprises:
On front end device layer deposition the first barrier layer;
Deposition materials is the first dielectric layer that plasma strengthens tetraethoxysilane on described the first barrier layer;
On described the first dielectric layer deposition the second barrier layer;
Pass described the first barrier layer, the second barrier layer and described the first dielectric layer and form through hole, in described through hole, fill metal level;
Carry out chemico-mechanical polishing, remove part and the second barrier layer that metal level exceeds the first dielectric layer;
On described metal level and described the first dielectric layer deposition the 3rd barrier layer;
Deposition materials is the second dielectric layer that plasma strengthens tetraethoxysilane on described the 3rd barrier layer.
14. method, semi-conductor device manufacturing method as claimed in claim 13 is characterized in that, the thickness of described the first dielectric layer is the 25000-35000 dust.
15. method, semi-conductor device manufacturing method as claimed in claim 13, it is characterized in that, described the first dielectric layer is by plasma reinforced chemical vapour deposition method deposition, and the low frequency power of precipitation equipment is 150～190 watts, high frequency power is 710～810 watts, and depositing temperature is 395～405 degrees centigrade.
16. method, semi-conductor device manufacturing method as claimed in claim 13 is characterized in that, the stress of described the first dielectric layer is-180～-80 MPas.
17. method, semi-conductor device manufacturing method as claimed in claim 13 is characterized in that, the thickness of described the second dielectric layer is 3600～4400 dusts.
18. method, semi-conductor device manufacturing method as claimed in claim 13, it is characterized in that, described the second dielectric layer is by plasma reinforced chemical vapour deposition method deposition, the low frequency power of the radio-frequency unit of selecting is 230～290 watts, high frequency power is 780～940 watts, and depositing temperature is 395～405 degrees centigrade.
19. method, semi-conductor device manufacturing method as claimed in claim 13 is characterized in that, the stress of described the second dielectric layer is-180～-80 MPas.
20. method, semi-conductor device manufacturing method as claimed in claim 13 is characterized in that, described metal level is copper.
21. method, semi-conductor device manufacturing method as claimed in claim 13 is characterized in that, described metal level is filled with physical vapour deposition (PVD) or plating mode.
22. method, semi-conductor device manufacturing method as claimed in claim 13 is characterized in that, described front end device layer is front end active device or front end interconnection layer.
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| CN105460883B (en) * | 2014-09-05 | 2017-11-14 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN111128868A (en) * | 2019-12-25 | 2020-05-08 | 上海华力集成电路制造有限公司 | Method for improving flatness of wafer in ultra-thick metal interconnection process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1158002A (en) * | 1995-10-03 | 1997-08-27 | 德克萨斯仪器股份有限公司 | Intermetal dielectric planarization ULSI circuits |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1158002A (en) * | 1995-10-03 | 1997-08-27 | 德克萨斯仪器股份有限公司 | Intermetal dielectric planarization ULSI circuits |
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