CN107293513A - A kind of semiconductor devices and its manufacture method and electronic installation - Google Patents
A kind of semiconductor devices and its manufacture method and electronic installation Download PDFInfo
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- CN107293513A CN107293513A CN201610220688.3A CN201610220688A CN107293513A CN 107293513 A CN107293513 A CN 107293513A CN 201610220688 A CN201610220688 A CN 201610220688A CN 107293513 A CN107293513 A CN 107293513A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
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Abstract
The invention provides a kind of semiconductor devices and its manufacture method and electronic installation.Methods described includes：The first substrate is provided, first substrate has first surface and second surface on the other side, is formed with function material layer in the first surface side of first substrate, transistor and the first interconnection structure are formed with the function material layer；The first metal layer at top, the second metal layer at top and the 3rd metal layer at top for being embedded in the functional material layer surface are formed, first metal layer at top is electrically connected with first interconnection structure；Second substrate is provided, the second substrate is engaged with the function material layer；Reduction processing is carried out to first substrate from the second surface side；Second metal layer and conductive plunger are formed simultaneously, and the second metal layer is electrically connected with second metal layer at top, and the conductive plunger is electrically connected with the 3rd metal layer at top.Methods described processing step is simpler, improves the performance and yield of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its
Manufacture method and electronic installation.
Background technology
In technical field of semiconductors, with radio circuit (RF) working frequency and integrated level
Raising, influence of the backing material to circuit performance be increasing.Silicon-on-insulator (SOI)
Substrate because its good electric property and it is compatible with CMOS technology the characteristics of, in radio circuit
It is widely used Deng field.
In existing two-sided thin SOI technology, when embedded IP D techniques are done in front,
The Cu layers of several thickness are needed plus done, the stress of full wafer wafer can be increased, cause the exception of technique,
And make that preparation technology is cumbersome, dramatically increase cost.
Therefore, it is to solve above-mentioned technical problem of the prior art, it is necessary to propose a kind of new
Semiconductor devices and its manufacture method and electronic installation.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be specific real
Apply in mode part and be further described.The Summary of the present invention is not meant to
Attempt to limit the key feature and essential features of technical scheme claimed, less
Mean the protection domain for attempting to determine technical scheme claimed.
In order to overcome the problem of presently, there are, the embodiments of the invention provide a kind of semiconductor devices
Manufacture method, methods described includes：
The first substrate is provided, first substrate has first surface and the second table on the other side
Face, is formed with function material layer, in the function in the first surface side of first substrate
Transistor and the first interconnection structure are formed with material layer；
Form the first metal layer at top, the second top-gold for being embedded in the functional material layer surface
Belong to layer and the 3rd metal layer at top, first metal layer at top and first interconnection structure electricity
Connection；
The second substrate is provided, by the function of second substrate and first substrate surface
Material layer is engaged；
Reduction processing is carried out to first substrate from the second surface side；
Second metal layer and conductive plunger are formed simultaneously, and the second metal layer and the conduction are inserted
Plug formed from the second surface side of first substrate, and the second metal layer with
The second metal layer at top electrical connection, the conductive plunger and the 3rd metal layer at top electricity
Connection.
Alternatively, methods described also includes：
Bottom metal layers and pad layer are formed simultaneously in the second surface side, wherein the bottom
Portion's metal level is located at the lower section of the second metal layer, and the pad layer is located at the conductive plunger
Lower section.
Alternatively, methods described is still further comprised：
In the bottom metal layers and the passivation layer formed below of the pad layer, described in covering
Bottom metal layers and the pad layer；
The passivation layer is patterned, with pad layer described in exposed portion.
Alternatively, first substrate is silicon-on-insulator substrate, including body silicon from bottom to top,
Buried oxide and top layer silicon.
Alternatively, forming the second metal layer and the method for the conductive plunger includes：
Since the second surface of first substrate, buried oxide and dielectric are sequentially etched
Layer is to second metal layer at top and the 3rd metal layer at top is exposed, to form opening；
Metal material is filled in said opening, to form the second metal layer and the conduction
Connector.
Alternatively, the first substrate bag radio-frequency devices region, integrated passive devices region and weldering
Disk area, the transistor, the first interconnection structure and radio-frequency devices are formed at the radio-frequency devices
Region, second metal layer at top and second metal layer are formed at the integrated passive devices area
Domain, the 3rd metal layer at top and the conductive plunger are formed at the welding disking area.
Alternatively, second metal layer at top is in the curvilinear structures of snail.
Present invention also offers a kind of semiconductor devices, the semiconductor devices includes：
First substrate, first substrate has first surface and second surface on the other side,
Function material layer is formed with the first surface side of first substrate, in the functional material
Transistor and the first interconnection structure are formed with layer；
First metal layer at top, in the function material layer and positioned at the described first interconnection
The top of structure, first metal layer at top is electrically connected with first interconnection structure；
Second metal layer at top and the 3rd metal layer at top, in the function material layer and
Positioned at the outside of first metal layer at top；
Second metal layer, is formed at the second surface of first substrate, positioned at described
The lower section of two metal layer at top and electrically connected with second top metal；
Conductive plunger, is formed at the second surface of first substrate, positioned at the described 3rd
The lower section of metal layer at top and electrically connected with the 3rd top metal；
Second substrate, the function material layer of second substrate and first substrate surface
Engage.
Alternatively, the semiconductor devices also includes bottom metal layers and pad layer, wherein described
Bottom metal layers are located at the lower section of the second metal layer and electrically connected with the second metal layer,
The pad layer is located at the lower section of the conductive plunger and electrically connected with the conductive plunger.
Alternatively, the semiconductor devices also includes bottom metal layers and pad layer, wherein described
Bottom metal layers are located at the lower section of the second metal layer, and the pad layer is located at described conductive slotting
The lower section of plug.
Alternatively, the semiconductor devices also includes second table for covering first substrate
Face but expose the pad routing area passivation layer.
Alternatively, it is characterised in that first substrate is silicon-on-insulator substrate.
The invention provides a kind of electronic installation, including above-mentioned semiconductor devices.
In order to solve problem present in current technique, the present invention is prepared in the semiconductor devices
In the order in processing step is changed, be no longer to be initially formed conductive plunger and then to re-form
The step of second metal layer at top, but forming the first top-gold above the first interconnection structure
The second metal layer at top (being used to form passive device) and the 3rd top-gold are formed during category layer simultaneously
Belong to layer (be used for electrically connect the second interconnection structure), form second metal layer at top and the
After three metal layer at top, then form second metal layer and conductive plunger simultaneously, respectively with it is described
Second metal layer at top and the electrical connection of the 3rd metal layer at top, will form the technique of second metal layer
Integrated with the technique for forming the conductive plunger, solve the multiple steps of needs and form difference
The step of metal level of device so that processing step is simpler, stress in technique is reduced,
The cost of semiconductor devices is further reduced, the performance and yield of device can also be improved.
The semiconductor devices of the present invention, as a result of above-mentioned manufacture method, thus equally has
Above-mentioned advantage.The electronic installation of the present invention, as a result of above-mentioned semiconductor device, thus together
Sample has above-mentioned advantage.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 is a kind of manufacture method of semiconductor devices of an alternative embodiment of the invention
Indicative flowchart；
Fig. 2A-Fig. 2 E be one embodiment of the invention in a kind of semiconductor devices manufacturer
The sectional view of the structure of the correlation step formation of method；
Fig. 3 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, and it will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from beginning to end
Icon note represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then in the absence of element or layer between two parties.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term is limited.These terms be used merely to distinguish element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience herein and by using from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.If for example, the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, element, the presence or addition of part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
Herein with reference to the horizontal stroke of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Sectional view come describe invention embodiment.As a result, it is contemplated that due to such as manufacturing technology and/
Or the change caused by tolerance from shown shape.Therefore, embodiments of the invention should not limit to
Given shape in area shown here, but including inclined due to for example manufacturing caused shape
Difference.For example, be shown as the injection region of rectangle generally has circle at its edge or bending features and
/ or implantation concentration gradient, rather than the binary change from injection region to non-injection regions.Equally,
The surface passed through when by injecting the disposal area formed the disposal area and injection can be caused to carry out
Between area in some injection.Therefore, the area shown in figure be substantially it is schematical, it
Shape be not intended display device area true form and be not intended limit the present invention
Scope.
In order to thoroughly understand the present invention, detailed step and in detail will be proposed in following description
Thin structure, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is detailed
Carefully it is described as follows, but in addition to these detailed descriptions, the present invention can also have other implementations
Mode.
There is provided a kind of semiconductor devices in order to solve the problem of current technique is present by the present invention
Manufacture method, methods described includes：
The first substrate is provided, first substrate has first surface and the second table on the other side
Face, is formed with function material layer, in the function in the first surface side of first substrate
Transistor and the first interconnection structure are formed with material layer；
Form the first metal layer at top, the second top-gold for being embedded in the functional material layer surface
Belong to layer and the 3rd metal layer at top, first metal layer at top and first interconnection structure electricity
Connection；
The second substrate is provided, by the function of second substrate and first substrate surface
Material layer is engaged；
Reduction processing is carried out to first substrate from the second surface side；
Second metal layer and conductive plunger are formed simultaneously, and the second metal layer and the conduction are inserted
Plug formed from the second surface side of first substrate, and the second metal layer with
The second metal layer at top electrical connection, the conductive plunger and the 3rd metal layer at top electricity
Connection.
Forming the method for the second metal layer and the conductive plunger includes：
Since the second surface of first substrate, buried oxide and dielectric are sequentially etched
Layer is to second metal layer at top and the 3rd metal layer at top is exposed, to form opening；
Metal material is filled in said opening, to form the second metal layer and the conduction
Connector.
Wherein, the integrated level of the semiconductor devices is high in the present invention, is not simply formed with radio frequency
Device is also formed with passive device and the structure (such as electrostatic preventing structure) comprising pad,
Therefore how to make all techniques can be each other the progress integration of all techniques in preparation process
Compatibility turns into the problem of needing to pay special attention to.
In order to solve problem present in current technique,
The present invention is changed in semiconductor devices preparation to the order in processing step,
No longer it is to be initially formed the step of then conductive plunger re-forms the second metal layer at top, but in shape
The second metal layer at top is formed during the first metal layer at top above into the first interconnection structure simultaneously
(being used to form passive device) and the 3rd metal layer at top (are used to electrically connect the second mutually link
Structure), after second metal layer at top and the 3rd metal layer at top is formed, then shape simultaneously
Into second metal layer and conductive plunger, respectively with second metal layer at top and the 3rd top-gold
Belong to layer electrical connection, the technique for forming second metal layer and the technique for forming the conductive plunger are entered
Row is integrated, the step of solving the metal level for needing multiple step formation different components so that work
Skill step is simpler, reduces stress in technique, further the cost of reduction semiconductor devices,
The performance and yield of device can also be improved.
The semiconductor devices of the present invention, as a result of above-mentioned manufacture method, thus equally has
Above-mentioned advantage.The electronic installation of the present invention, as a result of above-mentioned semiconductor device, thus together
Sample has above-mentioned advantage.
Embodiment one
Below, reference picture 1 and Fig. 2A to Fig. 2 E propose to describe the embodiment of the present invention
The detailed step of one illustrative methods of manufacture method of semiconductor devices.Wherein, Fig. 1 is this
A kind of indicative flowchart of the manufacture method of semiconductor devices of another embodiment of invention,
Specifically include：
Step S1：The first substrate is provided, first substrate has first surface and therewith phase
To second surface, be formed with function material layer in the first surface side of first substrate,
Transistor and the first interconnection structure are formed with the function material layer；
Step S2：Formed be embedded in the functional material layer surface the first metal layer at top,
Second metal layer at top and the 3rd metal layer at top, first metal layer at top and described first
Interconnection structure is electrically connected；
Step S3：The second substrate is provided, by second substrate and first substrate surface
The function material layer engage；
Step S4：Reduction processing is carried out to first substrate from the second surface side；
Step S5：Form second metal layer and conductive plunger simultaneously, the second metal layer and
The conductive plunger is formed from the second surface side of first substrate, and described
Two metal levels are electrically connected with second metal layer at top, the conductive plunger and the described 3rd top
Portion's metal level electrical connection.
The manufacture method of the semiconductor devices of the present embodiment, specifically includes following steps：
Perform step one there is provided the first substrate 100, first substrate have first surface and
Second surface on the other side, functional material is formed in the first surface side of first substrate
The bed of material, is formed with the interconnection structure of transistor 1011 and first in the function material layer；Shape
Into the first metal layer at top 1012, the second top-gold for being embedded in the functional material layer surface
Belong to the metal layer at top 103 of layer 102 and the 3rd, first metal layer at top and described first mutual
Link structure electrical connection.
As shown in Figure 2 A there is provided the first substrate 100, the first of first substrate 100
Surface side forms the front end for the first interconnection structure for including transistor 1011 and being positioned above
Device.
Subsequent technique is also formed with the outside of first interconnection structure of the front-end devices
In the metal layer at top of passive device that will be formed, i.e. the second metal layer at top 102 and will
The metal layer at top above the second interconnection structure formed, i.e. the 3rd metal layer at top 103, its
In, formation and first top-gold of second metal layer at top and the 3rd metal layer at top
Category layer is formed simultaneously.
Specifically, the first substrate 100 can be at least one of following material being previously mentioned：
Silicon, silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, on insulator it is laminated germanium
SiClx (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI)
Deng.As an example, in the present embodiment, the first substrate 100 is silicon-on-insulator (SOI), bag
Include body silicon 1001, buried oxide 1002 and top layer silicon 1003 from bottom to top.
Wherein, the first substrate bag radio-frequency devices region (RF), integrated passive devices region
(integrated passive device, IPD) and welding disking area (PAD).
Wherein, the bottom metal formed in semiconductor devices of the present invention in subsequent step
The second metal layer at top formed in layer, second metal layer and the step collectively forms passive device
The pad layer that is formed in part, subsequent step, conductive plunger constitute the second interconnection architecture and with the 3rd
Metal layer at top is electrically connected, the interconnection structure of transistor 1011 and first and the described first top
Portion's metal level formation front-end devices.
Wherein, the front-end devices include radio-frequency devices and are formed at the radio-frequency devices region,
The passive device is located at the integrated passive devices region, and second interconnection structure is located at institute
State welding disking area.
Alternatively, the passive device can include metal-insulating layer-metal capacitor (MIM),
Spiral inductor etc..
As an example, being also formed with radio-frequency devices on the first surface of the first substrate.In this reality
Apply in example, transistor 1011 is used to constitute various circuits, and radio-frequency devices are used to form radio frequency group
Part or module, the first interconnection structure are used to connect transistor 1011, radio-frequency devices and front end
Other assemblies in device.
Wherein, transistor 1011 can for normal transistor, high-k/metal gate transistors,
Fin transistor or other suitable transistors.First interconnection structure can include metal level (example
Such as layers of copper or aluminium lamination), metal plug.Radio-frequency devices can include inductance (inductor) etc.
Device.
In addition to including transistor 1011, radio-frequency devices and the first interconnection structure, front-end devices are also
Other various feasible components can be included, such as resistance, electric capacity, MEMS,
It is not defined herein.
Wherein, the concrete structure and forming method of each component in front-end devices, this area
Technical staff can be selected with reference to prior art according to actual needs, and here is omitted.
Wherein, second metal layer at top and the 3rd metal layer at top can be described first
Metal layer at top is formed while making, and its forming method can select conventional preparation method,
Function material layer for example is being formed, then such as dielectric layer patterns to the dielectric layer,
It is open with being formed and from the conductive material filling opening, sequentially forms each metal level and lead
Electric plug, to form the interconnection architecture, further sinks after the metal layer at top is formed
Product dielectric layer, to cover the metal layer at top and planarize, as shown in Figure 2 A.
Wherein, first metal layer at top, the second metal layer at top and the 3rd top-gold
Category layer choosing uses metal material Al, the metal material Al deposition process to be chemical gaseous phase
(CVD) method of deposition, physical vapour deposition (PVD) (PVD) method or ald (ALD)
Low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the choosing of the formation such as method
One kind in epitaxial growth (SEG) is selected, in the present invention preferably physical vapour deposition (PVD) (PVD)
Method.
Step 2 is performed there is provided the second substrate 200, by second substrate and the described first lining
The function material layer of basal surface is engaged.
Specifically, as shown in Figure 2 B, in the present embodiment, the second substrate 200 can be half
Conductor substrate or carrying substrate (carrier wafer).
Alternatively, second substrate 200 is carrying substrate (carrier in this embodiment
Wafer), for after technique subsequently to the first substrate 100 progress reduction processing and other
Carrying and protection front-end devices in continuous technique.
Further, the second substrate 200 can be common silicon substrate or other suitable substrates,
This is not defined.
By bonding technology by by the work(of second substrate and first substrate surface
Energy material layer engages (bonding), as shown in Figure 2 B.Wherein, bonding technology can be using this
Any method is carried out known to art personnel, such as oxide fusion bonding technology.
Step 3 is performed, first substrate is carried out from thinned from the second surface side
Reason.
Specifically, as shown in Figure 2 C, first substrate 100 is SOI substrate, and this is thinned
Processing is stopped on the buried oxide 1002 in SOI substrate.
Wherein, the reduction processing can be for CMP (cmp) or other are suitable
Method.
Step 4 is performed, while form second metal layer 105 and conductive plunger 104, described the
Two metal levels and the conductive plunger are formed from the second surface side of first substrate,
And the second metal layer 105 is electrically connected with second metal layer at top 102, described to lead
Electric plug 104 is electrically connected with the 3rd metal layer at top 103.
Specifically, as shown in Figure 2 D, in the second surface side shape of first substrate
Into the second metal layer 105, while forming the method for the conductive plunger 104 includes：
First, since the second surface of first substrate, it is sequentially etched buried oxide
With dielectric layer to second metal layer at top and the 3rd metal layer at top is exposed, to be formed
Opening；
Then, metal material is filled in said opening, to form the second metal layer and institute
State conductive plunger.
Specifically, as shown in Figure 2 D, the second surface from first substrate 100 is opened
Begin, etch first substrate 100, until the exposure metal layer at top, to form opening.
Exemplarily, when first substrate 100 is SOI substrate, from first substrate
100 second surface starts, and is sequentially etched buried oxide 1002 and dielectric layer, until
The exposure metal layer at top.
Wherein, the etching for buried oxide 1002 be able to can also both have been adopted using dry etching
Use wet etching.Dry etching can use the anisotropic etching method based on carbon fluoride gas.
Wet etching can use hydrofluoric acid solution, such as buffer oxide etch agent
(buffer oxide etchant (BOE)) or hydrofluoric acid cushioning liquid
(buffer solution of hydrofluoric acid (BHF)), etching stopping is in metal layer at top.
Then metal material is filled in said opening, to form conductive plunger and second gold medal
Belong to layer.
Wherein, the metal material can select copper, gold, silver, tungsten and other similar materials,
Physical vapour deposition (PVD) can be passed through as conductive material from metallic copper in this embodiment
(PVD), chemical vapor deposition (CVD) or the method for Cu electroplating (ECP) are filled out
Fill the opening.
Preferably, in this embodiment, in order to reduce because dead resistance and parasitic capacitance cause
The RC delay times, in the present invention between the metal material is deposited, be additionally included in institute
State the step of forming barrier layer (not shown) in opening.
Further, copper barrier layer (copper barrier), the copper can be formed in the present invention
The forming method on barrier layer (copper barrier) can be mainly to select physical vaporous deposition
And chemical vapour deposition technique, specifically, evaporation, electron beam evaporation, plasma can be selected
Jet deposition and sputtering, in the present invention preferred plasma spray deposition and sputtering method shape
Into the copper barrier layer.The thickness of the copper barrier layer is not limited to a certain numerical value or scope
It is interior, it can be adjusted as needed.
Then the opening is filled from metallic copper, in this embodiment preferred Cu electroplating
(ECP) method fills the groove, needs to fill the groove in the present invention, therefore
Additive is needed to use in plating, the additive is flat dose (LEVELER), is accelerated
Agent (ACCELERATORE) and inhibitor (SUPPRESSOR).
Preferably, can also further include the step of annealing after the metallic copper is formed being formed
Suddenly, annealing can be carried out 2-4 hours at 80-160 DEG C, to promote, with recrystallizing, to grow up
Crystal grain, reduction resistance and raising stability.
Wherein, the integrated level of the semiconductor devices is high in the present invention, is not simply formed with radio frequency
Device is also formed with passive device and the structure (such as electrostatic preventing structure) comprising pad,
Therefore how to make all techniques can be each other the progress integration of all techniques in preparation process
Compatibility turns into the problem of needing to pay special attention to.
The present invention is changed in semiconductor devices preparation to the order in processing step,
No longer it is to be initially formed the step of then conductive plunger re-forms the second metal layer at top, but in shape
The second metal layer at top is formed during the first metal layer at top above into the first interconnection structure simultaneously
(being used to form passive device) and the 3rd metal layer at top (are used to electrically connect the second mutually link
Structure), after second metal layer at top and the 3rd metal layer at top is formed, then shape simultaneously
Into second metal layer and conductive plunger, respectively with second metal layer at top and the 3rd top-gold
Belong to layer electrical connection, the technique for forming second metal layer and the technique for forming the conductive plunger are entered
Row is integrated, the step of solving the metal level for needing multiple step formation different components so that work
Skill step is simpler, reduces stress in technique, further the cost of reduction semiconductor devices,
The performance and yield of device can also be improved.
The semiconductor devices of the present invention, as a result of above-mentioned manufacture method, thus equally has
Above-mentioned advantage.The electronic installation of the present invention, as a result of above-mentioned semiconductor device, thus together
Sample has above-mentioned advantage.
Perform step 5, the second metal layer bottom formed below in the second surface side
Portion's metal level 107, while the conduction of the second interconnection structure in the second surface side
Connector pad layer 106 formed below.
Alternatively, as shown in Figure 2 E, bottom metal layers 107 are formed in the second surface side
With pad layer 106, wherein, the pad layer 106 be used for by signal or power supply it is mutual by second
Link structure and the first interconnection structure is input to the inside of semiconductor devices.
Wherein, the material of pad layer 106 can be aluminium, copper or other suitable conductive materials.
It can deposit to be formed using methods such as physical vapour deposition (PVD), chemical vapor depositions.
The bottom metal layers 107 and pad layer 106 select metallic aluminium in this embodiment.
Step 6 is performed, in the passivation formed below of the bottom metal layers and the pad layer
Layer, to cover the bottom metal layers and the pad layer；The passivation layer is patterned, to reveal
Go out the part pad layer.
In one example, the second surface of covering first substrate 100 is formed but sudden and violent
Expose the passivation layer 108 in the routing area of the pad layer 106.
Wherein, passivation layer 108 is used to protect the first substrate 100 and pad layer 106.Passivation
The material of layer 108 can be silicon nitride or other suitable materials.Chemical vapor deposition can be used
Deposit to form passivation layer 108 etc. method.
So far, Jie of the committed step of the manufacture method of the semiconductor devices of the present embodiment is completed
Continue.By above-mentioned steps, the structure of two-sided thin SOI (silicon-on-insulator) is formd.Connect down
The manufacture of whole semiconductor devices can also be completed according to existing various methods.
In order to solve problem present in current technique, the present invention is prepared in the semiconductor devices
In the order in processing step is changed, be no longer to be initially formed conductive plunger and then to re-form
The step of second metal layer at top, but forming the first top-gold above the first interconnection structure
The second metal layer at top (being used to form passive device) and the 3rd top-gold are formed during category layer simultaneously
Belong to layer (be used for electrically connect the second interconnection structure), form second metal layer at top and the
After three metal layer at top, then form second metal layer and conductive plunger simultaneously, respectively with it is described
Second metal layer at top and the electrical connection of the 3rd metal layer at top, will form the technique of second metal layer
Integrated with the technique for forming the conductive plunger, solve the multiple steps of needs and form difference
The step of metal level of device so that processing step is simpler, stress in technique is reduced,
The cost of semiconductor devices is further reduced, the performance and yield of device can also be improved.
Embodiment two
The embodiment of the present invention provides a kind of semiconductor devices, and it uses the system in previous embodiment one
The method of making is prepared.The semiconductor devices, can be to include the collection of radio frequency (RF) device
Into circuit or integrated circuit intermediate products.
Below, reference picture 2E come describe the embodiment of the present invention proposition semiconductor devices one kind
Structure.Wherein, Fig. 2 E are a kind of section view of the structure of the semiconductor devices of the embodiment of the present invention
Figure.
As shown in Figure 2 E, the semiconductor devices of the present embodiment includes：
First substrate 100, first substrate has first surface and the second table on the other side
Face, is formed with function material layer, in the function in the first surface side of first substrate
The interconnection structure of transistor 1011 and first is formed with material layer, first interconnection structure
Top is provided with the first metal layer at top 1012, in the outer of first metal layer at top 1012
Side is separated with the second metal layer at top 102 and the 3rd metal layer at top 103 each other, described
Second metal layer 105 is provided with below two metal layer at top, in the 3rd metal layer at top
Lower section be provided with conductive plunger 104；
Second substrate 200, second substrate and the function with first substrate surface
Material layer is engaged.
Specifically, the first substrate 100 can be at least one of following material being previously mentioned：
Silicon, silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, on insulator it is laminated germanium
SiClx (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI)
Deng.As an example, in the present embodiment, the first substrate 100 is silicon-on-insulator (SOI), bag
Include body silicon 1001, buried oxide 1002 and top layer silicon 1003 from bottom to top.
Alternatively, the semiconductor devices also includes bottom metal layers 107 and pad layer 106,
Wherein described bottom metal layers are located at the lower section of the second metal layer, and the pad layer is located at institute
State the lower section of conductive plunger.
Wherein, the bottom metal layers, the second metal layer and the second metal layer at top are common
Passive device is constituted, the pad layer, conductive plunger constitute the second interconnection architecture and pushed up with the 3rd
Portion's metal level electrical connection, the interconnection structure of transistor 1011 and first and the described first top
Metal level formation front-end devices.
Wherein, the first substrate bag radio-frequency devices region (RF), integrated passive devices region
(integrated passive device, IPD) and welding disking area (PAD), the front-end devices
Including radio-frequency devices and the radio-frequency devices region is formed at, the passive device is located at the collection
Into passive device region, second interconnection structure is located at the welding disking area.
Alternatively, the passive device can include metal-insulating layer-metal capacitor (MIM),
Spiral inductor etc..
As an example, being also formed with radio-frequency devices on the first surface of the first substrate.In this reality
Apply in example, transistor 1011 is used to constitute various circuits, and radio-frequency devices are used to form radio frequency group
Part or module, the first interconnection structure are used to connect transistor 1011, radio-frequency devices and front end
Other assemblies in device.
Wherein, transistor 1011 can for normal transistor, high-k/metal gate transistors,
Fin transistor or other suitable transistors.First interconnection structure can include metal level (example
Such as layers of copper or aluminium lamination), metal plug.Radio-frequency devices can include inductance (inductor) etc.
Device.
In addition to including transistor 1011, radio-frequency devices and the first interconnection structure, front-end devices are also
Other various feasible components can be included, such as resistance, electric capacity, MEMS,
It is not defined herein.
Wherein, the concrete structure and forming method of each component in front-end devices, this area
Technical staff can be selected with reference to prior art according to actual needs, and here is omitted.
Wherein, second metal layer at top and three metal layer at top can be on the described first tops
Portion's metal level is formed while making, and its forming method can be from conventional preparation method, example
Dielectric layer such as is being formed, then the dielectric layer is being patterned, is being open and selects to be formed
Conductive material fills the opening, each metal level and conductive plunger is sequentially formed, to be formed
Interconnection architecture is stated, the further dielectric layer after the metal layer at top is formed, to cover
The metal layer at top is simultaneously planarized, as shown in Figure 2 A.
Wherein, the metal layer at top is from the heavy of metal material Al, the metal material Al
Product method can for chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD) method or
Low-pressure chemical vapor deposition (LPCVD), the laser of the formation such as ald (ALD) method burn
One kind in erosion deposition (LAD) and selective epitaxy growth (SEG), be preferably in the present invention
Physical vapour deposition (PVD) (PVD) method.
Wherein, the second substrate 200 can be Semiconductor substrate or carrying substrate (carrier
wafer)。
Alternatively, second substrate 200 is carrying substrate (carrier in this embodiment
Wafer), for after technique subsequently to the first substrate 100 progress reduction processing and other
Carrying and protection front-end devices in continuous technique.
Further, the second substrate 200 can be common silicon substrate or other suitable substrates,
This is not defined.
By bonding technology by the function of the side of the second substrate 200 and the first substrate 100
Material layer engages (bonding), as shown in Figure 2 B.Wherein, bonding technology can use ability
Any method is carried out known to field technique personnel, such as oxide fusion bonding technology.
It is formed with and the passive device in the second surface side of first substrate
The second metal layer 105 of metal layer at top electrical connection (the second metal layer at top), is formed simultaneously
There is the conductive plunger 104 electrically connected with the 3rd metal layer at top above the second interconnection structure.
Wherein, the conductive plunger and the second metal layer can select copper, gold, silver, tungsten
And other similar materials, in this embodiment from metallic copper as conductive material, it can pass through
Physical vapour deposition (PVD) (PVD), chemical vapor deposition (CVD) or Cu electroplating (ECP)
Method fill the opening.
Preferably, in this embodiment, in order to reduce because dead resistance and parasitic capacitance cause
The RC delay times, in the present invention between the metal material is deposited, be additionally included in institute
State the barrier layer formed in opening.
Further, copper barrier layer (copper barrier), the copper can be formed in the present invention
The thickness on barrier layer is not limited in a certain numerical value or scope, can be adjusted as needed
It is whole.
The present invention is changed in semiconductor devices preparation to the order in processing step,
No longer it is to be initially formed the step of then conductive plunger re-forms the second metal layer at top, but in shape
The second metal layer at top is formed during the first metal layer at top above into the first interconnection structure simultaneously
(being used to form passive device) and the 3rd metal layer at top (are used to electrically connect the second mutually link
Structure), after second metal layer at top and the 3rd metal layer at top is formed, then shape simultaneously
Into second metal layer and conductive plunger, respectively with second metal layer at top and the 3rd top-gold
Belong to layer electrical connection, the technique for forming second metal layer and the technique for forming the conductive plunger are entered
Row is integrated, the step of solving the metal level for needing multiple step formation different components so that work
Skill step is simpler, reduces stress in technique, further the cost of reduction semiconductor devices,
The performance and yield of device can also be improved.
Second metal layer bottom metal layers formed below in the second surface side
107, while the conductive plunger pad layer formed below in the second surface side
106。
Wherein, the pad layer 106 be used for signal or power supply by the second interconnection structure and
First interconnection structure is input to the inside of semiconductor devices.
Wherein, the material of pad layer 106 can be aluminium, copper or other suitable conductive materials.
It can deposit to be formed using methods such as physical vapour deposition (PVD), chemical vapor depositions.
The bottom metal layers 107 and pad layer 106 select metallic aluminium in this embodiment.
In the bottom metal layers and the passivation layer formed below of the pad layer, to cover
State bottom metal layers and the pad layer.
Wherein, passivation layer 108 is used to protect the first substrate 100 and pad layer 106.Passivation
The material of layer 108 can be silicon nitride or other suitable materials.Chemical vapor deposition can be used
Deposit to form passivation layer 108 etc. method.
The semiconductor devices of the present embodiment, can be RF front-end module or other circuits or mould
Block.Because the performance of the semiconductor devices gets a promotion, thus more application environments can be met
Under to the demand of device performance.
Embodiment three
The embodiment of the present invention provides a kind of electronic installation, it include electronic building brick and with the electronics
The semiconductor devices of component electrical connection.Wherein, the semiconductor devices is included according to embodiment two
The semiconductor devices of the manufacture method manufacture of described semiconductor devices, or including the institute of embodiment one
The semiconductor devices stated.
The electronic installation, can be mobile phone, tablet personal computer, notebook computer, net book, trip
Gaming machine, television set, VCD, DVD, navigator, camera, video camera, recording pen,
Any electronic product such as MP3, MP4, PSP or equipment or with above-mentioned semiconductor
The intermediate products of device, for example：Cell phone mainboard with the integrated circuit etc..
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300 are set
It is equipped with the display portion 302 being included in shell 301, operation button 303, external connection terminal
Mouth 304, loudspeaker 305, microphone 306 etc..
Wherein described mobile phone handsets include foregoing semiconductor devices, or according to embodiment one
Semiconductor devices obtained by the preparation method of described semiconductor devices, the semiconductor devices
No longer it is to be initially formed the step of then conductive plunger re-forms the second metal layer at top, but in shape
The second metal layer at top is formed during the first metal layer at top above into the first interconnection structure simultaneously
(being used to form passive device) and the 3rd metal layer at top (are used to electrically connect the second mutually link
Structure), after second metal layer at top and the 3rd metal layer at top is formed, then shape simultaneously
Into second metal layer and conductive plunger, respectively with second metal layer at top and the 3rd top-gold
Belong to layer electrical connection, the technique for forming second metal layer and the technique for forming the conductive plunger are entered
Row is integrated, the step of solving the metal level for needing multiple step formation different components so that work
Skill step is simpler, reduces stress in technique, further the cost of reduction semiconductor devices,
The performance and yield of device can also be improved.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (12)
1. a kind of manufacture method of semiconductor devices, it is characterised in that methods described includes：
The first substrate is provided, first substrate has first surface and the second table on the other side
Face, is formed with function material layer, in the function in the first surface side of first substrate
Transistor and the first interconnection structure are formed with material layer；
Form the first metal layer at top, the second top-gold for being embedded in the functional material layer surface
Belong to layer and the 3rd metal layer at top, first metal layer at top and first interconnection structure electricity
Connection；
The second substrate is provided, by the function of second substrate and first substrate surface
Material layer is engaged；
Reduction processing is carried out to first substrate from the second surface side；
Second metal layer and conductive plunger are formed simultaneously, and the second metal layer and the conduction are inserted
Plug formed from the second surface side of first substrate, and the second metal layer with
The second metal layer at top electrical connection, the conductive plunger and the 3rd metal layer at top electricity
Connection.
2. the manufacture method of semiconductor devices according to claim 1, it is characterised in that
Methods described also includes：
Bottom metal layers and pad layer are formed simultaneously in the second surface side, wherein the bottom
Portion's metal level is located at the lower section of the second metal layer, and the pad layer is located at the conductive plunger
Lower section.
3. the manufacture method of semiconductor devices according to claim 2, it is characterised in that
Methods described is still further comprised：
In the bottom metal layers and the passivation layer formed below of the pad layer, described in covering
Bottom metal layers and the pad layer；
The passivation layer is patterned, with pad layer described in exposed portion.
4. the manufacture method of semiconductor devices according to claim 1, it is characterised in that
First substrate is silicon-on-insulator substrate, including body silicon from bottom to top, buried oxide and
Top layer silicon.
5. the manufacture method of semiconductor devices according to claim 4, it is characterised in that
Forming the method for the second metal layer and the conductive plunger includes：
Since the second surface of first substrate, buried oxide and dielectric are sequentially etched
Layer is to second metal layer at top and the 3rd metal layer at top is exposed, to form opening；
Metal material is filled in said opening, to form the second metal layer and the conduction
Connector.
6. the manufacture method of semiconductor devices according to claim 1, it is characterised in that
The first substrate bag radio-frequency devices region, integrated passive devices region and welding disking area, it is described
Transistor, the first interconnection structure and radio-frequency devices are formed at the radio-frequency devices region, described
Two metal layer at top and second metal layer are formed at the integrated passive devices region, the described 3rd
Metal layer at top and the conductive plunger are formed at the welding disking area.
7. the manufacture method of semiconductor devices according to claim 1, it is characterised in that
Second metal layer at top is in the curvilinear structures of snail.
8. a kind of semiconductor devices, it is characterised in that the semiconductor devices includes：
First substrate, first substrate has first surface and second surface on the other side,
Function material layer is formed with the first surface side of first substrate, in the functional material
Transistor and the first interconnection structure are formed with layer；
First metal layer at top, in the function material layer and positioned at the described first interconnection
The top of structure, first metal layer at top is electrically connected with first interconnection structure；
Second metal layer at top and the 3rd metal layer at top, in the function material layer and
Positioned at the outside of first metal layer at top；
Second metal layer, is formed at the second surface of first substrate, positioned at described
The lower section of two metal layer at top and electrically connected with second top metal；
Conductive plunger, is formed at the second surface of first substrate, positioned at the described 3rd
The lower section of metal layer at top and electrically connected with the 3rd top metal；
Second substrate, the function material layer of second substrate and first substrate surface
Engage.
9. semiconductor devices according to claim 8, it is characterised in that described partly to lead
Body device also includes bottom metal layers and pad layer, wherein the bottom metal layers are located at described the
The lower section of two metal levels is simultaneously electrically connected with the second metal layer, and the pad layer is located at described lead
The lower section of electric plug is simultaneously electrically connected with the conductive plunger.
10. semiconductor devices according to claim 9, it is characterised in that described partly to lead
Body device also includes covering the second surface of first substrate but exposes the pad
Routing area passivation layer.
11. semiconductor devices according to claim 8, it is characterised in that its feature exists
In first substrate is silicon-on-insulator substrate.
12. a kind of electronic installation, it is characterised in that including one of claim 8 to 11 institute
The semiconductor devices stated.
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