CN107316855A - A kind of semiconductor devices and its manufacture method and electronic installation - Google Patents
A kind of semiconductor devices and its manufacture method and electronic installation Download PDFInfo
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- CN107316855A CN107316855A CN201610269833.7A CN201610269833A CN107316855A CN 107316855 A CN107316855 A CN 107316855A CN 201610269833 A CN201610269833 A CN 201610269833A CN 107316855 A CN107316855 A CN 107316855A
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- metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
The present invention relates to a kind of semiconductor devices and its manufacture method and electronic installation.The semiconductor devices includes：First wafer；Second wafer, is engaged positioned at the top of first wafer and with first wafer；First metal layer at top, is electrically connected in first wafer and with the first functional part in first wafer；Second metal layer, in second wafer and positioned at the top of first metal layer at top, the second metal layer is electrically connected with the second functional part in second wafer；Electric connection structure, wherein described electric connection structure is through second wafer and the second metal layer and extends in first metal layer at top in first wafer, so that second functional part in second wafer is electrically connected with the first functional part in first wafer.The structure can form an electric connection structure and can electrically connect first wafer and second wafer, can reduce the area of chip.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its
Manufacture method and electronic installation.
Background technology
In consumer electronics field, multifunctional equipment is increasingly liked by consumer, compared to
The simple equipment of function, multifunctional equipment manufacturing process will be more complicated, than if desired in circuit
The chip of integrated multiple difference in functionalitys in version, thus occur in that 3D integrated circuits (integrated
Circuit, IC) technology, 3D integrated circuits (integrated circuit, IC) are defined as one
System-level integrated morphology is planted, multiple chips are stacked in vertical plane direction, so that space is saved,
The marginal portion of each chip can draw multiple pins as needed, and these are utilized as needed
Pin, it would be desirable to which the chip of interconnection is interconnected by metal wire, but aforesaid way is still deposited
In many deficiencies, such as stacked chips quantity is more, and the annexation between chip compares
It is complicated, then just to may require that, using many metal lines, final wire laying mode is more chaotic, and
And also result in volume increase.
Therefore, at present in the 3D integrated circuits (integrated circuit, IC) technology
Mostly using silicon hole (Through Silicon Via, TSV) and above silicon hole
Metal interconnection structure formation electrical connection, then further realize the bonding between wafer.
In the three-dimensional composite technologies of 3D IC, silicon hole (TSV), intermediate plate (Interposer) etc. are closed
Under key technology, the assistance of encapsulation spare part, maximum chip is carried out in limited areal and is folded
Plus with integration, further reduce chip area, encapsulation volume and lift chip communication efficiency.Cause
This, the Cu-Cu engagements (Wafer level Cu-Cu bonding) in wafer level are used as 3D
A key technology in IC, has important application trend on high-end product.
Bottom wafers and top wafer are being engaged into conjunction in current technique, but the side
Method does not only take up larger chip area, and need to perform two steps formed deep silicon hole and
Shallow silicon hole is, it is necessary to multiple masks, perform multiple etching steps, and technique is cumbersome, make technique into
This increase.
Therefore, it is to solve the above-mentioned technical problem in current technique, it is necessary to propose a kind of new
Semiconductor devices and its manufacture method and electronic installation.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be specific real
Apply in mode part and be further described.The Summary of the present invention is not meant to
Attempt to limit the key feature and essential features of technical scheme claimed, less
Mean the protection domain for attempting to determine technical scheme claimed.
In order to overcome the problem of presently, there are, the embodiment of the present invention one provides a kind of semiconductor device
Part, the semiconductor devices includes：
First wafer；
Second wafer, is engaged positioned at the top of first wafer and with first wafer；
First metal layer at top, in first wafer and with first wafer
One functional part is electrically connected；
Second metal layer, in second wafer and positioned at first metal layer at top
Top, the second metal layer is electrically connected with the second functional part in second wafer；
Electric connection structure, wherein the electric connection structure runs through second wafer and described second
Metal level is simultaneously extended in first metal layer at top in first wafer, so that described
Second functional part in second wafer and the first functional part in first wafer
Electrical connection.
Alternatively, the second metal layer is set around the periphery of the electric connection structure.
Alternatively, the second metal layer be in hollow loop configuration, the electric connection structure with
Hollow space in the loop configuration matches and is embedded in the loop configuration.
Alternatively, the second metal layer is square hollow ring structure, circular hollow ring junction
Structure or polygonal hollow ring structure.
Alternatively, the hollow space size is bigger than the size of the second metal layer by 1/3~2/3.
Alternatively, the electric connection structure includes silicon hole.
Alternatively, first wafer is logic wafer, and second wafer is schemed for CMOS
As sensor wafer.
Present invention also offers a kind of preparation method of semiconductor devices, methods described includes：
First wafer and the second wafer, second wafer and the first wafer phase mutual connection are provided
It is integrated, wherein, second wafer is located at the top of first wafer, described first
The first metal layer at top, first metal layer at top and first wafer are formed with wafer
In the electrical connection of the first functional part, be formed with second metal layer in second wafer, it is described
Second metal layer is electrically connected and second metal with the second functional part in the second wafer
Layer is the hollow bulb in the loop configuration with hollow space, and the second metal layer
Divide projection in vertical direction positioned at the top of first metal layer at top；
Second wafer, the second metal layer and first wafer are patterned, to remove
The hollow space in the second metal layer simultaneously forms opening, exposes first top-gold
Belong to layer；
Electric connection structure is formed in said opening, by the first function in first wafer
The second functional part formation electrical connection in part and second wafer.
Alternatively, the second metal layer is square hollow ring structure, circular hollow ring
Shape structure or polygonal hollow ring structure.
Alternatively, the size of the hollow space is bigger than the size of the second metal layer
1/3~2/3.
Alternatively, the electric connection structure includes silicon hole.
Alternatively, first wafer is logic wafer, and second wafer is schemed for CMOS
As sensor wafer.
Present invention also offers a kind of electronic installation, including above-mentioned semiconductor devices.
In order to solve problem present in current technique, the present invention is prepared in the semiconductor devices
The middle shape for changing the second metal layer in second wafer, by the second metal layer
The loop configuration with hollow space electrically connected with functional part in the second wafer is designed as, so
The hollow space is located at first metal layer at top after being engaged with the first wafer afterwards
Top, patterns second wafer and first wafer, can remove second metal
The hollow space in layer, forms the second metal layer of annular, and exposes first top
Metal level, eventually forms electric connection structure, so that second function in second wafer
The first functional part electrical connection in part and first wafer.
The second metal layer in the second wafer is designed as hollow-core construction in the present invention, by described
Change can form an electric connection structure can be by first wafer and second wafer
Electrical connection, i.e., by the connection of two wafers above and below silicon hole (TSV) realization, and mesh
Although preceding technique also forms silicon hole, it is by two silicon holes (TSV), one
Deep silicon hole extends to the first metal layer at top of following first wafer, a shallow silicon hole connection
To the second metal layer to the second wafer, latter two right silicon hole is interconnected at top, is realized simultaneously
Two wafer circuits above and below control.The method of the invention can not only subtract relative to current technique
The area of small chip, and need to further simplify processing step, reduce mask and etching
Number, technique is simpler, process costs is further reduced, and improves and described partly lead
The performance and yield of body device.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 is a kind of manufacture method of semiconductor devices of an alternative embodiment of the invention
Indicative flowchart；
Fig. 2A-Fig. 2 C be one embodiment of the invention in a kind of semiconductor devices manufacturer
The sectional view of the structure of the correlation step formation of method；
Fig. 3 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, and it will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from beginning to end
Icon note represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then in the absence of element or layer between two parties.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term is limited.These terms be used merely to distinguish element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience herein and by using from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.If for example, the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, element, the presence or addition of part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
Herein with reference to the horizontal stroke of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Sectional view come describe invention embodiment.As a result, it is contemplated that due to such as manufacturing technology and/
Or the change caused by tolerance from shown shape.Therefore, embodiments of the invention should not limit to
Given shape in area shown here, but including inclined due to for example manufacturing caused shape
Difference.For example, be shown as the injection region of rectangle generally has circle at its edge or bending features and
/ or implantation concentration gradient, rather than the binary change from injection region to non-injection regions.Equally,
The surface passed through when by injecting the disposal area formed the disposal area and injection can be caused to carry out
Between area in some injection.Therefore, the area shown in figure be substantially it is schematical, it
Shape be not intended display device area true form and be not intended limit the present invention
Scope.
In order to thoroughly understand the present invention, detailed step and in detail will be proposed in following description
Thin structure, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is detailed
Carefully it is described as follows, but in addition to these detailed descriptions, the present invention can also have other implementations
Mode.
By bottom wafers and top wafer in method, semi-conductor device manufacturing method described in current technique
Engage, it usually needs form two silicon of deep silicon hole and shallow silicon hole being electrically connected to each other and lead to
Hole, wherein metal level or interconnection structure connection in the shallow silicon hole connection top wafer, institute
State deep via and penetrate the interconnection structures, two such as pad of the top wafer into the bottom wafers
Individual silicon hole is interconnected at top, to realize the electrical connection of the top wafer and bottom wafers, real
Two wafer circuits now control simultaneously above and below.But methods described does not only take up larger chip face
Product, and need perform two steps form deep silicon hole and shallow silicon hole, it is necessary to multiple masks,
Multiple etching steps are performed, technique is cumbersome, increases process costs.
In order to solve the problem, the invention provides a kind of preparation method of semiconductor devices, institute
The method of stating includes：
First wafer and the second wafer, second wafer and the first wafer phase mutual connection are provided
It is integrated, wherein, second wafer is located at the top of first wafer, described first
The first metal layer at top, first metal layer at top and first wafer are formed with wafer
In the electrical connection of the first functional part, be formed with second metal layer in second wafer, it is described
Second metal layer is electrically connected and second metal with the second functional part in the second wafer
Layer is the hollow bulb in the loop configuration with hollow space, and the second metal layer
Divide projection in vertical direction positioned at the top of first metal layer at top；
Second wafer, the second metal layer and first wafer are patterned, to remove
The hollow space in the second metal layer simultaneously forms opening, exposes first top-gold
Belong to layer；
Electric connection structure is formed in said opening, by the first function in first wafer
The second functional part formation electrical connection in part and second wafer.
Wherein, the second metal layer is in hollow loop configuration, the electric connection structure and institute
The hollow space for stating loop configuration matches and is embedded in the hollow space.
Further, the second metal layer is square hollow ring structure, circular hollow ring junction
Structure or polygonal hollow ring structure.
Further, the size of the hollow space of the second metal layer is than second metal
The size of layer is big by 1/3~2/3.
In order to solve problem present in current technique, the present invention is prepared in the semiconductor devices
The middle shape for changing the second metal layer in second wafer, by the second metal layer
The loop configuration with hollow space electrically connected with functional part in the second wafer is designed as, so
The hollow space is located at first metal layer at top after being engaged with the first wafer afterwards
Top, patterns second wafer and first wafer, can remove second metal
The hollow space in layer, forms the second metal layer of annular, and exposes first top
Metal level, eventually forms electric connection structure, so that second function in second wafer
The first functional part electrical connection in part and first wafer.
The second metal layer in the second wafer is designed as hollow-core construction in the present invention, by described
Change can form an electric connection structure can be by first wafer and second wafer
Electrical connection, i.e., by the connection of two wafers above and below silicon hole (TSV) realization, and mesh
Although preceding technique also forms silicon hole, it is by two silicon holes (TSV), one
Deep silicon hole extends to the first metal layer at top of following first wafer, a shallow silicon hole connection
To the second metal layer to the second wafer, latter two right silicon hole is interconnected at top, is realized simultaneously
Two wafer circuits above and below control.The method of the invention can not only subtract relative to current technique
The area of small chip, and need to further simplify processing step, reduce mask and etching
Number, technique is simpler, process costs is further reduced, and improves and described partly lead
The performance and yield of body device.
The semiconductor devices of the present invention, as a result of above-mentioned manufacture method, thus equally has
Above-mentioned advantage.The electronic installation of the present invention, as a result of above-mentioned semiconductor device, thus together
Sample has above-mentioned advantage.
Embodiment one
In order to solve the problem, the invention provides a kind of semiconductor devices, below in conjunction with the accompanying drawings
2A- Fig. 2 C are described further to the semiconductor devices.
Wherein, the semiconductor devices includes：
First wafer 201；
Second wafer 203, positioned at the top of first wafer 201 and with first wafer
It is combined into one；
First metal layer at top 202, in first wafer and with first wafer
The first functional part electrical connection；
Second metal layer 204, in second wafer and positioned at the first metal layer
Top, the second metal layer is electrically connected with the second functional part in second wafer；
Electric connection structure 205, wherein the electric connection structure runs through second wafer and described
Second metal layer is simultaneously extended in first metal layer at top in first wafer, so that
Second functional part in second wafer and the first function in first wafer
Part is electrically connected.
Wherein, the first wafer 201 can be at least one of following material being previously mentioned：Silicon,
Silicon (SSOI) is laminated on silicon-on-insulator (SOI), insulator, SiGe is laminated on insulator
(S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI)
Deng.
Wherein described first wafer is logic wafer, is formed with various logic in first wafer
Device, such as being formed with various cmos devices and passive device.
As an example, transistor, interconnection architecture and radio frequency can also be formed with the first wafer
Device.In the present embodiment, transistor is used to constitute various circuits, and radio-frequency devices are used to be formed
Radio frequency component or module.
Wherein, transistor can be brilliant for normal transistor, high-k/metal gate transistors, fin
Body pipe or other suitable transistors.Interconnection structure can include metal level (such as layers of copper or aluminium
Layer), metal plug etc..Radio-frequency devices can include the devices such as inductance (inductor).
In addition to including transistor, radio-frequency devices and interconnection structure, cmos device can also include
Other various feasible components, such as resistance, electric capacity, MEMS, herein not
It is defined.
Wherein, the concrete structure and forming method of each component in cmos device, this area
Technical staff can be selected according to actual needs with reference to prior art, herein no longer go to live in the household of one's in-laws on getting married
State.
Wherein, first metal layer at top is pad structure, the first top metal layer choosing
The deposition process for using metal material Al, the metal material Al can be chemical vapor deposition
(CVD) method, physical vapour deposition (PVD) (PVD) method or ald (ALD) method etc.
Outside low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selection of formation
One kind in epitaxial growth (SEG), in the present invention preferably physical vapour deposition (PVD) (PVD) method.
Wherein, second wafer 203 can be at least one in the following material being previously mentioned
Kind：Silicon, silicon-on-insulator (SOI), stacking silicon (SSOI), insulator upper strata on insulator
Folded SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator
(GeOI) etc..
Various logic device can also be formed with wherein described second wafer, for example, is formed with each
Cmos device and passive device etc. are planted, is sensed here by cmos image of the second wafer
Illustrated exemplified by device (CIS) wafer, specially dorsal part is according to the CIS set.
Specifically, layer of bonding material is formed with the surface of first wafer, wherein described
Layer of bonding material selects oxide, such as from SiO2Deng, it is not limited to the example,
Wherein described layer of bonding material should have preferable adhesion property.
Alternatively, the surface of second wafer is also formed with layer of bonding material, wherein described connect
Condensation material layer choosing oxide, such as from SiO2Deng.
First wafer and second wafer are engaged by bonding technology.Pass through bonding
Technique is by the front and the front (side for being formed with front-end devices) of the first wafer of the second wafer
Engage (bonding).
Wherein, second metal layer is formed with second wafer, the second metal layer is
Pad in second wafer, the pad is coupled with the logical device in the second wafer, mutually
Structure and other functional parts are connected.
Wherein, the second metal layer is from the heavy of metal material Al, the metal material Al
Product method can for chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD) method or
Low-pressure chemical vapor deposition (LPCVD), the laser of the formation such as ald (ALD) method burn
One kind in erosion deposition (LAD) and selective epitaxy growth (SEG), be preferably in the present invention
Physical vapour deposition (PVD) (PVD) method.
Wherein, the second metal layer around the electric connection structure periphery set, with institute
State electric connection structure connection.
Alternatively, the second metal layer be in hollow loop configuration, the electric connection structure with
The hollow space of the loop configuration matches and is embedded in the hollow space.
Alternatively, the second metal layer is square hollow ring structure, circular hollow ring junction
Structure or polygonal hollow ring structure.
Further, the second metal layer is located at the top of first metal layer at top, for example
The projection of the hollow space in vertical direction in the second metal layer is located at described the
The top of one metal layer at top.
Specifically, the hollow in the vertical direction of the second metal layer is located at the described first top
The surface of metal level, is just set to first metal layer at top, so that the binding that is electrically connected
Structure is located at the surface of first metal layer at top, and connects simultaneously in first wafer
Metal level in metal level and the second wafer, to realize patrolling in the second wafer and the first wafer
Device is collected to be connected.
Wherein, the second metal layer 204 be square, circular or polygonal loop configuration,
As illustrated by figures 2 b and 2 c.
Wherein, the size of the hollow space of the second metal layer is than the second metal layer
Size it is big by 1/3~2/3.
Wherein, the electric connection structure 205, can be silicon hole.
The silicon hole includes including barrier layer, backing layer and conductive material successively from outside to inside.
Wherein, the conductive material can pass through low-pressure chemical vapor deposition (LPCVD), plasma
Body assistant chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD) and
Ald (ALD) or other advanced deposition techniques are formed.
It is preferred that conductive material is tungsten material.In another embodiment, conductive material can be cobalt
(Co), molybdenum (Mo), titanium nitride (TiN) and contain the conductive material of tungsten or its combination.
Further, the conductive layer in the silicon hole selects metallic copper.
The present invention changes described the in second wafer in semiconductor devices preparation
The shape of two metal levels, the second metal layer is designed as and functional part electricity in the second wafer
The loop configuration with hollow space of connection, then in described after being engaged with the first wafer
Empty part is located at the top of first metal layer at top, patterns second wafer and described
First wafer, can remove the hollow space in the second metal layer, form annular
Second metal layer, and expose first metal layer at top, electric connection structure is eventually formed, with
Make the first work(in second functional part and first wafer in second wafer
Can part formation electrical connection.
The second metal layer in the second wafer is designed as hollow-core construction in the present invention, by described
Change can form an electric connection structure can be by first wafer and second wafer
Electrical connection, i.e., by the connection of two wafers above and below silicon hole (TSV) realization, and mesh
Although preceding technique also forms silicon hole, it is by two silicon holes (TSV), one
Deep silicon hole extends to the first metal layer at top of following first wafer, a shallow silicon hole connection
To the second metal layer to the second wafer, latter two right silicon hole is interconnected at top, is realized simultaneously
Two wafer circuits above and below control.The method of the invention can not only subtract relative to current technique
The area of small chip, and need to further simplify processing step, reduce mask and etching
Number, technique is simpler, process costs is further reduced, and improves and described partly lead
The performance and yield of body device.
The semiconductor devices of the present invention is formed, as a result of above-mentioned manufacture method, thus equally
With above-mentioned advantage.The electronic installation of the present invention, as a result of above-mentioned semiconductor device, because
And equally there is above-mentioned advantage.
Embodiment two
Below, reference picture 1 and Fig. 2A-Fig. 2 C describe the half of proposition of the embodiment of the present invention
The detailed step of one illustrative methods of manufacture method of conductor device.Wherein, Fig. 1 is this hair
A kind of indicative flowchart of the manufacture method of semiconductor devices of another bright embodiment, tool
Include body：
Step S1：First wafer and the second wafer, second wafer and described first are provided
Wafer, which is bonded with each other, to be integrated, wherein, second wafer is located at the top of first wafer,
Be formed with the first metal layer at top in first wafer, first metal layer at top with it is described
The second metal is formed with the first functional part electrical connection in first wafer, second wafer
Layer, the second metal layer is electrically connected and described the with the second functional part in the second wafer
Two metal levels are described in the loop configuration with hollow space, and the second metal layer
The projection of hollow space in vertical direction is positioned at the top of first metal layer at top；
Step S2：Pattern second wafer, the second metal layer and first crystalline substance
Circle, to remove the hollow space in the second metal layer and form opening, exposes described
First metal layer at top；
Step S3：Electric connection structure is formed in said opening, by first wafer
The first functional part and second wafer in the second functional part formation electrical connection.
The manufacture method of the semiconductor devices of the present embodiment, specifically includes following steps：
Performing step one, there is provided the first wafer 201 and the second wafer 203, second wafer
203 are bonded with each other with first wafer 201 is integrated, wherein, second wafer 203
Positioned at the top of first wafer 201, the first top is formed with first wafer 201
Metal level 202, first metal layer at top 202 and the first function in first wafer
Part is electrically connected, and second metal layer 204, second metal are formed with second wafer
Layer electrically connected with the second functional part in the second wafer and the second metal layer for
The hollow space in the loop configuration of hollow space, and the second metal layer is vertical
Projection on direction is positioned at the top of first metal layer at top.
Specifically, as described in Fig. 2A, wherein, the first wafer 201 can be following carried
At least one of material arrived：Silicon, silicon-on-insulator (SOI), it is laminated silicon on insulator
(SSOI) SiGe (S-SiGeOI), germanium on insulator SiClx, are laminated on insulator
And germanium on insulator (GeOI) etc. (SiGeOI).
Wherein described first wafer is logic wafer, is formed with various logic in first wafer
Device, such as being formed with various cmos devices and passive device.
As an example, the first functional part, such as crystal can also be formed with the first wafer
Pipe, interconnection architecture and radio-frequency devices.In the present embodiment, transistor is used to constitute various circuits,
Radio-frequency devices are used to form radio frequency component or module.
Wherein, transistor can be brilliant for normal transistor, high-k/metal gate transistors, fin
Body pipe or other suitable transistors.Interconnection structure can include metal level (such as layers of copper or aluminium
Layer), metal plug etc..Radio-frequency devices can include the devices such as inductance (inductor).
In addition to including transistor, radio-frequency devices and interconnection structure, cmos device can also include
Other various feasible components, such as resistance, electric capacity, MEMS, herein not
It is defined.
Wherein, the concrete structure and forming method of each component in cmos device, this area
Technical staff can be selected according to actual needs with reference to prior art, herein no longer go to live in the household of one's in-laws on getting married
State.
Wherein, first metal layer at top is the metal layer at top (pad structure), described
Metal layer at top can be change from metal material Al, the metal material Al deposition process
Learn vapour deposition (CVD) method, physical vapour deposition (PVD) (PVD) method or ald (ALD)
Low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the choosing of the formation such as method
One kind in epitaxial growth (SEG) is selected, in the present invention preferably physical vapour deposition (PVD) (PVD)
Method.
Wherein, the forming method of the interconnection structure can select conventional manufacture method, for example
Dielectric layer is formed, then the dielectric layer is patterned, is open and from conductive with being formed
Material fills the opening, sequentially forms each metal level and through hole, to form the mutual link
Structure, the further dielectric layer after the metal layer at top is formed, to cover the top
Metal level is simultaneously planarized.
Second wafer 203 is provided and engaged with first wafer.
Wherein, second wafer 203 can be at least one in the following material being previously mentioned
Kind：Silicon, silicon-on-insulator (SOI), stacking silicon (SSOI), insulator upper strata on insulator
Folded SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator
(GeOI) etc..
Various logic device can also be formed with wherein described second wafer, for example, is formed with each
Cmos device and passive device etc. are planted, is sensed here by cmos image of the second wafer
Illustrated exemplified by device (CIS) wafer, specially dorsal part is according to the CIS set.
Specifically, layer of bonding material is formed with the surface of first wafer, wherein described
Layer of bonding material selects oxide, such as from SiO2Deng, it is not limited to the example,
Wherein described layer of bonding material should have preferable adhesion property.
Alternatively, the surface of second wafer is also formed with layer of bonding material, wherein described connect
Condensation material layer choosing oxide, such as from SiO2Deng.
First wafer and second wafer are engaged by bonding technology.
The front and the front of the first wafer of second wafer (are formed with by front end by bonding technology
The side of device) engage (bonding).
Wherein, bonding technology can be carried out using any method well known to those skilled in the art, example
Such as oxide fusion bonding technology.
Layer of bonding material is formed on first wafer in the process, then described
Layer of bonding material is formed on two wafers, is mutually bonded the layer of bonding material in bonding, so that
First wafer and second wafer are engaged.
Wherein, second metal layer is formed with second wafer, the second metal layer is
Pad in second wafer, the pad is connected with the second functional part in the second wafer
Connect, such as described pad is connected with logical device, interconnection architecture and other functional parts.
Wherein, the second metal layer is from the heavy of metal material Al, the metal material Al
Product method can for chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD) method or
Low-pressure chemical vapor deposition (LPCVD), the laser of the formation such as ald (ALD) method burn
One kind in erosion deposition (LAD) and selective epitaxy growth (SEG), be preferably in the present invention
Physical vapour deposition (PVD) (PVD) method.
Further, the second metal layer has the loop configuration of hollow space, and described
Hollow space in two metal levels is located at the top of first metal layer at top, such as and described the
The projection of the hollow space in vertical direction in two metal levels is located at the described first top
The top of metal level.
Specifically, there is the second metal layer hollow space in the vertical direction to be located at described the
The surface of one metal layer at top, is just set to first metal layer at top, to form institute
While connecting in the metal level and the second wafer in first wafer when stating electric connection structure
Logical device in second wafer and the first wafer, is connected by metal level with realizing.
Wherein, the second metal layer 204 be square, circular or polygonal loop configuration,
As illustrated by figures 2 b and 2 c.
Wherein, the size of the hollow space of the second metal layer is than the second metal layer
Size it is big by 1/3~2/3.
Step 2 is performed, first wafer 201, the and of the second metal layer 204 is patterned
Second wafer 203, to remove the hollow space in the second metal layer and be formed
Opening, exposes first metal layer at top.
The photoresist layer of deposit patterned on the back side of second wafer, with the photoresist
Layer is the wafer of mask etch second, second metal layer and first wafer, forms via openings,
So ashing removes the photoresist layer.
Wherein, remove in this step second metal layer center filling sacrifice layer or
The wafer material of person second, to form loop configuration, and the loop configuration is located at described first
The top of metal layer at top, is completely exposed first metal layer at top.
Step 3 is performed, electric connection structure is formed in said opening, by first wafer
In the first functional part and second wafer in the second functional part formation electrical connection.
Specifically, conductive material is filled in the through hole, electric connection structure 205, example is formed
Electric connection structure 205, can be silicon hole as described.
Wherein, the conductive material can pass through low-pressure chemical vapor deposition (LPCVD), plasma
Body assistant chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD) and
Ald (ALD) or other advanced deposition techniques are formed.
It is preferred that conductive material is tungsten material.In another embodiment, conductive material can be cobalt
(Co), molybdenum (Mo), titanium nitride (TiN) and contain the conductive material of tungsten or its combination.
Alternatively, before filling the conductive material, can also in the through hole deposition medium
Layer, the dielectric layer is included two layers, respectively barrier layer and backing layer, is then re-formed described
Silicon hole.
Further, the conductive layer in the silicon hole selects metallic copper.
Wherein, the second metal layer surround the binding that is electrically connected after the silicon hole is formed
The periphery of structure is set, and the electric connection structure and the hollow space of the loop configuration match simultaneously
It is embedded in the hollow space.
By the change can be formed an electric connection structure can by first wafer and
The second wafer electrical connection, it is no longer necessary to form two silicon of deep silicon hole and shallow silicon hole and lead to
Hole, methods described can not only reduce the area of chip, and need to further simplify technique
Step, reduces mask and etching number, and technique is simpler, process costs is further dropped
It is low, and improve the performance and yield of the semiconductor devices.
So far, the introduction for preparing the semiconductor gas device of the embodiment of the present invention is completed.
After above-mentioned steps, other correlation steps can also be included, here is omitted.Also, remove
Outside above-mentioned steps, the manufacture method of the present embodiment can also among each above-mentioned step or
Include other steps between different steps, these steps can be by each in current technique
Plant technique to realize, here is omitted.
In order to solve problem present in current technique, the present invention is prepared in the semiconductor devices
The middle shape for changing the second metal layer in second wafer, by the second metal layer
The loop configuration with hollow space electrically connected with functional part in the second wafer is designed as, so
It is located at the top of first metal layer at top after being engaged with the first wafer afterwards, patterns institute
The second wafer and first wafer are stated, can be removed described hollow in the second metal layer
Structure, forms the second metal layer of annular, and exposes first metal layer at top, last shape
Into electric connection structure, so that second functional part and described first in second wafer
The first functional part electrical connection in wafer.
The second metal layer in the second wafer is designed as hollow-core construction in the present invention, by described
Change can form an electric connection structure can be by first wafer and second wafer
Electrical connection, i.e., by the connection of two wafers above and below silicon hole (TSV) realization, and mesh
Although preceding technique also forms silicon hole, it is by two silicon holes (TSV), one
Deep silicon hole extends to the first metal layer at top of following first wafer, a shallow silicon hole connection
To the second metal layer to the second wafer, latter two right silicon hole is interconnected at top, is realized simultaneously
Two wafer circuits above and below control.The method of the invention can not only subtract relative to current technique
The area of small chip, and need to further simplify processing step, reduce mask and etching
Number, technique is simpler, process costs is further reduced, and improves and described partly lead
The performance and yield of body device.
The semiconductor devices of the present invention, as a result of above-mentioned manufacture method, thus equally has
Above-mentioned advantage.The electronic installation of the present invention, as a result of above-mentioned semiconductor device, thus together
Sample has above-mentioned advantage.
Embodiment three
The embodiment of the present invention provides a kind of electronic installation, it include electronic building brick and with the electronics
The semiconductor devices of component electrical connection.
Wherein, the semiconductor devices includes the system of the semiconductor devices according to embodiment two
The semiconductor devices of method manufacture is made, or including the semiconductor devices described in embodiment one.
The electronic installation, can be mobile phone, tablet personal computer, notebook computer, net book, trip
Gaming machine, television set, VCD, DVD, navigator, camera, video camera, recording pen,
Any electronic product such as MP3, MP4, PSP or equipment or with above-mentioned semiconductor
The intermediate products of device, for example：Cell phone mainboard with the integrated circuit etc..
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300 are set
It is equipped with the display portion 302 being included in shell 301, operation button 303, external connection terminal
Mouth 304, loudspeaker 305, microphone 306 etc..
Wherein described mobile phone handsets include foregoing semiconductor devices, or according to embodiment one
Semiconductor devices obtained by the manufacture method of described semiconductor devices, the semiconductor devices
Including the first wafer；Second wafer, positioned at the top of first wafer and with it is described first brilliant
Circle is engaged；First metal layer at top, in first wafer and with first wafer
In the first functional part electrical connection；Second metal layer, in second wafer and is located at
The top of the first metal layer, the second metal layer and the second work(in second wafer
Can device electrical connection；Electric connection structure, wherein the electric connection structure runs through second wafer
With the second metal layer and first metal layer at top that extends in first wafer
On, so that second function element in second wafer and the in first wafer
One functional part is electrically connected.Can form an electric connection structure by the change can be by institute
The first wafer and second wafer electrical connection are stated, but methods described can not only reduce chip
Area, and need to further simplify processing step, reduce mask and etching number,
Technique is simpler, process costs is further reduced, and improves the semiconductor devices
Performance and yield.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (13)
1. a kind of semiconductor devices, it is characterised in that the semiconductor devices includes：
First wafer；
Second wafer, is engaged positioned at the top of first wafer and with first wafer；
First metal layer at top, in first wafer and with first wafer
One functional part is electrically connected；
Second metal layer, in second wafer and positioned at first metal layer at top
Top, the second metal layer is electrically connected with the second functional part in second wafer；
Electric connection structure, wherein the electric connection structure runs through second wafer and described second
Metal level is simultaneously extended in first metal layer at top in first wafer, so that described
Second functional part in second wafer and the first functional part in first wafer
Electrical connection.
2. semiconductor devices according to claim 1, it is characterised in that described second
Metal level is set around the periphery of the electric connection structure.
3. semiconductor devices according to claim 1, it is characterised in that described second
Metal level be in hollow loop configuration, the electric connection structure with it is hollow in the loop configuration
Part matches and is embedded in the loop configuration.
4. the semiconductor devices according to claim 1 or 3, it is characterised in that described
Second metal layer is square hollow ring structure, circular hollow loop configuration or polygonal hollow
Loop configuration.
5. semiconductor devices according to claim 3, it is characterised in that described hollow
Portion size is bigger than the size of the second metal layer by 1/3~2/3.
6. semiconductor devices according to claim 1, it is characterised in that described to be electrically connected
Binding structure includes silicon hole.
7. semiconductor devices according to claim 1, it is characterised in that described first
Wafer is logic wafer, and second wafer is cmos image sensor wafer.
8. a kind of preparation method of semiconductor devices, it is characterised in that methods described includes：
First wafer and the second wafer, second wafer and the first wafer phase mutual connection are provided
It is integrated, wherein, second wafer is located at the top of first wafer, described first
The first metal layer at top, first metal layer at top and first wafer are formed with wafer
In the electrical connection of the first functional part, be formed with second metal layer in second wafer, it is described
Second metal layer is electrically connected and second metal with the second functional part in the second wafer
Layer is the hollow bulb in the loop configuration with hollow space, and the second metal layer
Divide projection in vertical direction positioned at the top of first metal layer at top；
Second wafer, the second metal layer and first wafer are patterned, to remove
The hollow space in the second metal layer simultaneously forms opening, exposes first top-gold
Belong to layer；
Electric connection structure is formed in said opening, by the first function in first wafer
The second functional part formation electrical connection in part and second wafer.
9. method according to claim 8, it is characterised in that the second metal layer
Hollow ring structure, circular hollow ring structure or the polygonal hollow ring knot being square
Structure.
10. method according to claim 8, it is characterised in that the hollow space
Size is bigger than the size of the second metal layer by 1/3~2/3.
11. method according to claim 8, it is characterised in that the electric connection structure
Including silicon hole.
12. method according to claim 8, it is characterised in that first wafer is
Logic wafer, second wafer is cmos image sensor wafer.
13. a kind of electronic installation, it is characterised in that including one of claim 8 to 12 institute
The semiconductor devices stated.
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Application publication date: 20171103 |