CN101542701B - Bonding method of three dimensional wafer lamination based on silicon through holes - Google Patents

Bonding method of three dimensional wafer lamination based on silicon through holes Download PDF

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Publication number
CN101542701B
CN101542701B CN2008800000362A CN200880000036A CN101542701B CN 101542701 B CN101542701 B CN 101542701B CN 2008800000362 A CN2008800000362 A CN 2008800000362A CN 200880000036 A CN200880000036 A CN 200880000036A CN 101542701 B CN101542701 B CN 101542701B
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China
Prior art keywords
wafer
silicon
adhesive layer
space
stack
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CN2008800000362A
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Chinese (zh)
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CN101542701A (en
Inventor
仲镇华
史训清
马薇
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香港应用科技研究院有限公司
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Priority to PCT/CN2008/071193 priority Critical patent/WO2009146587A1/en
Publication of CN101542701A publication Critical patent/CN101542701A/en
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Publication of CN101542701B publication Critical patent/CN101542701B/en

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    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract

The invention describes a mixed bonding method of three dimensional wafer lamination based on silicon through hole. Adjacent wafers in the lamination are connected by glue layers with patterns, meanwhile, the welding bond between the silicon through holes are taken as the electrical signal connection between the wafer laminations. The patterns designed on the glue layers are used for discharging the gases generated during welding and eliminating the stress.

Description

基于硅通孔的三维晶圆叠层的键合方法 Based on the three-dimensional bonding method of the silicon wafer stack vias

技术领域 FIELD

[0001] 本发明涉及基于硅通孔(through-Silicon-via,TSV)的三维晶圆叠层的键合方法,特别涉及采用粘胶和焊接键合的混合键合方法。 [0001] The present invention relates to a bonding method based on a three-dimensional silicon wafer stack vias (through-Silicon-via, TSV) is, in particular, relates to a hybrid welding and adhesive bonding method of bonding. 本发明也涉及形成的晶圆叠层装配。 The present invention also relates to the wafer stack formed by fitting.

[0002] 发明背景 [0002] Background of the Invention

[0003] 随着电子设备的,特别是便携式设备:如手机等的,体积变得越来越小,提供的功能越来越广泛,很有必要在不增加设备尺寸,保持一个较小的形状的前提下集成更多功能的芯片,。 [0003] As electronic devices, especially portable devices: such as mobile phones, the volume becomes smaller and smaller, the functionality provided more and more widely, the shape is not necessary to increase the size of the apparatus, to maintain a smaller integrate more functions under the premise of chips. 仅在一个二维结构里增加电子组件数目无法实现这些目标,所以三维(3D)封装正日益被采用,以便能够提供更大的功能和更高的组件密度,但仍然保持一个较小的形状。 Only increasing the number of electronic components in a two-dimensional structure can not achieve these objectives, it is a three-dimensional (3D) packages are increasingly being employed in order to provide greater functionality and higher component density, but still maintain a small form.

[0004] 在这种3D结构里,各种电子组件,如具有不同有源IC装置的半导体芯片被集成在一个多层的叠层结构里。 [0004] In such a 3D structure, the various electronic components such as semiconductor chips having different active IC devices are integrated in a laminated structure in a plurality of layers. 传统的引线键合(如US 6,933,172)被用来建立芯片之间的电信号的互连,而引线键合要求较大的内面尺寸(in-plane size)和外面尺寸(out-of-plane size),这与最大化组件密度的目标不一致。 Conventional wire bonding (e.g. US 6,933,172) is used to establish electrical interconnections between the chip and the wire bonding requires a larger size of the inner surface (in-plane size) and an outer dimension (OUT- of-plane size), it is inconsistent with the goal of maximizing the component density. 为了集成不同层上的组件,硅通孔(TSV)技术可以被用来提供电互连,并提供机械支撑。 In order to integrate components on different layers, silicon vias (TSV) techniques may be used to provide electrical interconnections and to provide mechanical support. 在TSV技术里,通孔是通过半导体工艺过程在其有不同有源IC装置或其它装置的硅芯片上制成,然后被填充金属如铜、金、钨、焊料或高掺杂半导体材料如多晶硅。 In the TSV technology, the through hole is formed by a semiconductor process on a silicon chip with a different active IC devices or other devices in which, and then be filled with metal such as copper, gold, tungsten, solder, or a highly doped semiconductor material such as polysilicon . 最后,具有此通孔的多个组件被堆叠并键合在一起。 Finally, this assembly has a plurality of through-holes are stacked and bonded together.

现有技术 current technology

[0005] 键合技术(bonding method)是制作叠层电子组件的一个重要环节。 [0005] Bonding (bonding method) is an important part of the production of laminated electronic components. 一个理想的键合方法应该是可靠且低成本的。 An ideal bonding method should be reliable and inexpensive. TSV互连已经被提出作为引线键合互连的一个替代方法,一些键合方法,包括扩散键合(diffusionbonding)、焊接键合、以及粘胶键合(adhesive bonding),可以与TSV互连一起用来连接晶圆/芯片。 TSV interconnection has been proposed as an alternative method of interconnecting the wire bonding, some of the bonding method include a diffusion bonding (diffusionbonding), solder bonding, and adhesive bonding (adhesive bonding), may be interconnected with TSV for connecting wafer / chip.

[0006] 在扩散键合里,一个薄金属键合层(例如,最好由铜制成,但也可能是锡、铟、金、 镍、银、钯、钯镍合金或钛)被加到将被连接的半导体组件的各个键合表面。 [0006] In diffusion bonding, the bonding layer is a thin metal (e.g., preferably made of copper, but can also be tin, indium, gold, nickel, silver, palladium, palladium-nickel or titanium) is added the respective keys of the semiconductor assembly is attached, the surface. 组件被键合时,如果施加合适的温度和压力条件,两个金属键合层相互扩散而形成一个金属间化合物(IMC),形成键合连接。 Assembly is bonded to, if appropriate conditions of temperature and pressure is applied, two metal bonding layer is formed between the interdiffusion of a metal compound (the IMC), connected to form a bond. 扩散连接可产生一个良好质量的可靠键合,但此方法的缺点是要求两个半导体组件的键合面有非常好的共平面度,并需要一个高键合温度。 Diffusion bonding produces a good quality and reliable bonding, but the disadvantage of this method is the requirement of two bonding surfaces of the semiconductor components have a very good co-planarity, and requires a high bonding temperature. 所以,实施此方法很困难且昂贵。 Therefore, this method is difficult to implement and expensive. 一个扩散连接方法的典型例子如US 7,157,787所示。 A typical example of a method of diffusion bonding as shown in US 7,157,787.

[0007] 粘胶键合是一个低成本选择,其方法为在将被键合在一起的表面上提供一个粘胶层。 [0007] The adhesive bonding is a low cost option, which provides a method for the adhesive layer on the surface to be bonded together. 一个粘胶键合的例子如US 6,593,645所示。 Examples of a viscose-bonded as shown in US 6,593,645. US 6. 448,661显示一个现有技术的例子, 其中芯片是使用导电胶如各向异性导电膜(ACF)或各向异性导电胶(ACA)进行连接。 US 6. 448,661 show a prior art example, wherein the chip using a conductive adhesive such as anisotropic conductive film (ACF) or an anisotropic conductive adhesive (ACA) is connected. 另一个粘胶键合的例子如US 4,897,708所示,其中晶圆是通过粘胶进行键合,而电互连是通过一种导电液体建立。 Another example adhesive bonded as shown in US 4,897,708, where the wafer is bonded by adhesive, and electrically interconnected by an electrically conductive liquid is established. 但是,虽然粘胶键合是低成本的,并且不会发生重大的制造问题,但它在通孔上提供较差的电信号的互连,通常不适用于高电流,因此并不可靠。 However, although the adhesive bonding is a low cost, and without a significant manufacturing problem, but it provides a poor electrical interconnection on the through-hole, generally not suitable for high current, and therefore not reliable.

[0008] 一个焊接键合方法的例子如US 6,577,013所示。 [0008] Examples of a bonding method of welding as shown in US 6,577,013. 在焊接键合时,焊料被施加在将被叠层的半导体组件上的通孔结合(junction)处。 Bonded to the solder, the solder is applied to the through hole on a semiconductor stack assembly is combined (Junction) at. 焊接键合不需要如扩散键合所需要的高温度,但仍能产生一个良好可靠的键合。 The diffusion welding does not require high bonding temperatures required for bonding, but still produce a good reliable bond. 但是,随着被叠层组件数目的增加,焊接键合将遭遇难题。 However, as the number of stack assembly is increased, the bonding solder will encounter difficulties. 一个焊接键合的例子可以在US 7,317,256内找到,其描述了多个叠层晶圆的键合,另一个例子是US 7,215,033。 Examples of a weld bond can be found in the US 7,317,256, which describes a plurality of bonding wafers stacked, another example US 7,215,033. 但是,在此方法里,当一个新晶圆被添加到叠层中时,需进行焊接过程而形成一个IMC,将新晶圆连接到叠层,在其它晶圆之间之前形成的IMC在高焊接温度下迅速生长。 However, in this method, when a new wafer is added to the stack, the need for a welding process to form the IMC, the connection to the new wafer stack, before the IMC is formed between the other wafer high grow rapidly at soldering temperatures. 由于IMC通常是一个硬而脆的材料,很易出现失效问题(如在坠落鉴定测试中出现)。 Since IMC is often a hard and brittle material, it is prone to failures (such as identification tests appear in the fall). 此外,如果在制作过程中没有控制好焊料量,在多个焊接步骤上没有形成IMCs的剩余焊料将再次回焊,这样将破坏其可靠性,并产生制造瑕疵,在严重情况下可能导致失效。 Further, if the amount of solder is not good control in the production process, is not formed in the step of welding a plurality of IMCs the remaining solder reflow again, which would destroy its reliability, and generate manufacturing defects, in severe cases may lead to failure.

[0009] 发明概述 [0009] Summary of the Invention

[0010] 本发明提供一个形成晶圆叠层的方法,步骤包括:将多个晶圆叠放,每个所述晶圆具有至少一个硅通孔,焊料填充在硅通孔中并延伸至相邻晶圆的硅通孔处,所述晶圆通过在相邻晶圆之间的粘胶层被键合在一起,并使所述叠层仅经历一次焊接过程,从而使所述硅通孔通过所述焊料达成电互连。 [0010] The present invention provides a method of forming a wafer stack, comprising the steps of: stacking a plurality of wafers, each wafer having at least one silicon vias, and a solder filled vias extend through the silicon phase TSV at the neighborhood of the wafer, the wafer by an adhesive layer between the adjacent wafers together are keys, and the laminate subjected to only one welding process, such that said TSV electrically interconnected by the solder reached.

[0011] 为更好地实现键合,粘胶层被图案化以定义从至少一些所述硅通孔延伸到一个叠层边缘的通道。 [0011] To better achieve bonding, the adhesive layer is patterned to define extending from at least some silicon via a stack to the edge of the channel. 例如,粘胶层需具有感光性,可通过曝光被图案化。 For example, for an adhesive layer having photosensitivity, the exposure can be patterned.

[0012] 在本发明中,粘胶层被图案化以定义出围住晶圆内每个硅通孔的互连空间。 [0012] In the present invention, the adhesive layer is patterned to define an enclosed space for each interconnecting through holes in the silicon wafer. 空间可以是环形的,或任何其它合适的形状。 Space may be annular, or any other suitable shape. 在通常情况下,一个晶圆内至少有两个硅通孔,其互连空间通过通道连接。 Under normal circumstances, there is a wafer of silicon through at least two holes, connected by a passage space which interconnects. 例如,一个晶圆可以具有规则排列的硅通孔,而每个互连空间通过通道被连接到所有相邻硅通孔的互连空间。 For example, a silicon wafer may have through-holes regularly arranged, while the space is connected to each of the interconnect all adjacent silicon vias are interconnected through the channel space.

[0013] 在一个特别的实施例里,所述粘胶层的图案依晶圆的芯片设计被分割成多个部分,其分割线在所述粘胶层上形成主通道,并延伸到至少一个晶圆边缘,其中每个所述部分包括至少一个硅通孔,有一个通道从所述硅通孔的互连空间延伸到一个所述主通道。 [0013] In one particular embodiment, the adhesive layer of the pattern is divided into a plurality of portions of a wafer according to chip design, which parting line is formed on the main channel in the adhesive layer, and extending into the at least one wafer edge, wherein each said portion comprises at least one silicon vias, interconnect has a channel extending from the space to the silicon via said main channel a.

[0014] 特别地,叠层在所述焊接键合过程期间需被实施压力(loadingcompression)。 [0014] In particular, the welding stack during the bonding process pressure needs to be implemented (loadingcompression).

[0015] 依照本发明另一个方面,一个晶圆叠层,包括在一个叠层内排列的多个晶圆,每个晶圆包括至少一个硅通孔,其中相邻晶圆通过一个介入其间的粘胶层被键合在一起,其中晶圆之间的电互连是通过相邻层上硅通孔之间的焊料而形成。 [0015] According to another aspect of the present invention, a wafer stack, comprising a plurality of wafers arranged in a stack, each comprising at least one silicon wafer through hole, through which a wafer adjacent intervening therebetween bond adhesive layer are brought together, wherein the electrical interconnection between the wafer is formed by solder between adjacent layers on silicon vias.

[0016] 粘胶层被图案化以定义从至少一些所述硅通孔延伸到叠层装配边缘的通道。 [0016] The adhesive layer is patterned to define extending from at least some of the stacked assembly TSV edge channel. 特别地,粘胶层可以被图案化以定义一个围住晶圆上每个硅通孔的互连空间。 In particular, the adhesive layer may be patterned to define a space surrounded interconnect vias on each silicon wafer. 此空间可以是环形的,或任何其它合适的形状。 This annular space may be, or any other suitable shape.

[0017] 在特别实施例里,每个晶圆上形成至少两个硅通孔,围住所述硅通孔的互连空间通过通道连接。 [0017] In a particular embodiment, the through-holes are formed at least two silicon wafers each, interconnect space enclosing said silicon vias are connected through the channel. 例如,一个晶圆可以有规则排列的硅通孔,其中每个所述硅通孔的互连空间通过通道被连接到所有相邻互连空间。 For example, a silicon wafer may be regularly arranged through-holes, wherein each of said spaces interconnecting silicon vias are connected to all adjacent space through the interconnecting passage.

[0018] 在一个特别优选的实施例里,所述粘胶层的图案依晶圆的芯片设计被分割成多个部分,其分割线在所述粘胶层上形成主通道,并延伸到至少一个晶圆边缘,其中每个所述部分包括至少一个硅通孔,有一个通道从所述硅通孔的互连空间延伸到一个所述主通道。 [0018] In a particularly preferred embodiment, the pattern of the adhesive layer is divided into a plurality of portions by a wafer chip design, which parting line is formed on the main channel in the adhesive layer, and extends at least a wafer edge, wherein each said portion comprises at least one silicon vias, interconnect has a channel extending from the space to the silicon via said main channel a.

附图说明 BRIEF DESCRIPTION

[0019] 现参考附图并通过范例,将描述本发明的一些实施例,其中: [0019] Referring now to the drawings and by way of example, some embodiments of the present invention will be described, wherein:

[0020] 图1是依照本发明一个实施例的一个晶圆叠层的俯视图; [0020] FIG. 1 is a plan view in accordance with the present invention, a wafer stack according to the embodiment;

[0021] 图2是沿着图1内线AA的截面图; [0021] FIG. 2 is a sectional view taken along the extension of FIG. 1 AA;

4[0022] 图3是描述粘胶图案化的一个晶圆的截面图;和 4 [0022] FIG. 3 is a sectional view of a wafer patterned adhesive; and

[0023] 图4到12显示一个建立如图1和2所示的叠层晶圆装配的制作过程。 [0023] FIGS. 4-12 show the establishment of a production process as shown in FIG. 1 and the wafer stack assembly shown in Figure 2.

[0024] 优选实施例详述 [0024] Detailed Description of preferred embodiments

[0025] 图1显示本发明一个实施例,一个圆形晶圆叠层100,具有四个芯片110-113。 [0025] FIG. 1 shows an embodiment of the present invention, a circular wafer stack 100 having four chips 110-113. 图2 是沿着线AA的截面图,显示晶圆叠层的结构,多个TSV通过焊料实现电互连,各个晶圆通过粘胶层被连接在一起,粘胶层被图案化将在以下描述。 FIG 2 is a cross-sectional view along the line AA, shows the structure of the wafer stack, a plurality of electrically interconnected by solder TSV, the wafers are connected together by respective adhesive layer, the adhesive layer is patterned in the following description.

[0026] 在此例子里,每个芯片110-113有不同排列的通孔120 (如在110上是一个简单正方形,在111和112上是两行三个通孔,在芯片113上是一个正方形和一个中央通孔), 在每种情况下,粘胶层在每个通孔周围都形成一个互连空间,并直接通过通道或通过另一个互连空间连接到芯片边缘。 [0026] In this example, each different chips 110-113 are arranged with a through hole 120 (e.g., in a simple square 110, 111 and 112 are in two rows three through holes 113 on the chip is a squares and a central through-hole), in each case, the interconnection adhesive layer is formed a space around each through-hole, and directly connected to the chip through the channel or through another interconnection edge of space. 可以看到,粘胶层被互相垂直的主通道114-119分割成依晶圆上芯片的四个部分,主通道会连接到晶圆边缘。 Can be seen, the adhesive layer perpendicularly to each other by the main channel is divided into four sections 114-119 of the chips on the wafer, the main channel connects to the edge of the wafer. 在芯片110-113上的每个通道最终连接到一个主通道114-119,从而连接到晶圆边缘。 Each channel on the chip 110-113 is ultimately connected to a main channel 114-119 to connect to the edge of the wafer. 也可以理解,主通道114-119是由一个图案化的粘胶层形成,使得该粘胶层不是连续延伸覆盖在整个晶圆上,而是被分割成粘胶岛(adhesive island)对应四个芯片和晶圆周围部分。 It is also understood, 114-119 main channel is formed from a patterned layer of adhesive, such that the adhesive layer is not continuously extending over the entire wafer, but the island is divided into a glue (adhesive island) corresponding to the four chip and wafer peripheral portion. 通过这样分割粘胶层,可以在制作过程中释放应力。 By dividing the adhesive layer, the stress can be released during the production process.

[0027] 图2更详细地显示叠层晶圆的结构。 [0027] FIG. 2 shows the structure in greater detail of the wafer stack. 在此例子里,晶圆叠层包括6个晶圆10,其通过硅通孔(TSV) 12实现电互连。 In this case, the wafer stack comprises six wafers 10, which are electrically interconnected through the silicon vias (TSV) 12. TSV又通过位于TSV 12下端和金属焊盘15之间的焊料13 而互相键合,金属焊盘15在晶圆10上表面并覆盖TSV 12上端。 TSV and TSV 12 is positioned by the lower end of the solder and metal pads 15 between the 13 bond to each other, the metal pads 15 on the surface of the wafer 10 and the upper cover TSV 12. 晶圆10通过粘胶层16被物理键合在一起。 Wafer 10 by the adhesive layer 16 is physical keys together.

[0028] 为了便于理解,图3显示一个很简单的例子,其中TSV 12是一个简单的2X3阵列。 [0028] For ease of understanding, Figure 3 shows a very simple example, wherein the TSV 12 is a simple 2X3 array. 从图3可以看到,粘胶16被图案化以至在每个金属焊盘周围留下一个环形空间17。 As seen in Figure 3, as well as the adhesive 16 is patterned to leave an annular space 17 around each metal pad. 此外,粘胶16被图案化以定义互连通道18,其在每个环形空间17之间延伸,使得每个环形空间17通过这种互连通道都被连接到所有相邻的环形空间17,这样做的目的将在以下描述。 In addition, the adhesive 16 is patterned to define interconnect channels 18, each extending between the annular space 17, so that each annular space 17 are connected to all the adjacent annular space 17 through this interconnecting channels, the aim will be described below. 也会认识到,除了提供环形空间17之间的连接,还有一个互连通道18从每个环形空间17 通向叠层边缘19。 Will be appreciated, in addition to providing a connection between the annular space 17, there is a passage 18 leading to the interconnect stack 19 from each edge of the annular space 17.

[0029] 但是,应该注意到,图3仅显示本发明的一个简单实施例,其中TSV被安排成一个简单的规则的2X3阵列,其中每个TSV至少有一个互连通道18通向一个边缘19 (并且在四个角的TSV,有两个互连通道18通向两个边缘19)。 [0029] However, it should be noted that FIG. 3 only shows a simple embodiment of the present invention, wherein the TSV is arranged as a 2X3 array of simple rules, which each lead to a 18 TSV edge of at least one interconnecting channel 19 (and at the four corners of the TSV, there are two channels 18 leading to the two edges of the interconnect 19). 在更复杂或更大的结构里,可能有TSV被其它TSV围住所有边,所以可能无法直接连接到一个边缘,而是仅连接到其它周围的TSV0此外,虽然图3的例子是一个简单的规则阵列,其中互连通道互成直角,并且每个环形空间17连接四个互连通道18,在更复杂的图案里,可能有不同数目的通道18。 In larger or more complex configuration, the TSV may have other TSV all sides enclosed, it can not directly connect to one edge, but is connected only to the other around TSV0 Further, although the example of FIG. 3 is a simple regular array, wherein the interconnecting channels at right angles, and each of the annular space 17 is connected to four interconnecting channels 18, in a more complex patterns, may have different number of channels 18. 优选地,每个TSV都有互连通道18连接一个给定TSV到它的所有紧邻TSV,如果TSV在晶圆边缘的情况下,那么互连通道18就连接到边缘。 Preferably, each interconnect channels TSV has given a 18 TSV connections to all of its close proximity to TSV, if TSV wafer edge in the case, and even then the interconnecting channels 18 to the edge. 尽管这可能不是必需的,但是,重要的是提供了一个互连通道网络,使得对每个TSV而言,不管在不在晶圆边缘,都存在一个连续路径从围住TSV的环形空间17到晶圆边缘19,无论是直接地或经由其它环形空间17。 While this may not be necessary, however, important to provide a network of interconnected channels, such that for each TSV terms, whether in the absence of the wafer edge, there is a continuous path from the enclosed annular space 17 into the TSV crystal rounded edges 19, 17 either directly or via other annular space. 也可以理解,尽管在图1-3所示的实施例里,通过粘胶图案化环绕每个TSV 12的空间17是环形的,但这不是必需的,空间可以是其它可能的形状。 Can also be appreciated that although the embodiment illustrated in Figures 1-3, the adhesive is patterned by space 12 surrounding each TSV 17 is annular, but not necessarily, the space may be other possible shapes. 但是,可以理解,如果没有其它晶圆10被添加到叠层,将不会提供其它的粘胶层16到上表面。 However, it will be appreciated that, if no other wafer 10 are added to the stack, the other will not provide the adhesive layer 16 to the surface.

[0030] 以下描述将解释如何能够制作这种结构。 [0030] The following description will explain how such a structure can be produced. [0031] 起始点是一个由合适材料如硅制成的晶圆10(图4)。 [0031] The starting point is a wafer 10 (FIG. 4) is made of a suitable material is silicon. 接着,一个光刻胶层11被加在晶圆10的上表面,然后图案化,然后使用一个深反应离子蚀刻工艺来建立通孔12。 Next, a resist layer 11 is applied on the surface of the wafer 10 and then patterned, and then using a deep reactive ion etching process to create the through-hole 12. 在为通孔12制备了隔离层(如Si02)、粘附层(如Ti/W)和晶种层(如铜)之后,它们随后通过焊料电镀被填充满金属,通常是铜(Cu)或钨(W)或的其它合适材料,在完成填充金属的电镀之后,继续电镀一个薄焊料层(图5)。 In the through hole 12 of the insulating layer (such as Si02) is prepared, the adhesive layer (e.g., Ti / W) and the seed layer (e.g., copper), the metal which is subsequently filled up with solder plating, typically copper (Cu) or tungsten (W), or other suitable materials, after completion of plating the filler metal, a thin solder layer to continue plating (FIG. 5). 应该注意到,在此阶段,通孔12没有延伸穿过晶圆10的完全深度。 It should be noted that, at this stage, the through hole 12 does not extend through the full depth of the wafer 10. 然后,光刻胶层11被去除(图6),接着,晶圆10通过一个粘胶层20被安装在一个晶圆保持架14上(图7),然后,晶圆10经历一个去削过程如机械研磨、化学机械抛光、或化学或等离子蚀刻),直到通孔12的金属一直延伸穿过晶圆10(图8)。 Then, the photoresist layer 11 is removed (FIG. 6), then, a wafer 10 through adhesive layer 20 is attached to the holding bracket 14 (FIG. 7) on a wafer, and then, the wafer 10 undergoes a process to cut such as mechanical grinding, chemical mechanical polishing, or chemical or plasma etching) until the metal vias 12 extending through the wafer 10 (FIG. 8).

[0032] 仍然被系缚在托架14的晶圆10被倒转,接着在通孔12的露出端上形成金属焊盘15 (图9),在焊盘15和晶圆10之间有一个绝缘层。 [0032] In still anchor bracket 14 of the wafer 10 is inverted, and then forming a metal pad 12 on the exposed end of the through hole 15 (FIG. 9), the wafer 10 between the pad 15 and an insulation layer . 然后,一个粘胶层16被加到晶圆10的露出表面,并参照图1到3的以上所述和所示被图案化,使得一个环形空间17被定义在每个金属焊盘15周围。 Then, an adhesive layer 16 is applied to the exposed surface of the wafer 10, described above with reference to FIG. 1 to 3 and is patterned such that an annular space 17 is defined around each metal pad 15. 图案化粘胶层16也将包括如图1到3所示的互连通道18,其互连金属焊盘15周围的环形空间17,并且定义了将环形空间17连接到晶圆10边缘的通道。 The patterned adhesive layer 16 will also comprise 1 to 3, the interconnecting channels 18 as shown, the annular space 15 around the interconnected metal pad 17, and defines a passageway to the annular space 17 is connected to the edge of the wafer 10 . 特别地,粘胶层16是一个感光聚合物粘胶(如SU-8),其能够通过曝光被图案化。 In particular, the adhesive layer 16 is a photosensitive adhesive polymer (e.g., SU-8), which can be patterned by light exposure. 当然,可以理解,空间17不一定是环形,可能是其它形状。 Of course, it is understood that not necessarily the annular space 17, other shapes are possible.

[0033] 如图11所示,接着,晶圆托架14被倒转,通过一层胶19连接被图案化的粘胶16, 晶圆10被固定到一个硬基板18。 [0033] As shown in FIG 11, then the wafer carrier 14 is reversed, a hard board 18 is connected the patterned adhesive 16, 10 is fixed to the wafer by a layer of glue 19. 然后,移走晶圆保持架14,并再次用于制作第二晶圆。 Then, remove the wafer holder 14, and the second for the production of wafers again. 一旦制成第二晶圆后,会利用第二晶圆的图案化粘胶层16接触连接第一晶圆顶表面,第二晶圆被固定到第一晶圆10。 Once the prepared second wafer, the wafer will by the contact of the second patterned adhesive layer 16 is connected to the top surface of the first wafer, the second wafer to the first wafer 10 is secured. 再次移走晶圆保持架14,按要求重复过程,直到如图12所示完成 Wafer holder 14 is removed again, the process is repeated as required until completed as shown in FIG. 12

晶圆叠层。 Wafer stack.

[0034] 在完成晶圆叠层装配之后,接着,该装配仅经历一个焊接过程,使得所有焊接部分被键合连接到各个金属焊盘。 [0034] After completion of the wafer stack assembly, then this assembly is only subjected to a welding process, such that all the welded portion is bonded to a respective metal pad connections. 同时,此焊接过程也用来充当粘胶层的后固化(post-cure)。 Meanwhile, this welding process is used to serve as the adhesive layer after curing (post-cure). 可选地,在焊接/后固化过程期间,该晶圆叠层装配在负载压力(compression loading)之下,通过粘胶层增强晶圆键合连接。 Alternatively, during the welding / post-curing process, the wafer stack assembly under a load pressure (compression loading), by wafer bonding adhesive layer reinforcing the connection. 使用一个焊接过程能够避免由现有技术中多个焊接步骤引起的问题。 Using a welding process can be avoided the problem caused by the prior art, a plurality of welding step.

[0035] 可以理解,以上所述的过程是一个混合焊接键合/粘胶键合过程。 [0035] It will be appreciated, the above process is a hybrid welding bonding / adhesive bonding process. 焊接键合用来提供通孔之间的良好电互连,其能够在高电流上运行,并具有良好的可靠性。 Solder bonding to provide a good electrical interconnection between the through-hole, which is capable of running on a high current and good reliability. 叠层装配时粘胶层提供层之间的机械支撑,从而更便于晶圆加工,并在最后的晶圆叠层内提供额外的键合强度。 When the adhesive layer laminated assembly to provide mechanical support between the layers, making it easier to wafer processing, and provides additional bonding strength in the final wafer stack. 粘胶层的图案化提供了通道,使得焊接期间释放的气体能够排出,而通过将粘胶层分割成不同区域,压力得以释放,而对称的夹层结构(粘胶-硅-粘胶)能够平衡由CTE 不匹配引起的潜在弯曲。 The patterned adhesive layer provides a channel, so that the gas released during welding can be discharged, through the adhesive layer is divided into different areas, the pressure is released, and symmetrical sandwich structure (viscose - Si - viscose) to balance potential bending caused by mismatched CTE. 在焊接键合过程之后,晶圆叠层将分割成单个芯片(singularity process),将底部填充剂注入到图案化的粘胶层后,每个芯片被注膜成型。 Bonding process after the welding, dividing the wafer stack into individual chips (singularity process), underfill is injected into the patterned adhesive layer after each chip is injection molded membrane.

Claims (15)

1. 一个形成晶圆叠层的方法,步骤包括:将多个晶圆叠放,每个所述晶圆具有至少一个硅通孔,焊料填充在硅通孔中并延伸至相邻晶圆的硅通孔处,晶圆首先被相邻晶圆之间的粘胶层键合在一起,并使所述叠层仅经历一次焊接过程,使所述硅通孔通过所述焊料达成电互连,其中所述粘胶层被图案化以定义从至少一些所述硅通孔延伸到一个叠层边缘的通道。 1. A method of forming a wafer stack, comprising the steps of: stacking a plurality of wafers, each wafer having at least one silicon vias, the solder filling and extending to an adjacent wafer in TSV silicon vias, the wafer is first bonded together with an adhesive layer bonds between adjacent wafers, and the laminate subjected to only one welding process, the silicon is electrically interconnected by vias to reach the solder wherein said adhesive layer is patterned to define extending from at least some silicon via a channel to the edge of the stack.
2.根据权利要求1所述的方法,其中所述粘胶是一个感光粘胶,并通过曝光而被图案化。 2. The method according to claim 1, wherein said photosensitive adhesive is a glue, and is patterned by exposure.
3.根据权利要求1所述的方法,其中所述粘胶层被图案化以定义一个围住晶圆内每个硅通孔的互连空间。 3. The method according to claim 1, wherein said adhesive layer is patterned to define a space for each interconnect vias in the silicon wafer enclosed.
4.根据权利要求3所述的方法,其中所述互连空间是环形的,或者是其它合适的形状。 4. The method according to claim 3, wherein said annular space interconnect, or other suitable shape.
5.根据权利要求3所述的方法,其中在一个晶圆上形成至少两个硅通孔,围住所述硅通孔的互连空间通过通道互连。 5. The method according to claim 3, wherein forming at least two vias in a silicon wafer, the silicon enclosed space interconnected by a passage interconnecting vias.
6.根据权利要求3所述的方法,其中一个所述晶圆具有规则排列的硅通孔,其中每个互连空间通过通道被连接到所有相邻的互连空间。 6. The method according to claim 3, wherein said a silicon wafer having through-holes regularly arranged, wherein each of the interconnect space is connected to all adjacent space through the interconnecting passage.
7.根据权利要求3所述的方法,其中所述粘胶层的图案依晶圆的芯片设计被分割成多个区域,其分割线在所述粘胶层上形成主通道,并延伸到至少一个晶圆边缘,其中每个所述区域包括至少一个硅通孔,有一个通道从所述硅通孔的互连空间延伸到一个所述主通道。 7. The method according to claim 3, wherein the pattern of the adhesive layer is divided into a plurality of regions by a wafer chip design, which parting line is formed on the main channel in the adhesive layer, and extends at least a wafer edge, wherein each said region comprises at least one silicon vias, interconnect has a channel extending from the space to the silicon via said main channel a.
8.根据权利要求1所述的方法,其中所述叠层在所述焊接过程期间会接受压力负荷(compression loading)0 8. The method according to claim 1, wherein said stack during the welding process will accept the pressure load (compression loading) 0
9.根据权利要求1所述的方法,其中在键合过程完成之后,晶圆被分割成个别芯片,然后其经历一个底部填充及注膜成型过程。 9. The method according to claim 1, wherein after the bonding process is completed, the wafer is divided into individual chips, which then undergoes a underfill film and the injection molding process.
10. 一个晶圆叠层装配,包括多个晶圆排列在一个叠层内,每个所述晶圆包括至少一个硅通孔,其中相邻晶圆通过一个介于其间的粘胶层而被键合在一起,其中所述晶圆之间的电互连是由在相邻层里的硅通孔之间的焊料形成,其中所述粘胶层被图案化以定义从至少一些所述硅通孔延伸到一个叠层装配边缘的通道。 10. a wafer stack assembly, comprising a plurality of wafers arranged in a stack, each of said silicon wafer comprises at least one through hole, through which a wafer adjacent the adhesive layer interposed therebetween is bonded together, wherein the electrical interconnection between the wafer is formed between the silicon solder in the vias in adjacent layers, wherein the adhesive layer is patterned to define at least some of the silicon from a through hole extending to the edge of the channel assembly stack.
11.根据权利要求10所述的一个晶圆叠层装配,其中所述粘胶层被图案化以定义一个围住晶圆上每个硅通孔的互连空间。 A wafer according to claim 10, said assembly stack, wherein the adhesive layer is patterned to define a space for each TSV interconnections on the wafer enclosed.
12.根据权利要求11所述的一个晶圆叠层装配,其中所述互连空间是环形的,或者任何其它合适的形状。 12. The wafer stack assembly as claimed in claim a 11, wherein said annular space interconnect, or any other suitable shape.
13.根据权利要求12所述的一个晶圆叠层装配,其中在一个晶圆上形成至少两个硅通孔,其互连空间通过通道连接。 13. a wafer stack assembly as claimed in claim 12, wherein forming at least two through-holes in a silicon wafer, which is connected by a passage interconnecting space.
14.根据权利要求13所述的一个晶圆叠层装配,其中一个所述晶圆具有规则排列的硅通孔,其互连空间通过通道被连接到所有相邻硅通孔的互连空间。 A wafer according to claim 13, said stack assembly, wherein a silicon wafer with the regularly arranged through-holes, which space is connected to the interconnection interconnecting all adjacent space silicon vias through the channel.
15.根据权利要求10所述的一个晶圆叠层装配,其中所述粘胶层上的图案依晶圆的芯片设计被分割成多个区域,其分割线在粘胶层上形成主通道,并延伸到至少一个晶圆边缘, 其中每个所述区域包括至少一个硅通孔,有一个通道从其互连空间延伸到一个所述主通道。 A wafer according to claim 10, said assembly stack, wherein the pattern design on said adhesive layer is divided into a plurality of regions by the wafer chip, which parting line is formed on the adhesive layer in the main channel, and extending into the at least one edge of the wafer, wherein each of said at least one region comprises silicon vias, interconnect has a channel extending from the space to a main channel.
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