CN108231747A - Semiconductor devices and preparation method thereof, electronic device - Google Patents
Semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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- CN108231747A CN108231747A CN201611192743.9A CN201611192743A CN108231747A CN 108231747 A CN108231747 A CN 108231747A CN 201611192743 A CN201611192743 A CN 201611192743A CN 108231747 A CN108231747 A CN 108231747A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, electronic device, which includes：Device wafers are provided, separation layer is formed in the device wafers, multilayer laminate constructions are formed on the separation layer, every layer of stepped construction includes one layer of metal layer and one layer of dielectric layer for covering the metal layer, metal layer described in multilayer forms at least one inductance coil structure, and magnetic core is formed in stepped construction position corresponding with the inductance coil structure centre region.The production method can improve the induction coefficient and inductance value of inductance component, and then improve the radio-frequency performance of the semiconductor devices such as RF devices.Advantage as the semiconductor devices and electronic device concrete kind.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technology
With the fast development of wireless mobile telecommunication technology, RF IC becomes more and more important, and radio frequency integrates electricity
Road is a kind of integrated circuit being operated in 300MHz~300GHz frequency ranges.In RF IC, inductor plays
Very important effect becomes a kind of electronic component of key and is widely used in various RF ICs, such as
Voltage controlled oscillator, low-noise amplifier and frequency mixer etc. are required for using inductor, with meet low-loss, it is highly integrated will
It asks.
And the inductance integrated in current semiconductor devices, induction coefficient is generally all relatively low, this is because inductor
Part area is smaller, and the number of turns is less, and the magnetic property of internal membrane is relatively low, this is unfavorable for meeting the integrated circuits such as radio frequency to inductance
Device increasingly higher demands.In current manufacture craft, in order to obtain the inductance value of bigger, need to make more toroids
Coil structures, this will occupy very more chip areas, be unfavorable for the integrated of chip.
It is, therefore, desirable to provide a kind of semiconductor devices and preparation method thereof, electronic device, above-mentioned to solve at least partly
Problem.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention proposes a kind of semiconductor devices and preparation method thereof, can improve electricity
The induction coefficient and inductance value of inductor component, and then improve the radio-frequency performance of the semiconductor devices such as RF devices.
In order to overcome the problems, such as that presently, there are one aspect of the present invention provides a kind of production method of semiconductor devices, packet
It includes：Device wafers are provided, separation layer is formed in the device wafers, multilayer laminate constructions is formed on the separation layer, often
The layer stepped construction includes one layer of metal layer and one layer of dielectric layer for covering the metal layer, and metal layer described in multilayer is formed at least
One inductance coil structure forms magnetic core in stepped construction position corresponding with the inductance coil structure centre region.
Further, every layer of stepped construction is formed by following step：On the separation layer or underlying dielectric layers
Form the first barrier layer and/or the first Seed Layer；Patterned light is formed on first barrier layer and/or the first Seed Layer
Photoresist layer, the patterned photoresist layer are used to define the pattern of every layer of metal layer；With the patterned photoresist
Layer carries out copper electroplating technology for mask, to form the metal layer；Remove the patterned photoresist layer；Removal is located at described
First barrier layer and/or the first Seed Layer except metal layer bottom；The dielectric layer for covering the metal layer is formed, and right
The dielectric layer is patterned, so as to form the first through hole for being connect with lower metal layer in the dielectric layer, with
And in the dielectric layer corresponding with inductance coil structure centre region position formed for fill magnetic material the
Two through-holes.
Further, corresponding second through-hole is sequentially communicated in every layer of dielectric layer.
Further, the dielectric layer is polyimides.
Further, the step of forming the dielectric layer for covering the metal layer, and being patterned to the dielectric layer is wrapped
It includes：The coating polyimide film on the metal layer is patterned the Kapton by exposed and developed,
So as to be formed in the Kapton for the first through hole that is connect with lower metal layer and in the polyimides
Position corresponding with the inductance coil structure centre region forms the second through-hole for filling magnetic material in film；To institute
It states Kapton to be toasted, so that the Kapton has dielectric property.
Further, magnetic core is formed in stepped construction position corresponding with the inductance coil structure centre region
Step includes：The second barrier layer and/or second seed are formed on the surface of the stepped construction and the bottom of second through-hole
Layer；The photoresist layer of figure, the patterned photoresist layer tool are formed on second barrier layer and/or second of sublayer
There is opening corresponding with second through-hole；The galvanizer of magnetic material is carried out using the patterned photoresist layer as mask
Skill to fill magnetic material in second through-hole, forms magnetic core.
Further, the magnetic core includes iron and nickel.
Further, the iron-holder of the magnetic core is 10%~80%.
Further, it further includes：The pad or convex block for encapsulation are formed on the surface of the stepped construction.
The production method of semiconductor device according to the invention forms inductance component by multilayer laminated metal layer, increases
Add the number of coils of inductance component, and magnetic core is formed by adding magnetic material in the central area of inductance component, so as to
Further improve inductance coefficent so that the inductance ability of inductance component greatly improves.
Another aspect of the invention provides a kind of semiconductor devices, including：Device wafers are formed in the device wafers
There is separation layer, multilayer laminate constructions are formed on the separation layer, include one layer of metal layer per multilayer laminated structure and one layer covers
The dielectric layer of the metal layer is covered, metal layer described in multilayer forms at least one inductance coil structure, in the dielectric layer and every
The corresponding position in central area of a inductance coil structure forms magnetic core.
Further, the dielectric layer is polyimides.
Further, the magnetic core includes iron and nickel.
Further, the iron-holder of the magnetic material is 10%~80%.
Semiconductor devices proposed by the present invention increases the number of coils of inductance component by multiple layer metal layer stackup, and
Increase induction coefficient by forming magnetic core in hub of a spool region, so as to substantially increase the inductance ability of device, Jin Erti
The radio-frequency performance of the semiconductor devices such as height RF devices.
Further aspect of the present invention provides a kind of electronic device, including semiconductor devices as described above and with it is described partly
The electronic building brick that conductor device is connected.
Electronic device proposed by the present invention since the semiconductor devices inductance ability included greatly improves, thus has
The advantages of similar.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 shows the illustrated steps flow of the production method of semiconductor devices according to an embodiment of the present invention
Figure；
The production method that Fig. 2A~Fig. 2 G show semiconductor devices according to an embodiment of the present invention is implemented respectively successively
Step obtains the schematic cross section schematic diagram of semiconductor devices；
Fig. 3 shows the schematic plan of semiconductor devices according to an embodiment of the present invention；
Fig. 4 shows the sectional view of semiconductor devices according to an embodiment of the present invention；
Fig. 5 shows the structure diagram of electronic device according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.Disclosure will be made thoroughly and complete, and will fully convey the scope of the invention on the contrary, providing these embodiments
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated phase from beginning to end
The identical element with reference numeral expression.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer or
There may be element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or during layer, then there is no elements or layer between two parties.Art can be used although should be understood that
Language first, second, third, etc. describe various elements, component, area, floor and/or part, these elements, component, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish an element, component, area, floor or part and another
Element, component, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and be used so as to describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further include using and
The different orientation of device in operation.For example, if the device overturning in attached drawing, then, is described as " below other elements "
Or " under it " or " under it " elements or features will be oriented to other elements or features " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
As previously mentioned, the inductance component inductance coefficent integrated in semiconductor devices at present is relatively low, and constraint device development, this hair
Bright to propose a kind of production method of semiconductor devices based on this, for making inductance component, which includes：Device is provided
Wafer forms separation layer in the device wafers, and multilayer laminate constructions are formed on the separation layer, and every layer of described is laminated is tied
Structure includes one layer of metal layer and one layer of dielectric layer for covering the metal layer, metal layer described in multilayer form at least one inductance coil
Structure forms magnetic core in stepped construction position corresponding with the inductance coil structure centre region.
The production method of semiconductor device according to the invention forms inductance component by multilayer laminated metal layer, increases
Add the number of coils of inductance component, and magnetic core is formed by adding magnetic material in the central area of inductance component, so as to
Further improve inductance coefficent so that the inductance ability of inductance component greatly improves.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiment.
Embodiment one
Production methods of Fig. 1, Fig. 2A~Fig. 2 G and Fig. 3 to the semiconductor devices of an embodiment of the present invention will be joined below
It is described in detail.
First, step 101 is performed, device wafers are provided, it is described to include Semiconductor substrate 200 and device including device wafers
Layer 201 forms separation layer 202 in the device wafers, the first barrier layer and/or Seed Layer is formed on the separation layer
203, the photoresist layer 204 of the change of figure is formed on first barrier layer and/or Seed Layer 203, with the change of the figure
Photoresist layer 204 for mask carry out copper electroplating technology, to form the first metal layer 205, the structure formed is as shown in Figure 2 A.
Semiconductor substrate 200 can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、SiGeC、
Either other III/V compound semiconductors further include multilayered structure of these semiconductors composition etc. or are by InAs, GaAs, InP
Silicon (SSOI) is laminated on silicon-on-insulator (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator are laminated on insulator
SiClx (SiGeOI) and germanium on insulator (GeOI) etc..As an example, in the present embodiment, the composition of Semiconductor substrate 200
Material selection monocrystalline silicon.Device layer 201 could be formed with various semiconductor devices and interconnection structure, such as can include such as
The various circuit structures of NMOS, PMOS transistor composition, interconnection layer can be various interconnection structures, for each semiconductor devices
It is electrically connected.In addition, can also be formed with isolation structure in the semiconductor substrate, the isolation structure is shallow trench isolation
(STI) structure or selective oxidation silicon (LOCOS) isolation structure.
Various dielectrics or dielectric material, such as oxide, nitride etc. may be used in separation layer 202, can pass through heat
The common methods such as oxidizing process, PVD (physical vapour deposition (PVD)), CVD (chemical vapor deposition), ALD (atomic layer deposition) are formed.
First barrier layer and/or Seed Layer 203 are according to the material selection suitable material of metal layer.Illustratively, at this
In embodiment, metal layer uses copper, thus the first barrier layer and/or Seed Layer 203 illustratively using titanium nitride barrier layer and
Copper seed layer.It certainly in other embodiments, can also be as needed only with barrier or Seed Layer.
The photoresist layer 204 of the change of figure is formed by photoetching process commonly used in the art, such as photoresist layer coating, exposure
The operations such as light, development are formed, and the photoresist layer 204 of the change of figure is used to define the pattern of the first metal layer 205 namely definition electricity
Feel the shape or structure of coil.It is exemplary, as shown in figure 3, the coil as shown in Fig. 3 300 may be used in the first metal layer 205
Shape and structure.
The first metal layer 205 is the first layer coil of inductance component, and the photoresist layer 204 by the change of figure is to cover
Film is formed by copper electroplating technology, and copper electroplating technology is maturation process commonly used in the art, and this will not be repeated here.
Then, step 102 is performed, removes 204 and first barrier layer of photoresist layer and/or the Seed Layer of the change of figure
203 are located at the part except the first metal layer 205, and the structure formed is as shown in Figure 2 B.
The photoresist layer 204 of the change of figure can be removed by the methods of suitable photoresist solvent or ashing (Ash).
The part that first barrier layer and/or Seed Layer 203 are located at except the first metal layer 205 can be gone by wet processing
It removes, such as the wet method work carried out by using one or more of mixed liquors such as hydrofluoric acid, nitric acid, phosphoric acid, acetic acid, hydrogen peroxide, water
Skill removes.
Then, step 103 is performed, the first medium layer 206 of covering the first metal layer 205 is formed, in the first medium
The first through hole 207 for being connect with the first metal layer is formed in layer 206, and in 206 and first gold medal of first medium layer
Belong to the corresponding position formation in central area of layer 205 for filling the second through-hole 208 of magnetic material, the structure formed is as schemed
Shown in 2C.
Various dielectric materials, such as oxide, nitride, nitrogen oxides etc. may be used in first medium layer 206.In this reality
It applies in example, in order to which preferably integrated copper electroplating technology and magnetic material electroplating technology, first medium layer 206 use polyimides
(Polyimide).First medium layer 206 is illustratively formed by following step：
First, the coating polyimide material on separation layer 202 and the first metal layer 205, to cover the first metal layer 205
Kapton is covered with separation layer 202；Then, it is formed and is used in Kapton by the operation such as expose, develop
The first through hole 207 that is connect with the first metal layer and in Kapton it is corresponding with the central area of metal layer 205
Position forms the second through-hole 208 for filling magnetic material；Baking process is finally performed, makes Kapton that medium be presented
The property of layer, may be used as dielectric layer, makes adjacent metal layer electrically isolated from one.
Then, step 104, i.e. repeatedly step 101~103 are performed, to form multilayer laminate constructions.
Illustratively, repeatedly step 101~103 in the present embodiment, to form second metal layer 209 and second dielectric layer
210.Wherein shown in pattern reference Fig. 3 coils 300 of second metal layer 209, be formed in second dielectric layer 210 for
The first through hole 211 of second metal layer connection, and in the central area of the second dielectric layer 210 and second metal layer 209
Corresponding position forms the second through-hole 208 for filling magnetic material.In first medium layer 206 and second dielectric layer 210
Second through-hole 208 communicates with each other, and collectively forms the second through-hole for filling magnetic material, the structure formed such as Fig. 2 D institutes
Show.
It is understood that the quantity of metal layer and dielectric layer can form multilayered structure according to the design of inductance coil,
Such as layer 2-4, in the present embodiment, 2 two metal layers and dielectric layer are only shown schematically, but it is not formed to the present invention's
It limits.
Then, step 105 is performed, magnetic material is filled in second through-hole 208, to form magnetic core 215, is formed
Structure as shown in Figure 2 E.
First, the second barrier layer/or Seed Layer 212 are formed on 210 surface of second dielectric layer and 208 bottom of the second through-hole,
Second barrier layer/or Seed Layer 212 are exemplary for iron/nickel barrier layer/or Seed Layer.
Then, patterned photoresist layer 213, patterned photoresist are formed on the second barrier layer/or Seed Layer 212
213 have and 208 corresponding opening 214 of the second through-hole.Then electroplating technology is passed through for mask with patterned photoresist layer 213
Magnetic material is filled, to form magnetic core 215.
Wherein, the magnetic material of magnetic material such as iron and nickel composition, wherein iron content is, for example, 10%~80%, example
Property, such as iron content is 25%.
It is appreciated that the quantity inductance component of magnetic core 215 or the quantity of coil are set, only show in attached drawing 2A~Fig. 2 G
Meaning property provides one, as shown in figure 3, when including two inductance coils 300, it can be in each 300 structure of inductance coil
Heart district domain forms a magnetic core 301.
Then, step 106 is performed, removes patterned 213 and second barrier layer/of photoresist layer or Seed Layer 212
Part except 215 bottom of magnetic core, the structure formed is as described in Fig. 2 F.
Patterned photoresist layer 213 can be removed by suitable photoresist solvent or ashing method, and the second barrier layer/
Or the part that Seed Layer 212 is located at except 215 bottom of magnetic core can be removed by suitable wet processing, for example, by using hydrogen fluorine
The wet processing removal that the one or more mixed liquor such as acid, nitric acid, phosphoric acid, acetic acid, hydrogen peroxide, water carries out.
Further, in the process, also removal simultaneously is located at photoresist or barrier/seed layers in first through hole 211
Deng.
Finally, step 107 is performed, copper post or convex block for encapsulation, institute are formed in the first through hole of top dielectric layer
The structure of formation is as shown in Figure 2 G.
Illustratively, in the present embodiment, the copper for encapsulation is formed in the first through hole 211 of second dielectric layer 210
Column 216, copper post 216 are formed by common photoetching, plating, wet processing, and details are not described herein.
Illustratively, in the present embodiment, copper post 216 include underlying copper post part and positioned at copper post at least
Soldering ball portion.
So far, the processing step implemented according to the method for the embodiment of the present invention is completed, it is to be understood that the present embodiment
Manufacturing method of semiconductor device not only includes above-mentioned steps, before above-mentioned steps, among or may also include other needs later
The step of.
Although it is understood that in the production method of this implementation, the more metal layers and dielectric layer of formation are used for shape
Into inductance component structure, but in other embodiments, other than forming inductance component structure, can also be formed and lower section
Interconnection layer or the interconnection line of device layer connection.
Although it will also be appreciated that in the present embodiment using polyimides as dielectric layer, in other implementations
In example, other dielectric layers, such as oxide, nitride etc. can be also used as needed.
The production method for the semiconductor devices that the present embodiment proposes, by integrating the materials such as photoresist copper electroplating technology and iron
Electroplating technology, and using polyimides as dielectric layer, to form the stepped construction of more metal layers and dielectric layer, wherein gold
Belong to layer in inductance coil structure, position corresponding with inductance coil central area forms through-hole in the dielectric layer, and fills magnetism
Material forms magnetic core, which not only adds the number of coils of inductance component, and due to the central area shape in inductance coil
Into there is magnetic core, the induction coefficient of inductance component is substantially increased so that the inductance ability of device improves.
Embodiment two
The present invention also provides a kind of semiconductor devices, as shown in figure 4, the semiconductor devices includes：Device wafers, the device
Part wafer includes Semiconductor substrate 400 and device layer 401, separation layer 402 is formed in the device wafers, in the isolation
Multilayer laminate constructions are formed on layer 402, one layer of metal layer 403 and one layer of Jie for covering the metal layer are included per multilayer laminated structure
Matter layer 404, metal layer 403 described in multilayer form at least one inductance coil structure, in the dielectric layer 404 and each described
The corresponding position in central area of inductance coil structure forms magnetic core 405.
Wherein, Semiconductor substrate 400 can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include multilayered structure of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.As an example, in the present embodiment, Semiconductor substrate 400
Constituent material select monocrystalline silicon.Be formed with device layer 401 in Semiconductor substrate 400, device layer 401 include such as NMOS,
PMOS transistor, resistance, the various circuit structures of capacitance composition and the interconnection structure for connecting these devices, for various
Device, which is realized, to be electrically connected.In addition, can also be formed with isolation structure in the semiconductor substrate, the isolation structure is shallow trench
(STI) structure or selective oxidation silicon (LOCOS) isolation structure is isolated.
Various suitable metal materials, such as copper and aluminium may be used in metal layer 403, in the present embodiment, illustratively,
Metal layer 403 uses copper metal material.
Dielectric layer 404 can be various suitable dielectric materials, such as oxide, nitride or organic matter etc..It is exemplary
Ground, in the present embodiment, using polyimides as dielectric layer 404.
Various magnetic materials, such as iron and nickel may be used in magnetic core 405, and illustratively the iron-holder of magnetic core 405 is 10%
~80%, such as 25%.
The semiconductor devices of the present embodiment increases the number of coils of inductance component by multiple layer metal layer stackup, and passes through
Magnetic core is formed in hub of a spool region to increase induction coefficient, so as to substantially increase the inductance ability of device.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic device, including semiconductor devices and with the semiconductor device
The electronic building brick that part is connected.Wherein, which includes：Device wafers are formed with separation layer in the device wafers,
Multilayer laminate constructions are formed on the separation layer, includes one layer of metal layer per multilayer laminated structure and one layer covers the metal layer
Dielectric layer, metal layer described in multilayer forms at least one inductance coil structure, in the dielectric layer with each inductance
The corresponding position in central area of loop construction forms magnetic core.
Wherein, device wafers include Semiconductor substrate and device layer.Semiconductor substrate can be the following material being previously mentioned
At least one of：Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, are also wrapped
Include multilayered structure of these semiconductors composition etc. or for silicon (SSOI), insulator is laminated on silicon-on-insulator (SOI), insulator
Upper stacking SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..Semiconductor serves as a contrast
It could be formed with device, such as NMOS and/or PMOS etc. on bottom.Equally, conductive member can also be formed in Semiconductor substrate,
Conductive member can be grid, source electrode or the drain electrode of transistor or the metal interconnection structure being electrically connected with transistor, etc.
Deng.In addition, can also be formed with isolation structure in the semiconductor substrate, the isolation structure is shallow trench isolation (STI) structure
Or selective oxidation silicon (LOCOS) isolation structure.As an example, in the present embodiment, the constituent material of Semiconductor substrate is selected
Monocrystalline silicon.
Wherein, the electronic building brick can be any electronic building bricks such as discrete device, integrated circuit.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment or
Any intermediate products including the semiconductor devices.
Wherein, Fig. 5 shows the example of mobile phone.The outside of mobile phone 500 is provided with the display portion being included in shell 501
502nd, operation button 503, external connection port 504, loud speaker 505, microphone 506 etc..
The electronic device of the embodiment of the present invention, should since the semiconductor devices inductance ability included greatly improves
Electronic device equally has the advantages that similar.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (14)
1. a kind of production method of semiconductor devices, which is characterized in that including：
Device wafers are provided, separation layer is formed in the device wafers, multilayer laminate constructions is formed on the separation layer, often
The layer stepped construction includes one layer of metal layer and one layer of dielectric layer for covering the metal layer, and metal layer described in multilayer is formed at least
One inductance coil structure forms magnetic core in stepped construction position corresponding with the inductance coil structure centre region.
2. production method according to claim 1, which is characterized in that every layer of stepped construction passes through following step shape
Into：
The first barrier layer and/or the first Seed Layer are formed on the separation layer or underlying dielectric layers；
Patterned photoresist layer, the patterned photoresist are formed on first barrier layer and/or the first Seed Layer
Layer is used to define the pattern of every layer of metal layer；
Copper electroplating technology is carried out by mask of the patterned photoresist layer, to form the metal layer；
Remove the patterned photoresist layer；
Removal is located at first barrier layer and/or the first Seed Layer except the metal layer bottom；
The dielectric layer for covering the metal layer is formed, and the dielectric layer is patterned, so as to the shape in the dielectric layer
Into the first through hole for being connect with lower metal layer and in the dielectric layer with the inductance coil structure centre region
Corresponding position forms the second through-hole for filling magnetic material.
3. production method according to claim 2, which is characterized in that corresponding second through-hole connects successively in every layer of dielectric layer
It is logical.
4. production method according to claim 2, which is characterized in that the dielectric layer is polyimides.
5. production method according to claim 4, which is characterized in that form the dielectric layer for covering the metal layer, and right
The step of dielectric layer is patterned includes：
The coating polyimide film on the metal layer,
The Kapton is patterned by exposed and developed, is used so as to be formed in the Kapton
In the first through hole being connect with lower metal layer and in the Kapton with the inductance coil structure centre area
The corresponding position in domain forms the second through-hole for filling magnetic material；
The Kapton is toasted, so that the Kapton has dielectric property.
6. production method according to claim 2, which is characterized in that in the stepped construction and the inductance coil structure
The step of corresponding position in central area forms magnetic core includes：
The second barrier layer and/or second of sublayer are formed on the surface of the stepped construction and the bottom of second through-hole；
The photoresist layer of figure, the patterned photoresist layer are formed on second barrier layer and/or second of sublayer
With opening corresponding with second through-hole；
The electroplating technology of magnetic material is carried out using the patterned photoresist layer as mask, to be filled in second through-hole
Magnetic material forms magnetic core.
7. production method according to claim 1, which is characterized in that the magnetic core includes iron and nickel.
8. production method according to claim 7, which is characterized in that the iron-holder of the magnetic core is 10%~80%.
9. production method according to claim 1, which is characterized in that further include：
The pad or convex block for encapsulation are formed on the surface of the stepped construction.
10. a kind of semiconductor devices, which is characterized in that including：Device wafers are formed with separation layer in the device wafers,
Multilayer laminate constructions are formed on the separation layer, includes one layer of metal layer per multilayer laminated structure and one layer covers the metal layer
Dielectric layer, metal layer described in multilayer forms at least one inductance coil structure, in the dielectric layer with each inductance
The corresponding position in central area of loop construction forms magnetic core.
11. semiconductor devices according to claim 10, which is characterized in that the dielectric layer is polyimides.
12. semiconductor devices according to claim 10, which is characterized in that the magnetic core includes iron and nickel.
13. semiconductor devices according to claim 12, which is characterized in that the iron-holder of the magnetic material for 10%~
80%.
14. a kind of electronic device, which is characterized in that including the semiconductor device as described in any one in claim 10-13
Part and be connected with the semiconductor devices and electronic building brick.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN113539650A (en) * | 2020-04-17 | 2021-10-22 | 深南电路股份有限公司 | Method for processing inductance device in printed circuit board and printed circuit board |
| CN113690214A (en) * | 2020-05-19 | 2021-11-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method for forming semiconductor structure |
| CN113963935A (en) * | 2021-09-30 | 2022-01-21 | 厦门云天半导体科技有限公司 | Inductance structure and manufacturing method thereof |
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