CN105655316A - Chip-use polymer frame being connected with capacitor in series and having at least one hole - Google Patents

Chip-use polymer frame being connected with capacitor in series and having at least one hole Download PDF

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Publication number
CN105655316A
CN105655316A CN201510836740.3A CN201510836740A CN105655316A CN 105655316 A CN105655316 A CN 105655316A CN 201510836740 A CN201510836740 A CN 201510836740A CN 105655316 A CN105655316 A CN 105655316A
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CN
China
Prior art keywords
chip
layer
hole
socket
electrical condenser
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CN201510836740.3A
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Chinese (zh)
Inventor
卓尔·赫尔维茨
黄士辅
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Zhuhai Advanced Chip Carriers and Electronic Substrate Solutions Technologies Co Ltd
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Zhuhai Advanced Chip Carriers and Electronic Substrate Solutions Technologies Co Ltd
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Priority claimed from US14/555,633 external-priority patent/US10446335B2/en
Application filed by Zhuhai Advanced Chip Carriers and Electronic Substrate Solutions Technologies Co Ltd filed Critical Zhuhai Advanced Chip Carriers and Electronic Substrate Solutions Technologies Co Ltd
Publication of CN105655316A publication Critical patent/CN105655316A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

A chip-use polymer frame being connected with capacitor in series and having at least one hole limits a chip socket and includes at least one hole column layer. At least one hole surrounding the socket and passing through the frame includes at least one capacitor. The capacitor includes a lower electrode, a dielectric layer, and an upper electrode contacted with the hole columns.

Description

There is the chip polymer frame of at least one through hole connected with electrical condenser
Technical field
The present invention relates to the Chip Packaging of improvement, it is specifically related in Chip Packaging to be provided with the embedded chip of passive device such as electrical condenser and wave filter.
Background technology
Under the drive that the miniature requirement for more and more complicated electron device is increasing, such as the integrated level of the consumption electronic product such as computer and telecommunication apparatus is more and more higher. This has caused requirement supporting structure to be electrically insulated from each other by dielectric materials as IC substrate and IC plug-in unit have and highdensity multiple conductive layer and through hole.
The overall requirement of this kind of supporting structure is that reliability and suitable electric property, thinness, rigidity, Flatness, thermal diffusivity be good and competitive unit price.
Realizing in the various approach that these require, between the layer creating of a kind of extensive enforcement, the manufacturing technology of through-hole interconnection adopts laser drill, the hole bored out penetrates the dielectric substrate of follow-up layout until last metal level, follow-up filler metal, normally copper, this metal is deposited on wherein by coating technology. This kind of forming hole method is also sometimes referred to as " brill is filled out ", and consequent through hole can be called " through hole filled out by brill ".
Brill is filled out through-hole approaches and be there is multiple shortcoming. Because each through hole needs separately boring, thus productivity is limited and cost that is that manufacture complicated multi-through hole IC substrate and plug-in unit becomes high. In large-scale array, it is difficult to produce the closely adjacent each other of high-density and high-quality by boring embankment method and it is of different sizes the through hole with shape. In addition, the through hole that laser drilling goes out has through the coarse sidewall of dielectric materials thickness and interior to tapering. This tapering reduces the effective diameter of through hole. Particularly when super small through hole diameter, it is also possible to the electrical contact for conductive metal layer formerly has a negative impact, thus cause reliability problem. In addition, when the matrix material that drilled dielectric medium is glass or the ceramic fiber comprising in polymeric matrix, sidewall is coarse especially, and this kind of coarse spuious inductance that may produce to add.
The filling process of the through hole bored normally has been electroplated by copper. Electroplating deposition technology can cause indenture, wherein pitting occurs in via top. Or, when being filled the copper exceeding its saturation when through-hole passage, it is possible to cause spilling, thus produce the domed upper surface protruding past adjacent material. Indenture and overflow and often cause difficulty when such as manufacturing high-density base board and follow-up stacked on top through hole required during plug-in unit. Furthermore, it should be recognized that big through-hole passage is difficult to even filling, time near the small through hole of the same interconnection layer being particularly positioned at plug-in unit or IC substrate design at it.
Although As time goes on acceptable size and reliability are improved, but shortcoming mentioned above is the latent defect boring technology of filling out, and estimates to limit possible clear size of opening scope. It is further to be noted that laser drill is the best method manufacturing circular through-hole passage. Although the through-hole passage of shape of slit can be manufactured in theory by laser milling, but the geometrical shape scope that in fact can manufacture is more limited, and through hole in given supporting structure normally cylindrical and be substantially identical.
By boring, to fill out manufacture technics through hole be expensive, and is difficult to utilize the electroplating technology copper relatively with cost benefit all even unanimously to fill the through-hole passage thus formed.
In fact the hole that laser drilling goes out in composite dielectric material is limited in 60 �� 10-6M diameter, and due to involved ablation process and the character of matrix material bored, even therefore it is subjected to the disadvantageous effect of significant conical shape and coarse sidewall.
Except other restriction of laser drill mentioned above, bore another that fill out technology and it is limited in the through hole being difficult to produce different diameter within the same layer, this is because when bore out different size through-hole passage and subsequently with metal filled to manufacture different size through hole time, caused by the fill rate difference of through-hole passage. Therefore, worsened as the indenture of characteristic or the typical problem of spilling boring technology of filling out, because different size through hole can not be optimized deposition technique simultaneously.
The optional solution overcoming the multiple shortcomings boring embankment method is the technology utilizing and being also called " pattern plating ", by copper or other metal deposit being manufactured in the pattern formed in the photoresist.
In pattern plating, first deposit Seed Layer. Then deposit photoresist layer thereon, form pattern with post-exposure, and optionally remove to make the groove exposing Seed Layer. By depositing copper to, photoresist material groove forms through hole post. Then remove remaining photoresist material, etch away Seed Layer, and thereon and peripheral tier pressure be generally the dielectric materials of polymer impregnated glass mat, to surround described through hole post. , it is possible to use various technology and technique carry out dielectric materials described in planarization, then remove its part to expose the top of through hole post, thus allow thus conductive earthing, for forming next metal level thereon. Follow-up metal conductor layer and through hole post can be deposited thereon, to form required multilayered structure by repeating this process.
Substitute at one but in namely hereafter alleged " the panel plating " of the technology of closely association, continuous print metal or alloy is deposited on substrate. Photoresist layer is deposited at the top of substrate, and the pattern that develops wherein. Shelling the pattern except the photoresist material developed, optionally expose the metal under it, this metal can be etched subsequently. The photoresist material not developed protects the metal below it not etched, and leaves upright feature structure and the pattern of through hole.
Stripping except the photoresist material not developed after, it is possible in upright copper feature structure and/or through hole post or peripheral tier press dielectric materials, such as polymer impregnated glass mat. After planarization, follow-up metal conductor layer and through hole post is deposited thereon by repeating this process, to form required multilayered structure.
The via layer created by above-mentioned pattern plating or panel solution and coating method is called as " through hole post " and copper characteristic layer usually.
It will be appreciated that the general impellent that microelectronics develops relates to manufacturing less, thinner, lighter and more high-power has high reliability product.Use thick and have the interconnection of core can not obtain the product of ultra-thin. In order to form more highdensity structure in interconnection IC substrate or " plug-in unit ", it is necessary to have the more multi-layered of even less connection. In fact, sometimes wish to overlap each other stacking device.
If depositing coating layer laminated structure in the sacrificial substrate that copper or other are suitable, then can etch away substrate, staying independent of core laminate structures. Other layer can be deposited on the side being attached in advance in sacrificial substrate, thus can form dual-area layer, thus to greatest extent reduce warpage and contribute to realizing planarization.
A kind of flexible technique manufacturing high density interconnect builds the metal through hole or feature structure that are included in dielectric matrix at the multilayered structure of interior pattern or panel plating. Metal can be copper, and dielectric medium can be fiber-reinforced polymer, normally has high glass-transition temperature (Tg) polymkeric substance, such as polyimide. These interconnection can be have core or without core, and can comprise the cavity for stacking device. They can have odd number or even number layer. The technology realized describes in the existing patent authorizing Amitec-AdvancedMultilayerInterconnectTechnologiesLtd..
Such as, the US Patent No. 7 being entitled as " senior multilayered coreless support structure and manufacture method (Advancedmultilayercorelesssupportstructuresandmethodfort heirfabrication) thereof " of the people such as Hull dimension thatch (Hurwitz), 682, 972 describe a kind of method that manufacture comprises the independent film of via-hole array in the dielectric, described film is used as to build the precursor of excellent electronics supporting structure, the method comprises the following steps: manufacture conductive through hole film in the dielectric medium surrounding sacrificial carrier, with described film be separated with sacrificial carrier to be formed independent layer keep a situation well under one's control row. electric substrate based on this independent film subtracts thin and planarization by row of being kept a situation well under one's control by described layer, terminates through hole subsequently and is formed. this publication is incorporated to herein by reference comprehensively.
The US Patent No. 7 of being entitled as of the Hull dimension thatch people such as (Hurwitz) " for Chip Packaging without core cavity substrate and manufacture method (Corelesscavitysubstratesforchippackagingandtheirfabricat ion) thereof ", 669,320 describe a kind of method manufacturing IC supporter, and described IC supporter is for supporting the IC chip with the 2nd IC chip-in series; Described IC supporter is included in the stacking of the alternating layer of copper feature structure and the through hole insulated in adjacent material, a described IC chip can be bonded to described IC supporter, described 2nd IC chip can be bonded in the cavity of described IC supporter inside, and the copper that wherein said cavity falls accumulation by etching away copper socket and selective etch is formed. This publication is all incorporated to herein by reference.
The US Patent No. 7 being entitled as " integrated circuit support structures and manufacture method (integratedcircuitsupportstructuresandtheirfabrication) thereof " of the people such as Hull dimension thatch (Hurwitz), 635,641 describe a kind of method manufacturing electric substrate, comprise the following steps: (A) selects first foundation layer; (B) etch stop layer is deposited on described first foundation layer; (C) forming the first half stacked bodies of conductive layer alternately and insulation layer, described conductive layer interconnects by running through the through hole of insulation layer; (D) the 2nd basal layer is coated on described the first half stacked bodies; (E) photoresist material supercoat is coated on the 2nd basal layer;(F) described first foundation layer is etched away; (G) described photoresist material supercoat is removed; (H) described first etch stop layer is removed; (I) forming the 2 half stacked body of conductive layer alternately and insulation layer, conductive layer interconnects by running through the through hole of insulation layer; Wherein said 2 half stacked body has the structure substantially symmetrical with the first half stacked bodies; (J) insulation layer is coated on described 2 half stacked body of conductive layer alternately and insulation layer; (K) described 2nd basal layer is removed, and, (L) is by by through hole ends exposed and terminating thing to its coating and terminate substrate on the outside surface of described stacked body. This publication is all incorporated to herein by reference.
Along with the transition of time, it is contemplated that technology filled out by brill and through hole post deposition technique all can produce the substrate with more miniatureization and higher through hole and feature structure density. It will be apparent, however, that the development of through hole column technology probably will be retained its competitive edge.
Substrate can be realized chip and is connected by interface with other device. Chip must be engaged to substrate by assembling process, and this assembling process provides the telecommunication of electrical connection reliably to realize between chip and substrate.
It is embedded in plug-in unit to connect extraneous chip and can reduce Chip Packaging, shorten and extraneous connection, namely eliminate the assembling process of chip join substrate by simplified manufacturing technique and cost savings are provided, and potential improve reliability.
Substantially, embedded active part is such as simulated, numeral and the concept of MEMS chip relate to and be structured in chip supporting structure or the substrate that chip circumference has through hole.
The method realizing embedded chip manufactures a chip supporting structure on the chip array on wafer, and wherein the circuit of supporting structure is greater than chip unit size. This kind of method is known as fan-out wafer layer encapsulation (FOWLP). Although the size of Silicon Wafer constantly increases, but wafer size is still limited in 12 inches by the material module of costliness and processing procedure, thus limit the FOWLP element number can placed on wafer. Although in fact considering the wafer of 18 inches, but required investment, material module and equipment still belong to unknown. The quantity of the chip supporting structure that once can process is restricted and causes FOWLP unit cost to rise, and thus for the market needing high competition, such as radio communication, household electrical appliance and automobile market, cost is too high.
Also there is performance limitations in FOWLP, this is because be arranged on Silicon Wafer as the thickness of fan-out or the metal feature structure of fan-in circuit to be limited in several microns. This causes resistance problems.
The manufacture method of a kind of replacement relates to cutting wafer and with separating chips and is embedded in the panel being made up of dielectric layer and copper-connection by chip. An advantage of this kind of alternative method is that panel can do very big, thus embeds much more chip in first procedure. Such as, 12 inch wafer can realize the FOWLP chip that primary treatment 2500 is of a size of 5mm �� 5mm, and the panel that applicant and Zhuhai use before getting over suborder is 25 inches �� 21 inches, it is possible to realizes primary treatment 10000 chips. Because the price processing this panel is significantly lower than the price of process wafer, and the output of each panel is 4 times of wafer throughput, so unit price can significantly reduce, thus opens new market.
In these two kinds of technology, the line-spacing and the conductor width that adopt in the industry reduce in time, and for panel, standard is reduced to 10 microns from 15 microns, for wafer, are then reduced to 2 microns from 5 microns.
Embedded mode has many advantages. The first step is assembled the cost that such as wire-bonded, flip-chip or SMD (surface mount device) weld and is reduced. Due to the seamless link in single product of chip and substrate, so electrical property improves. Encapsulation chip becomes thinner, obtains better shape-dependent constant, and the upper surface embedding Chip Packaging is available due to other purposes, comprises further space and saves configuration, such as, uses the purposes of stacked chips and PoP (package on package) technology.
At FOWLP with based on, in both embedded core chip technology of panel, chip is packaged into array (on substrate or panel), and after finalization of the manufacture, passes through cutting and separating.
RF (radio frequency) technology, such as Wi-Fi, bluetooth etc., be just widely used in various equipment, comprising mobile telephone and automobile.
Except Base-Band Processing and memory chip, RF device also needs passive device especially, such as various types of electrical condenser, inducer and wave filter. This kind of passive device can surface mount, but in order to more significant miniatureization and cost savings can be realized, this type of device can be embedded in substrate.
The US13/962 being entitled as " ThinFilmCapacitorsEmbeddedinPolymerDielectric " that Hull dimension thatch (Hurwitz) was submitted on August 8th, 2013,075 describes a kind of substrate containing electrical condenser, described electrical condenser is made up of metal electrode and pottery or metal-oxide dielectric layer, and described electrical condenser is embedded in polymer-based carbon encapsulating material and can carry out junction circuit by the through hole post being arranged on described electrical condenser.
The US13/962,316 being entitled as " MultilayerStructuresandEmbeddedFeatures " that on August 8th, 2013 submits to describes a kind of compound electric minor structure, comprises the via layer that at least one characteristic layer is adjacent with at least one; Described layer extends on an x-y plane and has height z, and wherein said structure comprises at least one electrical condenser connected in series or in parallel with at least one inducer to provide dress at least one wave filter; At least one electrical condenser described is clipped between at least one through hole at least one characteristic layer and at least one adjacent via layer, make at least one through hole described stand upright on described at least on electrical condenser, and in fisrt feature layer and adjacent via layer at least it one comprises at least one inducer extended on an x-y plane.
The US14/269 being entitled as " InterposerFramewithPolymerMatrixandMethodsofFabrication " that Hull dimension thatch (Hurwitz) was submitted on May 5th, 2014,884 teach a kind of chip receptacle array limited by organic substrate framework, described framework, around the socket passed from described organic substrate framework, also comprises the metal through hole grid passed from described organic substrate framework. Chip can be arranged in socket and in position by polymer-based dielectric subsequently, is thus embedded in the frame by chip.
Summary of the invention
First aspect present invention relates to a kind of chip socket limited by organic substrate framework, wherein said organic substrate framework comprises at least one through hole post layer, at least one through hole wherein passing the framework surrounding described socket comprises at least one electrical condenser, the top electrode that at least one electrical condenser described comprises lower electrode, dielectric layer and contacts with described through hole post.
Usually, the dielectric medium of described electrical condenser comprises Ta2O5��TiO2��BaxSr1-xTiO3��BaTiO3And Al2O3In at least one.
Usually, the lower electrode of described electrical condenser comprises precious metal.
Optionally, described lower electrode comprises the metal being selected from gold, platinum and tantalum.
In some embodiments, described top electrode comprises the metal being selected from gold, platinum and tantalum.
Usually, at least one through hole described stands upright at least one electrical condenser described.
Optionally, described top electrode comprises described through hole post.
Preferably, described electrical condenser has the sectional area limited by the sectional area of described through hole post, and this sectional area is carefully controlled the electrical capacity regulating electrical condenser.
In some embodiments, at least one electrical condenser described has the electrical capacity of 1.5pF��300pF.
In preferred embodiments, at least one electrical condenser described has the electrical capacity of 5pF��15pF.
Optionally, described framework also comprises at least one characteristic layer.
Optionally, at least one electron device is embedded in described socket and is electrically connected with at least one through hole described.
Optionally, at least one electron device described comprises the 2nd electrical condenser.
In some embodiments, described 2nd electrical condenser is discrete device, and described discrete device at least has metal terminal in one end at it.
In some embodiments, described 2nd electrical condenser is metal-insulator-metal type (MIM) electrical condenser.
In some embodiments, described metal-insulator-metal type (MIM) electrical condenser comprises by being selected from Ta2O5��TiO2��BaxSr1-xTiO3��BaTiO3And Al2O3In at least one dielectric medium form dielectric layer.
In some embodiments, the lower electrode of described metal-insulator-metal type (MIM) electrical condenser comprises precious metal.
In some embodiments, described lower electrode comprises the metal being selected from gold, platinum and tantalum.
In some embodiments, the top electrode of described metal-insulator-metal type (MIM) electrical condenser comprises the metal being selected from gold, platinum and tantalum.
Optionally, described metal-insulator-metal type (MIM) electrical condenser is attached on isolator carrier.
In some embodiments, described isolator carrier comprises and is selected from silicon (Si), SiO2(silicon-dioxide), glass, AlN, aluminum oxide and c-surface sapphire Al2O3(0001) at least one in.
In some embodiments, the pole plate of described metal-insulator-metal type (MIM) electrical condenser is connected to through hole by characteristic layer.
Usually, the device being embedded in described socket is connected with at least one through hole with embedded capacitor device by least one characteristic layer.
Optionally, the characteristic layer that described system is also included in described framework one side, and described embedding device comprises inducer.
Optionally, the embedding device in described framework, the embedding device in described socket and at least one feature structure in described characteristic layer provide the circuit being used as wave filter.
Optionally, described wave filter is selected from basis LC low-pass filter (basicLClowpassfilters), LC Hi-pass filter (LChighpassfilters), LC serial band pass filter (LCseriesbandpassfilters), LC bandpass filter (LCparallelbandpassfilters) in parallel and low pass parallel connection-Chebyshev's wave filter (LowPassParallel-Chebyshevfilters).
Optionally, the chip being arranged in socket is by comprising the Faraday's cage electromagnetic radiation shielding of through hole post, and thus maximum degree reduces electromagnetic interference.
In some embodiments, the characteristic layer that described Faraday's cage is also included in described framework.
The another aspect of the present invention relates to a kind of framework, and described framework comprises the multiple sockets for holding multiple chip, and wherein each socket comprises a framework, and described framework comprises grid and at least one electrical condenser of copper vias post.
Optionally, it is embedded in treater chip at the first socket and it is embedded in, at the 2nd socket, the passive chip comprising at least one electrical condenser.
Another aspect of the invention relates to a kind of framework, and described framework comprises the multiple chip sockets being arranged in array, wherein around there being framework around each chip socket.
Optionally, at least one socket embeds at least one treater chip.
The present invention relates in one aspect to again a kind of chip receptacle array, described array is limited by the organic substrate framework of the framework around socket, and comprise the metal through hole post grid through described organic substrate framework, wherein at least one metal through hole post and at least one electrical condenser are connected in series.
Optionally, described electrical condenser comprises lower electrode and dielectric layer, and is combined in the bottom of at least one through hole post so that at least one through hole post described stands upright at least one electrical condenser described.
Optionally, at least one through hole post described comprises the top electrode of at least one electrical condenser described.
Optionally, described framework comprises at least one characteristic layer, wherein forms at least one inducer at least one characteristic layer described.
Usually, described organic substrate framework also comprises glass fiber bundle.
Usually, each through hole has the width range of 25 microns��500 microns.
Usually, each through hole is cylindrical and has the diameter of 25 microns��500 microns.
Usually, the framework around at least one socket comprises through hole post alternately and characteristic layer, and comprises at least one through hole post layer and a characteristic layer.
Usually, described organic substrate framework comprises multiple layer and described grid comprises multiple through hole post layer, wherein each is separated by characteristic layer by continuous print through hole post layer.
In some embodiments, the framework around at least one socket comprises the continuous coil of through hole post alternately and feature structure, crosses at least one through hole post layer and a characteristic layer.
Optionally, at least one through hole post comprises the through hole post of elongation.
Optionally, multiple through hole post layer crossed over by the continuous coil of the through hole post of elongation.
Optionally, described array comprises the adjacent chips socket of different physical dimension.
Optionally, described array comprises the adjacent chips socket of different size.
Optionally, described array comprises the adjacent chips socket of different shapes.
Optionally, described framework comprises at least one characteristic layer and at least one adjacent via layer, described layer extends in X-Y plane and has height z, wherein said compound electric minor structure comprises at least one electrical condenser being connected with at least one inducer, at least one electrical condenser described comprises lower electrode and dielectric layer, it is arranged on the bottom of via layer, it is clipped between at least one characteristic layer and through hole post, at least one through hole described in making stands upright at least one electrical condenser described and optionally forms top electrode, wherein said via layer embeds in the polymer matrix, and at least one inducer wherein said be formed in fisrt feature layer and adjacent via layer at least its among one.
Optionally, at least one electrical condenser and at least one inducer are connected in series.
Optionally, described framework is included at least second feature layer above described via layer, and at least one electrical condenser described and at least one inducer described are connected in parallel by described characteristic layer.
Optionally, at least one inducer described is manufactured in described characteristic layer.
Optionally, at least one inducer described is screw winding coil.
Optionally, the inductance value of described inducer is at least 0.1nH.
Optionally, the inductance value of described inducer is less than 50nH.
Optionally, via layer manufactures another inducer.
Optionally, the inductance value of another inducer described is at least 0.1nH.
Optionally, at least one inducer and at least one electrical condenser described provide wave filter, and described wave filter is selected from basis LC low-pass filter (basicLClowpassfilters), LC Hi-pass filter (LChighpassfilters), LC serial band pass filter (LCseriesbandpassfilters), LC bandpass filter (LCparallelbandpassfilters) in parallel and low pass parallel connection-Chebyshev's wave filter (LowPassParallel-Chebyshevfilters).
Optionally; at least one socket comprises chip; at least one electrical condenser that described chip is included in polymeric matrix and framework; chip is thinned the end exposing through hole; apply to connect and terminal by laying photoresist material on the two sides subtracting thin polymeric matrix and deposit copper pad in photoresist material pattern; stripping subsequently except photoresist material and lays solder mask between copper pad, with after-applied supercoat.
The another aspect of the present invention relates to a kind of panel comprising chip receptacle array, each panel by organic substrate framework institute around and restriction, described organic substrate framework comprises the copper vias post grid through described organic substrate framework, wherein said panel comprises at least one region with the first group of physical dimension socket holding a kind of type chip and has the 2nd region of the 2nd group of physical dimension socket holding the 2nd type chip, and wherein at least one through hole post comprises film capacitor.
Optionally, utilize described panel that at least one through hole post is stood upright on described film capacitor.
Optionally, at least one through hole post described comprises the top electrode of film capacitor.
Optionally, described panel comprises the closely adjacent region with two kinds of different socket types.
The frame combination that there is built-in electrical condenser around chip socket provide extensively for RF (radio frequency) technology of such as mobile telephone and automobile such as miniatureization of the higher degree of the technology such as Wi-Fi, bluetooth, the reliability that manufactures economy and enhancing.
Described supercoat can be selected from ENEPIG and organic coatings.
Term micron or ��m refer to 10-6m��
Accompanying drawing explanation
In order to understand the present invention better and illustrate embodiments of the present invention, purely by way of example with reference to accompanying drawing.
Referring now particularly to accompanying drawing, it must be emphasized that concrete diagram is only example and for the object that the preferred embodiment of the invention is schematically discussed, it is provided that illustrated reason be sure of that accompanying drawing is the most useful and the principle of easy to understand the present invention and the explanation of concept. With regard to this, it does not have attempt that the present invention is understood necessary the level of detail to exceed by the CONSTRUCTED SPECIFICATION of the present invention substantially and illustrate; How several enforcement modes enabling those skilled in the art know the present invention with reference to the description of the drawings can be implemented. In the accompanying drawings:
Fig. 1 is the schematic diagram of the front elevational sectional of the polymer-based carbon dielectric frame that limits socket, and wherein said framework has the through hole post of embedding, and wherein at least one through hole post comprises film capacitor.
Fig. 2 is the schematic cross sectional views of the polymer-based carbon dielectric frame that limits socket, wherein said framework has the through hole post of embedding, at least one embeds through hole post and comprises film capacitor, described socket comprises embedding device, described embedding device comprises additional electrical condenser at this, wherein has the through hole post of embedded capacitor device in the frame and is connected by comprising the characteristic layer of inducer with the embedded capacitor device in socket.
In Fig. 3-7, for the sake of clarity, the through hole illustrated and feature structure do not have the dielectric medium of surrounding.
Fig. 3 is the schematic diagram of the inducer in characteristic layer and the adjacent through-holes post that is uprightly on the electrical condenser that described inducer is connected in series in through hole post layer.
Fig. 4 is the schematic diagram of the inducer through hole in via layer being connected in series in the base portion of through hole post and electrical condenser.
Fig. 5 is the schematic diagram of one pair of inducer, and one in characteristic layer, another is in via layer, and being one another in series connects and the base portion of through hole post in the via layer of described through hole inducer and electrical condenser are connected in series.
Fig. 6 is the schematic diagram of the inducer in characteristic layer, and described inducer and electrical condenser are connected in parallel, described electrical condenser and described inducer by through hole post and on the 2nd in characteristic layer or the lead-in wire of described multilayered structure outside link together.
Fig. 7 is the schematic diagram of the inducer in characteristic layer, and itself and inductance via are connected in series and are connected in parallel with electrical condenser, described electrical condenser and described inductance via by characteristic layer on the 2nd or the lead-in wire of multilayered structure outside link together.
Fig. 8 is the schematic sectional view of the through hole post layer being connected between characteristic layer, and shown in it a through hole post has integrated inducer.
Fig. 9 illustrates that a kind of manufacture has the schema of the method for the substrate of embedded filters, and described wave filter is made up of electrical condenser and inducer.
Fig. 9 (i)-Fig. 9 (xxxi) is a series of schematic sectional view, illustrates that a kind of manufacture has the method for the substrate of the embedded filters being made up of electrical condenser and inducer, and every width figure is corresponding to corresponding step in Fig. 9.
Figure 10 is the schema illustrating the method that the wave filter of Fig. 8 forms terminal.
Figure 10 (xxxii)-Figure 10 (xL) is a series of schematic sectional view, illustrates that the substrate with embedded filters forms the method for terminal, and every width figure is corresponding to the corresponding steps of Figure 10.
Figure 11 is the schematic diagram of framework, and described framework has and embeds three layers of coil being made up of the through hole extended wherein and comprise the electrical condenser of embedding, illustrates the handiness of manufacturing technology and it is how for the manufacture of the method for embedded filters etc.
Figure 12 a is the schematic three dimensional views of basis LC low-pass filter.
Figure 12 b illustrates how the basic LC low-pass filter of Figure 12 a can represent for LC filter circuit.
Figure 12 c is the schematic sectional view of the basic LC low-pass filter of Figure 12 a.
Figure 12 d is the schematic sectional view of the basic LC low-pass filter of Figure 12 a, and wherein the size of electrical condenser is mated mutually with the through hole post above it, this defines electrical condenser volume effective capacitance amount.
Figure 12 e is the schematic sectional view of the basic LC low-pass filter of Figure 12 a, and wherein top electrode is the through hole post above it.
Figure 13 a is the schematic three dimensional views of basis LC Hi-pass filter.
Figure 13 b illustrates how the basic LC Hi-pass filter of Figure 13 a can represent for LC filter circuit device.
Figure 14 a is the schematic three dimensional views of basis LC bandpass filter.
Figure 14 b illustrates how the basic LC bandpass filter of Figure 14 a can represent for LC filter circuit device.
Figure 15 a is that the basic LC comprising electrical condenser and inducer is with the schematic three dimensional views leading to parallel filtering device.
Figure 15 b illustrates that the basic LC of Figure 15 a is with how logical parallel filtering device can represent for LC filter circuit device.
Figure 16 a is the schematic three dimensional views of low pass parallel connection-Chebyshev's wave filter;
Figure 16 b illustrates how low pass parallel connection-Chebyshev's wave filter of Figure 16 a can represent for LC wave filter.
Figure 17 is the schematic diagram with the polymkeric substance of chip socket or a part for matrix material grid, wherein also has the clear opening around socket.
Figure 18 is the schematic diagram for the manufacture of the panel with the embedded chip around clear opening, illustrates how part panel ITIS can have the socket for dissimilar chip.
Figure 19 is the polymkeric substance of Figure 17 or the schematic diagram of a part for composite material frame, accommodates chip in each socket, is remained in correct position by chip by polymkeric substance or matrix material such as moulding compound.
Figure 20 is the schematic sectional view of a part for framework, illustrates the embedding chip kept by polymkeric substance in each socket, also illustrates the clear opening on panel two sides and pad.
Figure 21 be comprise embed chip bare chip schematic sectional view.
Figure 22 comprises one to the schematic sectional view of the package of not similar bare chip in adjacent outlet.
Figure 23 is the fish-eye view of package as shown in figure 21.
Figure 24 illustrates the schema comprising the polymkeric substance of clear opening array or the manufacture method of composite material face.
The schematic diagram of the middle minor structure that Figure 24 (a)-Figure 24 (n) obtains after being each step of flow process Figure 24.
How Figure 25 can use to bore the schema that punching press socket is produced plating through hole by technology of filling out.
The schematic diagram of the middle minor structure that Figure 25 (a)-25 (e) obtains after being each step of flow process Figure 25.
Figure 26 is the orthographic plan of the framework with the wave filter being embedded in chip socket side.
Should be understood that, accompanying drawing is only schematic, not draws in proportion. Extremely thin layer may seem very thick. The width of feature structure can show as not proportional to its length, etc.
Specifically, it is noted that owing to expecting the cause of further miniatureization, it is possible to set out the equivalent structure with very different spatial disposition, and may thus seem different.
Embodiment
Hereinafter, it relates to for embedding the socket of chip. Socket comprises the metal through hole in dielectric substrate, particularly copper vias in the polymer matrix, described the present invention relates to the chip socket with piezoelectricity film, described dielectric substrate is such as the polyimide of glass fiber reinforcement, epoxy resin or BT resin (bismaleimides/triazine) or its blend.
Hereafter described socket also comprises the electrical condenser being structured in jack frame. This kind of electrical condenser is metal-insulator-metal type (M-I-M) electrical condenser normally, comprises lower metal electrode (can be gold, titanium or tantalum) and inorganic dielectric layer (can be such as Ta2O5��TiO2��BaxSr1-x��TiO3��BaTiO3Or Al2O3). Electrical condenser can comprise special top electrode (being often gold, titanium or tantalum), or can deposit through hole (normally copper vias) on the capacitor as top electrode.
Because parallel plate capacitor comprises folder dielectric materials in-between the electrodes, and this dielectric materials normally has the material of very high dielectric constant, and institute, distinguishes with the dielectric medium with electrical condenser hereinafter referred to as encapsulating dielectric medium for the dielectric materials of encapsulating.
Accompanying drawing is explanation property, is not intended to draw in proportion. Further, it is illustrated that a small amount of through hole, single electrical condenser and wave filter, but jack frame can comprise multiple electrical condenser and wave filter and a large amount of through holes. In fact, the large-scale array of usual co-manufactured jack frame.
When adopting brill to fill out technology manufacture through hole, through hole has almost circular cross section usually, because through hole manufactures by boring laser hole first in the dielectric. Because encasement medium is non-homogeneous and anisotropy and is made up of polymeric matrix and mineral filler and glass fiber reinforcement body, so the rounded section of through hole usually has coarse edge and may slightly be out of shape and deviate real circle. In addition, usual brill is filled out through hole and is tending towards occurring some to tilt, and becomes inverse conical butt, instead of cylindrical.
" brill is filled out " method of use, due to the difficulty of cross section control and shape, causes producing non-circular through hole.Due to the restriction of laser drill, minimum vias size also can only be about 50-60 micron. These difficulties describe in background section above, particularly relate to due to copper vias fill the depression that causes of electroplating process and/or domed shape, the through hole that causes due to laser drill process tilts shape and sidewall is coarse and causes high cost owing to using expensive laser drill machine to carry out groove milling in " wiring (routing) " pattern to produce groove at polymkeric substance/glass dielectric.
Except the restriction of laser drill mentioned above, bore another that fill out technology and it is limited in the through hole being difficult to produce different diameter within the same layer, this is because when also filler metal is to manufacture different size through hole simultaneously for the through-hole passage boring out different size simultaneously, the fill rate of through-hole passage is different. Therefore, fill out the pit of the feature of technology as brill or cross the typical problem filling (dome) and worsen further, because the through hole of different size can not be optimized by deposition technique simultaneously simultaneously. Thus, in actual applications, boring and fill out through hole and have almost circular cross section, although causing some distortion sometimes due to the nonuniformity of substrate, and all through holes have identical cross section.
In addition, it should be noted that in fact the through hole that laser drilling goes out in the blend of matrix material dielectric medium such as polyimide/glass or epoxy resin/glass or BT (bismaleimides/triazine)/glass or they and pottery and/or other filler particles is limited in about 60 �� 10-6M diameter, even so due to the feature of matrix material holed and the cause of involved ablation process, through hole also exist significant tilt shape and coarse sidewall shortcoming.
As being incorporated to US7,682,972, US7 of the people such as Hurwitz herein by reference, 669,320 and US7,635, described in 641, the photoresist material of Zhuhai Yue Ya company and the feature of pattern or panel plating and lamination are that the face interior diameter for feature structure does not have the actual upper limit.
A kind of more accurately substitute manufacturing technology be more flexibly included in the pattern of development in photoresist material plated copper via layer and both characteristic layer (pattern plating) than boring technology of filling out, or panel plating layers of copper then selective etch fall unnecessary material. These two kinds of methods all leave upright through hole post and upright feature structure. These upright devices can be encapsulated by layer piezoelectric dielectric thereon subsequently, normally covers dielectric prepreg in upright feature structure and through hole post and makes the resin solidification of prepreg subsequently.
Utilize the handiness of the technology from bottom to top being included in the photoresist material of patterning to electroplate subsequent layer pressure (or panel plating, selective etch and layer pressure), it is possible to cost manufactures shape of through holes and the size of wide region effectively. In addition, it is possible to manufacture the through hole of different shapes and size within the same layer. This is advantageous particularly when using copper pattern solution and coating method, first metal refining Seed Layer, then deposit photoresist material material the smooth straight non-inclined groove that develops wherein, subsequently can by carrying out pattern in the Seed Layer of exposure and be plated in these grooves to deposit copper thus fill. Compared with filling out through-hole approaches with brill, through hole column technology can form groove to obtain the copper linker of less pit and less dome in photoresist layer to be filled. After copper deposits, then stripping is except photoresist material, removes technology Seed Layer, and thereon with apply permanent polymkeric substance-glass composite material encapsulating material around.Consequent " via conductors " structure can use the technical process described in US7,682,972, US7,669,320 and US7,635,641 such as people such as Hurwitz.
Utilize photoresist material can be less than boring the through hole filling out technology manufacture by another feature of the electroplating technology from bottom to top of plating manufacture through hole. At present, the diameter of through hole filled out by minimum brill is about 60 microns. Utilize the electroplating technology of photoresist material can realize the resolving power being better than 50 microns, even little of 25 microns. Being connected to by IC on such substrate is challenge. A kind of flip-chip method of attachment is to provide the copper pad flat together with dielectric surface. This kind of method is documented in the US13/9142,652 of the present inventor.
Except via conductors and feature structure, it has been found that can also manufacturing passive device such as electrical condenser and wave filter in structure, this comprises through hole column technology, plating, PVD and wrapper technology is utilized to manufacture electrical condenser and wave filter.
With reference to Fig. 1, illustrating the polymer-based dielectric framework 1 being limited with socket 2 in the diagram, the front portion of its middle frame 1 is clipped. Framework 1 has the through hole post 5,6,7 of embedding, and at least one in through hole post 5 comprises film capacitor 6. The through hole post manufactured by plating needs not to be circular, it is possible to extend on direction in a face. A shown through hole post is the through hole post 7 extended, and it extends in X-Y plane and can be used as inducer.
Fig. 2 is the schematic sectional view of the polymer-based dielectric framework 1 of the restriction socket 2 shown in Fig. 1, but wherein socket 2 comprises one or more embedding device, building-out condenser 8,9 in this case, wherein have in framework 1 embedding metal-insulator-metal (MIM) electrical condenser 6 through hole post 5 by embedded capacitor device 8,9. embedded capacitor device 9 that the feature structure 11,12 of characteristic layer is connected in socket 2 can be manufactured on insulated substrate 14 such as silicon (Si), silicon-dioxide (SiO2), glass, AlN, on Alpha-alumina or c-face aluminum oxide (sapphire). In addition, the socket 2 of filling comprising inducer 13 deposits second feature layer. Fig. 2 does not comprise the additional conventional through hole post 4 shown in Fig. 1, or is not at least on the position shown by Fig. 1. However, it should be understood that the framework 1 of the present invention can comprise one or more conventional through hole post 4, the through hole post 5 stood on electrical condenser 6 and inductance via post 7.
MIM capacitor in the through hole 5 of framework 1 and the MIM capacitor 8,9 being embedded at socket all can comprise lower metal electrode and inorganic dielectric layer, and wherein such as, lower metal electrode can be gold, tantalum or titanium, and inorganic dielectric layer can be Ta2O5��TiO2��BaxSr1-xTiO3��BaTiO3Or ��-Al2O3��
Electrical condenser can comprise special top electrode, normally gold, tantalum or titanium, or the through hole 5 of normally copper can be deposited on dielectric medium 6 and itself is used as top electrode. Similarly, the embedded capacitor device 8,9 embedding framework can comprise gold, tantalum or Ti electrode and inorganic dielectric, and it can be Ta2O5��TiO2��BaxSr1-xTiO3��BaTiO3Or Al2O3. This embedded capacitor device 8,9 can be manufactured on inorganic substrate such as c-face aluminum oxide (sapphire).
The combination of electrical condenser and inducer can be used as wave filter, in order to protect IC from the impact of wave current and noise. For RF communication such as WIFI, bluetooth etc., wave filter has special importance. Wave filter can be used for a part for circuit and other device isolation, to prevent interference.
With reference to Fig. 3, the schematic diagram of adjacent through-holes post 42 illustrating the inducer 40 in characteristic layer and being connected in series with inducer 40 in the through hole post layer stood on electrical condenser 44.For the sake of clarity, it does not have the encapsulating dielectric materials of surrounding is shown. Metal construction and electrical condenser are only shown. The structure of Fig. 3 can be made of copper, and wherein electrical condenser 44 comprises dielectric materials such as Ta2O5��TiO2��BaxSr1-xTiO3��BaTiO3Or Al2O3, and there is the electrode of tantalum or other precious metal usually. Usually, through hole post 42 can be encapsulated in polymer dielectric, and this polymer dielectric can comprise filler and weaving fiber prepreg can be utilized to manufacture. Can first deposit the characteristic layer comprising inducer 40, simultaneously lamination electrical condenser 44 and through hole post 42 thereon. Can at feature structure 40 and through hole post 42 overlaminate polymer-based dielectric material, this dielectric substance can be polymeric film or weaving fiber prepreg. As selection, through hole post 42 and electrical condenser 44 also laminated polymeric thing dielectric medium can be manufactured, then the inducer 40 that can be deposited in characteristic layer thereon, or thereunder deposit inducer 40 as shown in the figure, do not carry out layer pressure to make it to become surface traces, the inducer 13 of such as Fig. 2, or can subsequent layer pressure, also can together with other via layer layer pressure, not shown. Therefore, inducer 40 can be included in the upper layer in the characteristic layer as framework (1, a Fig. 1) part or above or below framework (1, Fig. 1), the parts 13 of such as Fig. 2. In addition, with continued reference to Fig. 2, if cavity filling 2 after embedding device 8 and 9 outside framework 1 and in the polymer dielectric 10 of such as moulding compound or prepreg, then inducer 40 (13) can partly be deposited on the cavity of filling.
It is appreciated that characteristic layer is very thin, usual thickness is about 10 microns. But, via layer can far be thicker than this. Fig. 4 is the schematic diagram extending in via layer the inducer through hole 56 being connected in series in the base portion of through hole post 52 and inducer 54. By being deposited in characteristic layer or trace 58 on framework surface is connected between electrical condenser 54 with inducer through hole 56, trace 58 is on the bottom in the diagram. The thickness of inducer through hole 56 can be about 30 microns and has the characteristic that the characteristic layer inducer 40 from Fig. 3 is different. Usually, inducer through hole 40 is the high Q inducer that inductance range is about 0.1nH��about 10nH. As shown in the figure, through hole post inducer 56 can be a coil quite closely. However, it should be understood that this coil can be formed in framework 1 and the complete socket 2 around framework 1, or can be embedded in the framework side on socket side.
With reference to Fig. 5, it should be understood that wave filter can manufacture and comprise one pair of inducer, i.e. the first inducer 60 in characteristic layer and the 2nd inducer 66 in through hole post layer. Referring again to Fig. 1 and 2, first inducer 60 can be surface mounted on framework 1, or be surface mounted in as the inducer 13 in Fig. 2 and be filled with on the fill frame above the cavity 2 of polymkeric substance 10, or can in the layer comprising feature structure 11 and 12 or in fact deposition below the filling chamber in succeeding layer. Wave filter shown in Fig. 5 is included in the 2nd inducer 66 in via layer, and described via layer also comprises conventional through hole post. 2nd inducer 66 can be manufactured in the framework 1 surrounding cavity 2 completely. Inducer 60,66 can be one another in series and the base portion of through hole post 62 in the via layer of through hole inducer 66 is connected with electrical condenser 64.
It is appreciated that need to be connected in parallel device for some filtering purposes.
Such as, Fig. 6 is the schematic diagram of the inducer 70 in characteristic layer, and inducer 70 is connected in parallel in the base portion of through hole post 71 and electrical condenser 74. Electrical condenser 74 and inducer 70 by through hole post 71,72 and on the 2nd trace 78 in characteristic layer or in multilayered structure outside link together. Referring again to Fig. 2, through hole post 71,72 will be positioned in framework 1. Inducer 70 and joint 78 can be deposited in the feature of framework, if framework is multilayer, or can by electroplating deposition in the photoresist material of fill frame 1 outside of Fig. 2, it is possible to spread over the top (or lower section) of the filler 10 of cavity 2.
Fig. 7 (is deposited on framework 1 at (framework 1) characteristic layer or undersurface layer and can be deposited on the cavity 2 of filling, such as, on the inducer 13 of Fig. 2) in the schematic diagram of inducer 88, all the other inductance vias 86 are connected, such as the through hole 7 of Fig. 1 and 2, and in parallel with electrical condenser 84. Electrical condenser 84 and inducer 86 are linked together by trace 88, and trace 88 is on the 2nd (such as figure, top) of framework is in characteristic layer or outside framework 1 (can cross over cavity 2).
With reference to Fig. 8, the sectional view of substrate 21 (framework 1 of such as Fig. 1) is shown, comprises the one layer of parallel plate capacitor 20 being made up of the dielectric materials layer 22 being clipped between copper characteristic layer 24 and copper post 26. Optionally, dielectric layer 22 is deposited on copper characteristic layer 24, then grows copper post 26 from dielectric layer 22. Dielectric materials can be such as Ta2O5��TiO2��BaxSr1-xTiO3��BaTiO3Or Al2O3, it is possible to by physical vaporous deposition as sputtering method or chemical Vapor deposition process deposit.
In order to obtain high-quality electrical condenser, dielectric materials can comprise the Ta by physical vaporous deposition deposition2O5��TiO2��BaxSr1-xTiO3��BaTiO3Or Al2O3, it is also possible to comprising in advance or an aluminium layer of subsequent deposition, this aluminium layer can by dielectric ceramics side sputtering sedimentation. After optional al deposition, it is possible to by structure in the presence of oxygen in process furnace or baking oven or be exposed to Far-infrared spoke and hit and heat. Like this, aluminium becomes aluminum oxide (Al with regard to in-situ transesterification2O3). Because Al2O3Density lower than the density of aluminium, so it covers on ceramic layer and defect after sealed ceramic layer, so that it is guaranteed that high-k and Leakage prevention.
Copper post 26,28,30,32 is encapsulated in encapsulating dielectric materials 34. When copper post 26,28,30,32 by after photoresist material, electroplate (or panel plating and etching) and when subsequent layer is pressed into through hole post, encapsulating dielectric materials 34 can be applied as glass fiber reinforced polymer resin prepreg material, is laminated on copper post 26,28,30,32.
Utilizing and be inverted pattern or panel plating, in multiple copper post 28,32 can be expansion inductance via post, the inductance via post 7 of such as Fig. 1 and 2.
Copper characteristic layer 24 can have about 15 micron thickness, and tolerance is about+-5 micron. Each through hole post layer has about 40 microns wide usually, but scope can be about 20 microns to 80 microns. The outer characteristic layer 24,38 that can be used as terminal pad also has about 15 microns wide usually, but scope can be about 10 microns to 25 microns.
It is well known that the capacitance of electrical condenser is multiplied by capacitor surface long-pending (i.e. the area of through hole post 26) by the specific inductivity of dielectric layer to determine divided by the thickness of dielectric layer 22.
For the simple single-layer capacitor 20 of Fig. 8, it is possible to optimize thickness and the deposition method thereof of dielectric materials 22. Capacitance is the specific inductivity of dielectric materials 22 and the attribute of metal electrode area, is the sectional area of copper post 26 at this metal electrode area.
In a typical implementation, noble metal electrode (be generally tantalum system, but be optionally made up of gold or platinum) is applied on the both sides of dielectric layer. Therefore, electrical condenser is introduced in the via layer at place of through hole base for post portion. Keeping the thickness of dielectric layer and characteristic constant, now through hole post limits top electrode, and it limits capacitance and can be used for trimmer value.
Hereinafter will illustrate in detail, even if use tantalum electrode, the through hole post depositing careful adjust size can realize the electrode of electrical condenser and the plasma etching of dielectric layer, only retains the selective etch such as hydrogen fluoride or oxygen candle by removing tantalum and tantalum oxide but do not damage copper and carves the electrical condenser obtained. In addition, because through hole post can be formed by plating, so through hole post needs not to be cylindrical, it is possible to have rectangle or other cross section present situation.
With reference to Fig. 8 and Fig. 9 (i)��9 (xxxi), particularly illustrate a kind of method being manufactured on the film capacitor being embedded in polymer dielectric below through hole post. It is appreciated that graphic technique may be used for the through hole post array that codeposition comprises film capacitor in framework. Conventional substantially cylindrical through hole post (the through hole post 4 of such as Fig. 1) and inductance via post (the inductance via post 7 of such as Fig. 1) can be deposited in same via layer. But, in order to keep accompanying drawing succinct, other through hole post that may relate in the following description is not shown.
Electrical condenser 248 shown in Fig. 9 (xx) has the electrode special of differing materials, and normally precious metal is such as gold, gold or tantalum. Usually tantalum is used, because it is more cheap than gold and gold. But, in alternative constructions, top electrode can be the through hole post 232 electroplated thereon.
First, obtain carrier 210-step 9 (i). Carrier 210 normally sacrifices copper base. In some embodiments, the quick release film that it can be copper carrier and be attached on copper.
Deposited barrier layer 212-step 9 (ii) on copper carrier 210. This barrier metal layer 212 can be made up of nickel, gold, tin, lead, palladium, silver and their combination. In some embodiments, the thickness range of barrier metal layer is 1 micron to 10 microns. Usually, blocking layer 212 comprises nickel. Thin nickel blocking layer 212 deposits by physical gas-phase deposition or by chemical deposition process, usually sputters or is electroplated onto on copper carrier 210. In order to accelerate treating processes, blocking layer 212 can be plated. In order to guarantee planarity and level and smooth surface, planarization-step 9 (iii) (Fig. 9 (iii) is identical with Fig. 9 (ii), such as, undertaken by cmp (CMP)) can be carried out subsequently.
Then, it is possible to thin layer copper 214 is deposited on blocking layer 212-step 9 (iv). The thickness of layers of copper 214 is generally several microns, and by sputtering or can manufacture by electroplating.
Then, the first electrode 216-step 9 (v) is deposited. Such as, the first electrode 216 can be manufactured by sputtering by tantalum.
Then, dielectric layer 218-step 9 (vi). For high performance capacitors, dielectric layer 218 must keep thin as far as possible, does not make electric charge leak the risk that fault occurs simultaneously. Multiple candidate material is had to use. These materials comprise Ta2O5��BaO4SrTi and TiO2, such as, deposit by sputtering. Usually, the thickness range of dielectric layer 218 is 0.1 to 0.3 micron.
Can deposit now the 2nd electrode 220-step 9 (vii). Such as, the 2nd electrode 220 can be manufactured by sputtering by tantalum.
In the method for a change, do not apply the 2nd noble metal electrode 220.But, Direct precipitation copper vias on the dielectric, the top electrode of its coverage area limited capacitor, the thus useful area of limited capacitor and capacitance.
But, this kind of method is difficult to manufacture the Ta not existing and electric charge may being caused to leak this defect2O5��BaO4SrTi or TiO2Thin dielectric layer. In order to overcome this problem, in some embodiments, at deposition Ta2O5��TiO2��BaxSr1-xTiO3��BaTiO3An aluminium layer (not shown) (optional step 9 (v) b or optional step 9 (vi) b-is shown in Fig. 9) is deposited before or after layer, and by heating in oxygen atmosphere, make aluminium layer be oxidized to high dielectric ceramic aluminum oxide ((Al2O3). The density of alumina ratio aluminium is little, and expands and enter in adjacent space. By this way, it is possible to customer service defect and guarantee the thin dielectric medium spaced electrodes of continuous print.
In main procedure, the 2nd electrode 220 deposits another layers of copper 222-step 9 (viii). This another layers of copper 222 can deposit with such as sputtering or electric plating method. This another layers of copper 222 can by panel clad deposit to, in the photoresist material of patterning, photoresist material pattern can manufacture to provide such as pad, conductor and inducer by printing and etch. Photoresist layer 208 can be applied to the lower section of copper carrier 210, and the 2nd photoresist layer 224 is applied to above another layers of copper 222 and develops to pattern-step 9 (ix).
Etching away regions-the step 9 (x) that will not be patterned photoresist material 224 in another layers of copper 222 and protect. Wet corrosion can be used to carve. Such as, a kind of method etched away is protected to comprise the solution of ammonium hydroxide that sacrificial substrate is exposed to intensification by another layers of copper 222 is not patterned photoresist material 224. Alternatively, it is possible to use cupric chloride or the etching of wet type iron trichloride.
The electrode layer 216,220 exposed and dielectric layer 218 can utilize plasma etch process to remove-step 9 (xi) by dry etching. Such as, hydrogen fluoride and oxygen plasma etching may be used for etching TiO2Or Ta2O5, hydrogen fluoride and argon plasma etch may be used for etching BaO4SrTi(BST)��CF4:O2Typical concentration be between 50:50��95:5 than scope, wherein 95 is CF4Concentration. CF4: the typical concentration of Ar is than being any ratio between 50:50 to 5:95, and wherein 95 is the concentration of argon.
In the method for a change, as mentioned above, it is necessary, do not deposit top electrode 220. But direct manufactured copper through hole on the dielectric material. No matter being the cross-sectional dimension and the shape that utilize the photoresist material of template or laser patterning can both accurately control through hole, this through hole is used as top electrode and the capacitance of limited capacitor, this is because capacitance is directly proportional to the useful area of through hole electrode.
In main procedure, then strip pattern photoresist material 224-step 9 (xii), usually as the 2nd photoresist layer 208. But, due to the 2nd photoresist layer 208 of short duration by similar photoresist layer 228 substitute-therefore it can alternatively retain.
In the layers of copper 214 of electrical condenser and exposure and around deposition copper seed layer 226-step 9 (xiii). In order to contribute to adhering to, it is possible to first deposit the first titanium Seed Layer.
Referring now to Fig. 9 (xiv) of different scale; apply another photoresist layer 228 to protect copper base (assuming that the layer 208 shown in Fig. 9 (ix) is removed), Seed Layer 226 deposits also patterning one photoresist material thick-layer 230 and deposits (step 9 (xiv)). In the pattern that photoresist material 230 produces, plating forms copper-connection 232-step 9 (xv).
Then, stripping, except photoresist layer 228 (208), 230-step 9 (xvii), thus exposes electrical condenser 248, and it is by Seed Layer 226 short circuit, and copper vias post 232 interconnects.
Now, etch away Seed Layer 226-step 9 (xvii), carry out fast-etching to reduce the damage of layers of copper 214 and via layer 232 as far as possible, but guarantee that layers of copper 214 and copper vias 232 are kept apart by electrical condenser 248 each other.
The method can have many changes. Such as, with reference to Fig. 9 (xviii), before copper base and through hole overlaminate polymer-based carbon dielectric materials 234, this structure can carry out plasma etching, plasma-etching method used is copper tolerance etching, but tantalum and titanium oxide are easily etched, the mixing-step 9 (xviii) of such as hydrogen fluoride and oxygen. The size of electrical condenser 348 is decreased to the size of through hole post 232 by this. Because through hole post 232 is made by plating in the photoresist, this provide the possibility of a kind of high precision manufacture almost any size and dimension, and shape can be square or rectangle, and it is not only circle, so that tap density can be higher. Removing excessive capacitor material makes the high-bulk-density between device become possibility.
Then, by copper base and through hole overlaminate one layer of polymeric base dielectric materials 234, electrical condenser 348 or electrical condenser 248 being embedded in polymer-based carbon dielectric materials 234-step 9 (xix). This polymer-based carbon dielectric materials 234 is polyimide, epoxy resin or BT (bismaleimides/triazine) or their blend normally, and can use glass fiber reinforcement. In some embodiments, it is possible to use one by the prepreg of polymer resin impregnated weaving fiber pad. Polymeric matrix can comprise inorganic particles packing, usually has the median size of 0.5 micron to 30 microns, and this polymkeric substance generally includes the particle of 15wt%��30wt%.
Although sometimes referred to as being dielectric medium, but polymer-based carbon dielectric materials 234 has the specific inductivity of the remarkable dielectric layer 218 lower than electrical condenser 248, this is more peculiar material such as Ta usually2O5Or BaO4SrTi or TiO2Deng characteristic.
Then, the polymer-based carbon dielectric materials 234 of solidification is subtracted thin and planarization-step 9 (xx), such as, by cmp (CMP), thus expose the end of copper vias 232. Then, the end of polymer-based dielectric material 234 and copper vias 232 deposits another copper seed layer 236-step 9 (xxi). Seed Layer 236 applies photoresist layer 238 disease by photoresist layer 238 patterning-step 9 (xxii). Then in pattern, electroplate another layers of copper 240-step 9 (xxiii).
Can shell now except photoresist layer 238-step 9 (xxiv).
In this stage, lower layers of copper 214 is connected to upper layers of copper 240 via the electrical condenser 248 being embedded in copper-connection 232 by copper-connection 232.
Can deposit and patterning another photoresist layer 242-step 9 (xxv), and can in pattern electro-coppering through hole 244-step 9 (xxvi).
Photoresist layer 242 can be stripped, and leaves upright copper vias 244-step 9 (xxvii), then etches away copper seed layer 236-step 9 (xxviii). Copper seed layer by dry plasma etch or can utilize the short period of time etching of such as cupric chloride or ammonium chloride solution to remove.
With reference to Fig. 9 (xxix), dielectric materials 234 can be laminated on upright through hole 244.
Copper carrier 210 now can be etched, and general use cupric chloride or ammonium chloride solution carry out-step 9 (xxx), utilize blocking layer 212 (normally nickel) as etching stopping layer.
Then, it is possible to use suitable etching technique is such as plasma etching or utilizes special chemical etching reagent to remove blocking layer 212-step 9 (xxxi).Such as, copper is not removed in order to etch away nickel, it is possible to use the mixture of nitric acid and hydrogen peroxide. Other substitute of the dissolving nickel that can use comprises the iron(ic) chloride (III) of hydrochloric acid+hydrogen peroxide, hot concentrated sulfuric acid and hcl acidifying.
Then, polymer layer 246 is subtracted thin and planarization-step 9 (xxxii), to expose the end of copper vias 244. The cmp (CMP) of grinding, polishing or combination can be used.
Up to the present, show and can how the high performance capacitors 248 of advanced person has been embedded in composite structure 250, this composite structure 250 comprises the copper vias layer comprising copper vias 232 standing upright on film capacitor 248, but, as shown in Figure 1, it is also possible to comprise inductance via 7 and conventional through hole post 4.
If framework 1 comprises single via layer, then after step 9 (xx), stamp out cavity 2 (Fig. 1) in the frame, being positioned at by device (8 and 9 in such as Fig. 2) in framework 1 and utilize polymer-based carbon dielectric materials 10 to be embedded, polymer-based carbon dielectric materials 10 can be fibre-reinforced polymer packing or apply as woven fibrous preform.
In this case, characteristic layer 240 and upper via layer 244 can being deposited on the framework of filling, the framework of filling utilizes CMP grinding smooth and is processed into substrate for long-pending layer further.
In addition, framework can comprise characteristic layer 240, perhaps can comprise the 2nd via layer 244, even comprises other layer being embedded in polymer-based carbon dielectric substrate 234,246. Then, it is possible to punching press or cut out cavity in multistory frame.
Owing to condenser coating and dielectric interior shape determine by the photoresist material of patterning, so should be realized that electrical condenser can make almost any shape. Usually, electrical condenser is square or rectangle, but can also be circular, or in fact can be almost other shape any. Electrical condenser can have one layer, two layers, three layers or more layers. Dielectric thickness can carefully control, and therefore can be customized by the electrical condenser of the method manufacture so that it is has the substantially any capacitance on a large scale, and can accurately control capacitance value, be optimized for specific run frequency.
It is also important to note that, through hole 244 is not limited to simple cylindrical hole post, manufactures because it does not fill out technology by brill. Manufacturing by utilizing to electroplate in the pattern of photoresist material 242, through hole 244 can also have any shape and size substantially. Because through hole 244 can be the extensive wire in via layer, through hole 244 can be inducer, and the high Q inducer of can be inductance value be about 0.1nH��about 10nH.
It is appreciated that the combination of electrical condenser 248 and inducer 244 can provide RF wave filter.
With reference to step 10 (xxxiii) to step 10 (xL) and correspondence figure (xxxiii) to 10 (xL), a kind of method for the manufacture of port of wave filter is below described.
It is appreciated that such port can be deposited on framework 1, but normally deposit in structure, the cavity filling 2 that this structure comprises framework 1 and framework 1 surrounds, and the assembly 8,9 embedded and extra play in both sides usually.
With reference to step 10 (xxxiii), sputtered titanium Seed Layer 252 in the exposed end of matrix 246 and copper (inducer) through hole 244 now. With reference to step 10 (xxxiv), titanium layer 252 sputters layers of copper 254.
With reference to step 10 (xxxv), the two sides of composite structure 250 applies photoresist layer 256,258 and patterning.With reference to step 10 (xxxvi), in the photoresist layer 256,258 of patterning, electro-coppering 260,262 creates port.
With reference to step 10 (xxxvii), stripping is except photoresist layer 256,258 now, leaves upright copper port 260,262. With reference to step 10 (xxxviii), etch away titanium layer 252 and layers of copper 254. In this process, (copper pad 260,262 will be slightly impaired).
Solder mask 264-step 10 (xxxix) can be filled in the cavity thus formed, and protect copper-step 10 (xL) or other suitable terminal technology with ENEPIG266.
As described above, it may also be useful to preferred through hole column technology, in the photoresist and the electroplating ventilating hole of subsequent layer pressure can have shape and size on a large scale to deposition. In addition, framework can comprise the via layer of separated by pad 2 or more.
With reference to Figure 11, this kind of handiness makes it possible to embed copper coil 1200, generally includes through hole post, is embedded in the dielectric frame 1202 of surrounding cavity 1204. Only exemplarily, shown coil 1200 has three through hole post layers 1206,1207,1208 extended, and through hole post can be deposited on characteristic layer. Layer 1206,1207,1208 is linked together by vertical devices 1209,1210. Vertical devices 1209,1210 can be through hole post or characteristic layer or the through hole post on characteristic layer.
Electrical condenser 1250 can be fabricated in the lower section of inducer or its in, usually in the base portion of through hole post 1209. The manufacture method of electrical condenser is described above with reference to Fig. 8 and 9. In practice, copper vias post coil 1200 generally includes the slightness hole post linked together by characteristic layer or the elongated features layer linked together by through hole post. Usually, it is necessary to build through hole post layer alternately and characteristic layer and coil layer by layer.
By combined capacitor and inducer, it is provided that wave filter. The example of wave filter is shown in Figure 12-16. Should be understood that, these wave filters any or analogue can be manufactured in the framework of chip socket and provide, with embedded chip combination, the flush type circuit comprising chip and wave filter. Substrate can comprise the two or more socket for two or more chip, and described chip is such as treater chip and memory chip. In addition, some layer can be fabricated in and embed on chip, the electrical condenser that such as can be deposited in characteristic layer on chip or inducer.
With reference to Figure 12 a, this 3-D view illustrates the structure of Figure 10 (xL), Figure 12 b is equivalent-circuit diagram, Figure 12 c is the floor map of the structure of Figure 10 (xL), it is appreciated that consequent structural nature is a kind of basic LC low-pass filter 300 with four port P1, P2, P3, P4, electrical condenser C and inducer L.
With reference to Figure 12 d, in the modification manufacturing technology using the plasma etch step shown in Fig. 9 (xviii), the coverage area of through hole V2 defines capacitance and the size of electrical condenser C2, and wherein unnecessary material is etched away by plasma etching mode. Therefore, Figure 12 d is the schematic cross-section of the basic LC low-pass filter being equal to Figure 12 a, and wherein through hole post V2 defines the electrode of electrical condenser and the size of dielectric layer, as in the structure of Fig. 3-7.
Figure 12 e is the schematic cross-section of the basic LC low-pass filter of another kind of Figure 12 a, and wherein the top electrode of electrical condenser C3 is through hole post V3, instead of the top electrode of first depositing noble metal. In the manufacture of this kind of structure, it has to be noted that remove all copper seed layers from dielectric medium.
It is appreciated that the technology described in detail in Fig. 9 and Fig. 9 (i) to Fig. 9 (xxxii) and Figure 10 (xxxiii) to Figure 10 (xL) can be used for creating the filter circuit in wide region with different qualities.As shown in Figure 2, these circuit many can comprise the electrical condenser 8,9 being embedded in cavity 2 or protect the active part being embedded in cavity 2.
Such as, with reference to Figure 13 a and 13b, it is possible to manufacture a kind of basis LC Hi-pass filter. With reference to Figure 14 a and 14b, it is possible to manufacture a kind of basis LC serial band pass filter, as with reference to Figure 15 a and 15b, it is possible to manufacture a kind of basis LC bandpass filter in parallel. With reference to Figure 16 a and 16b, utilize suitable change programme, through the correction of necessity, it is possible to manufacture low pass parallel connection-Chebyshev's wave filter.
Although single strainer is illustrated, it is to be understood that, practice is the large-scale array of co-manufactured this kind of wave filter on big plate, then can be individualized by it. Other device cooperatively can manufacture with wave filter. Wave filter 260 can be surface mounted on substrate or be embedded in substrate by depositing other characteristic layer and via layer around it.
As mentioned below, in some embodiments, aforesaid wave filter can embed in a substrate and perforate forms socket for holding chip on substrate, such as treater chip or memory chip, manufacturing full-embedded type RF circuit to realize, it can comprise such as treater and wave filter.
Usually, obvious although embedding the advantage improving integrated level, it should be understood that embedded device exists intrinsic shortcoming, as long as namely there is mistake in any part, then this device and embed structure wherein and all must be dropped. Sometimes, the path reason of diagnosis problem may be difficult, because device wherein can not be tested separated and separately. But, owing to the demand of area expensive on substrate surface and the popular tendency of miniaturization, the passive device such as embedded filters and active part such as treater and storer are had significant advantage.
A feature of the present invention is that the passive devices such as wave filter can manufacture the stand-alone product for surface mounting. But, once be optimized, this treating processes can be integrated in the manufacturing processed of substrate in order to embed such device.
It is appreciated that the capacitance of electrical condenser depends on battery lead plate area, dielectric thickness and specific inductivity thereof. Usually, the electrical condenser of RF wave filter has the capacitance between about 5pF to about 1pF. Use the techniques described herein, it is possible to capacitance controlled in close limit, such as 9��12pF, even 10��11pF.
The inducer of the present invention can have the inductance range of nanohenry profit. I.e. 0.2nH��300nH, but normally 1nH��about 10nH.
The inductance value of these inducers can control in close limit, according to appointment 4nH��about 8nH, or even when the scope needed is less than 1 nanohenry profit, i.e. about 5nH��about 6nH.
As mentioned above, it is necessary, the substrate with embedded passive device can be manufactured. Utilizing the technology hereinafter more fully described, active part such as chip can be surface mounted on such substrate or be embedded in the socket of this substrate. Embodiment of the present invention propose a kind of method manufacturing embedded passive device in the framework of socket, can embed chip subsequently, such as memory chip or treater chip in socket.
Such framework can be arranged in the big frame surrounding receptacle array. Each socket in array can be identical, for holding identical chip. As an alternative, array can be included in the different sockets in some or all frameworks of socket with different embedded passive devices.Such as, array can comprise the socket for Storage and Processing chip alternately. Socket can also hold and comprise passive device such as the chip of electrical condenser or wave filter. Passive and active part can be embedded in socket. Such as, many jack frame can comprise one or more socket for passive device and one or more for active part such as the socket of memory chip or treater chip. For the ease of manufacturing, such chip can deposit in socket by robot, is then kept in position by chip by toppling over polymer dielectric around it, and polymer dielectric can comprise fiber reinforced material. In some cases, chip can be kept in position by laminated polymeric thing film thereon.
It is all with high costs for connecting all methods of chip and plug-in part. Lead-in wire bonding and flip chip technology (fct) are all high cost and disconnect can causing trouble. Embedding chip instead of surface mounting can reduce manufacturing cost and improve reliability and good article rate.
Hereinafter describe for the manufacture of socket and the technology that chip is embedded this kind of socket.
With reference to Figure 17, illustrating a part for the array 1010 of the chip socket 1012 limited by framework, this framework comprises polymeric matrix 1016 and the array of the metal through hole 1014 through polymeric matrix framework 1016.
Array 1010 can be a part for the arraying bread board comprising chip socket 1012, and each socket is surrounded by polymeric matrix framework 1018 and limits, and framework 1018 comprises the grid of the copper vias 1014 of the polymkeric substance 1016 through polymeric matrix framework 1018. Polymeric matrix 1016 generally includes glass fibre reinforcement, and the most typically manufactures by resin impregnation weaving fiber prepreg.
Therefore, each chip socket 1012 is surrounded by the framework 1018 of polymeric matrix 1016, and the multiple copper vias through framework 1018 are arranged in around socket 1012'.
Framework 1018 can be made up of polymkeric substance, as polymer sheet application, can also be maybe the polymkeric substance of glass fiber reinforcement, apply as prepreg. More details finding hereinafter with reference to Figure 22 and 23, can wherein discuss manufacture method.
With reference to Figure 18, the more sub-panel 1020 in applicant Zhuhai is divided into 2 �� 2 arrays of square 1021,1022,1023,1024 usually, and described square is separated from one another by main frame, and main frame comprises horizontal bar 1025, vertical bar 1026 and housing 1027. These squares comprise array-Figure 17 of chip socket 1012. Assume to adopt 5mmx5mm chip socket and Zhuhai more sub-21 " x25 " panel, this kind of manufacturing technology achieves and encapsulates 10000 chips on each panel. In contrast, it should be noted that, maximum 12 the industry uses at present " wafer manufactures Chip Packaging only can realize primary treatment 2500 chips, it may also be useful to the economical efficiency of scale of the more sub-technology in Zhuhai on big panel will be marvellous.
But, the panel being applicable to this technology can carry out some changes in size. Usually, panel is about 12 " x12 " and 24 " x30 " between. Some standard sizes used at present are 20 " x16 ", 20.3 " x16.5 " and 24.7 " x20.5 ".
It not that all squares of panel 1020 all need to have the identical chip socket 1012 of size. Such as, in the schematic diagram of Figure 18, the chip socket 1028 of upper right square 1022 is greater than the chip socket 1029 of other square 1021,1023,1024.In addition, not only one or more square 1022 can be used for holding the different size socket of different size chip, and any subarray of any size can be used to manufacture any specific die package, although so turnout is big, but a small amount of die package of short run can be manufactured, it is embodied as the different particular customer die package that processing treatment is different simultaneously, or manufactures different encapsulation for different clients. Therefore, panel 1020 can comprise at least one region 1022 of the first group of size socket 1028 having for holding first kind chip and have the 2nd region 1021 for the 2nd group of size socket 1029 holding the 2nd type chip.
As described in above with reference to Figure 17, each chip socket 1012 (1028,1029, Figure 18) surrounded by polymer frame 1018 and be in each square (1021,1022,1023,1024-Figure 18) in, the array of socket 1028 (1029) is located.
With reference to Figure 19, chip 1035 can be positioned in each socket 1012, space around chip 1035 can be filled with polymkeric substance 1036 or polymer matrix composite, this polymkeric substance can be or can not be with for the manufacture of framework 1016 polymer phase with polymkeric substance. Such as, it is possible to be moulding compound. In some embodiments, the matrix of filled polymers 1036 and the matrix of framework 1016 can use similar polymkeric substance, but have different fortifying fibres. Such as, framework can comprise fortifying fibre, and the polymkeric substance 1036 being used as socket filler can not contain fiber.
Typical die-size can be about 1.5mmx1.5mm, up to about 31mmx31mm, jack sizes slightly big to hold predetermined tube core and there is gap. The thickness of plug-in part framework at least must equal the degree of depth of tube core, it is preferable that 10 microns to 100 microns. Usually, the degree of depth of framework is die thickness+20 microns.
Owing to embedding chip 1035 in socket 1012, so each independent chip is all surrounded by framework 1038, framework 1038 has through the through hole 1014 wherein and around each chip edge arranged.
The technology utilizing Zhuhai more sub-, no matter it is pattern plating or panel plating selective etch again, through hole 1014 can manufacture through hole post and subsequent layer pressure dielectric materials, and this dielectric materials uses polymeric film or uses the prepreg of the weaving glass fiber bundle comprising in polymeric matrix in order to increase stability. In one embodiment, dielectric materials is Hitachi705G. In another embodiment, it may also be useful to MGC832NXANSFLCA. In the 3rd embodiment, it is possible to use SumitomoGT-K. In another embodiment, it may also be useful to SumitomoLAZ-4785 series membranes. In another embodiment, it may also be useful to SumitomoLAZ-6785 series. Alternative material comprises such as TaiyoHBI and Zaristo-125.
Alternatively, through hole can use to be commonly referred to and bore the method filling out technology and manufacture. First, manufacture polymkeric substance or fibre-reinforced polymeric matrix, then after hardening to its boring, by machine drilling or pass through laser drill. Then, boring can be filled copper by plating.
But, utilize through hole column technology instead of brill to fill out technology manufacture through hole and there is many advantages. In through hole column technology, because all through holes can manufacture simultaneously, thus through hole column technology to fill out technology than the brill of separately boring faster. In addition, the through hole bored out is substantially cylindrical, and through hole post can have any shape. In practice, all brill filling vias have identical diameter (in tolerance zone), and through hole post can have different shapes and size.And, in order to strengthen rigidity, it is preferable that polymeric matrix is fibre-reinforced, usually use fiberglass braided Shu Zengqiang. When the fiber in polymkeric substance prepreg is applied on upright through hole post and is cured, the characteristic of through hole post is to have smooth and vertical side. But, brill is filled out through hole and is usually had some taperings when drilling through matrix material; Through hole has coarse surface usually, thus causes the spuious inductance causing noise.
Usually, the width of through hole 1014 is in the scope of 40 microns to 500 microns. If cylindrical, such as bore fill out required by technology and as in through hole column technology common, each through hole can have the diameter of 25 microns to 500 microns.
With further reference to Figure 19, after there is the polymeric matrix framework 1016 embedding through hole, it is possible to manufacture socket 1012 by CNC or punching press. Alternately, it may also be useful to panel plating or pattern plating, it is possible to deposited sacrificial copper billet. If copper vias post 1014 is optionally shielded, such as, make with photoresist, then this sacrifice copper billet can be etched to form socket 1012.
The polymer frame 1038 in the framework 1038 around each socket 1012 with the receptacle array of through hole 1014 may be used for creating single or multiple Chip Packaging, comprises multi-chip encapsulation and the encapsulation of lamination multilayer chiop, such as package on package " PoP " array.
Once chip 1035 is positioned in socket 1012, then polymkeric substance 1036 such as moulding compound, dry film or prepreg can be used to be fixed in position.
With reference to Figure 20, it is possible to manufactured copper wiring layer 1042,1043 on the one or both sides of framework 1040 being embedded with chip 1035. Usually, chip 1035 is flip-chip and is connected to fan-out and exceeds on the pad 1043 at chip 1035 edge. Utilizing through hole 1014, pad 1042 on an upper is allowed to connect another chip layer etc. for PoP encapsulation. In essence, it should be understood that pad 1042,1043 makes it possible to the other through hole post of lamination and wiring layer up and down, to create more complicated structure.
Parting tool 1045 is shown. It is to be understood that encapsulation chip 1035 array on panel 1040 is easily cut into single chip 1048, as shown in figure 21.
With reference to Figure 22, in some embodiments, adjacent chip socket can be of different sizes shape, comprises different size and/or different shapes. Such as, treater chip 1035 can be positioned in a socket and be connected to the memory chip 1055 being positioned in adjacent outlet. When this array is cut by scribing, adjacent socket can keep together. Therefore, an encapsulation can comprise more than one chip, and can comprise different chips, wherein can comprise passive filter chip, but should it is to be noted that utilize above-mentioned for the manufacture of the technology of electrical condenser and wave filter, it is possible to the co-manufactured as the part of framework.
Pad 1042,1043 is connected to chip by ball grid array BGA or land grid array LGA. In the current state of this area, the length of through hole post can be about 130 microns. When the thickness of chip 1035,1055 is greater than about 130 microns, it may be necessary at through hole top another through hole stacking. Technology for stacked via is known, particularly ties up in Hull in common pending application US13/482099 and US13/483185 of the people such as thatch and has discussed.
With reference to Figure 23, die package 1048 is shown from below, the tube core 1055 being included in polymer frame 1016 so that tube core 1055 is surrounded by framework 1016, and the through hole 1014 being centered around the framework 1016 of tube core 1055 periphery and passing is provided.Tube core is positioned in socket and is kept in position by the 2nd polymkeric substance 1036. Framework 1016 is made up to ensure stability of fibre-reinforced prepregs usually. 2nd polymkeric substance 1036 can also be prepreg, it may also be polymeric film or moulding compound. As shown in the figure, usually, through hole 1014 is simple cylindrical hole, but they can have different shapes and size. A part for the ball grid array welding ball 1057 on chip 1055 is connected to through hole 1014 by the pad 1043 of fan-out configuration. As shown in the figure, it is possible to there is the additional weldering ball being directly connected to beneath chips substrate. In some embodiments, in order to communicate and data processing, at least one through hole is same shaft through-hole. In other embodiments, at least one through hole is transmission line. Such as, in common pending application US13/483185, the technology for the manufacture of same shaft through-hole is given. Such as, US13/483234 provides the technology for the manufacture of transmission line.
Except being provided for chip-stacked contact, it is possible to use chip and its surrounding environment are kept apart by the through hole 1014 around chip, thus provide Faraday shield. Such shielding through hole can be connected to pad so that shielding through-hole interconnection on chip and be that chip provides shielding.
Can having the through hole more than a row around chip, and interior row can be used for sending signal, outer row is used for shielding. Outer row can be connected to the solid copper billet being manufactured on chip, thus can be used as the heat sink heat produced with the chip that dissipates. This kind of mode can be taked to encapsulate different tube cores. Should it is emphasized that, one or more through hole can be extend inducer, electrical condenser can co-manufactured and be embedded in framework so that inducer provides wave filter together with electrical condenser.
Utilize the embedded chip technology of the framework with through hole as herein described to be particularly suitable for simulation process because contact is very short and the number of contacts of each chip is relatively few.
Should be understood that, technology described herein is not limited to encapsulation IC chip. In some embodiments, tube core comprises the device being selected from safety fuse, electrical condenser, inducer and wave filter. The technology describing in the common pending application US13/962316 of the people such as thatch and manufacturing inducer and wave filter is tieed up in Hull.
With reference to Figure 24 and Figure 24 (a) to 24 (l), a kind of method manufacturing the chip receptacle array surrounded by organic substrate framework comprises the following steps: obtain sacrificial carrier 1080-24 (a).
Optionally, copper carrier 1080 applies in copper seed layer 1082-24 (b). Seed Layer 1082 applies resist layer 1084-24 (c), is usually made up of nickel and is usually deposited by physical vapor method such as sputtering method. As an alternative, such as can also be deposited by plating or electroless plating. Other candidate material comprises tantalum, tungsten, titanium, titanium-tungstenalloy, tin, lead, tin-lead alloy, and all these materials can sputter, and tin and lead can also be electroplated or electroless plating, and the thickness of barrier metal layer is generally 0.1 to 1 micron. (solvent that each candidate's barrier material later use is suitable or plasma etch conditions remove). After applying blocking layer, apply another copper seed layer 1086-24 (d). The thickness of copper seed layer is generally about 0.2 micron��5 microns.
Preferred steps 24 (b) to 24 (d) is good to guarantee that blocking layer and substrate adhere to, the good adhesion of through hole and growth, and makes it possible to follow-up remove substrate and do not damage through hole by etching.Although best result comprises these steps, but these steps are optional, and one or more step can not be used.
Then applying photoresist layer 1088-step 24 (e), Figure 24 (e), is patterned as and is had copper vias pattern-22 (f). Then, plating in pattern into copper 1090-24 (g), then stripping is except photoresist layer 1088-24 (h). With copper vias 1090-24 (i) that polymer dielectric 1092 layers pressure is upright, this dielectric medium can be fiber-reinforced polymer-matrix matter prepreg. The via-hole array of layer pressure carries out subtracting thin and planarization to expose the end-24 (j) of copper vias. Then this carrier is removed.
Optionally and preferably; planarizing polymer dielectric medium-24 (k) of the copper vias end with exposure is protected by applying erosion resistant 1094; erosion resistant is such as photoresist material or dielectric film, then removes copper carrier 1080-24 (l). Usually, carrier is copper carrier 1080, is removed by dissolved copper. Ammonium hydroxide or cupric chloride can be used to carry out dissolved copper.
, it is possible to etch away blocking layer-24 (m), then etch protection layer 1094-step 24 (n) can then be removed.
Although not describing herein, it is to be understood that, upright copper vias can to retain, through hole manufactures by the unnecessary copper of panel plating and selective etch. In fact, socket can also manufacture alternatively by the part that selective etch while shielding through hole falls copper panel.
As mentioned before, it should be understood that one or more through hole 1090 can be the improvement through hole 5 shown in Fig. 1, comprising electrical condenser 6. In addition, one or more through hole can be the inducer 7 in Fig. 1.
Although through hole column technology is preferred, but if only needing the improvement through hole 5 comprising electrical condenser 6 in simple through hole 1090 instead of Fig. 1 or the inducer through hole 7 in Fig. 1, then brill can also be used to fill out technology when only needing simple cylindrical hole.
With reference to Figure 25 and Figure 25 (a) to 25 (e), in another kind of changing method, obtain the carrier-25 (a) being made up of copper-clad plate (CCL) 1100. The thickness of CCL is tens microns to several hundred microns. A typical thickness is 150 microns. Through CCL drilling bore hole 1102-25 (b). Hole 1102 can have the diameter of tens microns to several hundred microns. Usually, the diameter in hole is 150 microns.
Then, plating through hole is to create plating through hole 1104-25 (c).
Then, grinding or etching copper clad laminate 1100, to remove surface layers of copper 1106,1108, obtain having veneer sheet 1110-25 (d) of plating through hole (Pth) copper vias 1104.
Then, utilize CNC or punching press, by veneer sheet manufacture for holding socket 1112-25 (e) of chip.
With reference to Figure 26, illustrating the framework 2000 wherein with embedded filters 2002 and the orthographic plan of multiple cloth line three-way hole 2004, framework can comprise socket 2006, for holding chip such as treater chip or memory chip. Such framework 2000 can make a part for big array, such as those shown in Figure 17-19. Framework 2000 as shown in the figure comprises a socket 2006, for holding single chip. However, it should be understood that framework can comprise two or more socket, for holding two or more chip. This kind of socket 2006 can be used for embedded processor chip, memory chip or passive chip, is embedded with wave filter etc. in passive chip.
In this manual, inducer has been described in detail and how electrical condenser can be manufactured to the passive device being embedded in organic substrate. The combination of such electrical condenser and inducer can provide wave filter. This specification sheets continues to explain subsequently and has the polymer frame embedding through hole and can how to manufacture and how they can be used as the socket of embedded active part. The combination of these technology achieves and comprises one or many
The manufacture of the encapsulation of individual embedding chip and Embedded Filter, it comprises active and passive device for minimum and highly integrated RF device.
Description above is only explanation property. Should be understood that, the present invention can have many change programmes.
Several embodiments of the present invention are described. However, it should be understood that various amendment can be carried out and do not depart from the spirit and scope of the invention. Therefore, other embodiment drops within the scope of appended claims.
Those skilled in the art are it will be appreciated that the invention is not restricted to above concrete diagram and the content described. And, the scope of the present invention is defined by the following claims, and comprises the combination of each technology feature mentioned above and sub-portfolio and its changes and improvements, and those skilled in the art will predict such combination, changes and improvements after reading aforementioned explanation.
In detail in the claims, term " comprises " and variant such as " comprises ", " containing " etc. refer to that cited assembly is included, but generally do not get rid of other assemblies.

Claims (61)

1. the chip socket that a kind is limited by organic substrate framework, wherein said organic substrate framework comprises at least one through hole post layer, at least one through hole wherein passing the framework surrounding socket comprises at least one electrical condenser, the top electrode that described electrical condenser comprises lower electrode, dielectric layer and contacts with described through hole post.
2. chip socket as claimed in claim 1, the dielectric medium of wherein said electrical condenser comprises Ta2O5��TiO2��BaxSr1- xTiO3��BaTiO3��BaO4SrTi and Al2O3In at least one.
3. chip socket as claimed in claim 1, the lower electrode of wherein said electrical condenser comprises precious metal.
4. chip socket as claimed in claim 1, wherein said lower electrode comprises the metal being selected from gold, platinum and tantalum.
5. chip socket as claimed in claim 1, wherein said top electrode comprises the metal being selected from gold, platinum and tantalum.
6. chip socket as claimed in claim 1, at least one through hole wherein said stands upright at least one electrical condenser described.
7. chip socket as claimed in claim 6, wherein said top electrode comprises described through hole post.
8. chip socket as claimed in claim 1, wherein said electrical condenser has the sectional area limited by the sectional area of described through hole post, and this sectional area is carefully controlled the electrical capacity regulating electrical condenser.
9. chip socket as claimed in claim 1, at least one electrical condenser wherein said has the electrical capacity of 1.5pF��300pF.
10. chip socket as claimed in claim 1, at least one electrical condenser wherein said has the electrical capacity of 5pF��15pF.
11. chip sockets as claimed in claim 1, wherein said framework also comprises at least one characteristic layer.
12. chip sockets as claimed in claim 1, wherein at least one electron device is embedded in described socket and is electrically connected with at least one through hole described.
13. chip sockets as claimed in claim 1, at least one electron device wherein said comprises the 2nd electrical condenser.
14. chip sockets as claimed in claim 13, wherein said 2nd electrical condenser is discrete device, and described discrete device at least has metal endpoints in one end at it.
15. chip sockets as claimed in claim 13, wherein said 2nd electrical condenser is metal-insulator-metal type (MIM) electrical condenser.
16. chip sockets as claimed in claim 13, wherein said metal-insulator-metal type (MIM) electrical condenser comprises by being selected from Ta2O5��TiO2��BaxSr1-xTiO3��BaTiO3��BaO4SrTi and Al2O3In at least one dielectric medium form dielectric layer.
17. chip sockets as claimed in claim 13, the lower electrode of wherein said metal-insulator-metal type (MIM) electrical condenser comprises precious metal.
18. chip sockets as claimed in claim 13, wherein said lower electrode comprises the metal being selected from gold, platinum and tantalum.
19. chip sockets as claimed in claim 13, the top electrode of wherein said metal-insulator-metal type (MIM) electrical condenser comprises the metal being selected from gold, platinum and tantalum.
20. chip sockets as claimed in claim 13, wherein said metal-insulator-metal type (MIM) electrical condenser is attached on isolator carrier.
21. chip sockets as claimed in claim 13, wherein said isolator carrier comprises and is selected from silicon (Si), SiO2(silicon-dioxide), glass, AlN, aluminum oxide and c-surface sapphire Al2O3(0001) at least one in.
22. chip sockets as claimed in claim 13, the pole plate of wherein said metal-insulator-metal type (MIM) electrical condenser is connected to through hole by characteristic layer.
23. chip sockets as claimed in claim 22, wherein the device of the characteristic layer in described framework one side and embedding comprises inducer.
24. chip sockets as claimed in claim 22, wherein the embedding device in described framework, socket and at least one feature structure in described characteristic layer provide wave filter.
25. chip sockets as claimed in claim 22, wherein said wave filter is selected from basis LC low-pass filter, LC Hi-pass filter, LC serial band pass filter, LC bandpass filter in parallel and low pass parallel connection-Chebyshev's wave filter.
26. chip sockets as claimed in claim 1, the chip being wherein arranged in socket by comprising the Faraday's cage electromagnetic radiation shielding of through hole post at described framework, and thus maximum degree reduces electromagnetic interference.
27. chip sockets as claimed in claim 26, extending in X-Y plane at least partially of wherein said through hole post.
28. 1 kinds of frameworks, described framework comprises the multiple sockets for holding multiple chip, and wherein each socket comprises a framework, and described framework comprises grid and at least one electrical condenser of copper vias post.
29. frameworks as claimed in claim 28, are wherein embedded in treater chip at the first socket and are embedded in, at the 2nd socket, the passive chip comprising at least one electrical condenser.
30. 1 kinds of frameworks, described framework comprises the multiple chip sockets being arranged in array, and wherein each chip socket is surrounded by framework.
31. frameworks as claimed in claim 30, wherein embed at least one treater chip at least one socket.
32. 1 kinds of chip receptacle array, described array is limited by the organic substrate framework of the framework surrounding socket, and comprise the metal through hole post grid through described organic substrate framework, wherein at least one metal through hole post and at least one electrical condenser are connected in series.
33. arrays as claimed in claim 32, wherein said electrical condenser comprises lower electrode and dielectric layer, and is combined in the base portion of at least one through hole post so that at least one through hole post described stands upright at least one electrical condenser described.
34. arrays as claimed in claim 32, at least one through hole post wherein said also comprises the top electrode of at least one electrical condenser described.
35. arrays as claimed in claim 32, wherein said framework comprises at least one characteristic layer, wherein forms at least one inducer at least one characteristic layer described.
36. arrays as claimed in claim 32, wherein said organic substrate framework also comprises glass fiber bundle.
37. arrays as claimed in claim 32, wherein each through hole has the width of 25 microns��500 microns.
38. arrays as claimed in claim 32, wherein each through hole is cylindrical and has the diameter of 25 microns��500 microns.
39. arrays as claimed in claim 32, the framework wherein surrounding at least one socket comprises through hole post alternately and characteristic layer, and comprises at least one through hole post layer and a characteristic layer.
40. arrays as claimed in claim 32, the metal through hole post grid wherein passing described organic substrate framework comprises multiple through hole post layer.
41. arrays as claimed in claim 32, the framework wherein surrounding at least one socket comprises through hole post alternately and the continuous coil of characteristic layer formation, and it crosses at least one through hole post layer and a characteristic layer.
42. arrays as claimed in claim 32, wherein at least one through hole post comprises the through hole post of elongation.
43. arrays as claimed in claim 32, multiple through hole post layer crossed over by the continuous coil of the through hole post wherein extended.
44. arrays as claimed in claim 32, wherein said array comprises the adjacent chips socket of different physical dimension.
45. arrays as claimed in claim 43, wherein said array comprises the adjacent chips socket of different size.
46. arrays as claimed in claim 42, wherein said array comprises the adjacent chips socket of different shapes.
47. arrays as claimed in claim 32, wherein said framework comprises at least one characteristic layer and at least one adjacent via layer, described layer extends in X-Y plane and has height z, wherein said compound electric minor structure comprises at least one electrical condenser being connected with at least one inducer, at least one electrical condenser described comprises lower electrode and dielectric layer, it is arranged on the bottom of via layer, it is clipped between at least one characteristic layer and through hole post, at least one through hole described in making stands upright at least one electrical condenser described and optionally forms top electrode, wherein said via layer embeds in the polymer matrix, and at least one inducer wherein said be formed in fisrt feature layer and adjacent via layer at least its among one.
48. arrays as claimed in claim 32, wherein at least one electrical condenser and at least one inducer are connected in series.
49. arrays as claimed in claim 32, wherein said framework is included at least second feature layer above described via layer, and at least one electrical condenser described and at least one inducer described are connected in parallel by described characteristic layer.
50. arrays as claimed in claim 49, at least one inducer wherein said is manufactured in described characteristic layer.
51. arrays as claimed in claim 32, at least one inducer wherein said is screw winding coil.
52. arrays as claimed in claim 32, the inductance value of wherein said inducer is at least 0.1nH.
53. arrays as claimed in claim 32, the inductance value of wherein said inducer is less than 50nH.
54. arrays as claimed in claim 32, wherein manufacture another inducer in via layer.
55. arrays as claimed in claim 54, the inductance value of another inducer wherein said is at least 0.1nH.
56. arrays as claimed in claim 32, wherein at least one inducer and at least one electrical condenser described provide a wave filter, and described wave filter is selected from basis LC low-pass filter, LC Hi-pass filter, LC serial band pass filter, LC bandpass filter in parallel and low pass parallel connection-Chebyshev's wave filter.
57. panels as claimed in claim 30; wherein at least one socket is filled with chip; at least one electrical condenser that described chip is included in polymeric matrix; framework and chip are thinned the end exposing through hole; apply to connect and terminal by laying photoresist material on the two sides subtracting thin polymeric matrix and deposit copper pad in photoresist material pattern; stripping subsequently except photoresist material and lays solder mask between copper pad, with after-applied supercoat.
58. 1 kinds comprise the panel of chip receptacle array, each panel is surrounded by organic substrate framework and limits, described organic substrate framework comprises the copper vias post grid through described organic substrate framework, wherein said panel comprises at least one region with the first group of physical dimension socket holding first kind chip and has the 2nd region of the 2nd group of physical dimension socket holding the 2nd type chip, and wherein at least one through hole post comprises film capacitor.
59. panels as claimed in claim 58, wherein at least one through hole post stands upright on described film capacitor.
60. panels as claimed in claim 58, at least one through hole post wherein said comprises the top electrode of film capacitor.
61. panels as claimed in claim 58, wherein said panel comprises the closely adjacent region with two kinds of different socket types.
CN201510836740.3A 2014-11-27 2015-11-25 Chip-use polymer frame being connected with capacitor in series and having at least one hole Pending CN105655316A (en)

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