TWI689954B - Polymer frame for chip with at least one through hole connected in series with capacitor - Google Patents

Abstract

A chip socket defined by an organic matrix frame, wherein the organic matrix frame includes at least one through-hole column layer, wherein at least one through hole surrounding the socket through the frame includes at least one capacitor, the capacitor includes a lower electrode, a dielectric layer And an upper electrode in contact with the via post.

Description

Polymer frame for chip with at least one through hole connected in series with capacitor

The present invention relates to an improved chip package, and in particular to an embedded chip in which passive devices such as capacitors and filters are installed.

Driven by the increasing demand for miniaturization of increasingly complex electronic devices, consumer electronics such as computers and telecommunications equipment have become increasingly integrated. This has led to requirements for supporting structures such as IC substrates and IC inserts to have multiple conductive layers and through holes that are electrically insulated from each other by a dielectric material and have a high density.

The overall requirements of this support structure are reliability and proper electrical performance, thinness, rigidity, flatness, good heat dissipation and competitive unit price.

Among the various ways to achieve these requirements, a widely implemented manufacturing technique for creating interlayer interconnect vias is to use laser drilling. The drilled holes penetrate through the subsequently placed dielectric substrate to the final metal layer and are subsequently filled with metal , Usually copper, where the metal is deposited by plating techniques. This method of forming holes is sometimes referred to as "drill-fill", and the resulting through-hole may be referred to as "drill-fill through-hole".

There are several disadvantages to the method of drilling and filling through holes. Because each through-hole needs to be drilled separately, productivity is limited and the cost of manufacturing complex multi-through-hole IC substrates and inserts becomes prohibitive. In large arrays, it is difficult to produce high-density and high-quality close to each other and Through holes with different sizes and shapes. In addition, laser drilled through holes have rough sidewalls and inward tapers that pass through the thickness of the dielectric material. This taper reduces the effective diameter of the through hole. Especially in the case of ultra-small via diameters, it may also adversely affect the electrical contact of the previous conductive metal layer, thereby causing reliability problems. In addition, when the dielectric being drilled is a composite material that includes glass or ceramic fibers in a polymer matrix, the sidewalls are particularly rough, and this roughness may create additional stray inductance.

The filling process of drilled through holes is usually done by copper electroplating. Electroplating deposition techniques can cause dents, in which small pits appear at the top of the via. Alternatively, when the via channel is filled with copper exceeding its holding capacity, it may cause overflow, resulting in a hemispherical upper surface protruding beyond the surrounding material. Dimples and overflows often cause difficulties in subsequent stacking of vias up and down as required for manufacturing high-density substrates and inserts. In addition, it should be recognized that large via channels are difficult to fill uniformly, especially when they are located near small vias within the same interconnect layer of an interposer or IC substrate design.

Although acceptable size and reliability are improving over time, the disadvantages described above are inherent flaws in the drill-fill technique and are expected to limit the range of possible via sizes. It should also be noted that laser drilling is the best method for manufacturing circular through-hole channels. Although it is theoretically possible to manufacture slit-shaped through-hole channels by laser milling, in reality the range of geometries that can be manufactured is relatively limited, and the through-holes in a given support structure are generally cylindrical and are substantially the same.

It is expensive to manufacture through-holes through a drill-fill process, and it is difficult to use a relatively cost-effective plating process to uniformly and uniformly fill the thus formed through-hole channels with copper.

Laser-drilled holes in composite dielectric materials are actually limited to a diameter of 60×10 ^-6 m, and due to the ablation process involved and the nature of the drilled composite material, they are even subject to significant taper shapes And the adverse effects of rough sidewalls.

In addition to the other limitations of laser drilling described above, another limitation of drill-fill technology is that it is difficult to create through holes of different diameters in the same layer, because when drilling through holes of different sizes and then using metal When filling to make through holes of different sizes, the filling rate of the via channels is different. As a result, the typical problem of dents or spills that are characteristic of the drill-fill technique is exacerbated because it is not possible to optimize the deposition technique for through holes of different sizes simultaneously.

An alternative solution to overcome many of the shortcomings of the drill-fill method is to manufacture by depositing copper or other metals into the pattern formed in the photoresist using a technique also known as "pattern plating".

In pattern plating, the seed layer is first deposited. A photoresist layer is then deposited thereon, followed by exposure to form a pattern, and selective removal to make a trench that exposes the seed layer. The via post is formed by depositing copper into the photoresist trench. The remaining photoresist is then removed, the seed layer is etched away, and a dielectric material, usually a polymer-impregnated glass fiber mat, is laminated on and around it to surround the via post. Various techniques and processes can then be used to planarize the dielectric material, removing a portion of it to expose the top of the via post, thereby allowing this conductive ground to be used to form the next metal layer thereon. The subsequent metal conductor layer and via post can be deposited on it by repeating this process to form the desired multilayer structure.

In an alternative but closely related technique, referred to below as "panel plating", a continuous layer of metal or alloy is deposited onto the substrate. A photoresist layer is deposited on top of the substrate, and a pattern is developed therein. The pattern of the developed photoresist is stripped to selectively expose the metal underneath, which can then be etched away. The undeveloped photoresist protects the metal underneath from being etched away, leaving a pattern of upright features and vias.

After stripping the undeveloped photoresist, a dielectric material, such as a polymer-impregnated glass fiber mat, can be laminated on or around the upright copper features and/or via posts. After planarization, the subsequent metal conductor layer and via post can be deposited thereon by repeating this process to form the desired multilayer structure.

The via layer created by the above-mentioned pattern plating or panel plating method is generally referred to as a "via pillar" and a copper feature layer.

It will be recognized that the general impetus for the evolution of microelectronics involves making smaller, thinner, lighter and more powerful products with high reliability. Using thick and cored interconnects does not result in ultra-thin products. In order to form higher density structures in interconnecting IC substrates or "plug-ins", more layers with even smaller connections are needed. In fact, it is sometimes desirable to stack devices on top of each other.

If a plated laminate structure is deposited on copper or other suitable sacrificial substrate, the substrate can be etched away, leaving a separate coreless laminate structure. Other layers can be deposited on the side previously attached to the sacrificial substrate, thereby enabling formation of a double-area layer, thereby minimizing warpage and helping to achieve planarization.

A flexible technique for manufacturing high-density interconnects is to build a multi-layer structure with patterns or panel plating including metal vias or features in a dielectric matrix. The metal may be copper and the dielectric may be a fiber-reinforced polymer, usually a polymer with a high glass transition temperature ( _Tg ), such as polyimide. These interconnects may be cored or coreless, and may include cavities for stacked devices. They can have odd or even layers. The technology implemented is described in the existing patent granted to Amitec-Advanced Multilayer Interconnect Technologies Ltd.

For example, Hurwitz et al. entitled "Advanced multilayer coreless support structures and method" US Patent 7,682,972 for "their fabrication" describes a method of manufacturing a stand-alone film including a through-hole array in a dielectric, which is used as a precursor for building an excellent electronic support structure, the method includes the following steps: Manufacturing a conductive via film in the dielectric surrounding the sacrificial carrier, and separating the film from the sacrificial carrier to form an independent laminated array. Electronic substrates based on this independent film can be thinned and planarized by the laminated array, Subsequent via hole formation is formed. This bulletin is fully incorporated by reference.

U.S. Patent No. 7,669,320, entitled "Coreless cavity substrates for chip packaging and their fabrication" by Hurwitz et al., "Coreless cavity substrates for chip packaging and their fabrication" Method, the IC support is used to support a first IC chip in series with a second IC chip; the IC support includes a stack of alternating layers of copper features and through holes in the insulating surrounding material, the The first IC chip may be adhered to the IC support body, and the second IC chip may be adhered to a cavity inside the IC support body, wherein the cavity is obtained by etching away the copper socket and selective etching Formed by removing accumulated copper. This gazette is fully incorporated herein by reference.

U.S. Patent No. 7,635,641, entitled "Integrated circuit support structures and their fabrication" by Hurwitz et al., describes a method of manufacturing electronic substrates, including the following steps: ( A) Selecting the first base layer; (B) depositing an etch barrier layer on the first base layer; (C) forming a first half-stack of alternating conductive layers and insulating layers, the conductive layers being insulated by penetration Through the layer through holes; (D) apply the second base layer to the first half stack; (E) apply the photoresist protective coating to the second base layer; (F) Etching away the first base layer; (G) removing the photoresist protective coating; (H) removing the first etching barrier layer; (I) forming a second alternating conductive layer and insulating layer Semi-stacked Body, the conductive layer is interconnected by a through hole penetrating the insulating layer; wherein the second half stack has a configuration substantially symmetrical to the first half stack; (J) applying the insulating layer to alternating conductive layers and insulation On the second half of the stack; (K) removing the second base layer, and (L) by exposing the end of the through hole on the outer surface of the stack and coating it with a terminator To terminate the substrate. This gazette is fully incorporated herein by reference.

Over time, it can be expected that both drill-fill technology and through-hole column deposition technology will be able to manufacture substrates with more miniaturized and higher through-hole and feature density. However, it is clear that the development of through-hole column technology is likely to maintain a competitive advantage.

The substrate can connect the chip with other devices through an interface. The chip must be bonded to the substrate through an assembly process that provides a reliable electrical connection to achieve electrical communication between the chip and the substrate.

A chip embedded in the plug-in to connect to the outside world can shrink the chip package and shorten the connection with the outside world. By simplifying the manufacturing process, the assembly process of the chip-bonding substrate is eliminated to provide cost savings and potentially improve reliability.

In essence, the concept of embedded active devices such as analog, digital, and MEMS chips involves building a chip support structure or substrate with through holes around the chip.

One method of implementing an embedded chip is to manufacture a chip support structure on a chip array on the chip, where the circuit of the support structure is larger than the chip unit size. This method is known as fan-out chip layer packaging (FOWLP). Despite the increasing size of silicon wafers, expensive material modules and processes still limit the wafer size to 12 inches, thereby limiting the number of FOWLP units that can be placed on the wafer. Despite the fact that 18-inch wafers are being considered, the required investment, material modules and equipment are still unknown. The number of chip support structures that can be processed at one time is limited. As a result, the unit cost of FOWLP has risen, so the cost is too high for markets that require a high degree of competition, such as the wireless communications, household appliances, and automotive markets.

FOWLP also has performance limitations, because the thickness of metal features that are placed on silicon wafers as fan-out or fan-in circuits is limited to a few microns. This causes resistance problems.

An alternative manufacturing method involves cutting the chip to separate the chip and embedding the chip into a panel composed of a dielectric layer and copper interconnects. One advantage of this alternative method is that the panel can be made very large, thereby embedding much more chips in one process. For example, a 12-inch chip can process 2,500 FOWLP chips with a size of 5 mm × 5 mm at a time, while the applicant, Zhuhai Yueya, currently uses a 25-inch × 21-inch panel that can process 10,000 chips at a time. Because the price of processing the panel is significantly lower than the price of processing wafers, and the output of each panel is four times the wafer output, the unit price can be significantly reduced, thereby opening up new markets.

In these two technologies, the line pitch and wire width used in the industry have shrunk over time. For panels, the standard is reduced from 15 microns to 10 microns, and for wafers, from 5 microns to 2 microns. .

The embedded method has many advantages. The cost of first-level assembly such as wire bonding, flip chip or SMD (surface mount device) soldering is reduced. Since the chip and the substrate are seamlessly connected in a single product, the electrical performance is improved. The packaged chip becomes thinner, resulting in a better form factor, and the upper surface of the embedded chip package is vacated due to other uses, including further space saving configurations, such as the use of stacked chips and PoP (package on package) technology.

In both FOWLP and panel-based embedded chip technology, the chips are packaged in an array (on a substrate or panel) and are separated by dicing after manufacturing is completed.

RF (radio frequency) technology, such as Wi-Fi, Bluetooth, etc., is being widely used in various Such devices include mobile phones and automobiles.

In addition to baseband processing and memory chips, RF devices also require passive devices, such as various types of capacitors, inductors, and filters. Such passive devices can be surface-mounted, but in order to achieve more significant miniaturization and cost savings, such devices can be embedded in the substrate.

US 13/962,075, entitled "Thin Film Capacitors Embedded in Polymer Dielectric", filed by Hurwitz on August 8, 2013, describes a substrate containing a capacitor made of metal electrodes and ceramic or metal An oxide dielectric layer is constructed, and the capacitor is embedded in a polymer-based encapsulating material and can be connected to a circuit through a via post provided on the capacitor.

US 13/962,316 entitled "Multilayer Structures and Embedded Features", filed on August 8, 2013, describes a composite electronic structure that includes at least one feature layer and at least one adjacent via layer; the layer is in the XY plane Extends above and has a height z, wherein the structure includes at least one capacitor connected in series or parallel with at least one inductor to provide at least one filter; the at least one capacitor is sandwiched between at least one characteristic layer and at least one adjacent pass Between at least one through hole in the hole layer such that the at least one through hole stands upright on the at least capacitor, and at least one of the first feature layer and the adjacent through hole layer includes at least one extending on the XY plane An inductor.

US 14/269,884, entitled "Interposer Frame with Polymer Matrix and Methods of Fabrication", filed by Hurwitz on May 5, 2014, teaches an array of chip sockets defined by an organic matrix frame, said frame Around the socket passing through the organic matrix frame, a grid of metal through holes passing through the organic matrix frame is also included. The chip may be placed in a socket and then fixed in place by a polymer-based dielectric, thereby embedding the chip in the frame.

The first aspect of the present invention relates to a chip socket defined by an organic matrix frame, wherein the organic matrix frame includes at least one through-hole column layer, wherein at least one through-hole passing through the frame surrounding the socket includes at least one capacitor, The at least one capacitor includes a lower electrode, a dielectric layer, and an upper electrode in contact with the via post.

Generally, the dielectric of the capacitor includes at least one of Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ and Al ₂ O ₃ .

Generally, the lower electrode of the capacitor includes a precious metal.

Optionally, the lower electrode includes a metal selected from gold, platinum, and tantalum.

In some embodiments, the upper electrode includes a metal selected from gold, platinum, and tantalum.

Generally, the at least one through hole stands upright on the at least one capacitor.

Optionally, the upper electrode includes the via post.

Preferably, the capacitor has a cross-sectional area defined by the cross-sectional area of the via post, which is carefully controlled to adjust the capacitance of the capacitor.

In some embodiments, the at least one capacitor has a capacitance of 1.5 pF to 300 pF.

In a preferred embodiment, the at least one capacitor has a capacitance of 5pF~15pF.

Optionally, the frame also includes at least one feature layer.

Optionally, at least one electronic device is embedded in the socket and One through hole is electrically connected.

Optionally, the at least one electronic device includes a second capacitor.

In some embodiments, the second capacitor is a discrete device having a metal terminal at at least one end.

In some embodiments, the second capacitor is a metal-insulator-metal (MIM) capacitor.

In some embodiments, the metal-insulator-metal (MIM) capacitor includes at least one dielectric selected from Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ and Al ₂ O ₃ Constitute the dielectric layer.

In some embodiments, the lower electrode of the metal-insulator-metal (MIM) capacitor includes a precious metal.

In some embodiments, the lower electrode includes a metal selected from gold, platinum, and tantalum.

In some embodiments, the upper electrode of the metal-insulator-metal (MIM) capacitor includes a metal selected from gold, platinum, and tantalum.

Optionally, the metal-insulator-metal (MIM) capacitor is attached to an insulator carrier.

In some embodiments, the insulator carrier includes at least one selected from silicon (Si), SiO ₂ (silicon dioxide), glass, AlN, aluminum oxide, and c-plane sapphire Al ₂ O ₃ (0001).

In some embodiments, the plate of the metal-insulator-metal (MIM) capacitor is connected to the via via the feature layer.

Generally, the device embedded in the socket is connected to at least one via with an embedded capacitor through at least one feature layer.

Optionally, the system further includes a feature layer on one side of the frame, and the embedded device includes an inductor.

Optionally, the embedded device in the frame, the embedded device in the socket, and at least one feature structure in the feature layer provide a circuit that functions as a filter.

Optionally, the filter is selected from a basic LC low pass filter, LC high pass filter, LC series band pass filter, LC Parallel band pass filters (LC parallel band pass filters) and low pass parallel-Chebyshev filters (Low Pass Parallel-Chebyshev filters).

Optionally, the chip installed in the socket is shielded from electromagnetic radiation by a Faraday cage including a via post, thereby minimizing electromagnetic interference.

In some embodiments, the Faraday cage also includes a feature layer within the frame.

Another aspect of the present invention relates to a frame including a plurality of sockets for accommodating a plurality of chips, wherein each socket includes a frame, and the frame includes a grid of copper via posts and at least one capacitor.

Optionally, a processor chip is embedded in the first socket and a passive chip including at least one capacitor is embedded in the second socket.

Yet another aspect of the present invention relates to a frame including a plurality of chip sockets arranged in an array, wherein each chip socket is surrounded by a frame.

Optionally, at least one processor chip is embedded in at least one socket.

Yet another aspect of the invention relates to a chip socket array, the array being defined by an organic matrix frame surrounding the frame of the socket, and further including A grid of metal via columns, wherein at least one metal via column is connected in series with at least one capacitor.

Optionally, the capacitor includes a lower electrode and a dielectric layer, and is bonded to the bottom of at least one via post so that the at least one via post stands upright on the at least one capacitor.

Optionally, the at least one via post includes an upper electrode of the at least one capacitor.

Optionally, the frame includes at least one feature layer, wherein at least one inductor is formed in the at least one feature layer.

Generally, the organic matrix frame also includes glass fiber bundles.

Generally, each through hole has a width ranging from 25 microns to 500 microns.

Generally, each through hole is cylindrical and has a diameter of 25 microns to 500 microns.

Generally, the frame surrounding at least one socket includes alternating via columns and feature layers, and includes at least one via column layer and one feature layer.

Typically, the organic matrix frame includes multiple layers and the grid includes multiple via column layers, where each pair of consecutive via column layers is separated by a feature layer.

In some embodiments, the frame surrounding the at least one socket includes alternating via columns and continuous coils of features spanning at least one via column layer and one feature layer.

Optionally, the at least one via post includes an elongated via post.

Optionally, a continuous coil of elongated via columns spans multiple via column layers.

Optionally, the array includes adjacent chip sockets of different physical dimensions.

Optionally, the array includes adjacent chip sockets of different sizes.

Optionally, the array includes adjacent chip sockets of different shapes.

Optionally, the frame includes at least one feature layer and at least one adjacent via layer, the layer extending in the XY plane and having a height z, wherein the composite electronic structure includes at least one connected to at least one inductor A capacitor, the at least one capacitor includes a lower electrode and a dielectric layer, is disposed at the bottom of the via layer, is sandwiched between at least one feature layer and the via post, such that the at least one via hole stands upright in the at least one capacitor An upper electrode is optionally formed, wherein the via layer is embedded in a polymer matrix, and wherein the at least one inductor is formed in at least one of the first feature layer and the adjacent via layer.

Optionally, at least one capacitor and at least one inductor are connected in series.

Optionally, the frame includes at least a second feature layer above the via layer, and the at least one capacitor and the at least one inductor are connected in parallel through the feature layer.

Optionally, the at least one inductor is fabricated in the feature layer.

Optionally, the at least one inductor is a spirally wound coil.

Optionally, the inductance of the inductor is at least 0.1 nH.

Optionally, the inductance of the inductor is less than 50nH.

Optionally, another inductor is fabricated in the via layer.

Optionally, the inductance value of the other inductor is at least 0.1 nH.

Optionally, at least one inductor and the at least one capacitor provide a filter selected from a basic LC low pass filter, LC high pass filter, LC LC series band pass filters, LC parallel band pass filters and low-pass parallel-Chebyshev filters Device (Low Pass Parallel-Chebyshev filters).

Optionally, at least one socket contains a chip that includes at least one capacitor and frame within a polymer matrix, the chip is thinned to expose the end of the through-hole, through both sides of the thinned polymer matrix A photoresist is laid and copper pads are deposited in the photoresist pattern to apply connections and terminals, then the photoresist is stripped and a solder mask is placed between the copper pads, and then a protective coating is applied.

Another aspect of the present invention relates to a panel including an array of chip sockets, each panel being surrounded and defined by an organic matrix frame including a grid of copper via columns passing through the organic matrix frame, wherein The panel includes at least one area having a first set of sockets for accommodating one type of chip and a second area having a second set of sockets for accommodating a second type of chip, wherein at least one via post includes a film capacitor.

Optionally, the panel is used to make at least one via post stand upright on the film capacitor.

Optionally, the at least one via post includes the upper electrode of the film capacitor.

Optionally, the panel includes closely adjacent areas with two different socket types.

The combination of frames with built-in capacitors around the chip socket provides a higher degree of miniaturization, manufacturing economy, and enhanced reliability of RF (radio frequency) technologies such as Wi-Fi, Bluetooth, etc., which are widely used in mobile phones and automobiles, for example.

The protective coating may be selected from ENEPIG and organic varnishes.

The term micron or μm refers to 10 ^-6 m.

1‧‧‧Frame

2‧‧‧Socket

3‧‧‧dielectric

4‧‧‧Through hole

5, 6, 7‧‧‧ through-hole column

8, 9‧‧‧ capacitor

10‧‧‧polymer

11.12‧‧‧Characteristic structure

13‧‧‧Inductor

14‧‧‧ substrate

20‧‧‧Capacitor

21‧‧‧ substrate

22‧‧‧Dielectric layer

24‧‧‧Feature layer

26 28 30 32‧‧‧Copper pillar

34‧‧‧Dielectric material

38‧‧‧Feature layer

40‧‧‧Inductor

42‧‧‧Through hole column

44‧‧‧Inductor

52‧‧‧Through hole column

54‧‧‧Capacitor

56‧‧‧Inductance via

60‧‧‧First inductor

62‧‧‧Through hole column

64‧‧‧Capacitor

66‧‧‧Second inductor

70‧‧‧Inductor

71‧‧‧Through hole column

72‧‧‧Through hole column

74‧‧‧Capacitor

78‧‧‧Connector

80‧‧‧Inductor

82‧‧‧Through hole column

84‧‧‧Capacitor

86‧‧‧Inductance via

88‧‧‧Trace

210‧‧‧Carrier

212‧‧‧ barrier

214‧‧‧thin copper layer

216‧‧‧First electrode

218‧‧‧dielectric layer

220‧‧‧Second electrode

222‧‧‧copper layer

224‧‧‧Photoresist

226‧‧‧Copper seed layer

228‧‧‧Photoresist layer

230‧‧‧Thick layer of photoresist

232‧‧‧Copper interconnect

234‧‧‧polymer-based dielectric matrix

236‧‧‧Copper seed layer

238‧‧‧Photoresist layer

240‧‧‧upper copper layer

242‧‧‧Photoresist layer

244‧‧‧copper through hole

246‧‧‧polymer-based dielectric matrix

248‧‧‧Capacitor

250‧‧‧Composite structure

252‧‧‧Titanium layer

254‧‧‧copper layer

256‧‧‧Photoresist layer

258‧‧‧Photoresist layer

260‧‧‧Bronze Port

262‧‧‧Bronze Port

264‧‧‧Solder mask

266‧‧‧ENEPIG

1200‧‧‧copper coil

1202‧‧‧Dielectric frame

1204‧‧‧ Cavity

1206, 1207, 1208

1209、1210‧‧‧Vertical components

1250‧‧‧Capacitor

P1, P2, P3, P4 ‧‧‧ port

L‧‧‧Inductor

C, C2, C3 ‧‧‧ capacitor

300‧‧‧Basic LC low-pass filter

V2, V3 ‧‧‧ through hole column

1010‧‧‧Array

1012、1012’‧‧‧Chip socket array

1014‧‧‧copper through hole

1016‧‧‧polymer

1018‧‧‧Frame

1020‧‧‧Panel

1021, 1022, 1023, 1024‧‧‧ block

1025‧‧‧level rod

1026‧‧‧Vertical pole

1027‧‧‧Outer frame

1028‧‧‧Socket

1029‧‧‧Socket

1030‧‧‧Array

1035‧‧‧chip

1036‧‧‧polymer

1038‧‧‧Frame

1040‧‧‧frame

1042, 1043‧‧‧ Copper wiring layer

1045‧‧‧Cutting tool

1048‧‧‧chip

1055‧‧‧chip

1057‧‧‧solder ball

1080‧‧‧Copper carrier

1082‧‧‧Copper seed layer

1084‧‧‧Anti-corrosion layer

1086‧‧‧Copper seed layer

1088‧‧‧Photoresist

1090‧‧‧copper through hole

1092‧‧‧ Polymer Dielectric

1094‧‧‧Anti-corrosion material

1100‧‧‧Copper-clad laminate

1102‧‧‧hole

1104‧‧‧plated through hole

1106, 1108‧‧‧surface copper layer

1110‧‧‧Laminate

1112‧‧‧Socket

2000‧‧‧frame

2002‧‧‧filter

2004‧‧‧Wiring via

2006‧‧‧Socket

FIG. 1 is a schematic diagram of a front-end cross-section of a polymer-based dielectric frame defining a socket, wherein the frame has embedded via posts, wherein at least one via post includes a film capacitor.

2 is a schematic cross-sectional view of a polymer-based dielectric frame defining a socket, wherein the frame has embedded via posts, at least one embedded via post includes a film capacitor, and the socket includes an embedded device, the embedded device In this case, additional capacitors are included, in which the via column with the embedded capacitor in the frame and the embedded capacitor in the socket are connected by a characteristic layer including an inductor.

In FIGS. 3-7, for clarity, the vias and features are shown without surrounding dielectric.

FIG. 3 is a schematic diagram of an inductor in a feature layer and an adjacent via column standing on a capacitor connected in series with the inductor in a via column layer.

4 is a schematic diagram of an inductor via in a via layer connected in series with a capacitor at the base of a via post.

5 is a schematic diagram of a pair of inductors, one in a feature layer and another in a via layer, connected in series with each other and the base of a via post in the via layer of the via inductor is connected in series with a capacitor .

6 is a schematic diagram of an inductor in a feature layer, the inductor and a capacitor being connected in parallel, the capacitor and the inductor passing through a via post and in the second upper feature layer or outside the multilayer structure The leads are connected together.

7 is a schematic diagram of an inductor in a feature layer, which is connected in series with an inductance via and in parallel with a capacitor, the capacitor and the inductance via pass through the second The leads in the feature layer or outside the multilayer structure are connected together.

8 is a schematic cross-sectional view of a via post layer connected between feature layers, where one via post shown has an integrated inductor.

FIG. 9 shows a flowchart of a method of manufacturing a substrate with an embedded filter, which is composed of a capacitor and an inductor.

9(i)-FIG. 9(xxxi) are a series of schematic cross-sectional views showing a method of manufacturing a substrate with an embedded filter composed of capacitors and inductors, each of which corresponds to the corresponding one in FIG. 9 step.

FIG. 10 is a flowchart showing a method of the filter of FIG. 8 to form a terminal.

10(xxxii)-FIG. 10(xL) are a series of schematic cross-sectional views showing a method of forming a terminal of a substrate with an embedded filter, and each figure corresponds to the corresponding step of FIG. 10.

11 is a schematic diagram of a frame having three layers of coils composed of elongated through-holes embedded therein and including embedded capacitors, showing the flexibility of manufacturing technology and how it can be used to manufacture embedded filters and the like .

Fig. 12a is a three-dimensional schematic diagram of a basic LC low-pass filter.

Figure 12b shows how the basic LC low-pass filter of Figure 12a can be represented as an LC filter circuit.

12c is a schematic cross-sectional view of the basic LC low-pass filter of FIG. 12a.

FIG. 12d is a schematic cross-sectional view of the basic LC low-pass filter of FIG. 12a, where the size of the capacitor matches the via post above it, which defines the effective capacitance of the capacitor.

12e is a schematic cross-sectional view of the basic LC low-pass filter of FIG. 12a, which The upper middle electrode is the via column above it.

Fig. 13a is a three-dimensional schematic diagram of a basic LC high-pass filter.

Figure 13b shows how the basic LC high-pass filter of Figure 13a can be represented as an LC filter circuit device.

Fig. 14a is a three-dimensional schematic diagram of a basic LC bandpass filter.

Figure 14b shows how the basic LC bandpass filter of Figure 14a can be represented as an LC filter circuit device.

Fig. 15a is a three-dimensional schematic diagram of a basic LC bandpass parallel filter including a capacitor and an inductor.

Figure 15b shows how the basic LC bandpass parallel filter of Figure 15a can be represented as an LC filter circuit device.

Fig. 16a is a three-dimensional schematic diagram of a low-pass parallel-Chebyshev filter; Fig. 16b shows how the low-pass parallel-Chebyshev filter of Fig. 16a can be represented as an LC filter.

17 is a schematic view of a portion of a polymer or composite grid with a chip socket, which also has a straight through hole surrounding the socket.

FIG. 18 is a schematic diagram of a panel used for manufacturing an embedded chip surrounding a through hole, showing how a part of the panel IT IS can have sockets for different types of chips.

Fig. 19 is a schematic view of a portion of the polymer or composite material frame of Fig. 17, with a chip contained in each socket, the chip being held in place by a polymer or composite material such as molding compound.

20 is a schematic cross-sectional view of a portion of the frame, shown in each socket In the embedded chip held by the polymer, the through holes and pads on both sides of the panel are also shown.

21 is a schematic cross-sectional view of a bare chip containing embedded chips.

22 is a schematic cross-sectional view of a package including a pair of dissimilar bare chips in adjacent sockets.

Fig. 23 is a bottom view of the package shown in Fig. 21.

24 is a flowchart showing a method of manufacturing a polymer or composite material panel including an array of through holes.

24(a)-FIG. 24(n) are schematic diagrams of the intermediate sub-structure obtained after each step of flowchart 24.

FIG. 25 is a flow chart of how a drilled-and-fill technique can be used to create plated through holes for a punched socket.

25(a)-25(e) are schematic diagrams of the intermediate substructure obtained after each step of flowchart 25.

Fig. 26 is a plan view of a frame with a filter embedded next to a chip socket.

It should be understood that the drawings are only schematic and are not drawn to scale. Very thin layers may appear very thick. The width of the feature structure may appear to be disproportionate to its length, and so on.

Specifically, it should be noted that, since further miniaturization is desired, an equivalent structure having extremely different spatial arrangements may be provided, and may therefore look different.

For a better understanding of the invention and to show embodiments of the invention, reference is made purely to the drawings.

With specific reference now to the drawings, it must be emphasized that the specific drawings are only examples and for the purpose of schematically discussing the preferred embodiment of the present invention, the reason for providing the drawings is to make sure that the drawings are the most useful and easy to understand the principles of the present invention And concept description. In this regard, no attempt is made to illustrate the structural details of the present invention beyond the level of detail necessary for a basic understanding of the present invention; the description with reference to the accompanying drawings enables those skilled in the art to know how several embodiments of the present invention can be implemented.

In the following, it refers to a socket for embedding a chip. The socket structure includes metal through holes in a dielectric matrix, especially copper through holes in a polymer matrix. The present invention relates to a chip socket with a piezoelectric film, such as a glass fiber reinforced polyacryl Imine, epoxy resin or BT resin (bismaleimide/triazine) or blends thereof.

The socket structure described below also includes a capacitor built within the socket frame. Such capacitors are usually metal-insulator-metal (MIM) capacitors, including a lower metal electrode (which can be gold, titanium or tantalum) and an inorganic dielectric layer (which can be, for example, Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _{1- x} , TiO ₃ , BaTiO ₃ or Al ₂ O ₃ ). The capacitor may include a dedicated upper electrode (often gold, titanium, or tantalum), or a through hole (usually a copper through hole) may be deposited on the capacitor as the upper electrode.

Since the parallel plate capacitor includes a dielectric material sandwiched between electrodes, and the dielectric material is usually a material with an extremely high dielectric constant, the dielectric material used for encapsulation is hereinafter referred to as an encapsulating dielectric to The dielectric of the capacitor is different.

The drawings are illustrative and are not intended to be drawn to scale. In addition, a few vias, a single capacitor and filter are shown, however the socket frame may include multiple capacitors Filters and filters and a large number of through holes. In fact, large arrays of socket frames are commonly co-manufactured.

When drilling and filling techniques are used to manufacture through holes, the through holes generally have a substantially circular cross section because the through holes are manufactured by first drilling laser holes in the dielectric. Because the encapsulating medium is non-uniform and anisotropic and is composed of a polymer matrix as well as inorganic fillers and glass fiber reinforcements, the circular cross-section of the through holes usually has rough edges and may also be slightly deformed to deviate from the true circle. In addition, the drilled and filled through-holes tend to have some inclination and become reverse frusto-conical rather than cylindrical.

Using the "drill-and-fill" method, due to the difficulty of cross-section control and shape, it is impossible to manufacture non-circular through holes. Due to the limitation of laser drilling, the minimum via size can only be about 50-60 microns. These difficulties are described in the background section above, especially related to the depression and/or dome shape due to the copper via filling electroplating process, the inclined shape of the via hole due to the laser drilling process and the roughness of the side wall and the The "routing" mode uses expensive laser drilling machines for slot milling to create trenches in the polymer/glass dielectric resulting in high costs.

In addition to the limitations of laser drilling described above, another limitation of drilling and filling technology is that it is difficult to create through holes of different diameters in the same layer, because when drilling through holes of different sizes and filling metal at the same time When the through holes of different sizes are manufactured at the same time, the filling rate of the via channels is different. Therefore, the typical problem of pits or overfill (dome), which is a feature of the drill-fill technique, is further exacerbated because it is impossible to simultaneously optimize the deposition technique for through holes of different sizes. Therefore, in practical applications, the drill-filled through-holes have a substantially circular cross-section, although sometimes they are somewhat distorted due to the non-uniform characteristics of the substrate, and all the through-holes have the same cross-section.

In addition, it should be noted that in composite dielectrics such as polyimide/glass or epoxy/glass or BT (bismaleimide/triazine)/glass or their and ceramic and/or other filler particles The laser drilled through holes in the blend are actually limited to about 60×10-6m in diameter. Even so, due to the characteristics of the composite material being drilled and the ablation process involved, there are still significant through holes Disadvantages of inclined shapes and rough sidewalls.

As described in US 7,682,972, US 7,669,320 and US 7,635,641 of Hurwitz et al., which are incorporated herein by reference, the features of the photoresist and pattern or panel plating and lamination technology of Zhuhai Yueya Company are for the feature structure There is no practical upper limit for the in-plane diameter.

An alternative manufacturing technique that is more accurate and flexible than the drill-fill technique includes plating both copper via layers and feature layers in patterns developed in the photoresist (pattern plating), or copper plating on the panel and then selective etching Remove excess material. Both methods leave upright via columns and upright features. These upstanding devices can then be encapsulated by a piezoelectric layer on top of them, usually by covering the upstanding features and via posts with a dielectric prepreg and then curing the resin of the prepreg.

Utilizing the flexibility of bottom-up technology including electroplating in patterned photoresist followed by lamination (or panel plating, selective etching and lamination), a wide range of via shapes and sizes can be cost-effectively manufactured . In addition, through holes of different shapes and sizes can be manufactured in the same layer. This is particularly advantageous in the case of using a copper pattern plating method, first depositing a metal seed layer, then depositing a photoresist material and developing a smooth and straight non-inclined trench in it, which can then be patterned on the exposed seed layer Plating deposits copper in these trenches for filling. Compared with the method of drilling and filling through holes, the through hole column technology can form trenches in the photoresist layer to be filled to obtain fewer copper holes with fewer pits and fewer domes. Deposited on copper Then, the photoresist is stripped, the technology seed layer is removed, and a permanent polymer-glass composite encapsulation material is applied on and around it. The resulting "via conductor" structure can use the process flow described in US 7,682,972, US 7,669,320, and US 7,635,641 of Hurwitz et al.

Another feature of the bottom-up electroplating technique that uses photoresist to make through holes by electroplating may be smaller than the via holes made by the drill-fill technique. Currently, the diameter of the smallest drilled through hole is about 60 microns. The electroplating technology using photoresist can achieve a resolution better than 50 microns, and even as small as 25 microns. Connecting ICs to such substrates is challenging. One flip chip connection method is to provide a copper pad flush with the surface of the dielectric. This method is described in US 13/9142,652 by the inventor.

In addition to through-hole conductors and features, it has been found that passive devices such as capacitors and filters can also be fabricated within the structure. This includes through-hole column technology, using electroplating, PVD and encapsulation technologies to manufacture capacitors and filters.

Referring to FIG. 1, a polymer-based dielectric frame 1 defining a socket 2 is shown in a schematic diagram, in which the front portion of the frame 1 is cut off. The frame 1 has embedded through-hole pillars 5, 6, 7, and at least one of the through-hole pillars 5 includes a film capacitor 6. The via posts made by electroplating do not have to be circular, and can extend in one in-plane direction. One via post shown is an elongated via post 7, which extends in the X-Y plane and can be used as an inductor.

2 is a schematic cross-sectional view of the polymer-based dielectric frame 1 shown in FIG. 1 defining a socket 2, but wherein the socket 2 includes one or more embedded devices, in this case additional capacitors 8, 9, wherein the frame 1. The via post 5 with an embedded metal insulator metal (MIM) capacitor 6 is connected to the embedded capacitors 8 and 9 in the socket 2 through the characteristic structures 11 and 12 of the characteristic layer. The embedded capacitor 9 can be manufactured on an insulating substrate 14 such as silicon (Si), silicon dioxide (SiO ₂ ), glass, AlN, α-alumina or c-plane alumina (sapphire). In addition, a second feature layer is deposited on the filled socket 2 including the inductor 13. The additional conventional via post 4 shown in FIG. 1 is not included in FIG. 2, or at least not in the position shown in FIG. However, it should be understood that the frame 1 of the present invention may include one or more conventional via posts 4, via posts 5 standing on the capacitor 6, and inductive via posts 7.

Both the MIM capacitor in the through hole 5 of the frame 1 and the MIM capacitors 8 and 9 embedded in the socket may include a lower metal electrode and an inorganic dielectric layer, wherein, for example, the lower metal electrode may be gold, tantalum or titanium, inorganic dielectric The electric layer may be Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ or α-Al ₂ O ₃ .

The capacitor may include a dedicated upper electrode, usually gold, tantalum or titanium, or a through hole 5 which is usually copper may be deposited on the dielectric 6 and itself serves as the upper electrode. Similarly, the embedded capacitors 8, 9 embedded in the frame may include gold, tantalum or titanium electrodes and an inorganic dielectric, which may be Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO _3, BaTiO ₃ or Al ₂ O ₃ . The embedded capacitors 8, 9 can be manufactured on an inorganic substrate such as c-plane alumina (sapphire).

The combination of capacitor and inductor can be used as a filter to protect the chip from fluctuating current and noise. For RF communications such as WIFI, Bluetooth, etc., filters are of particular importance. The filter can be used to isolate part of the circuit from other devices to prevent interference.

Referring to FIG. 3, a schematic diagram of the inductor 40 in the feature layer and the adjacent via post 42 connected in series with the inductor 40 in the via post layer standing on the capacitor 44 is shown. For clarity, the surrounding encapsulating dielectric material is not shown. Only metal structures and capacitors are shown. The structure of FIG. 3 may be made of copper, where the capacitor 44 includes a dielectric material such as Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO _3, BaTiO ₃ or Al ₂ O ₃ , and usually has electrodes of tantalum or other precious metals . Generally, the via post 42 will be encapsulated in a polymer dielectric, which may include fillers and may be manufactured using woven fiber prepreg. The characteristic layer including the inductor 40 may be deposited first while the capacitor 44 and the via post 42 are stacked thereon. A polymer-based dielectric material may be laminated on the feature structure 40 and the via post 42, which may be a polymer film or a woven fiber prepreg. Alternatively, the via post 42 and the capacitor 44 may be fabricated and a polymer dielectric laminated, and then the inductor 40 may be deposited thereon in the feature layer, or the inductor 40 may be deposited underneath as shown, without layering The pressure is turned into a surface trace, such as the inductor 13 of FIG. 2, or it can be laminated later or together with another via layer, not shown in the figure. Therefore, the inductor 40 may be included in the feature layer as part of the frame (1, FIG. 1) or in the surface layer above or below the frame (1, FIG. 1), such as the component 13 of FIG. Furthermore, with continued reference to FIG. 2, if the cavity 2 is filled outside the frame 1 and after the devices 8 and 9 are embedded in the polymer dielectric 10 such as molding compound or prepreg, the inductor 40 (13) may be partially deposited in On the filled cavity.

It should be understood that the feature layer is very thin, usually about 10 microns thick. However, the via layer can be much thicker than this. FIG. 4 is a schematic diagram of an inductor via 56 extending in series with the inductor 54 at the base of the via post 52 in the via layer. The capacitor 54 and the inductor via 56 are connected by a trace 58 deposited in the feature layer or on the surface of the frame, in FIG. 4 the trace 58 is on the bottom surface. The thickness of the inductor via hole 56 may be about 30 micrometers and has different characteristics from the characteristic layer inductor 40 of FIG. 3. Generally, the inductor via 40 is a high-Q inductor having an inductance ranging from about 0.1 nH to about 10 nH. As shown, the via post inductor 56 can be a fairly compact Coil. However, it should be understood that the coil may be formed in the frame 1 and completely surround the socket 2 of the frame 1, or may be embedded in one side of the frame beside the socket.

Referring to FIG. 5, it should be understood that the filter may be manufactured to include a pair of inductors, that is, the first inductor 60 in the feature layer and the second inductor 66 in the via column layer. Referring again to FIGS. 1 and 2, the first inductor 60 may be surface-mounted on the frame 1, or as the inductor 13 in FIG. 2, on the filling frame above the cavity 2 filled with the polymer 10, or may It is deposited in the layer including the features 11 and 12 or actually below the filled cavity in the subsequent layer. The filter shown in FIG. 5 includes a second inductor 66 in a via layer, which also includes a conventional via post. The second inductor 66 can be completely manufactured within the frame 1 surrounding the cavity 2. The inductors 60, 66 may be connected in series with each other and the base of the via post 62 within the via layer of the via inductor 66 is connected to the capacitor 64.

It should be understood that for certain filtering applications, devices need to be connected in parallel.

For example, FIG. 6 is a schematic diagram of the inductor 70 in the feature layer, which is connected in parallel with the capacitor 74 at the base of the via post 71. Capacitor 74 and inductor 70 are connected together by via posts 71, 72 and traces 78 in the second upper feature layer or outside the multilayer structure. Referring again to FIG. 2, the through-hole columns 71, 72 will be positioned within the frame 1. The inductor 70 and the joint 78 can be deposited in the features of the frame, if the frame is a multi-layer, or can be deposited by electroplating into the photoresist filling the outside of the filled frame 1 of FIG. 2 and can be spread over the filler 10 of the cavity 2 (Or below).

7 is a schematic diagram of a characteristic layer (of frame 1) or an inductor 88 (deposited on frame 1 and may be deposited on a filled cavity 2, such as inductor 13 of FIG. 2), with the remaining inductance vias 86 connected in series , As shown in the through holes 7 of FIGS. 1 and 2, and in parallel with the capacitor 84. Capacitor 84 and the inductor 86 are connected together by a trace 88, which is in the second (as shown above) feature layer of the frame or on the outside of the frame 1 (which can span the cavity 2).

Referring to FIG. 8, a cross-sectional view of a substrate 21 (eg, frame 1 of FIG. 1) is shown, including a layer of parallel plate capacitor 20 composed of a layer 22 of dielectric material sandwiched between a copper feature layer 24 and a copper pillar 26. Optionally, a dielectric layer 22 is deposited on the copper feature layer 24, and then copper pillars 26 are grown from the dielectric layer 22. The dielectric material can be, for example, Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ or Al ₂ O ₃ , which can be deposited by physical vapor deposition methods such as sputtering or chemical vapor deposition .

In order to obtain high-quality capacitors, the dielectric material may include Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ or Al ₂ O ₃ that can be deposited by physical vapor deposition, and may also include pre- or An aluminum layer deposited subsequently, which can be deposited by sputtering next to the dielectric ceramic. After optional aluminum deposition, the structure can be heated in the presence of oxygen in a furnace or oven or exposed to far infrared radiation. In this way, aluminum is converted into alumina (Al ₂ O ₃ ) in situ. Because the density of Al ₂ O ₃ is lower than that of aluminum, it covers the ceramic layer and seals the defects after the ceramic layer, thereby ensuring a high dielectric constant and preventing leakage.

Copper pillars 26, 28, 30, 32 are encapsulated in encapsulating dielectric material 34. When the copper pillars 26, 28, 30, 32 are made into through-hole pillars by electroplating (or panel plating and etching) after photoresist and subsequent lamination, the encapsulating dielectric material 34 can be pre-treated as a glass fiber reinforced polymer resin For dipping applications, laminated on copper pillars 26, 28, 30, 32.

Using an inverted pattern or panel plating, one of the plurality of copper pillars 28, 32 may be an extended inductance via pillar, such as the inductance via pillar 7 of FIGS. 1 and 2.

The copper feature layer 24 may have a thickness of about 15 microns with a tolerance of about +-5 microns. each Each via column layer generally has a width of about 40 microns, but can range from about 20 microns to 80 microns. The outer feature layers 24, 38 that can be used as terminal pads also generally have a width of about 15 microns, but can range from about 10 microns to 25 microns.

As is well known, the capacitance value of a capacitor is determined by the dielectric constant of the dielectric layer multiplied by the surface area of the capacitor (ie, the area of the via post 26) divided by the thickness of the dielectric layer 22.

For the simple single layer capacitor 20 of FIG. 8, the thickness of the dielectric material 22 and its deposition method can be optimized. The capacitance value is a property of the dielectric constant of the dielectric material 22 and the area of the metal electrode, where the area of the metal electrode is the cross-sectional area of the copper pillar 26.

In a typical embodiment, noble metal electrodes (usually made of tantalum, but optionally made of gold or platinum) are applied on both sides of the dielectric layer. Therefore, the capacitor is introduced into the via layer at the base of the via post. Keeping the thickness and characteristics of the dielectric layer unchanged, the via post defines the upper electrode, which defines the capacitance value and can be used to fine-tune the capacitance value.

As will be explained in detail below, even if tantalum electrodes are used, depositing carefully sized vias can achieve plasma etching of capacitor electrodes and dielectric layers, leaving only selective etching by removing tantalum and tantalum oxide without damaging copper For example, capacitors etched by hydrogen fluoride or oxygen. In addition, because the via post may be formed by electroplating, the via post does not have to be cylindrical, and may have a rectangular or other cross-section status quo.

Referring to FIGS. 8 and 9(i) to 9(xxxi), a method of manufacturing a thin film capacitor embedded in a polymer dielectric under a via post is specifically shown. It should be understood that the illustrated method can be used to co-deposit an array of via columns including thin film capacitors in the frame. Conventional substantially cylindrical via posts (such as via post 4 of FIG. 1) and inductive via posts (such as inductive via post 7 of FIG. 1) can be deposited in the same via layer. However, in order to keep the drawings concise, Other via columns that may be involved in the following description.

The capacitor 248 shown in FIG. 9(xx) has dedicated electrodes of different materials, usually noble metals such as gold, gold, or tantalum. Tantalum is usually used because it is cheaper than gold and gold. However, in an alternative configuration, the upper electrode may be a via post 232 plated thereon.

First, the carrier 210 is obtained-step 9(i). The carrier 210 is usually a sacrificial copper substrate. In some embodiments, it may be a copper carrier and a quick release film attached to copper.

A barrier layer 212 is deposited on the copper carrier 210-step 9(ii). The barrier metal layer 212 may be made of nickel, gold, tin, lead, palladium, silver, and combinations thereof. In some embodiments, the thickness of the barrier metal layer ranges from 1 micron to 10 microns. Generally, the barrier layer 212 includes nickel. The thin nickel barrier layer 212 may be deposited by a physical vapor deposition process or by a chemical deposition process, usually sputtered or electroplated onto the copper carrier 210. To speed up the process, the barrier layer 212 may be electroplated. In order to ensure planarity and a smooth surface, planarization may be performed subsequently-step 9(iii) (FIG. 9(iii) is the same as FIG. 9(ii), for example, by chemical mechanical polishing (CMP)).

Next, a thin layer of copper 214 may be deposited onto the barrier layer 212-step 9 (iv). The thickness of the copper layer 214 is usually a few microns, and can be manufactured by sputtering or by electroplating.

Next, the first electrode 216 is deposited-step 9(v). For example, the first electrode 216 may be made of tantalum by sputtering.

Then, a dielectric layer 218 is deposited-step 9(vi). For high-performance capacitors, the dielectric layer 218 must be kept as thin as possible, without risking failure of charge leakage. There are a variety of candidate materials that can be used. These materials include Ta ₂ O _5, BaO ₄ SrTi and TiO ₂ , which can be deposited by sputtering, for example. Generally, the thickness of the dielectric layer 218 ranges from 0.1 to 0.3 microns.

The second electrode 220 can now be deposited-step 9 (vii). For example, the second electrode 220 may be made of tantalum by sputtering.

In a variant method, the second precious metal electrode 220 is not applied. Instead, a copper via is directly deposited on the dielectric, and its coverage area defines the upper electrode of the capacitor, thereby defining the effective area and capacitance value of the capacitor.

However, this method is difficult to fabricate a thin dielectric layer of Ta ₂ O _5, BaO ₄ SrTi, or TiO ₂ that does not have the defect that may cause charge leakage. To overcome this problem, in some embodiments, an aluminum layer (not shown) is deposited before or after the deposition of Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ layers (optional step) 9(v)b or optional step 9(vi)b-see Figure 9), and by heating in an oxygen atmosphere, the aluminum layer is oxidized into high dielectric ceramic alumina ((Al ₂ O ₃ ). Oxidation Aluminum has a lower density than aluminum and expands into adjacent voids. In this way, defects can be serviced and continuous thin dielectric separation electrodes can be ensured.

In the main process, another copper layer 222 is deposited on the second electrode 220-step 9 (viii). The other copper layer 222 may be deposited by a method such as sputtering or electroplating. This other copper layer 222 may be deposited into the patterned photoresist by panel plating, and the photoresist pattern may be manufactured by printing and etching to provide, for example, pads, conductors, and inductors. A photoresist layer 208 may be applied under the copper carrier 210, and a second photoresist layer 224 is applied over another copper layer 222 and developed into a pattern-step 9 (ix).

The area on the other copper layer 222 that is not protected by the patterned photoresist 224 is etched away-step 9(x). Wet etching can be used. For example, the unpatterned photolithography on another copper layer 222 One method for the glue 224 to protect the etch away includes exposing the sacrificial substrate to a warmed ammonium hydroxide solution. As an alternative, copper chloride or wet ferric chloride etching can also be used.

The exposed electrode layers 216, 220 and the dielectric layer 218 can be removed by dry etching using a plasma etching process-step 9 (xi). For example, hydrogen fluoride and oxygen plasma etching can be used to etch TiO ₂ or Ta ₂ O ₅ , and hydrogen fluoride and argon plasma etching can be used to etch BaO ₄ SrTi (BST). The typical concentration ratio of CF ₄ :O ₂ ranges from 50:50 to 95:5, where 95 is the concentration of CF ₄ . A typical concentration ratio of CF ₄ :Ar can be any ratio between 50:50 and 5:95, where 95 is the concentration of argon.

In a variant method, as described above, the upper electrode 220 is not deposited. Instead, copper vias are made directly on the dielectric material. Whether using a template or a laser-patterned photoresist can accurately control the cross-sectional size and shape of the through hole, which is used as an upper electrode and defines the capacitance value of the capacitor, because the capacitance value and the effectiveness of the via electrode The area is proportional.

In the main process, the patterned photoresist 224 is then stripped-step 9 (xii), usually as the second photoresist layer 208. However, since the second photoresist layer 208 is briefly replaced by a similar photoresist layer 228-it can be retained instead.

A copper seed layer 226 is deposited on and around the capacitor and the exposed copper layer 214-step 9 (xiii). To facilitate adhesion, a first titanium seed layer can be deposited first.

Now referring to FIG. 9(xiv) of different scales, another photoresist layer 228 is applied to protect the copper substrate (assuming the layer 208 shown in FIG. 9(ix) is removed), deposited and patterned on the seed layer 226 A thick layer of photoresist 230 is deposited (step 9 (xiv)). The copper interconnect 232 is electroplated in the pattern produced by the photoresist 230-step 9 (xv).

Next, strip the photoresist layer 228 (208), 230-step 9 (xvii), by This exposes the capacitor 248, which is short-circuited by the seed layer 226, and the copper via posts 232 are interconnected.

Now, the seed layer 226 is etched away-step 9 (xvii), and rapid etching is performed to minimize damage to the copper layer 214 and the via layer 232, but ensure that the copper layer 214 and the copper via 232 are separated from each other by the capacitor 248.

This method can have many variations. For example, referring to FIG. 9 (xviii), before laminating the polymer-based dielectric material 234 on the copper substrate and the via hole, the structure can be subjected to plasma etching. The plasma etching method used is copper-resistant etching, but tantalum and oxide Titanium is easily etched, such as a mixture of hydrogen fluoride and oxygen-step 9 (xviii). This reduces the size of the capacitor 348 to the size of the via post 232. Because the via post 232 is made by electroplating in photoresist, this provides a possibility of manufacturing high-precision almost any size and shape, and the shape can be square or rectangular, not just round, to make the stack The density can be higher. Removal of excess capacitor material makes possible a high packing density between components.

Then, by laminating a layer of polymer-based dielectric material 234 on the copper substrate and the via hole, the capacitor 348 or the capacitor 248 is embedded in the polymer-based dielectric material 234-step 9 (xix). The polymer-based dielectric material 234 is usually polyimide, epoxy resin, or BT (bismaleimide/triazine) or a blend thereof, and may be reinforced with glass fiber. In some embodiments, a prepreg impregnated with a woven fiber mat by a polymer resin may be used. The polymer matrix may include an inorganic particulate filler, usually having an average particle size of 0.5 to 30 microns, and the polymer generally includes 15 wt% to 30 wt% of particles.

Although sometimes referred to as a dielectric, the polymer-based dielectric material 234 has a dielectric constant that is significantly lower than the dielectric layer 218 of the capacitor 248, which is usually a more exotic material such as Ta ₂ O ₅ or BaO ₄ SrTi or TiO ₂ Etc.

Then, the cured polymer-based dielectric material 234 is thinned and planarized—step 9 (xx), for example, by chemical mechanical polishing (CMP), thereby exposing the end of the copper via 232. Next, another copper seed layer 236 is deposited on the ends of the polymer-based dielectric material 234 and the copper via 232-step 9 (xxi). Applying a photoresist layer 238 on the seed layer 236 patterns the photoresist layer 238-step 9 (xxii). Then another copper layer 240 is electroplated in the pattern-step 9 (xxiii).

The photoresist layer 238 can now be stripped-step 9 (xxiv).

At this stage, the lower copper layer 214 is connected to the upper copper layer 240 via the copper interconnect 232 via the capacitor 248 embedded in the copper interconnect 232.

Another photoresist layer 242 can be deposited and patterned-step 9 (xxv), and copper vias 244 can be plated in the pattern-step 9 (xxvi).

The photoresist layer 242 may be stripped, leaving upright copper vias 244-step 9 (xxvii), and then the copper seed layer 236-step 9 (xxviii) is etched away. The copper seed layer can be removed by dry plasma etching or short time etching using, for example, copper chloride or ammonium chloride solution.

Referring to FIG. 9 (xxix), the dielectric material 234 may be laminated on the upright via 244.

The copper carrier 210 can now be etched away, generally using copper chloride or ammonium chloride solution-step 9 (xxx), using a barrier layer 212 (usually nickel) as an etch stop layer.

Then, the barrier layer 212 can be removed using a suitable etching technique such as plasma etching or using a special chemical etchant-step 9 (xxxi). For example, to etch away nickel without removing copper, a mixture of nitric acid and hydrogen peroxide can be used. Other alternatives to dissolved nickel that can be used include hydrochloric acid + hydrogen peroxide, hot concentrated sulfuric acid, and ferric chloride acidified with hydrochloric acid (III).

Next, the polymer layer 246 is thinned and planarized-step 9 (xxxii) to expose the end of the copper via 244. Grinding, polishing, or combined chemical mechanical polishing (CMP) can be used.

So far, it has been shown how the advanced high-performance capacitor 248 can be embedded in the composite structure 250, which includes a copper via layer containing copper vias 232 standing on the film capacitor 248, but, as As shown in FIG. 1, it may further include an inductance via 7 and a conventional via post 4.

If the frame 1 includes a single through-hole layer, after step 9 (xx), a cavity 2 (FIG. 1) is punched out in the frame, and components (such as 8 and 9 in FIG. 2) are positioned in the frame 1 and utilized The polymer-based dielectric material 10 embeds it, and the polymer-based dielectric material 10 may be a fiber-reinforced polymer filler or applied as a woven fiber preform.

In this case, the feature layer 240 and the upper via layer 244 may be deposited on the filled frame, which is smoothed by CMP and processed into a substrate for further lamination.

In addition, the frame may include a feature layer 240, perhaps a second via layer 244, and even other layers embedded in the polymer-based dielectric matrix 234, 246. Then, the cavity can be punched or cut in the multi-layer frame.

Since the in-plane shape of the capacitor plate and dielectric is determined by the patterned photoresist, it should be recognized that the capacitor can be made in almost any shape. Generally, the capacitor is square or rectangular, but it can also be round, or indeed it can be almost any other shape. The capacitor may have one layer, two layers, three layers or more layers. The thickness of the dielectric can be carefully controlled, so the capacitor manufactured by this method can be customized to have Basically any capacitance value in a wide range, and the capacitance value can be accurately controlled and optimized for a specific operating frequency.

It should also be noted that the through-hole 244 is not limited to a simple cylindrical through-hole column because it is not manufactured by drill-fill technology. By using electroplating in the pattern of the photoresist 242, the through hole 244 may also have substantially any shape and size. Because the via 244 may be a wide-ranging wire in the via layer, the via 244 may be an inductor, and may be a high-Q inductor having an inductance value of about 0.1 nH to about 10 nH.

It should be understood that the combination of capacitor 248 and inductor 244 can provide an RF filter.

Referring to step 10 (xxxiii) to step 10 (xL) and the corresponding figures (xxxiii) to 10 (xL), a method for manufacturing a filter port is explained below.

It should be understood that such ports can be deposited on the frame 1, but are usually deposited on the structure, which includes the frame 1 and the filled cavity 2 surrounded by the frame 1, and the embedded components 8, 9 and usually in two Additional layer on the side.

Referring to step 10 (xxxiii), a titanium seed layer 252 is now sputtered on the exposed ends of the substrate 246 and copper (inductor) vias 244. Referring to step 10 (xxxiv), a copper layer 254 is sputtered on the titanium layer 252.

Referring to step 10 (xxxv), photoresist layers 256, 258 are applied on both sides of the composite structure 250 and patterned. Referring to step 10 (xxxvi), copper 260, 262 is plated in the patterned photoresist layer 256, 258 to create a port.

Referring to step 10 (xxxvii), the photoresist layers 256, 258 are now stripped away, leaving upright copper ports 260, 262. Referring to step 10 (xxxviii), the titanium layer 252 and the copper layer 254 are etched away. (During this process, the copper pads 260, 262 will be slightly damaged).

The cavity thus formed can be filled with solder mask 264-step 10 (xxxix), and protecting copper with ENEPIG 266-step 10 (xL) or other suitable terminal technology.

As described above, using the preferred via post technique, electroplated vias deposited in photoresist and then laminated can have a wide range of shapes and sizes. In addition, the frame may include 2 or more via layers separated by pads.

Referring to FIG. 11, this flexibility enables the embedding of copper coils 1200, usually including via posts, embedded in the dielectric frame 1202 surrounding the cavity 1204. Merely by way of example, the illustrated coil 1200 has three extended via pillar layers 1206, 1207, 1208, which may be deposited on the feature layer. The layers 1206, 1207, 1208 are connected together by vertical devices 1209, 1210. The vertical devices 1209, 1210 may be via posts or feature layers or via posts on the feature layers.

The capacitor 1250 may be fabricated under or in the inductor, usually at the base of the via post 1209. The method of manufacturing the capacitor has been described above with reference to FIGS. 8 and 9. In practice, the copper via-pillar coil 1200 generally includes elongated via-pillars connected together by a feature layer or elongated vias connected by a via-pillar. In general, it is necessary to build layers of alternating via columns and feature layers and coils.

By combining capacitors and inductors, filters can be provided. Examples of filters are shown in Figures 12-16. It should be understood that any of these filters or the like can be manufactured within the framework of a chip socket and combined with an embedded chip to provide an embedded circuit that includes a chip and a filter. The substrate may include more than two sockets for more than two chips, such as processor chips and memory chips. In addition, certain layers can be fabricated on embedded chips For example, capacitors or inductors that can be deposited in the feature layer on the chip.

Referring to FIG. 12a, the three-dimensional view shows the structure of FIG. 10(xL), FIG. 12b is an equivalent circuit diagram, and FIG. 12c is a schematic plan view of the structure of FIG. 10(xL). It should be understood that the essence of the resulting structure Above is a basic LC low-pass filter 300 with four ports P1, P2, P3, P4, capacitor C and inductor L.

Referring to FIG. 12d, in a variant manufacturing technique using the plasma etching step shown in FIG. 9 (xviii), the coverage area of the via V2 defines the capacitance value and size of the capacitor C2, wherein the excess material is etched by plasma Etch away. Therefore, FIG. 12d is a schematic cross-section equivalent to the basic LC low-pass filter of FIG. 12a, wherein the via post V2 defines the dimensions of the capacitor electrode and the dielectric layer, as in the structure of FIGS. 3-7.

Fig. 12e is a schematic cross section of another basic LC low-pass filter of Fig. 12a, in which the upper electrode of the capacitor C3 is a via post V3 instead of the upper electrode where noble metal is first deposited. In the manufacture of this structure, care must be taken to remove all copper seed layers from the dielectric.

It should be understood that the techniques detailed in Figures 9 and 9(i) to 9(xxxii) and 10(xxxiii) to 10(xL) can be used to create filter circuits with different characteristics over a wide range . As shown in FIG. 2, many of these circuits may include capacitors 8, 9 embedded in the cavity 2 or protect active devices embedded in the cavity 2.

For example, referring to FIGS. 13a and 13b, a basic LC high-pass filter can be manufactured. Referring to FIGS. 14a and 14b, a basic LC series bandpass filter can be manufactured, as with reference to FIGS. 15a and 15b, a basic LC parallel bandpass filter can be manufactured. Referring to FIGS. 16a and 16b, with appropriate modification schemes, after necessary modification, a low-pass parallel-Chebyshev filter can be manufactured.

Although a single filter has been described, it should be understood that in practice, a large array of such filters is co-manufactured on a large board, which can then be singulated. Other devices can be manufactured together with the filter. The filter 260 may be surface mounted on the substrate or embedded in the substrate by depositing other feature layers and via layers around it.

As described below, in some embodiments, the aforementioned filter may be embedded in a substrate and a hole is formed in the substrate to form a socket for accommodating a chip, such as a processor chip or a memory chip, to achieve manufacturing of a fully embedded RF circuit, It may include, for example, a processor and a filter.

In general, although the advantages of embedding to improve integration are obvious, it should be understood that embedded devices have inherent shortcomings, that is, as long as any part has an error, the device and its embedded structure must be discarded. Sometimes, diagnosing the path cause of a problem may be difficult because the devices in it cannot be separated and tested separately. However, due to the demand for expensive areas on the substrate surface and the general trend of miniaturization, passive devices such as embedded filters and active devices such as processors and memories have significant advantages.

One feature of the present invention is that passive devices such as filters can be manufactured as stand-alone products for surface mounting. However, once optimized, this process can be integrated into the manufacturing process of the substrate to embed such devices.

It should be understood that the capacitance value of the capacitor depends on the electrode plate area, the thickness of the dielectric and its dielectric constant. Generally, the capacitor of the RF filter has a capacitance value between about 5 pF and about 1 pF. Using the technique described in this article, the capacitance value can be controlled within a narrow range, such as 9~12pF, or even 10~11pF.

The inductor of the present invention may have an inductance range of nano-henry. 0.2nH ~300nH, but usually 1nH ~ about 10nH.

The inductance of these inductors can be controlled within a narrow range, such as about 4nH to about 8nH, or even when the required range is less than 1 nanoHenry, that is, about 5nH to about 6nH.

As described above, a substrate with embedded passive devices can be manufactured. Using techniques described more fully below, active devices such as chips can be surface mounted on such a substrate or embedded in a socket of the substrate. Embodiments of the present invention propose a method of manufacturing embedded passive devices in a frame surrounding a socket, and then a chip, such as a memory chip or a processor chip, can be embedded in the socket.

Such a frame may be arranged in a large frame surrounding the socket array. Each socket in the array can be the same and used to house the same chip. Alternatively, the array may include different sockets with different embedded passive devices in some or all of the frames surrounding the socket. For example, the array may include alternating sockets for storing and processing chips. The socket may also accommodate chips including passive devices such as capacitors or filters. Both passive and active devices can be embedded in the socket. For example, a multi-socket frame may include one or more sockets for passive devices and one or more sockets for active devices such as memory chips or processor chips. For ease of manufacturing, such a chip can be deposited into a socket by a robot, and then held in place by pouring a polymer dielectric around it, which may include fiber-reinforced materials. In some cases, the chip can be held in place by laminating a polymer film thereon.

All methods for connecting the chip and the interposer are costly. Both wire bonding and flip chip technology are costly and disconnection can cause failures. Embedding chips instead of surface mounting can reduce manufacturing costs and improve reliability and yield.

The following describes techniques for manufacturing sockets and embedding chips in such sockets.

Referring to FIG. 17, there is shown a portion of an array 1010 of chip sockets 1012 defined by a frame that frames a polymer matrix 1016 and an array of metal vias 1014 passing through the polymer matrix frame 1016.

The array 1010 may be part of an array panel including chip sockets 1012, each socket being surrounded and defined by a polymer matrix frame 1018 including a grid of copper vias 1014 through the polymer 1016 of the polymer matrix frame 1018. The polymer matrix 1016 generally includes glass fiber reinforced materials, and is most typically made of resin impregnated woven fiber prepreg.

Therefore, each chip socket 1012 is surrounded by a frame 1018 of a polymer matrix 1016, and a plurality of copper vias passing through the frame 1018 are arranged around the socket 1012'.

The frame 1018 may be made of a polymer and applied as a polymer sheet, or it may be a glass fiber-reinforced polymer and applied as a prepreg. More details can be found below with reference to FIGS. 22 and 23, where the manufacturing method is discussed.

Referring to FIG. 18, the panel 1020 of the applicant Zhuhai Yueya is generally divided into a 2×2 array of blocks 1021, 1022, 1023, 1024, the blocks being separated from each other by a main frame including a horizontal bar 1025 and a vertical bar 1026 And frame 1027. These squares include an array of chip sockets 1012-FIG. 17. Assuming a 5mm x 5mm chip socket and Zhuhai Yueya's 21" x 25" panel, this manufacturing technology enables the packaging of 10,000 chips on each panel. On the contrary, it should be noted that the manufacturing of chip packages on the largest 12” wafer currently used in the industry only enables the processing of 2500 chips at a time. The economies of scale on large panels using Zhuhai Yueya technology will make Amazing.

However, the panel suitable for this technology can be changed in size. Usually, the panel is between about 12" x 12" and 24" x 30". Some standard sizes currently in use are 20" x 16", 20.3" x 16.5" and 24.7" x 20.5".

Not all squares of the panel 1020 need to have chip sockets 1012 of the same size. For example, in the schematic diagram of FIG. 18, the chip socket 1028 in the upper right block 1022 is larger than the chip sockets 1029 in the other blocks 1021, 1023, and 1024. In addition, not only one or more blocks 1022 can be used to accommodate different size sockets of different size chips, but also any sub-array of any size can be used to manufacture any specific chip package, so despite the large production volume, a small amount of small quantities can be manufactured Chip packaging, to achieve simultaneous processing of different chip packages for different specific customers, or to make different packages for different customers. Accordingly, the panel 1020 may include at least one area 1022 having a first set of size sockets 1028 for accommodating chips of the first type and a second area 1021 having a second set of size sockets 1029 for accommodating chips of the second type.

As described above with reference to FIG. 17, each chip socket 1012 (1028, 1029, FIG. 18) is surrounded by the polymer frame 1018 and in each square (1021, 1022, 1023, 1024-FIG. 18), the socket 1028 (1029 ) Is positioned.

Referring to FIG. 19, a chip 1035 may be positioned in each socket 1012, and the space around the chip 1035 may be filled with a polymer 1036 or a polymer-based composite material, which may or may not be polymerized with the frame 1016 used to manufacture The same polymer. For example, it can be a molding compound. In some embodiments, the matrix of the filler polymer 1036 and the matrix of the frame 1016 may use similar polymers, but have different reinforcing fibers. For example, the frame may include reinforcing fibers, and the polymer 1036 used as a filler for the socket may be fiber-free.

A typical chip size may be about 1.5 mm x 1.5 mm, at most about 31 mm x 31 mm, and the socket size is slightly larger to accommodate a predetermined chip and have a gap. The thickness of the interposer frame must be at least equal to the depth of the chip, preferably 10 microns to 100 microns. Generally, the depth of the frame is the chip thickness + 20 microns.

Since the chip 1035 is embedded in the socket 1012, each individual chip is surrounded by the frame 1038 having a through hole 1014 passing therethrough and arranged around the edge of each chip.

Using Zhuhai Yueya's technology, whether it is pattern plating or panel plating and then selective etching, the via 1014 can be fabricated as a via post and then laminated with a dielectric material that uses a polymer film or in order to increase stability A prepreg that includes woven glass fiber bundles in a polymer matrix is used. In one embodiment, the dielectric material is Hitachi 705G. In another embodiment, MGC 832 NXA NSFLCA is used. In the third embodiment, Sumitomo GT-K can be used. In another embodiment, Sumitomo LAZ-4785 series membranes are used. In another embodiment, Sumitomo LAZ-6785 series is used. Alternative materials include, for example, Taiyo HBI and Zaristo-125.

As an alternative, the through hole can be manufactured using a method commonly known as drill-fill technology. First, a polymer or fiber-reinforced polymer matrix is manufactured, and then it is drilled after curing, by mechanical drilling or by laser drilling. Then, the hole can be filled with copper by electroplating.

However, the use of through-hole column technology rather than drilling and filling technology to produce through-holes has many advantages. In the through-hole column technology, because all the through-holes can be manufactured at the same time, the through-hole column technology is much faster than the drilling and filling technology of drilling alone. In addition, the drilled through holes are basically cylindrical Shaped, while the via post may have any shape. In practice, all drill-filled through-holes have the same diameter (within tolerance), while the through-hole columns can have different shapes and sizes. Moreover, in order to enhance the rigidity, it is preferred that the polymer matrix is fiber reinforced, usually reinforced with glass fiber woven bundles. When the fibers in the polymer prepreg are applied to an upright through-hole column and cured, the through-hole column is characterized by having smooth and vertical sides. However, drilling and filling through holes usually has some taper when drilling composite materials; through holes usually have rough surfaces, resulting in stray inductance that causes noise.

Generally, the width of the through hole 1014 is in the range of 40 microns to 500 microns. If it is cylindrical, as required by drill-fill technology and as is common in through-hole column technology, each through hole may have a diameter of 25 microns to 500 microns.

With further reference to FIG. 19, after having a polymer matrix frame 1016 with embedded through holes, the socket 1012 may be manufactured by CNC or stamping. Alternatively, using panel plating or pattern plating, sacrificial copper blocks may be deposited. If the copper via post 1014 is selectively shielded, for example using photoresist, the sacrificial copper block can be etched away to form the socket 1012.

There are through holes 1014 in the frame 1038 around each socket 1012. The socket array polymer frame 1038 can be used to create single or multiple chip packages, including multi-chip packages and laminated multi-layer chip packages, such as a "PoP" array on package .

Once the chip 1035 is positioned in the socket 1012, it can be fixed in place using a polymer 1036 such as molding compound, dry film, or prepreg.

Referring to FIG. 20, copper wiring layers 1042 and 1043 may be manufactured on one side or both sides of the frame 1040 in which the chip 1035 is embedded. Generally, the chip 1035 is a flip chip and is connected to the pad 1043 that is fanned out beyond the edge of the chip 1035. Using the through hole 1014, the The pad 1042 allows another chip layer or the like for the PoP package to be connected. Essentially, it should be understood that the upper and lower pads 1042, 1043 enable the lamination of additional via posts and wiring layers to create more complex structures.

The cutting tool 1045 is shown. It should be understood that the array of packaged chips 1035 on the panel 1040 can be easily cut into a single chip 1048, as shown in FIG. 21.

Referring to FIG. 22, in some embodiments, adjacent chip sockets may have different sizes and shapes, including different sizes and/or different shapes. For example, the processor chip 1035 may be positioned in one socket and connected to the memory chip 1055 positioned in an adjacent socket. When the array is diced, adjacent sockets can be held together. Therefore, a package may include more than one chip, and may include different chips, which may include passive filter chips, but it should be noted that the above-mentioned techniques for manufacturing capacitors and filters can be used as part of the framework And joint manufacturing.

The pads 1042, 1043 may be connected to the chip through a ball grid array BGA or a contact grid array LGA. In the current state of the art, the length of the via post may be about 130 microns. When the thickness of the chips 1035, 1055 is greater than about 130 microns, it may be necessary to stack another through hole on top of one through hole. Techniques for stacking vias are known, especially discussed in the co-pending applications of Hewlitz et al. USSN 13/482099 and USSN 13/483185.

Referring to FIG. 23, a chip package 1048, a chip 1055 included in the polymer frame 1016 is shown from below, so that the chip 1055 is surrounded by the frame 1016, and a through hole 1014 is provided through the frame 1016 around the periphery of the chip 1055. The chip is positioned in the socket and held in place by the second polymer 1036. The frame 1016 is usually made of fiber reinforced prepreg to Guarantee stability. The second polymer 1036 may also be a prepreg, but may also be a polymer film or molding compound. Generally, as shown, the through holes 1014 are simple cylindrical holes, but they may have different shapes and sizes. A part of the ball grid array of solder balls 1057 on the chip 1055 is connected to the through hole 1014 through the pad 1043 in a fan-out configuration. As shown, there may be additional solder balls directly connected to the substrate under the chip. In some embodiments, for communication and data processing, at least one via is a coaxial via. In other embodiments, at least one via is a transmission line. For example, a technique for manufacturing coaxial vias is given in co-pending application US 13/483185. For example, a technique for manufacturing transmission lines is provided in US 13/483234.

In addition to providing contacts for chip stacking, vias 1014 surrounding the chip can be used to isolate the chip from its surrounding environment, thereby providing Faraday shielding. Such shielding vias can be connected to the pads so that the shielding vias on the chip interconnect and provide shielding for the chip.

There can be more than one row of through holes around the chip, and the inner row can be used to send signals and the outer row can be used for shielding. The outer row can be connected to a solid copper block fabricated on the chip, and thus can be used as a heat sink to dissipate the heat generated by the chip. Different chips can be packaged in this way. It should be particularly noted that one or more through-holes may be extended inductors, and capacitors may be co-manufactured and embedded into the frame so that the inductor and capacitor together provide a filter.

The embedded chip technology using the frame with through holes described herein is particularly suitable for analog processing because the contacts are short and the number of contacts per chip is relatively small.

It should be understood that the technology described herein is not limited to packaging IC chips. In some embodiments, the chip includes a device selected from fuses, capacitors, inductors, and filters. The manufacturing of inductors is described in the co-pending application USSN 13/962316 of Helwitz et al. And filter technology.

24 and 24(a) to 24(l), a method of manufacturing a chip socket array surrounded by an organic matrix frame includes the following steps: obtaining a sacrificial carrier 1080-24(a).

Optionally, a copper seed layer 1082-24(b) is applied on the copper carrier 1080. A resist layer 1084-24(c) is applied on the seed layer 1082, which is usually composed of nickel and is usually deposited by a physical vapor method such as sputtering. As an alternative, it can also be deposited by electroplating or electroless plating, for example. Other candidate materials include tantalum, tungsten, titanium, titanium-tungsten alloy, tin, lead, tin-lead alloy, all of these materials can be sputtered, and tin and lead can also be electroplated or chemically plated, the thickness of the barrier metal layer is usually It is 0.1~1 microns. (Each candidate barrier material is subsequently removed using appropriate solvent or plasma etching conditions). After applying the barrier layer, another copper seed layer 1086-24(d) is applied. The thickness of the copper seed layer is usually about 0.2 to 5 microns.

Steps 24(b) to 24(d) are preferred to ensure that the barrier layer adheres well to the substrate, good adhesion and growth of the vias, and enables subsequent removal of the substrate by etching without damaging the vias. Although the best results include these steps, these steps are optional and one or more steps may not be used.

Then a photoresist layer 1088 is applied-step 24(e), FIG. 24(e), which is patterned to have a copper via pattern-22(f). Then, copper 1090-24(g) is plated into the pattern, and then the photoresist layer 1088-24(h) is stripped. Upright copper vias 1090-24(i) are laminated with a polymer dielectric 1092, which can be a fiber-reinforced polymer matrix prepreg. The laminated via array is thinned and planarized to expose the end of the copper via-24(j). Then remove the carrier.

Optionally and preferably, the planarized polymer dielectric-24(k) with exposed copper vias ends is protected by applying a resist material 1094, such as a photoresist or The dielectric film, and then the copper carrier 1080-24(l) is removed. Generally, the carrier is a copper carrier 1080, which is removed by dissolving copper. Ammonium hydroxide or copper chloride can be used to dissolve the copper.

Then, the barrier layer-24(m) can be etched away, and then the etch protection layer 1094-step 24(n) can be removed.

Although not described in this article, it should be understood that upright copper vias can be fabricated by panel plating and selective etching of excess copper to retain the vias. In fact, the socket can alternatively be manufactured by selectively etching away a part of the copper panel while shielding the through hole.

As described above, it should be understood that the one or more through holes 1090 may be the improved through holes 5 shown in FIG. 1, which include the capacitor 6. In addition, one or more through holes may be the inductor 7 in FIG. 1.

Although the via-pillar technique is preferred, if only a simple via 1090 is required instead of the modified via 5 in FIG. 1 which includes the capacitor 6 or the inductor via 7 in FIG. 1, then only a simple cylindrical shape is required Drilling and filling techniques can also be used for through holes.

Referring to FIGS. 25 and 25(a) to 25(e), in another variation method, a carrier-25(a) composed of a copper clad laminate (CCL) 1100 is obtained. The thickness of the CCL is from a dozen microns to hundreds of microns. A typical thickness is 150 microns. Drill holes 1102-25(b) through the CCL. The hole 1102 may have a diameter of dozens of microns to hundreds of microns. Typically, the diameter of the hole is 150 microns.

Next, the through holes are plated to create plated through holes 1104-25(c).

Then, the copper-clad laminate 1100 is ground or etched to remove the surface copper layers 1106, 1108 to obtain a laminate 1110-25(d) having plated through-hole (Pth) copper vias 1104.

Then, using CNC or stamping, the laminate is manufactured to accommodate the chip Socket 1112-25(e).

Referring to FIG. 26, a plan view of a frame 2000 having an embedded filter 2002 and a plurality of wiring vias 2004 therein is shown. The frame may include a socket 2006 for accommodating a chip such as a processor chip or a memory chip. Such a frame 2000 can be made as part of a large array, such as those shown in FIGS. 17-19. The frame 2000 as shown includes a socket 2006 for receiving a single chip. However, it should be understood that the frame may include two or more sockets for accommodating two or more chips. This socket 2006 can be used to embed a processor chip, a memory chip or a passive chip, and a filter and the like are embedded in the passive chip.

In this specification, it has been described in detail how inductors and capacitors can be manufactured as passive devices embedded in an organic substrate. This combination of capacitor and inductor can provide a filter. This specification then continues to explain how polymer frames with embedded vias can be manufactured and how they can be used as sockets for embedded active devices. The combination of these technologies enables the manufacture of packages that include one or more embedded chips and embedded filters, which are used for extremely small and highly integrated RF devices, including active and passive devices.

The above description is only illustrative. It should be understood that the present invention can have many variations.

Several embodiments of the present invention have been described. However, it should be understood that various modifications can be made without departing from the spirit and scope of the invention. Therefore, other embodiments fall within the scope of the attached claims.

Those skilled in the art will recognize that the present invention is not limited to what is specifically illustrated and described above. Moreover, the scope of the present invention is defined by the appended claims, including combinations and sub-combinations of the various technical features described above, as well as changes and improvements thereof. After reading the foregoing description, the staff will anticipate such combinations, changes and improvements.

In the request, the term "include" and its variants such as "include", "include", etc. mean that the listed components are included, but generally do not exclude other components.

1‧‧‧Frame

2‧‧‧Socket

3‧‧‧dielectric

4‧‧‧Through hole

5, 6, 7‧‧‧ through-hole column

Claims (61)

A chip socket defined by an organic matrix frame, wherein the organic matrix frame includes at least one through-hole pillar layer, wherein at least one through-hole passing through the frame surrounding the socket includes at least one capacitor, the capacitor includes a lower electrode, a dielectric Layer and upper electrode in contact with the via post. The chip socket according to claim 1, wherein the dielectric of the capacitor includes at least one of Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ , BaO ₄ SrTi, and Al ₂ O ₃ . The chip socket according to claim 1, wherein the lower electrode of the capacitor includes a precious metal. The chip socket according to claim 1, wherein the lower electrode includes a metal selected from gold, platinum, and tantalum. The chip socket according to claim 1, wherein the upper electrode includes a metal selected from gold, platinum, and tantalum. The chip socket according to claim 1, wherein the at least one through hole stands upright on the at least one capacitor. The chip socket according to claim 6, wherein the upper electrode includes the via post. The chip socket according to claim 1, wherein the capacitor has a cross-sectional area defined by a cross-sectional area of the via post, which is carefully controlled to adjust the capacitance of the capacitor. The chip socket according to claim 1, wherein the at least one capacitor has a capacitance of 1.5pF to 300pF. The chip socket according to claim 1, wherein the at least one capacitor has a capacitance of 5pF~15pF. The chip socket according to claim 1, wherein the frame further includes at least one feature layer. The chip socket according to claim 1, wherein at least one electronic device is embedded in the socket and electrically connected to the at least one through hole. The chip socket of claim 1, wherein the at least one electronic device includes a second capacitor. The chip socket according to claim 13, wherein the second capacitor is a discrete device having a metal terminal at at least one end thereof. The chip socket according to claim 13, wherein the second capacitor is a metal-insulator-metal (MIM) capacitor. The chip socket according to claim 13, wherein the metal-insulator-metal (MIM) capacitor includes a material selected from the group consisting of Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ , BaO ₄ SrTi and A dielectric layer composed of at least one dielectric in Al ₂ O ₃ . The chip socket according to claim 13, wherein the lower electrode of the metal-insulator-metal (MIM) capacitor includes a precious metal. The chip socket according to claim 13, wherein the lower electrode includes a metal selected from gold, platinum, and tantalum. The chip socket according to claim 13, wherein the upper electrode of the metal-insulator-metal (MIM) capacitor includes a metal selected from gold, platinum, and tantalum. The chip socket according to claim 13, wherein the metal-insulator-metal (MIM) capacitor is attached to an insulator carrier. The chip socket according to claim 13, wherein the insulator carrier comprises a silicon (Si), SiO ₂ (silicon dioxide), glass, AlN, alumina, and c-plane sapphire Al ₂ O ₃ (0001) At least one. The chip socket according to claim 13, wherein the plate of the metal-insulator-metal (MIM) capacitor is connected to the through hole through the feature layer. The chip socket according to claim 22, wherein the feature layer and the embedded device on one side of the frame include an inductor. The chip socket of claim 22, wherein at least one characteristic structure within the frame, the embedded device within the socket, and the characteristic layer provides a filter. The chip socket according to claim 22, wherein the filter is selected from a basic LC low-pass filter, an LC high-pass filter, an LC series band-pass filter, an LC parallel band-pass filter, and a low-pass parallel-Chebyshev filter. The chip socket according to claim 1, wherein the chip installed in the socket shields electromagnetic radiation by a Faraday cage including a through-hole post in the frame, thereby minimizing electromagnetic interference. The chip socket of claim 26, wherein at least a portion of the via post extends in the X-Y plane. A panel including a plurality of chip sockets according to claim 1 for accommodating a plurality of chips, wherein each chip socket includes a frame, and the frame includes a grid of copper via holes and at least one Capacitors. The panel according to claim 28, wherein the processor chip is embedded in the first socket and the passive chip including at least one capacitor is embedded in the second socket. A panel comprising a plurality of chip sockets according to claim 1 arranged in an array, wherein each chip socket is surrounded by a frame. The panel according to claim 30, wherein at least one processor chip is embedded in at least one chip socket. An array of chip sockets, the array being defined by an organic matrix frame surrounding the chip socket of claim 1, and further comprising a grid of metal through-hole columns passing through the organic matrix frame, wherein at least one metal through-hole The column is connected in series with at least one capacitor. The array of claim 32, wherein the capacitor includes a lower electrode and a dielectric layer, and is combined at the base of at least one via post so that the at least one via post stands upright on the at least one capacitor. The array of claim 32, wherein the at least one via post further includes an upper electrode of the at least one capacitor. The array of claim 32, wherein the frame includes at least one feature layer, wherein at least one inductor is formed in the at least one feature layer. The array of claim 32, wherein the organic matrix frame further comprises glass fiber bundles. The array of claim 32, wherein each via has a width of 25 microns to 500 microns. The array of claim 32, wherein each through hole is cylindrical and has a diameter of 25 to 500 microns. The array of claim 32, wherein the frame surrounding the at least one socket includes alternating via columns and feature layers, and includes at least one via column layer and one feature layer. The array of claim 32, wherein the grid of metal via pillars through the organic matrix frame includes a plurality of via pillar layers. The array of claim 32, wherein the frame surrounding the at least one socket includes a continuous coil of alternating via columns and feature layers spanning at least one via column layer and one feature layer. The array of claim 32, wherein at least one via post comprises an elongate via post. The array of claim 32, wherein a continuous coil of elongated via posts spans multiple via post layers. The array of claim 32, wherein the array includes adjacent chip sockets of different physical dimensions. The array of claim 43, wherein the array includes adjacent chip sockets of different sizes. The array of claim 42, wherein the array includes adjacent chip sockets of different shapes. The array of claim 32, wherein the frame includes at least one feature layer and at least one adjacent via layer, the layer extends in the XY plane and has a height z, wherein the composite electronic structure includes at least one At least one capacitor connected to the inductor, the at least one capacitor including a lower electrode and a dielectric layer, disposed at the bottom of the via layer, sandwiched between at least one feature layer and the via post, so that the at least one via is upright An upper electrode is optionally formed on the at least one capacitor, wherein the via layer is embedded in a polymer matrix, and wherein the at least one inductor is formed on at least one of the first feature layer and the adjacent via layer One of them. The array of claim 32, wherein at least one capacitor and at least one inductor are connected in series. The array of claim 32, wherein the frame includes at least a second feature layer above the via layer, and the at least one capacitor and the at least one inductor are connected in parallel through the feature layer. The array of claim 49, wherein the at least one inductor is fabricated in the feature layer. The array of claim 32, wherein the at least one inductor is a spirally wound coil. The array of claim 32, wherein the inductance of the inductor is at least 0.1 nH. The array of claim 32, wherein the inductance of the inductor is less than 50nH. The array of claim 32, wherein another inductor is fabricated in the via layer. The array of claim 54 wherein the inductance value of the other inductor is at least 0.1 nH. The array of claim 32, wherein the at least one inductor and the at least one capacitor provide a filter selected from a basic LC low-pass filter, an LC high-pass filter, an LC series band-pass filter, LC parallel band-pass filter and low-pass parallel-Chebyshev filter. The panel of claim 30, wherein at least one socket is filled with a chip, the chip includes at least one capacitor in a polymer matrix, the frame and the chip are thinned to expose the end of the through hole, A thin polymer substrate is laid with photoresist on both sides and copper pads are deposited in the photoresist pattern to apply connections and terminals, then the photoresist is stripped and a solder mask is placed between the copper pads, and then protection is applied coating. A panel comprising the array of chip sockets according to claim 32, wherein each panel Surrounded and defined by an organic matrix frame, the organic matrix frame includes a grid of copper through-hole pillars passing through the organic matrix frame, wherein the panel includes at least a socket having a first set of external dimensions for accommodating a first type of chip An area and a second area having a second set of sockets that accommodate chips of the second type, wherein at least one via post includes a film capacitor. The panel of claim 58, wherein at least one via post stands upright on the film capacitor. The panel of claim 58, wherein the at least one via post includes an upper electrode of a thin film capacitor. The panel of claim 58, wherein the panel includes closely adjacent areas having two different socket types.

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