JP6695066B2 - Polymer frame for chips such that the frame comprises at least one via in series with a capacitor - Google Patents

Description

      The present invention is directed to improved chip packaging and, above all, embedded chips in which passive devices such as capacitors and filters are incorporated into the chip package.

      Driven by the ever-increasing demand for miniaturization of increasingly complex electronic components, consumer electronics such as computers and telecommunications devices are becoming more integrated. This has created a need for support structures such as IC substrates and IC interposers that have a high density of multiple conductive layers and vias that are electrically isolated from each other by dielectric materials.

      Typical requirements for this type of support structure are reliability and proper electrical performance, thinness, stiffness, planarity, good heat dissipation and competitive unit cost.

      Of the various approaches to achieving these requirements, one widely realized fabrication technique that creates interconnecting vias between layers is the subsequent filling with a metal, usually copper, deposited therein by a plating technique. For this purpose, a laser is used to drill through the metal layer previously deposited in the subsequently placed dielectric substrate. This approach of creating vias is sometimes referred to as "drill and fill," and the vias created thereby can be referred to as "drill and fill vias."

      There are several drawbacks to the drill and fill via approach. Since each via needs to be drilled separately, processing rates are limited and the cost of fabricating sophisticated multi-via IC substrates and interposers is prohibitive. With large arrays, it is difficult to produce high density, high quality vias with different sizes and shapes in close proximity to each other by drill and fill methodologies. In addition, laser drilled vias have rough sidewalls and tapers inside through the thickness of the dielectric material. This tapering reduces the effective diameter of the via. It may also adversely affect the electrical contact to the previous conductive metal layer, especially at very small via diameters, thereby causing reliability problems. Moreover, the sidewalls are particularly rough where the dielectric to be perforated is a composite material with glass or ceramic fibers in a polymer matrix, and this roughness may create additional stray inductance.

      The process of filling the drilled via holes is usually accomplished by electroplating copper. Electroplating deposition techniques can lead to recess formation, where small craters occur at the end of the via. Alternatively, overfill may occur where the via channel is filled with more copper than it can hold, and a hemispherical top surface that projects above the surrounding material is created. Both recess formation and overfill tend to create difficulties when subsequently stacking vias in stacks as needed when fabricating high density substrates and interposers. Moreover, it will be appreciated that large via channels are difficult to fill uniformly, especially when they are close to smaller vias in the same interconnect layer of an interposer or IC substrate design. That is.

      Although the acceptable size and reliability range has improved over time, the above drawbacks are inherent in drill-and-fill technology and are expected to limit the range of possible via sizes. It is further noted that laser drilling is best for creating round via channels. Although slot-shaped via channels can theoretically be produced by laser milling, in practice the range of geometric shapes that can be produced is somewhat limited, and the vias of a given support structure. Are generally cylindrical and substantially identical.

      Fabrication of vias by drill and fill is expensive, and it is difficult to uniformly and consistently fill via channels thereby created by copper using a relatively cost effective electroplating process.

Laser drilled vias in composite dielectric materials are practically limited to a diameter of 60 × 10 ⁻⁶ m (60 microns), and nonetheless, the composite material drilled as a result of the required removal process. Suffers from a significant tapering shape and rough sidewalls due to the nature of.

In addition to the other limitations of laser drilling described above, when different sized via channels are drilled and then filled with metal to make different sized vias, the via channels are exposed at different speeds. There is an additional limitation of drill-and-fill technology in that it is difficult to create vias of different diameters in the same layer because it is buried.
Thus, the typical problems of recess formation or overfill that characterize drill-and-fill techniques are exacerbated because it is not possible to simultaneously optimize the deposition technique for different sized vias.

      One alternative that overcomes many of the drawbacks of the drill-and-fill approach is to make vias by depositing copper or other metal into the pattern created in photoresist, also known as "pattern plating" technology. Is.

      In pattern plating, the seed layer is deposited first. A layer of photoresist is then deposited thereon and subsequently exposed to create a pattern and selectively removed to create trenches that expose the seed layer. Via posts are created by depositing copper in the photoresist trenches. The remaining photoresist is then removed to leave the upright via posts, the seed layer is etched away, and a dielectric material, typically a polymer-impregnated glass fiber mat, is placed over and around the via posts. To be laminated. Various techniques and processes are then used to planarize the dielectric material, removing a portion of it to expose the ends of the via posts and thereby to ground to thereby build up the next metal layer. Conductive connections may be possible. By repeating this process to build the desired multilayer structure, subsequent layers of metal conductors and via posts can be deposited thereon.

      In an alternative, but closely related technique, hereinafter known as "panel plating", a continuous layer of metal or alloy is deposited on a substrate. A layer of photoresist is deposited on the edge of the substrate and the pattern is developed therein. The pattern of developed photoresist is stripped, selectively exposing the metal beneath it, which can then be etched away. The undeveloped photoresist protects the underlying metal from being etched away, leaving a pattern of upstanding features and vias.

      After stripping the undeveloped photoresist, a dielectric material such as a polymer impregnated glass fiber mat can be laminated around and over the upstanding copper features and / or via posts. After planarization, the metal conductor and subsequent layers of via posts can be deposited thereon by repeating this process to build the desired multilayer structure.

      Via layers created by the pattern plating or panel plating methodologies described above are commonly known as "via pillars" and feature layers of copper origin.

      It will be appreciated that the general impetus for the evolution of microelectronics is directed towards making smaller, thinner, lighter and more powerful products with high reliability. is there. The use of thick, cored interconnects prevents reach for ultra-thin products. To create ever higher density structures in interconnect IC boards or "interposers", ever more and more layers of smaller and smaller connections are required. Indeed, sometimes it is desirable to stack components on the ends of each other.

      If the plated laminated structure is deposited on copper or other suitable sacrificial substrate, the substrate can be etched away, leaving a freestanding coreless layered structure. Additional layers can be deposited on the sides that were previously bonded to the sacrificial substrate, thereby allowing double-sided buildup, which helps minimize warpage and achieve planarity.

      One flexible technique for making high density interconnects is to build patterned or panel-plated multilayer structures consisting of metal vias or features in a dielectric matrix. The metal can be copper and the dielectric can be a fiber reinforced polymer. Generally, polymers with a high glass transition temperature (Tg) are used, such as polyimides. These interconnects can have cores or be coreless and can include cavities for stacking components. They can have odd or even layers. The enabling technology is described in earlier patents issued to Amitec-Advanced Multilayer Interconnect Technologies.

      For example, to Hurwitz et al. (US Pat. No. 6,037,049) describes a method of fabricating free-standing films containing via arrays in a dielectric for use as a precursor in the construction of higher level electronic support structures. .. The method includes fabricating a film of conductive vias in a dielectric surrounding on a sacrificial carrier and separating the film from the sacrificial carrier to form a self-supporting stacked array. Electronic substrates based on this type of free-standing film can be formed by thinning and planarizing the stacking sequence and then terminating the vias. This publication is incorporated herein by reference in its entirety.

      Hurwitz et al. (Patent Document 2) is a method for making an IC support for supporting a first IC die that is connected in series with a second IC die. The support comprises a stack of alternating layers of copper features and vias in an insulating perimeter, a first IC die bondable onto the IC support, and a second IC die within the cavity within the IC support. A method is described that is bondable and the cavities are formed by etching away the copper base and selectively etching away the built-up copper. This publication is incorporated herein by reference in its entirety.

      Hurwitz et al. (Patent Document 3) describes the following steps: (A) selecting a first base layer; and (B) a first etchant barrier on the first base layer. Depositing layers, (C) constructing a first half stack of alternating conductive and insulating layers, the conductive layers being interconnected by vias through the insulating layers, and (D) Applying a second base layer onto the first half stack; (E) applying a protective coating of photoresist to the second base layer; and (F) etching away the first base layer. And (G) removing the protective coating of the photoresist, (H) removing the first etch resistant barrier layer, and (I) a second half stack of alternating conductive and insulating layers. Building a conductive layer interconnected by vias through an insulating layer, the second half-stack having a substantially symmetrical lay-up to the first half-stack, and (J) alternating conductivity. Applying an insulating layer onto the second half stack of layers and insulating layer, (K) removing the second base layer, and (L) exposing the end of the via on the outer surface of the stack. Terminating the substrate with and adding terminations thereto, according to one method of making an electronic substrate. This publication is incorporated herein by reference in its entirety.

      Over time, both drill-and-fill technology and via pillar deposition are expected to enable further miniaturization and fabrication of substrates with higher density vias and features. Nevertheless, perhaps the development of via pillar technology seems to remain competitive.

      The substrate allows the chip to interface with other components. The chip must be bonded to the substrate through an assembly process that provides a reliable electronic connection to enable electronic communication between the chip and the substrate.

      Embedding the chip in the interposer to the outside world allows shrinking the chip package, shortening connections to the outside world, eliminating the die for the substrate assembly process, and potentially improving reliability. To provide cost savings through simpler manufacturing.

      Basically, the concept of embedding active devices such as analog, digital and MEMS chips requires the construction of a chip support structure or substrate with vias around the chip.

      One way to achieve embedded chips is to fabricate the chip support structure onto an array of chips on the wafer where the circuitry of the support structure is larger than the die unit size. This is known as fan-out wafer layer packaging (FOWLP). Despite the increasing size of silicon wafers, expensive material sets and manufacturing processes still limit the wafer diameter size to 12 inches, thereby limiting the number of FOWLP units that can be placed on a wafer. To do. Despite the consideration of 18-inch wafers, the required investment, material set and equipment are still unknown. A limited number of chip support structures that can be processed at one time increase the unit price of FOWLP and in markets that require highly competitive pricing such as the wireless communications, consumer electronics and automotive markets. In contrast, make it too expensive.

      FOWLP further represents a performance constraint, as metal features placed on silicon wafers as fan-out or fan-in circuits are limited to thicknesses of up to a few microns. This creates the challenge of electrical resistance.

      An alternative fabrication route involves cutting the wafer to separate the chips and embedding the chips in a panel of dielectric layers with copper interconnects. It is one advantage of this alternative route that the panel can be much larger, with very many chips embedded in a single process. For example, a 12-inch wafer allows 2,500 FOWLP chips having dimensions of, for example, 5 mm x 5 mm to be processed at one time, while the current panel used by Applicant Zhuhai Access is 25 inches x 21. Inches, allowing 10,000 chips to be processed at one time. Since the cost of processing this kind of panel is significantly cheaper than wafer processing, and the throughput per panel is 4 times higher than the throughput of wafer, the unit price is significantly decreased, thereby opening a new market. it can.

      In both technologies, the line spacing and width of the tracks used in the industry are shrinking over time, with standards on the panel dropping from 15 microns to 10 microns and wafers dropping from 5 microns to 2 microns.

      The advantages of embedding are many. First level assembly costs such as wire bonding, flip chip or SMD (Surface Mount Component) soldering are eliminated. Electrical performance is improved because the die and substrate are seamlessly connected within a single product. The packaged die is thinner and gives an improved form factor, and the upper surface of the embedded die package is a further space saving configuration such as those using stacked die and PoP (Package-on-Package) technology. Is open for other uses, including.

      In both FOWLP and panel-based embedded die technology, the chips are packaged as an array (on a wafer or panel) and, once fabricated, separated by dicing.

      RF (radio frequency) technologies, such as Wifi, Bluetooth, etc., are widely implemented in various devices including cell phones and automobiles.

      In addition to baseband processing and memory chips, RF devices especially require passive components such as various types of capacitors, inductors and filters. Passive devices of this kind can be surface-mounted, but devices of this kind can be embedded in the substrate in order to enable ever more powerful miniaturization and cost savings.

      To Hurwitz, U.S. Pat. No. 5,968,961 discloses a capacitor consisting of a metal electrode and a ceramic or metal oxide dielectric layer, which is embedded in a polymer-based encapsulant material and which is circuited by a via pillar standing above the capacitor. We describe a substrate with a capacitor that can be connected to.

      U.S. Pat. No. 6,037,049 comprises at least one feature layer and at least one adjacent via layer; these layers extend in the XY plane and have a height z, and the structure has at least one At least one capacitor connected in series or in parallel with at least one inductor to provide a filter; at least one capacitor such that at least one via overlies at least one capacitor Sandwiched between at least one feature layer and at least one via in the at least adjacent via layer, and at least one of the first feature layer and the adjacent via layer extends in the XY plane. A composite electronic structure is described, which comprises at least one inductor that

      Hurwitz, US Pat. No. 5,967,697 teaches an array of chip sockets defined by an organic matrix framework surrounding a socket through an organic matrix framework and further comprising a grid of metal vias through the organic matrix framework. The chip is placed in the socket and then held in place by the polymer-based dielectric, which allows the chip to be embedded within the frame.

U.S. Pat. No. 7,682,972, entitled "Tip Multilayer Coreless Support Structures and Methods for Making Them". U.S. Pat. No. 7,669,320, entitled "Coreless Cavity Substrates for Chip Packaging and Their Fabrication". U.S. Pat. No. 7,635,641 entitled "Integrated Circuit Support Structures and Their Fabrication" U.S. Patent Application No. 13 / 962,075, entitled "Thin Film Capacitors Embedded in Polymer Dielectric," filed Aug. 8, 2013. U.S. Patent Application No. 13 / 962,316, entitled "Multilayer Structures and Embedded Features," filed Aug. 8, 2013. U.S. Patent Application No. 14 / 269,884, entitled "Interposer Frame with Polymer Matrix and Method of Making," filed May 5, 2014. U.S. Patent Application No. 13 / 912,652 U.S. Patent Application No. 13 / 482,099 U.S. Patent Application No. 13 / 483,185 U.S. Patent Application No. 13 / 483,234

      The present invention claims priority to (Patent Document 4); (Patent Document 5) and (Patent Document 6).

      A first aspect is a chip socket defined by an organic matrix framework, the organic matrix framework comprising at least one via as a lower electrode, a dielectric layer and a via post through the framework around the socket. A chip socket comprising at least one via pillar layer comprising at least one capacitor with a contacting upper electrode.

Generally, the dielectric of the capacitor _comprises at least one of the group consisting of _{Ta 2 O 5, TiO 2,} Ba x Sr 1-x TiO 3, BaTiO 3 and _Al 2 _{O 3.}

      Generally, the lower electrode of the capacitor comprises a noble metal.

      Optionally, the lower electrode comprises a metal selected from the group consisting of gold, platinum and tantalum.

      In some embodiments, the upper electrode comprises a metal selected from the group consisting of gold, platinum and tantalum.

      Generally, at least one via stands above at least one capacitor.

      Optionally, the upper electrode comprises a via post.

      Preferably, the capacitor has a cross-sectional area defined by the cross-sectional area of the via post that is carefully controlled to adjust the capacitance of the capacitor.

      In some embodiments, at least one capacitor has a capacitance between 1.5 pF and 300 pF.

      In a preferred embodiment, at least one capacitor has a capacitance between 5 pF and 15 pF.

      Optionally, the framework further comprises at least one feature layer.

      Optionally, at least one electronic component is embedded in the socket and electrically coupled to the at least one via.

      Optionally, at least one electronic component comprises a second capacitor.

      In some embodiments, the second capacitor is a discrete component that has metal terminations on at least one end.

      In some implementations, the second capacitor is a metal-insulator-metal (MIM) capacitor.

In some embodiments, a metal - insulator - metal (MIM) dielectric capacitor is comprised of at least one of a group consisting of _{Ta 2 O 5, TiO 2,} Ba x Sr 1-x TiO 3, BaTiO 3 and _Al 2 _{O 3} With layers.

      In some embodiments, the lower electrode of a metal-insulator-metal (MIM) capacitor comprises a noble metal.

      In some embodiments, the lower electrode comprises a metal selected from the group consisting of gold, platinum and tantalum.

      In some embodiments, the metal-insulator-metal (MIM) upper electrode comprises a metal selected from the group consisting of gold, platinum and tantalum.

      Optionally, a metal-insulator-metal (MIM) capacitor is attached to the insulator carrier.

In some embodiments, the insulator carriers silicon (Si), SiO ₂ (silica) comprises glass, AlN, alumina, and c- plane sapphire _Al 2 _O 3 at least one of the group consisting of (0001).

      In some embodiments, a metal-insulator-metal (MIM) capacitor plate is connected to the via by a feature layer.

      Generally, a component embedded within a socket is coupled to at least one via having an embedded capacitor by at least one feature layer.

      Optionally, the system further comprises a feature layer on one side of the frame and the embedded component comprises an inductor.

      Optionally, embedded components in the frame, embedded components in the socket and at least one feature in the feature layer provide a circuit that functions as a filter.

      Optionally, the filter is selected from the group consisting of a basic LC low pass filter, an LC high pass filter, an LC series bandpass filter, an LC parallel bandpass filter and a low pass parallel Chebyshev filter.

      Optionally, the chip mounted in the socket is protected from electromagnetic radiation by a Faraday cage with via posts in the frame, thereby minimizing electromagnetic interference.

      In some implementations, the Faraday cage further comprises a feature layer within the frame.

      A further aspect is a framework comprising a plurality of sockets for receiving a plurality of chips, each socket comprising a frame, and the framework comprising a copper via post gridwork and at least one capacitor. With the goal.

      Optionally, the processor chip is embedded in one socket and the passive chip with at least one capacitor is embedded in the second socket.

      A further aspect is directed to a framework comprising a plurality of chip sockets arranged in an array, each chip socket surrounded by a frame.

      Optionally, at least one processor chip is embedded in at least one socket.

      A further aspect defines a grid of metal via posts defined by an organic matrix framework of a frame surrounding a socket, and wherein at least one metal via post is connected in series with at least one capacitor. The aim is to further provide an array of chip sockets.

      Optionally, the capacitor comprises a bottom electrode and a dielectric layer, and the at least one via pillar is incorporated into the base of the at least one via pillar so as to overlie the at least one capacitor.

      Optionally, at least one via pillar comprises at least one capacitor upper electrode.

      Optionally, the frame comprises at least one feature layer in which at least one inductor is formed in at least one feature layer.

      Generally, the organic matrix framework further comprises a glass fiber bundle.

      Generally, each via ranges from 25 microns to 500 microns wide.

      Generally, each via is cylindrical and has a diameter in the range of 25 microns to 500 microns.

      Generally, the frame around the at least one socket comprises alternating via posts and feature layers, and at least one via post layer and one feature layer.

      Generally, the organic matrix framework comprises multiple layers, and the gridwork comprises multiple via post layers, each pair of successive via post layers being separated by a feature layer.

      In some implementations, the frame around the at least one socket comprises alternating via posts and continuous coils of features spanning at least one via post layer and one feature layer.

      Optionally, at least one via post comprises an elongated via post.

      Optionally, a continuous coil of elongated via posts spans multiple via post layers.

      Optionally, the arrangement comprises adjacent chip sockets of different sizes.

      Optionally, the array comprises adjacent chip sockets of different sizes.

      Optionally, the arrangement comprises adjacent tip sockets of different shapes.

      Optionally, the framework comprises at least one feature layer and at least one adjacent via layer, said layer extending in the XY plane and having a height z, said composite electronic structure comprising at least At least one capacitor coupled to the one inductor, the at least one capacitor having a lower electrode and a dielectric layer, and the at least one via on the at least one capacitor; Embedded in the base of a via layer sandwiched between the at least one feature layer and the via pillar so as to stand and optionally form an upper electrode, the via layer embedded in a polymer matrix, and The at least one inductor is formed in at least one of the first feature layer and the adjacent via layer.

      Optionally, at least one capacitor and at least one inductor are coupled in series.

      Optionally, the frame comprises at least a second feature layer above the via layer, and the at least one capacitor and the at least one inductor are coupled in parallel via the feature layer.

      Optionally, the at least one inductor is fabricated in the feature layer.

      Optionally, the at least one inductor is spirally wound.

      Optionally, the inductance of this inductor is at least 0.1 nH.

      Optionally, the inductance of this inductor is less than 50 nH.

      Optionally, additional inductors are fabricated in the via layer.

      Optionally, the inductance of this further inductor is at least 0.1 nH.

      Optionally, at least one inductor and said at least one capacitor are selected from the group consisting of a basic LC low pass filter, an LC high pass filter, an LC series bandpass filter, an LC parallel bandpass filter and a low pass parallel Chebyshev filter. Bring a filter that will be.

      Optionally, at least one socket contains a chip comprising at least one capacitor in a polymer matrix, and the framework and chip are thinned to expose the ends of the via, and the connections and terminations. Parts are applied by placing a photoresist on each side of the thinned polymer matrix and by depositing a copper pad in the pattern of the photoresist, the photoresist is then stripped, and a solder mask is placed between the copper pads. Then a protective coating is applied.

      A further aspect is a panel comprising an array of chip sockets surrounded and defined by an organic matrix framework each comprising a grid of copper via posts through the organic matrix framework, said panel being of one type At least one region having a socket with a first set of dimensions for receiving a chip of a second type, and a socket with a second set of dimensions for receiving a second type of chip, and A panel having at least one via post comprising a second region containing a thin film capacitor is intended.

      Optionally, the panel causes at least one via post to stand above the thin film capacitor.

      Optionally, at least one via post comprises the upper electrode of the thin film capacitor.

      Optionally, the panel comprises regions in close proximity with two different socket types.

      The combination of a frame with a built-in capacitor around the chip socket allows for more advanced miniaturization and manufacturing for RF (radio frequency) technologies such as Wi-Fi, Bluetooth, which are widely used in mobile phones and automobiles. Brings economy and increased reliability.

      The protective coating can be selected from ENEPIG and organic varnishes.

The term micron or μm refers to micrometer or 10 ⁻⁶ m.

      For a better understanding of the invention and to show how it can be put into practice, reference is now made to the accompanying drawings, by way of example only.

      The details set forth herein with specific reference to the drawings in detail are by way of example only and for purposes of illustrative discussion of preferred embodiments of the invention, as well as of the principles and conceptual aspects of the invention. It is emphasized that it is presented to provide what is believed to be the most useful and easily understood explanation. In this regard, no attempt is made to show the structural details of the invention in more detail than is necessary for a basic understanding of the invention, and the description taken with the drawings sets forth some of the invention's details. It will be clear to the person skilled in the art how the morphology can be embodied as a practical matter. In the attached drawings:

1 is a schematic isometric view with a truncated front surface of a polymer-based dielectric frame defining a socket, the frame having embedded via posts, at least one of which contains a thin film capacitor. FIG. 3 is a schematic cutaway isometric view of a polymer-based dielectric frame defining a socket, the frame having embedded via posts, at least one of which includes a thin film capacitor, and the socket including embedded components, Via pillars, which in this case comprise additional capacitors, and with embedded capacitors in the frame, are connected to the embedded capacitors in the socket by means of a feature layer containing the inductor. FIG. 6 is a schematic perspective view of adjacent via pillars in a via pillar layer overlying an inductor in a feature layer and a capacitor coupled in series with the inductor. Vias and features are shown without surrounding dielectric for clarity. FIG. 6 is a schematic projection view of inductor vias in a via layer connected in series with a capacitor at the base of a via pillar. Vias and features are shown without surrounding dielectric for clarity. FIG. 6 is a schematic projection of a pair of inductors, one in a feature layer and one in a via layer, coupled to a capacitor in series with each other and at the base of a via pillar in the via layer of the via inductor. Vias and features are shown without surrounding dielectric for clarity. FIG. 4 is a schematic projection of an inductor in a feature layer coupled in parallel with a capacitor, where the capacitor and inductor are coupled together by a via pillar and a trace in the second upper feature layer or on the outside of the multilayer structure. Vias and features are shown without surrounding dielectric for clarity. FIG. 7 is a schematic projection of an inductor in a feature layer coupled in series with an inductive via and in parallel with a capacitor, the capacitor and inductor vias coupled together by a trace in a second upper feature layer or on the outside of a multi-layer structure. Has been done. Vias and features are shown without surrounding dielectric for clarity. FIG. 6 is a schematic cross-sectional view through a layer of via posts that are connected between feature layers, with one via post shown having an integrated capacitor. 3 is a flow chart illustrating a process for making a substrate with an embedded filter of capacitors and inductors; 3 is a flow chart illustrating a process for making a substrate with an embedded filter of capacitors and inductors; 3 is a flow chart illustrating a process for making a substrate with an embedded filter of capacitors and inductors; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 10 is a series of schematic cross-sectional illustrations illustrating a process for making a substrate with an embedded filter of capacitors and inductors, each illustration corresponding to a corresponding step in FIG. 9; 9 is a flow diagram illustrating a process for terminating the filter of FIG. 8; 11 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with an embedded filter, each illustration corresponding to a corresponding step in FIG. 10; 11 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with an embedded filter, each illustration corresponding to a corresponding step in FIG. 10; 11 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with an embedded filter, each illustration corresponding to a corresponding step in FIG. 10; 11 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with an embedded filter, each illustration corresponding to a corresponding step in FIG. 10; 11 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with an embedded filter, each illustration corresponding to a corresponding step in FIG. 10; 11 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with an embedded filter, each illustration corresponding to a corresponding step in FIG. 10; 11 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with an embedded filter, each illustration corresponding to a corresponding step in FIG. 10; 11 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with an embedded filter, each illustration corresponding to a corresponding step in FIG. 10; 11 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with an embedded filter, each illustration corresponding to a corresponding step in FIG. 10; FIG. 1 is a schematic view of a frame consisting of elongated vias and having a three-layer coil embedded therein including embedded capacitors, showing the flexibility of the manufacturing process and how it is used to fabricate embedded filters and the like. Indicate what can be done; 3 is a schematic three-dimensional view of a basic LC low pass filter; Figure 12a shows how the basic LC low pass filter of Figure 12a can be represented as an LC filter circuit; 12b is a schematic cross section of the basic LC low pass filter of FIG. 12a; FIG. 12b is a schematic cross section of the basic LC low pass filter of FIG. 12a with the capacitor defining the effective capacitance of the capacitor being dimensioned to the via posts above it; 12a is a schematic cross section of the basic LC low pass filter of FIG. 12a with the top electrode being a via post above it; 3 is a schematic three-dimensional view of a basic LC high pass filter; FIG. 13a shows how the basic LC high pass filter of FIG. 13a can be represented as an LC filter circuit component; FIG. 3 is a schematic three-dimensional view of a basic LC band series filter; FIG. 14a shows how the basic LC band-series filter of FIG. 14a can be represented as an LC filter circuit component; FIG. 3 is a schematic three-dimensional view of a basic LC band-parallel filter with a capacitor and an inductor; Figure 15 shows how the basic LC band-parallel filter of Figure 15a can be represented as an LC filter circuit component; Schematic 3D diagram of low-pass parallel Chebyshev filter, and We show how a low pass parallel Chebyshev filter can be represented as an LC filter. 3 is a schematic illustration of a portion of a polymer or composite grid having a socket therein for the chip and further having through vias around the socket; 1 is a schematic illustration of a panel used to fabricate an embedded chip with peripheral through vias, showing how part of the panel IT IS can have sockets for different types of chips; FIG. 18 is a schematic illustration of a portion of the polymer or composite framework of FIG. 17 with a tip in each socket held in place by a polymer or composite material such as a mold compound; FIG. 6 is a schematic illustration of a cross-section through a portion of the framework showing embedded chips retained within each socket by a polymeric material and further showing through vias and pads on both sides of the panel; 1 is a schematic illustration of a section through a die containing embedded chips; 1 is a schematic illustration of a cross section through a package containing a pair of different dies in adjacent sockets; 22 is a schematic bottom view of a package such as that shown in FIG. 21; 6 is a flow chart showing a manufacturing process for making a polymer or composite panel comprising an array of through vias; Figure 25 is a schematic illustration of an intermediate substructure obtained after each step of Flowchart 24; Figure 25 is a schematic illustration of an intermediate substructure obtained after each step of Flowchart 24; Figure 25 is a schematic illustration of an intermediate substructure obtained after each step of Flowchart 24; Figure 25 is a schematic illustration of an intermediate substructure obtained after each step of Flowchart 24; Figure 25 is a schematic illustration of an intermediate substructure obtained after each step of Flowchart 24; Figure 25 is a schematic illustration of an intermediate substructure obtained after each step of Flowchart 24; Figure 25 is a schematic illustration of an intermediate substructure obtained after each step of Flowchart 24; Figure 25 is a schematic illustration of an intermediate substructure obtained after each step of Flowchart 24; Figure 25 is a schematic illustration of an intermediate substructure obtained after each step of Flowchart 24; Figure 25 is a schematic illustration of an intermediate substructure obtained after each step of Flowchart 24; Figure 25 is a schematic illustration of an intermediate substructure obtained after each step of Flowchart 24; Figure 25 is a schematic illustration of an intermediate substructure obtained after each step of Flowchart 24; Figure 25 is a schematic illustration of an intermediate substructure obtained after each step of Flowchart 24; Figure 25 is a schematic illustration of an intermediate substructure obtained after each step of Flowchart 24; 3 is a flow chart showing how drill fill technology can be used to create plated through holes with stamped sockets; 25 is a schematic illustration of an intermediate substructure obtained after each step of flow chart 24. 25 is a schematic illustration of an intermediate substructure obtained after each step of flow chart 24. 25 is a schematic illustration of an intermediate substructure obtained after each step of flow chart 24. 25 is a schematic illustration of an intermediate substructure obtained after each step of flow chart 24. 25 is a schematic illustration of an intermediate substructure obtained after each step of flow chart 24. FIG. 9 is a plan view of a frame with a filter embedded with a socket for a chip.

      It will be appreciated that the figures are schematic illustrations only and not to scale. Very thin layers may appear thick. The widths of the features may appear out of proportion with their length and the like.

      In particular, it will be noted that the equivalent structures can be arranged to have very different spatial arrangements, and therefore somewhat different, due to the demand for ever smaller strengths. It may look like this.

      In the following description, a socket structure for embedding a chip is considered. The socket structure consists of metal vias in a dielectric matrix, especially copper via pillars in a polymer matrix, such as polyimide, epoxy or BT (Bismaleimide / Triazine) or mixtures thereof, reinforced by glass fibers. ..

The socket structure described below further comprises a capacitor incorporated into the frame of the socket. Capacitors of this kind generally include a lower metal electrode, which may be gold, tantalum or tantalum, and, for example, Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ or Al ₂ O. ₃ is a Metal Insulator Metal (M-I-M) capacitor with an inorganic dielectric layer that can be ₃ . The capacitor may have a dedicated top electrode, which is typically gold, tantalum or tantalum, or a via, typically copper, may be deposited thereover as a top electrode.

      The dielectric material used for encapsulation distinguishes it from the capacitor's dielectric because parallel plate capacitors typically have a dielectric material sandwiched between electrodes, which is a material with a very high dielectric constant. Therefore, it will be referred to as an encapsulating dielectric below.

      The figure is illustrative and no attempt is made to show the scale. In addition, a few vias and individual capacitors and filters are shown, while the socket frame may include some capacitors and filters and multiple vias. In fact, generally a large array of socket frames are manufactured together.

      Where the vias are made by drill and fill techniques, the vias generally have a substantially circular cross section, as they are made by first drilling a laser hole in the dielectric. The circular cross-section of the via is generally rough and slightly rounded from the true-round shape because the encapsulating dielectric is heterogeneous and anisotropic, and consists of a polymer matrix with inorganic filler and glass fiber reinforcement. It may be distorted. In addition, drill and fill vias generally tend to be somewhat tapered and have an inverted frustoconical shape instead of a cylindrical shape.

      Fabricating non-circular vias using the "drill and fill via" approach is prohibited due to cross-section control and shape difficulties. There is also a minimum via size of about 50-60 microns diameter due to laser drilling limitations. These difficulties have been described in detail in the background section above, and among other things, the recess formation and / or hemispherical molding resulting from the copper via fill electroplating process, the vias resulting from the laser drilling process. It is associated with taper shape and sidewall roughness, and the higher cost due to using an expensive laser driller to mill the slots in a "routing" mode that creates grooves in the polymer / glass dielectric.

      In addition to the other limitations of laser drilling described above, when different size via channels are drilled and then simultaneously filled with metal to simultaneously fabricate different size vias, the different via channels are different. There is an additional limitation of the drill-and-fill technique in that it is difficult to create vias of different diameters in the same layer because it fills at speed. Thus, the typical problems of recess formation or overfill (hemispherical formation) that characterize drill-and-fill techniques are exacerbated because it is not possible to simultaneously optimize the deposition technique for different size vias. Therefore, in practical applications, drill-and-fill vias have a substantially circular cross section, and all vias have a substantially similar cross section, although they are sometimes somewhat distorted due to the heterogeneous nature of the substrate. Have.

Furthermore, laser drilled vias in composite dielectric materials such as polyimide / glass or epoxy / glass or BT (bismaleimide / triazine) / glass or ceramics and / or their blends with other filler particles are practical. It is noted that the diameter of the composite material is limited to about 60 × 10 ⁻⁶ m, and as a result, the required removal process results in a significant tapering shape due to the nature of the composite material to be punched, as well as Suffers on rough sidewalls.

      As described in (Patent Document 1), (Patent Document 2) and (Patent Document 3) assigned to Hurwitz et al., Which are incorporated herein, there is no effective upper limit on the in-plane dimension of a feature. That is a feature of Access's photoresist and pattern or panel plating and lamination techniques.

      An alternative, more accurate and more flexible manufacturing technique than drill-and-fill, is to plate both copper via and feature layers in a pattern that is developed in photoresist (pattern plating), or panel-plate copper layers. And then selectively etching away excess material. Both of these routes leave upright via posts and upright features. These upright elements are then typically encapsulated by placing a layer of dielectric prepreg over the upright features and via posts and then curing the resin in the prepreg, thereby laminating the dielectric material thereon. You can

      A wide range of via shapes and sizes can be cost-effective with the flexibility of a bottom-up approach with electroplating to patterned photoresist, followed by lamination (or panel plating, selective etching and lamination) Can be manufactured in. Moreover, different via shapes and sizes can be fabricated in the same layer. A metal seed layer is first deposited, and then a photoresist material is deposited and a smooth, straight, non-tapered groove is developed therein, which is deposited on the exposed seed layer. This can be especially facilitated when a copper pattern plating approach is used, by being able to be subsequently filled by depositing copper in these trenches by pattern plating. In contrast to the drill-and-fill via approach, via post technology allows trenches in the photoresist layer to be filled to obtain hemispherical copper connectors without recesses. After copper deposition, the photoresist is then stripped, the metal seed layer is removed, and a permanent, polymeric glass composite encapsulant material is applied over and around. The "via conductor" structure created in this way can use the process flows described in Hurwitz et al.

      It is a further feature of bottom-up electroplating technology that vias made by electroplating with photoresist can be narrower than vias created by drill and fill. Currently, the narrowest drill and fill vias are about 60 microns. By electroplating with photoresist, a resolution better than 50 microns or even 25 microns can be achieved. It is difficult to connect an IC to this type of substrate. One approach for flip-chip connection is to provide copper pads that are coplanar with the surface of the dielectric. An approach of this kind is described in US Pat.

      In addition to via conductors and features, electroplating, PVD and encapsulation techniques to create capacitors and filters can be used to fabricate passive devices such as capacitors and filters in structures that include via pillar technology. Was found to be.

      Referring to FIG. 1, a polymer-based dielectric frame 1 defining a socket 2 is shown in a schematic isometric view with a cutaway front surface of the frame 1. The frame 1 has embedded via posts 5, 6, 7 and at least one of the via posts 5 contains a thin film capacitor 6. Via posts made by electroplating need not be circular and can extend in one plane direction. The one via post shown is an elongated via post 7 that can extend in the XY plane to act as an inductor.

2 is a schematic cut-away isometric view of a polymer-based dielectric frame 1 defining the socket 2 of FIG. 1, but with the socket 2 having one or more embedded components, in this case an additional capacitor 8 , 9 and with the buried metal insulator metal (MIM) capacitors 6 in the frame 1 therewith are connected to the buried capacitors 8, 9 in the socket 2 by the features 11, 12 of the feature layer. .. The embedded capacitor 9 can be fabricated on an insulating substrate 14 such as silicon (Si), silica (SiO ₂ ), glass, AlN, α-alumina or c-plane alumina (sapphire). In addition, a second feature layer is deposited on the filled socket 2 containing the inductor 13. The additional conventional via posts 4 shown in FIG. 1 are not included in FIG. 2 or at least as shown in FIG. However, it will be appreciated that the frame 1 of the present invention may include one or more of conventional via posts 4, via posts 5 overlying capacitors 6 and inductive via posts 7.

Both the MIM capacitors in the vias 5 in the frame 1 and the MIM capacitors 8, 9 embedded in the sockets are lower metal electrodes, which can be gold, tantalum or tantalum and, for example, Ta ₂ O ₅ , TiO _2. , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ or Al ₂ O ₃ with an inorganic dielectric layer.

The capacitor may comprise a dedicated top electrode, which is typically gold, tantalum or tantalum, or a via 5, typically copper, may be deposited on the dielectric 6 and by itself. It can function as an upper electrode. Similarly, embedded capacitors 8 and 9 are embedded in the frame, gold, tantalum or tantalum electrodes and _{Ta 2 O 5, TiO 2,} Ba x Sr 1-x TiO 3, a BaTiO ₃ or _Al 2 _{O 3} An inorganic dielectric layer can be included. Embedded capacitors 8, 9 of this kind can be manufactured on an inorganic substrate such as c-plane Al ₂ O ₃ (sapphire).

      The combination of capacitors and inductors can act as a filter that protects the chip from wobble currents and noise. Filters are especially important for RF telecommunications such as WIFI, Bluetooth, and so on. Filters can help isolate parts of the circuit from other elements to prevent interference.

Referring to FIG. 3, a schematic perspective view of an inductor 40 in a feature layer and an adjacent via post 42 of a via post layer overlying a capacitor 44 coupled in series with the inductor 40 is shown. For clarity, the surrounding encapsulation dielectric material is not shown. Only metal structures and capacitors are shown. The structure of FIG. 3 can be made of copper, the capacitor 44 comprises a dielectric material such as Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ or Al ₂ O ₃ . And generally has tantalum or another noble metal electrode. In general, the via posts 42 are encapsulated within a polymer dielectric that can include fillers and can be fabricated using braided fiber prepreg. The feature layer containing the inductor 40 may be first deposited with the capacitor 44 and the via pillar 42 built thereon. A polymer-based dielectric material, which can be a polymer film or a knitted fiber prepreg, can be laminated onto the features 40 and via posts 42. Alternatively, via posts 42 and capacitors 44 can be fabricated and laminated with a polymer dielectric, then inductor 40 in the feature layer can be deposited or shown thereon. 2 below, and may be left unlaminated as surface traces, such as inductor 13 in FIG. 2, or subsequently laminated with additional via layers, perhaps not shown. Therefore, the inductor 40 is in a feature layer that is part of the frame (1, FIG. 1) or in a surface layer above or below the frame (1, FIG. 1), such as part 13 of FIG. Can be included. Further, and continuing with reference to FIG. 2, if applied outside the frame 1 and after embedding the components 8 and 9 in a polymer dielectric 10 such as a mold compound or prepreg in the cavity 2. For example, it can be partially deposited over the cavity filled with inductor 40 (13).

      It will be appreciated that the feature layer is very thin, typically about 10 microns. The via layer, however, can be rather thicker. FIG. 4 is a schematic perspective view of an inductor via 56 extending into a via layer connected in series with a capacitor 54 at the base of a via post 52. Capacitor 54 is connected to inductor via 56 by trace 58 deposited in the z-feature layer or on the surface of the frame, in this case on the bottom surface. The inductor via 56 can have a thickness of about 30 microns and has different characteristics than the feature layer inductor 40 of FIG. Generally, the inductor via 40 is a high Q inductor having an inductance ranging from about 0.1 nH to about 10 nH. As shown, via inductor 56 can be a properly tight coil. However, it will be understood that it can be formed in the frame 1 and can be completely wound around the socket 2 of the frame 1, or it can be wound together with the socket. It can be embedded within one side of the frame.

      It will be appreciated with reference to FIG. 5 that a filter can be fabricated that includes a pair of inductors; a first inductor 60 in the feature layer and a second inductor 66 in the via post layer. Is. Referring back to FIGS. 1 and 2, the first inductor 60 is surface mounted onto the frame 1 or onto a frame filled above the cavity 2 that is filled with polymer 10 like the inductor 13 of FIG. It can be done, or it can be deposited in the layer containing features 11 and 12, or indeed in a subsequent layer, below the filled cavity. The filter shown in FIG. 5 includes a second inductor 66 in the via layer that further comprises a regular via post. The second inductor 66 can be completely manufactured in the framework 1 around the cavity 2. The inductors 60, 66 can be coupled to the capacitor 64 in series with each other and at the base of the via posts 62 in the via layers of the via inductor 66.

      It will be appreciated that for some filtering purposes it may be necessary to concatenate the components in parallel.

      For example, FIG. 6 is a schematic projection of inductor 70 in a feature layer coupled in parallel with capacitor 74 at the base of via post 71. Capacitor 74 and inductor 70 are connected together by via posts 71, 72 and a trace 78 in the second, upper feature layer or on the outside of the multi-layer structure. Returning to FIG. 2, the via columns 71 and 72 are arranged in the frame 1. If the frame is multilayer, one or more of the inductor 70 and the connector 78 can be deposited in a feature layer of the frame or span as much as (or below) the filler 10 of the cavity 2. , Can be deposited by electroplating the photoresist on the outside of the filled frame 1 of FIG.

      FIG. 7 shows a feature layer (of frame 1) or (on frame 1 and possibly of FIG. 2) coupled in series with inductive via 86, like via 7 of FIGS. 1 and 2, and in parallel with capacitor 84. FIG. 9 is a schematic projection of inductor 88 in the lower surface layer (deposited on a filled cavity 2 such as inductor 13). Capacitor 84 and inductive via 86 are connected together by a trace 88 in the second (upper side as drawn) feature layer of the frame, or perhaps on the outside of frame 1 spanning cavity 2.

Referring to FIG. 8, through a substrate 21 (such as frame 1 in FIG. 1) that includes a single layer parallel plate capacitor 20 consisting of a layer of dielectric material 22 sandwiched between a copper feature layer 24 and a copper post 26. A cross-sectional view is shown. Optionally, dielectric layer 22 is deposited over copper feature layer 24 and copper posts 26 are then grown over dielectric layer 22. The dielectric material, for example by _{Ta 2 O 5, TiO 2,} Ba x Sr 1-x TiO 3, BaTiO 3 or _Al 2 _{O 3} it can be, and for example, sputtering such as physical vapor deposition process, or a chemical vapor deposition process Can be deposited by.

To obtain a high-quality capacitor dielectric may include a _{Ta 2 O 5, TiO 2,} Ba x Sr 1-x TiO 3, BaTiO 3 or _Al 2 _{O 3} which can be deposited by physical vapor process , And possibly also with a layer of aluminum metal previously or subsequently deposited by sputtering together with a dielectric ceramic. After optional aluminum deposition, the structure can be heated in the presence of oxygen, either in a furnace or oven or by exposure to infrared radiation. The aluminum is thereby converted in situ to aluminum oxide (alumina Al ₂ O ₃ ). Because Al ₂ O ₃ is less dense than aluminum, it spreads and seals defects within the ceramic layer, ensuring a high dielectric constant and preventing leakage.

      The copper posts 26, 28, 30, 32 are encapsulated within an encapsulating dielectric material 34. Where the copper pillars 26, 28, 30, 32 are fabricated as via pillars by electroplating (or by panel plating and etching) into photoresist and then laminated, an encapsulating dielectric material 34 is deposited on the copper pillars 26, 28, 30 ,. It can be applied as a glass fiber reinforced polymer resin prepreg laminated on 32.

      Using a bottom-up pattern or panel plating, one or more of the copper posts 28, 32 can be a wide range of induction via posts, such as the induction via posts 7 of FIGS.

      The copper feature layer 24 can have a thickness of about 15 microns with a tolerance of about + -5 microns. Each via post layer is typically about 40 microns wide, but can be anywhere from 20 microns to 80 microns, for example. The outer feature layers 24, 38, which can be termination pads, are again typically about 15 microns, but can be anywhere from 10 microns to 25 microns, for example.

As is known, the capacitance of the capacitor, (dielectric constant of the dielectric layer) × (surface area of the capacitor) is defined by the [contact area of via posts 26] ÷ (thickness of the dielectric layer 22).

      The simple single layer capacitor of FIG. 8 can be used to optimize the thickness of the dielectric material 22 and its deposition process. Capacitance is a characteristic of the dielectric constant of the dielectric material 22 and in the region of the metal electrodes, which in this case is the cross-sectional area of the copper posts 26.

      In an exemplary embodiment, a noble metal electrode, generally made of tantalum, but optionally gold or platinum, is applied to either side of the dielectric layer. The capacitors are thus incorporated in the via layer at the base of the via pillars. Where the via pillar defines the upper electrode, preserving the thickness and nature of the dielectric layer constant; it can be used to define and fine tune the capacitance.

      As will be discussed in more detail below, even where tantalum electrodes are used, the deposition of carefully sized via pillars allows plasma etch removal of the capacitor electrodes and dielectric layers, removing tantalum and tantalum oxide. Remove but leave the capacitor sandwich only by selective etching that does not harm the copper, such as hydrogen fluoride and oxygen etching. Moreover, because the via post can be formed by electroplating, it need not be cylindrical, but can have a rectangular or other cross-sectional shape.

      With reference to FIGS. 9 and 9 (i) -9 (xxxi), one method of making a thin film capacitor under a via post embedded in a polymer dielectric is shown in more detail. It will be appreciated that the illustrated method can be used to co-deposit an array of via posts including thin film capacitors in a framework. Conventional substantially cylindrical via posts (eg via posts 4 in FIG. 1) and guided via posts (eg guided via posts 7 in FIG. 1) can be deposited in the same via layer. However, to keep the figure simple, additional via posts are not shown and are not associated in the following description.

      The capacitor 248 shown in FIG. 9 (xx) has a dedicated electrode of a different material, typically a noble metal such as gold, platinum or tantalum. Tantalum is commonly used because it is cheaper than gold or platinum. However, in an alternative configuration, the upper electrode can be a via post 232 that is electroplated thereon.

      First, the carrier 210 is procured-step 9 (i). Carrier 210 is typically a sacrificial copper substrate. In some embodiments, it can be a copper carrier with a quick release thin film of copper added to it.

      A barrier layer 212 is deposited on the copper carrier 210-step 9 (ii). The barrier metal layer 212 can be made of nickel, gold, tin, lead, palladium, silver and combinations thereof. In some embodiments, the barrier metal layer has a thickness in the range of 1 micron to 10 microns. Generally, barrier layer 212 comprises nickel. A thin barrier layer 212 of nickel can be deposited by a physical vapor deposition process or by a chemical deposition process, which is typically sputtered or electroplated onto the copper carrier 210. For high speed processing, the barrier layer 212 can be electroplated. To ensure planarity and a smooth surface, it can then be planarized, for example by chemical mechanical polishing (CMP) -step 9 (iii) (FIG. 9 (iii) with FIG. 9 (ii)). Are the same).

      A thin layer of copper 214 is then deposited on the barrier layer 212-step 9 (iv). The thickness of the copper layer 214 is typically a few microns and can be made by sputtering or by electroplating.

      The first electrode 216 is then deposited-step 9 (v). Illustratively, the first electrode 216 may be made of tantalum by sputtering.

The dielectric layer 218 is then deposited-step 9 (vi). For high performance capacitors, the dielectric layer 218 should be kept as thin as possible without risking failure that would allow charge leakage. There are various candidate materials that can be used. These include Ta ₂ O ₅ , BaO ₄ SrTi and TiO ₂ , for example it can be deposited by sputtering. Generally, the thickness of dielectric layer 218 is in the range of 0.1 to 0.3 microns.

      The second electrode 220 can then be deposited-step 9 (vii). As an example, the second electrode 220 can be made of tantalum by sputtering.

      In the deformation process, the second noble electrode 220 is not applied. Rather, copper vias are deposited directly on the dielectric, the footprint of which defines the upper electrode of the capacitor and thus the effective area and capacitance.

Moreover, it is difficult to fabricate thin dielectric layers of Ta ₂ O ₅ , BaO ₄ SrTi or TiO ₂ without defects that might lead to charge leakage. To overcome this problem, the aluminum layer in some embodiments (not shown) is _deposited before or after deposition of the _{Ta 2 O 5, TiO 2,} Ba x Sr 1-x TiO 3, BaTiO 3 layer (See optional step 9 (v) b or optional step 9 (vi) b—see FIG. 9) and exposed to heat in an oxygen environment to cause the aluminum layer to form a high dielectric ceramic alumina (Al ₂ O _{2). 3} ) is oxidized. Alumina is less dense than aluminum and expands into adjacent voids. In this way, it is possible to cure defects and ensure that the continuous thin dielectric separates the electrodes.

      In the main process, a further layer 222 of copper is deposited on the second electrode 220-step 9 (viii). For example, a further layer 222 of copper can be deposited by sputtering or by electroplating. A further copper layer 222 can be deposited on the patterned photoresist by pattern plating and can be produced by printing and etching, for example to provide pads, conductors and inductors. A photoresist layer 208 can be applied under the copper carrier 210, and a second photoresist layer 224 is applied over the further layer 222 of copper and developed into a pattern-step 9 ( ix).

      Areas of the further layer of copper 222 that are not protected by the patterned photoresist 224 are etched away-step 9 (x). Wet etching can be used. By way of illustration, one method of etching away the areas of the further layer of copper 222 that are not protected by the patterned photoresist 224 consists of exposing the sacrificial substrate to a solution of ammonium hydroxide at elevated temperature. Alternatively, a copper chloride or wet iron chloride etch can be used.

The exposed electrode layers 216, 220 and dielectric layer 218 can be removed by dry etching using a plasma etching process-step 9 (xi). For example, hydrogen fluoride and oxygen plasma etching can be used to etch TiO ₂ or Ta ₂ O ₅ , and hydrogen fluoride and argon plasma etching can be used to etch BaO ₄ SrTi (BST). Typical concentration ratios for CF ₄ : O ₂ are in the range between 50:50 and 95: 5, where 95 is the concentration of CF ₄ . A typical concentration ratio for CF ₄ : Ar can be any ratio between 50:50 and 5:95, where 95 is the concentration of Ar.

      In the modified method, no upper electrode 220 is deposited, as described above. Rather, copper vias are fabricated directly on the dielectric material. Patterning the photoresist by a stencil or by a laser allows precise control of the cross-sectional size and shape of the via, which acts as the top electrode and because the capacitance is proportional to the effective area of the via electrode. Specify the capacitance of the capacitor.

      In the main process, the patterned photoresist 224, also typically the second photoresist layer 208, is then stripped-step 9 (xii). However, since the second layer 208 of photoresist will soon be replaced by a similar layer of photoresist 228-it can be retained instead.

      A copper seed layer 226 is deposited in step 9 (xiii) on and around the capacitor and exposed copper layer 214. A first seed layer of titanium can be first deposited to aid adhesion.

      Moving forward to a different scale relative to FIG. 9 (xiv), an additional photoresist layer 228 protects the copper substrate (assuming layer 208 shown in FIG. 9 (xi) has been removed). And a thick photoresist layer 230 is deposited and patterned on the seed layer 226 (step 9 (xiv)). Copper interconnects 232 are electroplated in the pattern created by photoresist 230-step 9 (xv).

      Photoresist 228 (208), 230 is then stripped-step 9 (xvi), thereby exposing capacitor 248, which is shorted by seed layer 226 and copper via post 232 interconnect.

      Seed layer 226 is etched away by a quick etch that minimizes damage to copper layer 214 and via 232, but ensures that copper layer 214 and copper via 232 are insulated from each other by capacitor 248-step 9 (xvii).

      The process is subject to many variations. For example, with reference to FIG. 9 (xviii), prior to stacking the polymer-based dielectric material 234 over the copper substrate and vias, the structure may be a copper resistant but tantalum and titanium oxide susceptible to etching process. It can be plasma etched by plasma etching such as a mixture of hydrogen hydride and oxygen-step 9 (xviii). This reduces the size of the capacitor to that of via post 232. Since the via posts 232 are made by electroplating photoresist, this provides the possibility of being made with precision to virtually any size and shape, and to allow high packing density. , Can be square or rectangular instead of circular. Removing excess capacitor material allows for high packing density between components.

      Capacitor 348 or capacitor 248 is then embedded within polymer-based dielectric material 234 by laminating a layer of polymer-based dielectric material 234 over the copper substrate and vias-step 9 (xix). The polymer-based dielectric material 234 is typically polyimide, epoxy or BT (bismaleimide / triazine) or blends thereof and can be reinforced by glass fibers. In some embodiments, prepregs made of polymeric resin knitted fiber mats can be used. The polymer matrix may include an inorganic particulate filler, which generally has an average particle size of between 0.5 and 30 microns, and the polymer generally comprises between 15% and 30% by weight of particulates. Including.

Although sometimes referred to as a dielectric, the polymer-based dielectric material 234 is generally compared to that of the dielectric layer 218 of the capacitor 248, which is a more exotic material such as Ta ₂ O ₅ or BaO ₄ SrTi or TiO _2. And have a significantly lower dielectric constant.

      The cured polymer-based dielectric material 234 is then thinned-planarized by step 9 (xx), such as chemical mechanical polishing (CMP), thereby exposing the ends of the copper via 232. A further seed layer 236 of copper is then deposited over the polymer-based dielectric material 234 and the ends of the copper vias 232-step 9 (xxi). A photoresist layer 238 is applied over the seed layer 236 and the photoresist layer 238 is patterned-step 9 (xxii). A copper feature layer 240 is electroplated next to the pattern—step 9 (xxiii).

      The photoresist 238 can then be stripped-step 9 (xxiv).

      At this stage, the lower copper layer 214 is connected to the upper copper layer 240 by the copper interconnect 232 via a capacitor 248 embedded within the copper interconnect 232.

      An additional photoresist layer 242 can be deposited and patterned-step 9 (xxv), and copper vias 244 can be electroplated to the pattern-step 9 (xxvi).

      The photoresist 242 can be stripped, leaving the upright copper vias 244-step 9 (xxvii), and the copper seed layer 236 is then etched-step 9 (xviii). The copper seed layer can be removed by dry plasma etching or by short-term etching with eg copper chloride or with ammonium chloride solution.

      With reference to FIG. 9 (xxix), dielectric material 234 can be deposited over the upstanding vias 244.

      The copper carrier 210 can now be etched away, typically using a copper chloride or ammonium chloride solution to do so-step 9 (xxx), a (generally nickel) barrier layer 212. Functions as an etch stop layer.

      The barrier layer 212 can then be removed by a suitable etching technique such as plasma etching or by a particular chemical etchant-step 9 (xxxi). For example, a mixture of nitric acid hydrogen peroxide can be used to etch away nickel without removing copper. Other nickel-dissolving alternatives that can be used include hydrochloric acid + hydrogen peroxide, hot concentrated sulfuric acid and iron (III) chloride acidified with hydrochloric acid.

      Polymer layer 246 is then thinned and planarized—step 9 (xxxii), exposing the ends of copper vias 244. Grinding, polishing or combined chemical mechanical polishing (CMP) can be used.

      So far, it has been shown how an advanced, high performance capacitor 248 can be embedded in a composite structure 250 comprising a copper via layer comprising a copper via 232 overlying a thin film capacitor 248, but , And like those shown in FIG. 1, may further include inductive vias 7 and regular via posts 4.

      Where stage 1 comprises a single via layer, after step 9 (xx), cavity 2 (FIG. 1) is stamped into the frame and components (eg 8 and 9, FIG. 2) are placed in frame 1. Embedded and applied as a woven fiber prepreg with a polymer-based dielectric material 10 which can be a fiber reinforced polymer filler.

      In such a case, the feature layer 240 and the top via layer 244 can be deposited on a filled frame that is smoothly polished using CMP and treated as a substrate for further buildup. ..

      Alternatively, the frame may comprise a feature layer 240 and possibly a second via layer 244 and even additional layers embedded within the polymer-based dielectric matrix 234, 246. The cavities can then be stamped or cut from the multilayer frame.

      It will be appreciated that the capacitor plate and dielectric planar geometry is determined by patterning the photoresist, so that the capacitor can be fabricated in virtually any shape. Generally the capacitors are square or rectangular, but can be circular or have virtually any other shape. Capacitors can have one, two, three or more layers. Since the thickness of the dielectric can be carefully controlled, it is possible to tailor the capacitors made by this process to have virtually any capacitance over a large range, and accurately scale the capacitance. It is possible to control and optimize it for a particular operating frequency.

      It should also be noted that the via 244 is not limited to being a simple cylindrical via post, as it is not manufactured by the drill and fill technique. The vias 244 can also have virtually any shape and size, by making the pattern in the photoresist 242 using electroplating. Because the via 244 can be a wide range of wires in the via layer, the via 244 can be an inductor and a high Q inductor with an inductance ranging from about 0.1 nH to about 10 nH.

      It will be appreciated that the combination of capacitor 248 and inductor 244 enables the provision of an RF filter.

      With reference to steps 10 (xxxiii) to 10 (xL) and the corresponding FIGS. 10 (xxxiii) to 10 (xL), techniques for making the ports of the filter will now be described.

      Ports of this kind can be deposited on the frame 1, but generally around the cavity 2 filled by the buried components 8, 9 and generally additional layers on both sides. It will be appreciated that it will be deposited on a structure containing 1.

      Referring to step 10 (xxxiii), a titanium seed layer 252 is then sputtered onto the exposed ends of the matrix 246 and copper (inductor) vias 244. Referring to step 10 (xxxiv), a copper layer 254 is then sputtered on the titanium layer 252.

      Referring to step 10 (xxxv), a layer of photoresist 256, 258 is placed and patterned on each side of the composite structure 250. Referring to step 10 (xxxvi), copper 260, 262 is electroplated onto patterned photoresist 256, 258 to create ports.

      Referring to step 10 (xxxvii), the layers of photoresist 256, 258 are then stripped, leaving the upstanding copper ports 260, 262. Referring to step 10 (xxxviii), the titanium 252 and copper 254 layers are etched away. (The copper pads 260, 262 are slightly damaged in this process.)

      The dimples thus formed can be filled with a solder mask 264-step 10 (xxxix), and the copper is protected with EEPIG 266 or other suitable termination technique-step 10 (xL).

      As previously mentioned, using the preferred via post technique, electroplated vias deposited in photoresist and then deposited can have a wide range of shapes and sizes. In addition, the frame can include two or more via layers separated by pads.

      With reference to FIG. 11, this flexibility allows a copper coil 1200, typically with via posts, to be embedded within a dielectric frame 1202 around a cavity 1204. For example, the illustrated coil 1200 has three layers of extending via posts 1206, 1207, 1208, and possibly via posts deposited on a feature layer. The layers 1206, 1207, 1208 are connected together by vertical elements 1209, 1210. Vertical elements 1209, 1210 can be via posts or feature layers or via posts on feature layers.

      Capacitor 1250 can be fabricated under or in the inductor, typically at the base of via post 1209. Techniques for making capacitors are described above with reference to FIGS. 8 and 9. As a practical matter, the coil of copper via posts 1200 comprises elongate via posts that are generally connected together by feature layers, or elongate feature layers that are connected by via posts. In general, via pillar layers alternate with feature layers, and coils must be built layer by layer.

      A filter can be provided by combining capacitors and inductors. Examples of filters are shown in Figures 12-16. It will be appreciated that any of these filters or the like can be fabricated in the frame of the chip socket and combined with an embedded chip to provide an embedded circuit containing both the chip and the filter. The substrate may include more than one socket for more than one chip, for example a processor chip and a memory chip. In addition, some layers can be fabricated on the embedded chip, for example capacitors or inductors in the feature layer can be deposited on the chip.

      Understanding with reference to FIG. 12a, which is a three-dimensional representation of the structure of FIG. 10 (xL), FIG. 12b, which is an equivalent circuit diagram, and FIG. 12c, which is a flat schematic view of the structure of FIG. 10 (xL). What will be done is that the structure created in this way is a basic LC low pass filter 300 consisting essentially of four ports, P1, P2, P3, P4, a capacitor C and an inductor L. is there.

      Referring to FIG. 12d, in a modified fabrication technique using the plasma etching step shown in FIG. 9 (xviii), the footprint of via V2 defines the capacitance and size of capacitor C2, where excess material is etched by plasma etching. To be removed. Therefore, 12d is a schematic cross section of a basic LC low pass filter equal to FIG. 12a, where the via pillar V2 defines the size of the electrodes and dielectric layers of the capacitors of the structures of FIGS.

      FIG. 12e is a schematic cross section of yet another basic LC low pass filter of FIG. 12a, where the top electrode of capacitor C3 is a via pillar V3 without first depositing a noble metal top electrode. Care must be taken in the fabrication of this type of structure to remove all of the copper seed layer from the dielectric.

      It will be appreciated that the techniques detailed in FIGS. 9 and 9 (i) to 9 (xxxii) and 10 (xxxiii) to 10 (xL) have very different characteristics. It can be used to create a wide range of filter circuits. Many of these, as shown in FIG. 2, or may include capacitors 8, 9 embedded within the cavity 2 to protect active devices embedded within the cavity 2.

      For example, with reference to Figures 13a and 13b, a basic LC high pass filter can be fabricated. With reference to Figures 14a and 14b, a basic LC series bandpass filter can be fabricated, and similarly with reference to Figures 15a and 15b, a basic LC parallel bandpass filter can be fabricated. With reference to Figures 16a and 16b, with appropriate modification and necessary modifications, a low pass parallel Chebyshev filter can be fabricated.

      Although a single filter was illustrated, it will be understood that, in practice, a huge array of filters of this kind are made together in a large plate that can then be divided. is there. Other components can be made with the filter. The filter 260 can be surface mounted to the substrate or embedded in the substrate by depositing additional features and via layers around it.

      As described below, in some embodiments, a filter as described above can be embedded in a substrate, and a socket allows for the fabrication of a fully embedded RF circuit that can include, for example, a processor and a filter. Can be stamped through a substrate to house a chip, such as a processor chip or memory chip.

      In general, despite the obvious advantages of embedding to improve integration, it will be appreciated that if something goes wrong, the component and structure in which it is embedded must be discarded. , There are inherent drawbacks with embedded components. Sometimes diagnosing the root cause of a problem can be difficult where the components are not isolated and cannot be tested individually. However, due to the high cost (area) requirement on the surface of the substrate and the general trend towards miniaturization, embedding filters and other passive components, as well as active components such as processors and memories. Has significant advantages.

      It is a feature of the invention that filters and other passive components can be made as stand-alone products for surface mounting. However, once optimized, the process can be integrated into the substrate fabrication process to embed components of this type.

      It will be appreciated that the capacitance of a capacitor depends on the electrode plate area, the thickness of the dielectric and its dielectric constant. Generally, capacitors for RF filters have a capacitance between about 5 and about 15 pF. Using the techniques described herein, it is possible to control the capacitance in a narrow range, for example between 9 and 12 pF, and even between 10 and 11 pF.

      The inductor of the present invention can have an inductance in the nanohenry range. For example 0.2 nH to 300 nH, but generally 1 nH to about 10 nH.

      Control the inductance of these inductors in a narrow range, such as having a range of about 4 nH to about 8 nH, or even where needed, for example, less than 1 nanohenry between about 5 nH and about 6 nH. It is possible to

      As mentioned above, the substrate can be made of embedded passive components. Active devices such as chips can be surface-mounted on such substrates, or embedded in sockets within such substrates using the techniques described more fully below. Embodiments of the invention propose to fabricate embedded passive components in a frame around a socket in which a chip such as a memory chip or a processor chip can then be embedded.

      This type of frame can be laid out in a large framework around an array of sockets. Each socket in the array can be identical to accommodate the same chip. Alternatively, the array may consist of different sockets with different embedded passive elements around them in some or all of the frames. For example, the array can include alternating sockets for memory and processing chips. The socket may further accommodate a chip with passive elements such as capacitors or filters. Both passive and active components can be embedded in the socket. For example, a multi-socket frame can include one or more sockets for passive devices and one or more sockets for active devices such as memory chips or processor chips. To facilitate fabrication, this type of chip can be robotically deposited in a socket, and then by injecting a polymer dielectric around it, which can include fiber reinforcements. Can be held in place. In some cases, the chip can be held in place by laminating a polymer film on it.

      All methods of attaching the chip to the interposer are expensive. Wire bonding and flip chip technology are expensive and broken connections result in failure. Embedding chips rather than surface mount can reduce manufacturing costs and improve reliability and yield.

      Techniques for making sockets and for embedding chips in such sockets will now be described.

      Referring to FIG. 17, a portion of an array 1010 of chip sockets 1012 defined by a framework comprising a polymer matrix 1016 and an array of metal vias 1014 through the polymer matrix framework 1016 is shown.

      The array 1010 may be part of a panel comprising an array of chip sockets 1012, each defined by being surrounded by a polymer matrix framework 1018 comprising a grid of copper vias 1014 through a polymer 1016 of the polymer matrix framework 1018. it can. Polymer matrix 1016 generally comprises glass fiber reinforcement and is most commonly made of resin impregnated knitted fiber prepreg.

      Each chip socket 1012 is thus surrounded by a frame 1018 of polymer matrix 1016 with a plurality of copper through vias through a frame 1018 located around the socket 1012 '.

      The frame 1018 can be made of a polymer applied as a polymer sheet or it can be a glass fiber reinforced polymer applied as a prepreg. More details can be found below where the method of fabrication is discussed with reference to FIGS.

      With reference to FIG. 18, Applicant Zhuhai Access's panel 1020 is in a 2x2 array of blocks 1021, 1022, 1023, 1024, which are separated from each other by a main frame generally consisting of horizontal bars 1025, vertical bars 1026 and outer frames 1027. Will be divided. The block comprises an array of chip sockets 1012-FIG. Assuming a 5 mm x 5 mm chip socket and an Access 21 "x 25" panel, this manufacturing method allows 10,000 chips to be packaged on each panel. It should be noted, in contrast, that producing a chip package on a 12-inch wafer, the largest wafer currently used in the industry, allows only 2,500 chips to be processed at one time. It is to be understood that the economies of scale in making large panels using the Zhuhai Access technology will be understood.

      Panels suitable for this technique, however, vary somewhat in size. Generally, the panel is between about 12 inches by 12 inches and about 24 inches by 30 inches. Some standard sizes for current use are 20 inches x 16 inches, 20.3 inches x 16.5 inches and 24.7 inches x 20.5 inches.

      Not all blocks of panel 1020 need to have the same size chip socket 1012 therein. For example, in the schematic illustration of FIG. 18, the tip socket 1028 of the top right block 1022 is larger than the tip sockets 1029 of the other blocks 1021, 1023, 1024. Moreover, one or more blocks 1022 can not only be used in different sized sockets to accommodate different sized chips, but any sub-array of any size will make any particular die package. Can be used to produce small runs of a small number of die packages despite the large throughput, and different die packages can be processed simultaneously for different customers or different. Allows packages to be manufactured for different customers. Thus, the panel 1020 has at least one area 1022 having a socket 1028 with a first set of dimensions for receiving one type of chip and a second set of two for receiving a second type of chip. A second region 1021 having a socket 1029 with dimensions can be provided.

      As described above, with reference to FIG. 17, each chip socket 1012 (1028, 1029 FIG. 18) is surrounded by a polymer frame 1018, and each chip socket 1028 (1029 (1029, 1029, 1024, FIG. 18) is surrounded by a polymer frame 1018. ) Array is arranged.

      Referring to FIG. 19, a chip 1035 can be placed in each socket 1012, and is the space around the chip 1035 a polymer 1036 or the same polymer that is used to make the frame 1016? Or it can be filled with polymer-based composites that may not be the same. It can be, for example, a mold compound. In some embodiments, a matrix of filler polymer 1036 and a frame 1016 that is a similar polymer but with different reinforcing fibers can be used. For example, the frame can include reinforcing fibers, while the polymer 1036 used to fill the socket can be fiber-free.

      Typical die sizes can be anywhere from about 1.5 mm x 1.5 mm to about 31 mm x 31 mm with slightly larger sockets to accommodate the intended dies at a distance. The thickness of the interposer frame must be at least the depth of the die and is preferably 10 to 100 microns. Generally, the frame depth is the die thickness plus an additional 20 microns.

      As a result of the embedding of chips 1035 in sockets 1012, the individual chips are surrounded by a frame 1038 having vias 1014 disposed thereabout around the edge of each die.

      Via 1014 can be fabricated as a via post by pattern plating using Access's via post technology, or by panel plating followed by selective etching, within a polymer film or polymer matrix for added stability. Can be subsequently laminated with a dielectric material using a prepreg consisting of a woven glass fiber bundle. In one embodiment, the dielectric material is Hitachi 705G. In another embodiment, MGC 832 NXA NSFLCA is used. In the third embodiment, Sumitomo GT-K can be used. In another embodiment, Sumitomo LAZ-4785 series film is used. In another embodiment, the Sumitomo LAZ-6785 series is used. For example, alternative materials include Taiyo HBI and Zaristo-125.

      Alternatively, the vias can be made using what is known as drill fill technology. First, a polymer or fiber reinforced polymer matrix is produced, then after curing it is punched by either mechanical drilling or laser drilling. The drill holes can then be filled with copper by electroplating.

      However, there are many advantages in making vias using via posts rather than drill fill technology. With via post technology, via posts are faster than drill-and-fill, while holes are drilled individually, because all vias can be made at the same time. Moreover, the perforated vias are essentially cylindrical, while the via posts can have any shape. As a practical matter, all drill fill vias have the same diameter (within tolerance), while the via posts can have different shapes and sizes. Furthermore, due to the increased stiffness, preferably the polymer matrix is a fiber, which is generally reinforced by a braided bundle of glass fibers. Where the fibers in the polymer prepreg are placed and cured on upstanding via posts, the posts are characterized by smooth vertical sides. However, drill fill vias are generally somewhat tapered, and where the composite is pierced; vias generally have a roughness that results in stray inductance that causes noise.

      Generally, vias 1014 range in width from 40 microns to 500 microns. In the case of a cylinder, each via can have a diameter in the range of 25 microns to 500 microns, as required for drill fills and, as is often the case for via posts, for example.

      With further reference to FIG. 19, after fabricating the polymer matrix framework 1016 with embedded vias, the socket 1012 can be CNC or stamped. Alternatively, either panel plating or pattern plating can be used to deposit the sacrificial copper blocks. If the copper via posts 1014 are selectively shielded, for example using photoresist, this type of sacrificial copper block can be etched away to create sockets 1012.

      The polymer framework of the socket array 1038 with vias 1014 within the frame 1038 around each socket 1012 allows for individual chip packages as well as multi-chip packages and built-up multi-layer chip packages such as package "PoP" arrays on the package. It can be used to create multiple chip packages including.

      Once the chips 1035 are placed in the sockets 1012, they can be fixed in place using a polymer 1036 such as mold compound, dry film or prepreg.

      Referring to FIG. 20, copper routing layers 1042, 1043 can be fabricated on one or both sides of framework 1040 in which chips 1035 are embedded. In general, chip 1035 is flip chip and is connected to pads 1043 that fan out beyond the edges of chip 1035. Thanks to the through vias 1014, the pads 1042 on the upper surface allow connecting additional layers of the chip to PoP packaging and the like. Basically, it will be appreciated that the upper and lower pads 1042, 1043 allow to build additional via posts and routing layers to create more complex structures.

      Dicing tool 1045 is shown. It will be appreciated that the array of chips 1035 packaged in panel 1040 can be easily diced into individual chips 1048 as shown in FIG.

      With reference to FIG. 22, in some implementations, adjacent chip sockets can have different dimensions, including different sizes and / or different shapes. For example, the processor chip 1035 may be arranged in one socket and may be connected to the memory chip 1055 arranged in an adjacent socket. When the array is diced, adjacent sockets can be held together. Thus, the package can include multiple chips and possibly different chips, including passive filter chips, but using the techniques described above to fabricate the capacitors and filters, the framework It will be noted that they can be manufactured together as part.

      The pads 1042 and 1043 can be connected to the chip via a ball grid array BGA or a land grid array LGA. With current state of the art, via posts can be about 130 microns long. Where the chips 1035, 1055 are thicker than about 130 microns, it may be necessary to stack one via over another. Techniques for stacking vias are well known and are discussed, among others, in co-pending US Pat.

      Referring to FIG. 23, a die package 1048 comprising a die 1055 in a polymer frame 1016 is shown from below, wherein the die 1055 is surrounded by the frame 1016 and through vias 1014 are passed around the periphery of the die 1055 through the frame 1016. It is provided. The die is placed in the socket and held in place by the second polymer 1036. Frame 1016 is typically made of fiber reinforced prepreg for stability. The second polymer 1036 can also be a prepreg, but can be a polymer film or mold compound. Generally, as shown, through vias 1014 are simple cylindrical vias, but they can have different shapes and sizes. A portion of the ball grid array of solder balls 1057 on chip 1055 is connected to through via 1014 by pad 1043 in a fan-out configuration. As shown, there can be additional solder balls that are directly connected to the substrate under the chip. For communication and data processing, in some embodiments at least one of the through vias is a coaxial via. In another embodiment, at least one via is a transmission line. For example, a technique for manufacturing coaxial vias is given in co-pending US Pat. Techniques for making transmission lines are shown, for example, in US Pat.

      In addition to providing contacts for chip stacking, through vias 1014 surrounding the chip can be used to isolate the chip from its surroundings and provide a Faraday shield. This type of shield via can be coupled to a pad that interconnects the shield via on the chip and provides a shield to it.

      There can be multiple rows of through vias surrounding the chip, with the inner row used for signals and the outer row used for shielding. The outer row can be connected to a solid copper block fabricated on the chip, which can thereby act as a heat sink to dissipate the heat generated by the chip. Different dies can be packaged in this way. Of particular note is that one or more vias can be a wide range of inductors, as well as capacitors can be made together, and that the inductors and capacitors are embedded within the frame to provide a filter together. Is possible.

      The embedded chip technology with frames having through vias described herein is particularly suitable for analog processing because of the short contacts and the relatively small number of contacts per chip.

      It will be appreciated that the techniques described herein are not limited to packaging IC chips. In some embodiments, the die comprises a component selected from the group consisting of fuses, capacitors, inductors and filters. Techniques for making inductors and filters are described in co-pending US Pat.

24 and 24 (a) to 24 (l), a method of making an array of chip sockets surrounded by an organic matrix framework includes the following steps:
Obtain sacrificial carrier 1080-24 (a).

      Optionally, a copper seed layer 1082 is applied onto copper carrier 1080-24 (b). An etch resistant layer 1084 is applied over the seed layer 1082 at -24 (c), is typically made of nickel, and is typically deposited by a physical vapor process such as sputtering. For example, it can alternatively be deposited by electroplating or electroless plating. Other candidate materials include tantalum, tungsten, titanium, titanium-tungsten alloys, tin, lead, tin-lead alloys, all of which can be sputtered, and tin and lead are further electroplated or It can be electroless plated and the barrier metal layer is typically 0.1 to 1 micron thick. (Each candidate barrier layer material is later removed by suitable solvent or plasma etching conditions). After application of the barrier layer, an additional copper seed layer 1086 is applied-24 (d). The copper seed layer is typically about 0.2 to 5 microns thick.

      Steps 24 (b) to 24 (d) ensure subsequent good removal of the substrate by etching to ensure good adhesion of the barrier layer to the substrate, good adhesion and growth of the vias, and without damaging the vias. Preferred to allow. Although the best results include these steps, they are optional, however, one or more may not be used.

      A layer of photoresist 1088 is then applied—step 24 (e), FIG. 24 (e), and patterned with a pattern of copper vias-24 (f). Copper 1090 is then plated on the pattern -24 (g), and photoresist 1088 is stripped off -24 (h). Upright copper vias 1090 are laminated -24 (i) with a polymer dielectric 1092, which can be a fiber reinforced polymer matrix prepreg. The stacked via array is thinned and planarized to expose the edges of the copper vias-24 (j). The carrier is then removed.

      Optionally and preferably, a planarized polymer dielectric with exposed ends of copper vias is etch resistant, such as photoresist or dielectric film, before the copper carrier 1080 is removed-24 (l). Protected by applying material 1094-24 (k). Generally, the carrier is a copper carrier 1080 that is removed by melting copper. Ammonium hydroxide or copper chloride can be used to dissolve the copper.

      The barrier layer can then be etched away-24 (m) and the etching protection layer 1094 can be removed-step 24 (n).

      It will be understood, though not described here, that the upright copper vias are made by panel plating and the excess copper can be selectively etched away to leave the vias. Indeed, while shielding the vias, sockets could alternatively be made by selectively etching away parts of the copper panel.

      It will be appreciated, as previously mentioned, that one or more vias 1090 can be the modified vias 5 of FIG. 1 including capacitors 6 therein. Further, one or more vias can be inductor vias 7 of FIG.

      Via pillar technology where only a simple via 1090 is required and not the modified via 5 of FIG. 1 with the capacitor 6 or the inductor via 7 of FIG. 1 therein, but only a simple cylindrical via is required. Although preferred, drill-and-fill technology can also be used.

      With reference to FIG. 25 and FIGS. 25 (a) to 25 (e), a carrier made of a copper clad laminate (CCL) 1100 is obtained in another modification method −25 (a). CCL has a thickness of tens to hundreds of microns. Typical thickness is 150 microns. A hole 1102 is drilled through the CCL-25 (b). The holes 1102 can have a diameter of tens to hundreds of microns. Generally, the hole diameter is 150 microns.

      The through holes are then plated-25 (c) to create plated through holes 1104.

      The copper clad laminate 1100 is then polished or etched to remove the surface copper layers 1106, 1108, leaving a laminate 1110 with plated through-hole (Pth) copper vias 1104-25 (d).

      Next, using CNC or stamping, socket 1112 is fabricated through the laminate to house the chip-25 (e).

      Referring to FIG. 26, a top view of a frame 2000 with an embedded filter 2002 therein is shown, and various routing vias 2004 include sockets 2006 for housing chips such as processor chips or memory chips. Can be included. This type of frame 2000 can be made as part of a larger array such as that shown in FIGS. 17-19. The frame 2000 as shown includes one socket 2006 for housing a single chip. However, it will be appreciated that the frame may include more than one socket to accommodate more than one chip. This kind of socket 2006 can be used to embed a processor chip, a memory chip or a passive chip with a filter or the like embedded therein.

      This document has described in great detail how inductors and capacitors can be fabricated as embedded passives in organic substrates. This type of capacitor and inductor combination can provide a filter. The description then continues to explain how polymer frames with embedded vias can be made and how they can be used as sockets for embedded active devices. The combination of these techniques allows the fabrication of packages with one or more embedded chips and embedded filters for very small highly integrated RF components, including both active and passive components.

      The above description is provided for illustration only. It will be appreciated that the invention is capable of many variations.

      Several embodiments of the invention have been described. Nevertheless, it is understood that various changes can be made without departing from the spirit and scope of the invention. Accordingly, other implementations are within the scope of the following claims.

      Therefore, those skilled in the art will recognize that the invention is not limited to what has been particularly described above with reference to the figures. Rather, the scope of the invention is defined by the appended claims, and combinations and subcombinations of the various features described above, as well as variations and modifications that will occur to those of ordinary skill in the art upon reading the foregoing description. Including both changes.

      In the claims, the word "comprise" and variations thereof, such as "comprises", "comprising", and the like, include the recited components, but generally other Indicates that the component is not excluded.

1 Frame 2 Socket Cavity 4 Via Pillar 5 Via Pillar 6 Via Pillar Capacitor Dielectric 7 Via Pillar 8, 9 Capacitor 10 Polymer Dielectric Filler 11, 12 Feature 13 Inductor 14 Substrate 20 Capacitor 21 Substrate 22 Dielectric Layer 24 Feature Layer 26, 28, 30, 32 Copper pillar 34 Encapsulating dielectric material 38 Feature layer 40 Inductor 42 Via pillar 44 Capacitor 52 Via pillar 54 Capacitor 56 Inductor via 58 Trace 60 First inductor 62 Via pillar 64 Capacitor 66 Second inductor 70 Inductor 71, 72 Via Pillar 74 Capacitor 78 Trace Connector 84 Capacitor 86 Induction Via 88 Inductor Trace 208 Photoresist Layer 210 Carrier 212 Barrier Metal Layer 214 Copper Layer 216 First Electrode 218 Dielectric Layer 220 Second Electrode 222 Copper Layer 224 Photoresist Layer 226 Seed Layer 228 Photoresist layer 230 Photoresist layer 232 Via pillar interconnect 234 Dielectric material 236 Seed layer 238 Photoresist layer 240 Feature layer Copper layer 242 Photoresist layer 244 Copper via 246 Polymer layer 248 Capacitor 250 Composite structure 252 Titanium seed layer 254 Copper Layers 256, 258 Photoresist 260 Copper Filter 262 Copper 264 Solder Mask 300 Basic LC Low Pass Filter 348 Capacitor 1010 Array 1012 Chip Socket 1012 'Socket 1014 Metal Via 1016 Polymer Matrix Frame 1018 Polymer Matrix Framework 1020 Panel 1021, 1022, 1023 1024 block 1025 horizontal bar 1026 vertical bar 1027 outer frame 1028 chip socket 1029 chip socket 1035 chip 1036 polymer 1038 frame socket arrangement 1040 framework panel 1042 routing layer pad 1043 routing layer pad 1045 dicing tool 1048 chip die package 1055 memory chip 1057 solder Sphere 1080 Carrier 1082 Seed layer 1084 Etch resistant layer 1086 Seed layer 1088 Layer of photoresist 1090 Copper via 1092 Polymer dielectric 1094 Etch resistant material 1100 CCL
1102 holes 1104 through holes 1106, 1108 copper layer 1110 laminate 1112 socket 1200 coil 1202 dielectric frame 1204 cavities 1206, 1207, 1208 via pillars 1209, 1210 vertical element 1250 capacitor 2000 frame 2002 embedded filter 2004 routing via 2006 socket

Claims (12)

A chip socket for an embedded chip defined by an organic matrix frame, said organic matrix frame comprising at least one via layer, wherein in said via layer at least one via post passing through the frame around said chip socket. Connected to at least one capacitor comprising a lower electrode, a dielectric layer and an upper electrode,
The via pillar includes the upper electrode and is incorporated in an organic matrix frame around the chip socket,
The capacitor comprises a lower electrode and a dielectric layer, the at least one via pillar standing on the dielectric layer and functioning as an upper electrode of the capacitor;
The capacitor has a cross-sectional area defined by the cross-sectional area of the via post that is controlled to adjust the capacitance of the capacitor,
(A contact area of the via pillar in contact with the dielectric layer) × (dielectric constant of the dielectric layer) ÷ (thickness of the dielectric layer) = (capacitance of the capacitor) . The dielectric of the _capacitor, according to claim 1, characterized in that it comprises at least one of the group consisting of _{Ta 2 O 5, TiO 2,} BaxSr1-xTiO 3, BaTiO 3, BaO 4 SrTi and _Al 2 _{O 3} Chip socket.   The chip socket according to claim 1, wherein the lower electrode of the capacitor comprises a noble metal.   The chip socket according to claim 1, wherein the lower electrode of the capacitor comprises a metal selected from the group consisting of gold, platinum and tantalum.   The chip socket according to claim 1, wherein the upper electrode of the capacitor comprises a metal selected from the group consisting of gold, platinum and tantalum. The chip socket according to claim 1, wherein the capacitor includes a lower electrode, a dielectric layer, and an upper electrode, and the at least one via pillar stands on the capacitor.   The chip socket according to claim 1, wherein the at least one capacitor has a capacitance between 1.5 pF and 300 pF.   The chip socket according to claim 1, wherein the at least one capacitor has a capacitance between 5 pF and 45 pF.   The chip socket of claim 1, wherein the organic matrix frame further comprises at least one feature layer.   The chip socket of claim 1, wherein at least one electronic component is embedded within the socket and electrically coupled to the at least one via post.   The chip socket of claim 1, wherein the at least one electronic component comprises a second capacitor. The chip socket according to claim 11 , wherein the second capacitor is a discrete component having a metal termination on at least one end.

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