JP2016103623A - Polymer frame used for chip and comprising at least one via in series with capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip socket with which passive elements such as capacitors and filters are incorporated within a chip package.SOLUTION: There is provided a chip socket defined by an organic matrix framework. The organic matrix framework comprises at least one via post layer, where at least one via through a frame 1 around a socket 2 includes at least one capacitor 6 comprising a lower electrode, a dielectric layer and an upper electrode in contact with a via post 5.SELECTED DRAWING: Figure 1

Description

      The present invention is directed to improved chip packaging, and embedded chips in which passive components such as capacitors and filters, among others, are incorporated within the chip package.

      Driven by the ever-increasing demand for miniaturization of increasingly complex electronic components, consumer electronics such as computers and telecommunications equipment are becoming more integrated. This has created a need for support structures such as IC substrates and IC interposers having a high density of multiple conductive layers and vias that are electrically isolated from each other by a dielectric material.

      The general requirements for this type of support structure are reliability and adequate electrical performance, thinness, stiffness, flatness, good heat dissipation and competitive unit cost.

      Of the various approaches to achieve these requirements, one widely realized manufacturing technique that creates interconnect vias between layers is the subsequent filling with metal, usually copper, deposited therein by plating techniques. For this purpose, a laser is used to drill through the previously deposited metal layer in a dielectric substrate that is subsequently placed. This approach of creating vias is sometimes referred to as “drill and fill” and the vias created thereby can be referred to as “drill and fill vias”.

      There are several drawbacks to the drill and fill via approach. Since each via needs to be drilled separately, the processing rate is limited and the cost of fabricating sophisticated multi-via IC substrates and interposers is prohibitively high. With large arrays, it is difficult to produce high density high quality vias with different sizes and shapes in close proximity to each other by drill and fill methodologies. In addition, laser drilled vias have rough sidewalls and tapers inside through the thickness of the dielectric material. This tapering reduces the effective diameter of the via. It may also adversely affect electrical contact to the previous conductive metal layer, especially with ultra-small via diameters, thereby causing reliability problems. In addition, the sidewalls are particularly rough where the perforated dielectric is a composite material comprising glass or ceramic fibers in a polymer matrix, and this roughness may create additional stray inductances.

      The process of filling the drilled via hole is usually achieved by electroplating of copper. Electroplating deposition techniques can lead to recess formation, where a small crater occurs at the end of the via. Alternatively, overfill may occur where the via channel is filled with more copper than it can hold, and a hemispherical top surface is created that protrudes above the surrounding material. As needed when fabricating high density substrates and interposers, both recess formation and overfill tend to create difficulties when subsequently stacking vias one after the other. Furthermore, it will be appreciated that large via channels are difficult to fill uniformly, especially when they are in close proximity to smaller vias within the same interconnect layer of an interposer or IC board design. That is.

      Although the range of accepted sizes and reliability has improved over time, the above drawbacks are inherent in drill and fill technology and are expected to limit the range of possible via sizes. It is further noted that laser drilling is best for creating round via channels. Although slot-shaped via channels can theoretically be fabricated by laser milling, in practice the range of geometries that can be fabricated is somewhat limited and the vias of a given support structure Are generally cylindrical and substantially identical.

      Drill and fill via fabrication is expensive and it is difficult to uniformly and consistently fill via channels created by copper using a relatively cost effective electroplating process.

Vias drilled into a composite dielectric material are practically limited to a diameter of 60 × 10 ⁻⁶ m (60 microns), and yet the composite material is drilled as a result of the required removal process Suffers from significant tapered shape and rough sidewalls due to the nature of

In addition to the other limitations of laser drilling described above, when different size via channels are drilled and then filled with metal to produce different size vias, the via channels are at different speeds. There is an additional limitation of drill and fill technology in that it is difficult to create vias of different diameters in the same layer due to the reason for filling.
Thus, the typical problem of recess formation or overfill characterizing drill and fill technology is exacerbated because it is impossible to simultaneously optimize the deposition technique for different size vias.

      One alternative to overcoming many of the shortcomings of the drill and fill approach is to create vias by depositing copper or other metal into the pattern created in the photoresist, also known as “pattern plating” technology It is.

      In pattern plating, a seed layer is first deposited. A layer of photoresist is then deposited thereon and then selectively removed to create a pattern that exposes the seed layer, exposing it to a pattern. Via pillars are created by depositing copper in the photoresist trench. The remaining photoresist is then removed to leave upstanding via pillars, the seed layer is etched away, and a dielectric material, typically a polymer-impregnated glass fiber mat, over and around the via pillars Is laminated. Various techniques and processes are then used to planarize the dielectric material, removing a portion of it to expose the end of the via pillar and thereby against the ground to build the next metal layer there Conductive connections can be made possible. By repeating this process to build the desired multilayer structure, subsequent layers of metal conductors and via posts can be deposited thereon.

      In an alternative but closely related technique, hereinafter known as “panel plating”, a continuous layer of metal or alloy is deposited onto the substrate. A layer of photoresist is deposited on the edge of the substrate and the pattern is developed therein. The developed photoresist pattern is stripped, selectively exposing the metal beneath it, which can then be etched away. Undeveloped photoresist protects the underlying metal from being etched away, leaving upright patterns and via patterns.

      After stripping the undeveloped photoresist, a dielectric material such as a polymer-impregnated glass fiber mat can be laminated around and on the upstanding copper features and / or via posts. After planarization, subsequent layers of metal conductors and via posts can be deposited thereon by repeating this process to build the desired multilayer structure.

      Via layers created by the pattern plating or panel plating methodologies described above are generally known as “via pillars” and feature layers derived from copper.

      What will be understood is that the overall driving force of the evolution of microelectronics is directed towards producing increasingly smaller, thinner, lighter and more powerful products with high reliability. is there. The use of thick, cored interconnects prevents ultra-thin products from being reachable. In order to create increasingly denser structures within interconnect IC boards or “interposers”, increasingly more layers of increasingly smaller connections are required. Indeed, sometimes it is desirable to stack components on each other's ends.

      If the plated laminate structure is deposited on copper or other suitable sacrificial substrate, the substrate can be etched away, leaving a free standing coreless layered structure. Additional layers can be deposited on the side previously bonded to the sacrificial substrate, thereby allowing double-sided build-up, which helps minimize warpage and achieve planarity.

      One flexible technique for fabricating high density interconnects is to build a pattern or panel plated multilayer structure consisting of metal vias or features in a dielectric matrix. The metal can be copper and the dielectric can be a fiber reinforced polymer. Generally, a polymer with a high glass transition temperature (Tg), such as polyimide, is used. These interconnects can have a core or be coreless and can include cavities for stacking components. They can have odd or even layers. The enabling technology is described in a previous patent granted to Amitec-Advanced Multilayer Interconnect Technologies.

      For example, U.S. Pat. No. 6,057,836 to Hurwitz et al. Describes a method of fabricating a free-standing film that includes a via array in a dielectric for use as a precursor in the construction of a superior electronic support structure. . The method includes fabricating a film of conductive vias within a dielectric perimeter on a sacrificial carrier and separating the film from the sacrificial carrier to form a free-standing stacking array. Electronic substrates based on this type of free-standing film can be formed by thinning and planarizing the stacking arrangement and then terminating the vias. This publication is incorporated herein in its entirety.

      U.S. Pat. No. 6,057,049 to Hurwitz et al. Is a method for fabricating an IC support for supporting a first IC die connected in series with a second IC die, the IC The support comprises a stack of alternating layers of copper features and vias in an insulating perimeter, the first IC die can be bonded onto the IC support, and the second IC die is within the cavity within the IC support A method is described which is bondable and the cavities are formed by etching away the copper base and selectively etching away the built-up copper. This publication is incorporated herein in its entirety.

      (Patent Document 3) granted to Hurwitz et al. Includes the following steps: (A) selecting a first base layer; and (B) a first etchant barrier on the first base layer. Depositing layers; (C) constructing a first half stack of alternating conductive and insulating layers, wherein the conductive layers are interconnected by vias through the insulating layers; and (D) first Applying a second base layer onto one half stack; (E) applying a protective coating of photoresist to the second base layer; and (F) etching away the first base layer. (G) removing the protective coating of the photoresist; (H) removing the first etchant barrier layer; and (I) alternating conductive layers and insulation. Constructing a second half stack, wherein the conductive layers are interconnected by vias through the insulating layer, the second half stack having a substantially symmetric layup on the first half stack; , (J) applying an insulating layer over the second half stack of alternating conductive layers and insulating layers; (K) removing the second base layer; and (L) vias on the outer surface of the stack. Terminating the substrate by exposing an end of the substrate and adding a termination to the substrate. This publication is incorporated herein in its entirety.

      Over time, both drill and fill techniques and via column deposition are expected to allow for further miniaturization and fabrication of substrates with higher density vias and features. Nevertheless, the development of via pillar technology seems to remain competitive.

      The substrate allows the chip to interface with other components. The chip must be bonded to the substrate through an assembly process that provides a reliable electronic connection to allow electronic communication between the chip and the substrate.

      Embedding the chip in the interposer relative to the outside world allows the chip package to be reduced, shortens the connections to the outside world, eliminates the die for the substrate assembly process, and potentially increases reliability It provides cost savings through simpler manufacturing.

      Basically, the concept of embedding active elements such as analog, digital and MEMS chips requires a chip support structure or substrate configuration with vias around the chip.

      One way to achieve an embedded chip is to fabricate the chip support structure on a chip array on the wafer where the circuitry of the support structure is larger than the die unit size. This is known as fan-out wafer layer packaging (FOWLP). Despite the increased size of silicon wafers, expensive material sets and manufacturing processes still limit the wafer diameter size to 12 inches, thereby limiting the number of FOWLP units that can be placed on the wafer. To do. Despite the 18-inch wafer being considered, the required investment, material set and equipment are still unknown. A limited number of chip support structures that can be processed at once increase the unit price of FOWLP and in markets that require highly competitive pricing such as the wireless communications, consumer electronics and automotive markets It makes it too expensive.

      FOWLP further represents a performance constraint because metal features placed on a silicon wafer as a fan-out or fan-in circuit are limited to a thickness of up to a few microns. This creates an electrical resistance challenge.

      An alternative fabrication route involves cutting the wafer to detach the chip and embedding the chip in a panel of dielectric layers with copper interconnects. One advantage of this alternative route is that the panel can be made much larger with so many more chips embedded in a single process. For example, a 12-inch wafer allows 2,500 FOWLP chips having dimensions of, for example, 5 mm x 5 mm to be processed at one time, whereas the current panel used by applicant Zhuhai Access is 25 inches x 21 Inch, allowing 10,000 chips to be processed at a time. Because the price of processing this type of panel is significantly less than wafer processing, and the throughput per panel is four times higher than the throughput of the wafer, the unit price can be significantly reduced, thereby opening up new markets. it can.

      In both technologies, the line spacing and width of tracks used in the industry is shrinking over time, with standards on the panel dropping from 15 microns to 10 microns and from 5 microns to 2 microns on the wafer.

      There are many advantages of embedding. First level assembly costs such as wire bonding, flip chip or SMD soldering are eliminated. Electrical performance is improved because the die and substrate are connected seamlessly within a single product. Packaged dies are thinner, provide an improved form factor, and the upper surface of the embedded die package has additional space-saving features such as those using stacked die and PoP (package on package) technology Freed for other uses, including

      In both FOWLP and panel-based embedded die technologies, the chips are packaged as an array (on the wafer or panel) and, once fabricated, are separated by dicing.

      RF (radio frequency) technology, such as WiFi, Bluetooth, etc., is widely implemented in various devices including mobile phones and automobiles.

      In addition to baseband processing and memory chips, RF devices particularly require passive elements such as various types of capacitors, inductors and filters. Although this type of passive component can be surface mounted, this type of device can be embedded in a substrate to allow for more and more powerful miniaturization and cost reduction.

      (Patent Document 4) assigned to Hurwitz is a capacitor composed of a metal electrode and a ceramic or metal oxide dielectric layer, which is embedded in a polymer-based encapsulant and is circuitized by via posts that stand on the capacitor. A substrate comprising a capacitor that can be connected to is described.

      US Pat. No. 6,099,056 comprises at least one feature layer and at least one adjacent via layer; these layers extend in the XY plane and have a height z, and the structure has at least one At least one capacitor coupled in series or in parallel with at least one inductor to provide a filter; at least one capacitor such that at least one via stands on the at least one capacitor Is sandwiched between at least one feature layer and at least one via in the at least adjacent via layer, and at least one of the first feature layer and the adjacent via layer extends in the XY plane. A composite electronic structure is described that includes at least one inductor.

      U.S. Patent No. 6,057,836 to Hurwitz teaches an array of chip sockets defined by an organic matrix framework that surrounds a socket through an organic matrix framework and further comprising a grid of metal vias through the organic matrix framework. The chip is placed in a socket and then held in place by a polymer-based dielectric so that the chip can be embedded in the frame.

US Pat. No. 7,682,972, entitled “Advanced Multilayer Coreless Support Structures and Methods for Their Production” US Pat. No. 7,669,320, entitled “Coreless cavity substrates for chip packaging and their fabrication” U.S. Pat. No. 7,635,641, entitled “Integrated Circuit Support Structures and their Fabrication” US Patent Application No. 13 / 962,075, entitled “Thin Film Capacitor Embedded in Polymer Dielectric”, filed Aug. 8, 2013 US patent application Ser. No. 13 / 962,316, entitled “Multilayered Structure and Embedded Features”, filed Aug. 8, 2013 US patent application Ser. No. 14 / 269,884, entitled “Interposer Frame with Polymer Matrix and Method of Fabrication”, filed May 5, 2014 US patent application Ser. No. 13 / 912,652 US patent application Ser. No. 13 / 482,099 US patent application Ser. No. 13 / 483,185 US patent application Ser. No. 13 / 483,234

      The present invention claims priority over (Patent Document 4); (Patent Document 5) and (Patent Document 6).

      A first aspect is a chip socket defined by an organic matrix framework, wherein the organic matrix framework includes at least one via through the framework around the socket with a lower electrode, a dielectric layer, and a via post. A chip socket with at least one via post layer comprising at least one capacitor with an upper electrode in contact is intended.

Generally, the capacitor dielectric comprises at least one of the group consisting of Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ and Al ₂ O ₃ .

      Generally, the lower electrode of a capacitor comprises a noble metal.

      Optionally, the lower electrode comprises a metal selected from the group consisting of gold, platinum and tantalum.

      In some embodiments, the upper electrode comprises a metal selected from the group consisting of gold, platinum and tantalum.

      In general, at least one via stands on at least one capacitor.

      Optionally, the upper electrode comprises a via post.

      Preferably, the capacitor has a cross-sectional area defined by the cross-sectional area of the via post that is carefully controlled to adjust the capacitance of the capacitor.

      In some embodiments, at least one capacitor has a capacitance between 1.5 pF and 300 pF.

      In a preferred embodiment, at least one capacitor has a capacitance between 5 pF and 15 pF.

      Optionally, the framework further comprises at least one feature layer.

      Optionally, at least one electronic component is embedded in the socket and electrically coupled to the at least one via.

      Optionally, at least one electronic component comprises a second capacitor.

      In some embodiments, the second capacitor is a discrete component having a metal termination on at least one end.

      In some embodiments, the second capacitor is a metal-insulator-metal (MIM) capacitor.

In some embodiments, the metal-insulator-metal (MIM) capacitor is a dielectric comprising at least one of the group consisting of Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ and Al ₂ O _3. With layers.

      In some embodiments, the lower electrode of a metal-insulator-metal (MIM) capacitor comprises a noble metal.

      In some embodiments, the lower electrode comprises a metal selected from the group consisting of gold, platinum, and tantalum.

      In some embodiments, the metal-insulator-metal (MIM) upper electrode comprises a metal selected from the group consisting of gold, platinum and tantalum.

      Optionally, a metal-insulator-metal (MIM) capacitor is attached to the insulator carrier.

In some embodiments, the insulator carrier comprises at least one of the group consisting of silicon (Si), SiO ₂ (silica), glass, AlN, alumina, and c-plane sapphire Al ₂ O ₃ (0001).

      In some embodiments, a metal-insulator-metal (MIM) capacitor plate is connected to the via by a feature layer.

      Generally, a component embedded in a socket is connected by at least one feature layer to at least one via having an embedded capacitor.

      Optionally, the system further comprises a feature layer on one side of the frame and the embedded component comprises an inductor.

      Optionally, the embedded component in the frame, the embedded component in the socket, and at least one feature in the feature layer provide a circuit that functions as a filter.

      Optionally, the filter is selected from the group consisting of a basic LC low pass filter, an LC high pass filter, an LC series band pass filter, an LC parallel band pass filter and a low pass parallel Chebyshev filter.

      Optionally, the chip mounted in the socket is protected from electromagnetic radiation by a Faraday cage with via posts in the frame, thereby minimizing electromagnetic interference.

      In some embodiments, the Faraday cage further comprises a feature layer in the frame.

      A further aspect is a framework comprising a plurality of sockets for receiving a plurality of chips, each socket comprising a frame, and the framework comprising a gridwork of copper via posts and at least one capacitor. With the goal.

      Optionally, the processor chip is embedded in one socket and a passive chip with at least one capacitor is embedded in the second socket.

      A further aspect is directed to a framework comprising a plurality of chip sockets arranged in an array, wherein each chip socket is surrounded by a frame.

      Optionally, at least one processor chip is embedded in at least one socket.

      A further aspect is to provide a grid of metal via pillars through an organic matrix framework defined by an organic matrix framework of a frame surrounding the socket and wherein at least one metal via pillar is connected in series with at least one capacitor. Furthermore, it aims at the arrangement | sequence of the chip socket provided.

      Optionally, the capacitor comprises a lower electrode and a dielectric layer and is incorporated into the base of at least one via post such that at least one via post stands on the at least one capacitor.

      Optionally, the at least one via post comprises at least one capacitor upper electrode.

      Optionally, the frame comprises at least one feature layer in which at least one inductor is formed in the at least one feature layer.

      Generally, the organic matrix framework further comprises a glass fiber bundle.

      Generally, each via is in the range of 25 microns to 500 microns wide.

      Generally, each via is cylindrical and has a diameter in the range of 25 microns to 500 microns.

      In general, a frame around at least one socket comprises alternating via posts and feature layers and comprises at least one via post layer and one feature layer.

      In general, the organic matrix framework comprises a plurality of layers and the gridwork comprises a plurality of via pillar layers, with each pair of consecutive via pillar layers separated by a feature layer.

      In some embodiments, the frame around at least one socket comprises alternating coils of alternating via posts and features spanning at least one via post layer and one feature layer.

      Optionally, at least one via post comprises an elongated via post.

      Optionally, a continuous coil of elongated via posts spans multiple via post layers.

      Optionally, this arrangement comprises adjacent chip sockets of different dimensions.

      Optionally, this arrangement comprises adjacent chip sockets of different sizes.

      Optionally, this arrangement comprises adjacent chip sockets of different shapes.

      Optionally, the framework comprises at least one feature layer and at least one adjacent via layer, the layer extending in the XY plane and having a height z, the composite electronic structure comprising at least At least one capacitor coupled to an inductor, the at least one capacitor including a lower electrode and a dielectric layer, and the at least one via over the at least one capacitor. Embedded in the base of the via layer sandwiched between the at least one feature layer and the via post to stand and optionally form an upper electrode, the via layer embedded in the polymer matrix, and The at least one inductor is formed in at least one of the first feature layer and the adjacent via layer.

      Optionally, at least one capacitor and at least one inductor are connected in series.

      Optionally, the frame comprises at least a second feature layer above the via layer, and the at least one capacitor and the at least one inductor are coupled in parallel via the feature layer.

      Optionally, the at least one inductor is fabricated in the feature layer.

      Optionally, the at least one inductor is helically wound.

      Optionally, the inductance of this inductor is at least 0.1 nH.

      Optionally, the inductance of this inductor is less than 50 nH.

      Optionally, additional inductors are fabricated in the via layer.

      Optionally, the inductance of this further inductor is at least 0.1 nH.

      Optionally, the at least one inductor and the at least one capacitor are selected from the group consisting of a basic LC low pass filter, an LC high pass filter, an LC series band pass filter, an LC parallel band pass filter and a low pass parallel Chebyshev filter Results in a filter.

      Optionally, at least one socket contains a chip with at least one capacitor in a polymer matrix, and the framework and chip are thinned to expose the end of the via, and the connection and termination The photoresist is then applied by placing a photoresist on each side of the thinned polymer matrix and by depositing copper pads on the photoresist pattern, the photoresist is then stripped, and a solder mask is placed between the copper pads. A protective coating is applied.

      A further aspect is a panel comprising an array of chip sockets, each surrounded by and defined by an organic matrix framework comprising a grid of copper via posts through the organic matrix framework, the panel comprising one type At least one region having a socket with a first set of dimensions for receiving a second set of chips, and a socket with a second set of dimensions for receiving a second type of chips; and The panel is provided with a second region in which at least one via post includes a thin film capacitor.

      Optionally, the panel causes at least one via post to stand on the thin film capacitor.

      Optionally, at least one via post comprises an upper electrode of a thin film capacitor.

      Optionally, the panel comprises an area with two different socket types in close proximity.

      The combination of frames with built-in capacitors around chip sockets, for example, RF (radio frequency) technologies such as Wi-Fi, Bluetooth, etc. that are widely used in mobile phones and automobiles, more advanced miniaturization and manufacturing Provides economy and increased reliability.

      The protective coating can be selected from ENEPIG and organic varnish.

The term micron or μm refers to micrometer or 10 ⁻⁶ m.

      For a better understanding of the present invention and to show how it can be put into practice, reference is now made to the accompanying drawings, merely by way of example.

      The details given here by way of specific reference to the drawings are by way of example only and for illustrative discussion of preferred embodiments of the invention, and of the principles and conceptual aspects of the invention. It is emphasized that it is presented to provide what is believed to be the most useful and easily understood explanation. In this regard, no attempt is made to show the structural details of the present invention in more detail than is necessary for a basic understanding of the present invention, and the description made in conjunction with the drawings illustrates some of the present invention. It will be clear to those skilled in the art how the form can be embodied as a practical matter. In the accompanying drawings:

1 is a schematic isometric view with a front side cut out of a portion of a polymer-based dielectric frame defining a socket, the frame having embedded via posts, at least one of which includes a thin film capacitor. FIG. FIG. 2 is a schematic isometric view of a polymer-based dielectric frame defining a socket, the frame having embedded via posts, at least one of which includes a thin film capacitor, and the socket includes embedded components; It comprises in this case an additional capacitor, and a via post with an embedded capacitor in the frame is connected to the embedded capacitor in the socket by a feature layer containing an inductor. FIG. 6 is a schematic projection of an inductor in a feature layer and an adjacent via post in a via post layer standing on a capacitor connected in series with the inductor. Vias and features are shown without surrounding dielectric for clarity. FIG. 6 is a schematic projection of inductor vias in a via layer connected in series with a capacitor at the base of a via post. Vias and features are shown without surrounding dielectric for clarity. FIG. 4 is a schematic projection of a pair of inductors in one feature layer and one in a via layer coupled to a capacitor in series with each other and at the base of a via post in the via layer of the via inductor. Vias and features are shown without surrounding dielectric for clarity. FIG. 5 is a schematic projection of an inductor in a feature layer coupled in parallel with a capacitor, where the capacitor and inductor are coupled together by via posts and traces in the second upper feature layer or on the outside of the multilayer structure. Vias and features are shown without surrounding dielectric for clarity. FIG. 5 is a schematic projection of an inductor in a feature layer connected in series with an inductive via and in parallel with a capacitor, where the capacitor and inductor via are connected together by traces in the second upper feature layer or on the outside of the multilayer structure. Has been. Vias and features are shown without surrounding dielectric for clarity. FIG. 2 is a schematic cross-sectional view through layers of via pillars connected between feature layers, with one via pillar shown having an integrated capacitor. 2 is a flow diagram illustrating a process for fabricating a substrate with an embedded filter consisting of a capacitor and an inductor; 2 is a flow diagram illustrating a process for fabricating a substrate with an embedded filter consisting of a capacitor and an inductor; 2 is a flow diagram illustrating a process for fabricating a substrate with an embedded filter consisting of a capacitor and an inductor; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 10 is a series of schematic cross-sectional illustrations illustrating a process for fabricating a substrate with embedded filters consisting of capacitors and inductors, each illustration matching the corresponding steps of FIG. 9; FIG. 9 is a flow diagram illustrating a process for terminating the filter of FIG. 8; FIG. 8 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with embedded filters, each illustration matching the corresponding step of FIG. 10; FIG. 8 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with embedded filters, each illustration matching the corresponding step of FIG. 10; FIG. 8 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with embedded filters, each illustration matching the corresponding step of FIG. 10; FIG. 8 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with embedded filters, each illustration matching the corresponding step of FIG. 10; FIG. 8 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with embedded filters, each illustration matching the corresponding step of FIG. 10; FIG. 8 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with embedded filters, each illustration matching the corresponding step of FIG. 10; FIG. 8 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with embedded filters, each illustration matching the corresponding step of FIG. 10; FIG. 8 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with embedded filters, each illustration matching the corresponding step of FIG. 10; FIG. 8 is a series of schematic cross-sectional illustrations illustrating a process for terminating a substrate with embedded filters, each illustration matching the corresponding step of FIG. 10; FIG. 2 is a schematic view of a frame with a three-layer coil consisting of elongated vias and embedded therein that includes embedded capacitors, and the flexibility of the manufacturing process and how it is used to fabricate embedded filters and the like Show what can be done; FIG. 3 is a schematic three-dimensional view of a basic LC low pass filter; FIG. 12 shows how the basic LC low-pass filter of FIG. 12a can be represented as an LC filter circuit; 12b is a schematic cross section of the basic LC low pass filter of FIG. 12a; 12b is a schematic cross-section of the basic LC low-pass filter of FIG. 12b is a schematic cross section of the basic LC low-pass filter of FIG. 12a with the top electrode being a via post thereon; FIG. 3 is a schematic three-dimensional view of a basic LC high pass filter; FIG. 13 shows how the basic LC high-pass filter of FIG. 13a can be represented as an LC filter circuit component; 2 is a schematic three-dimensional view of a basic LC band series filter; FIG. 14 shows how the basic LC band series filter of FIG. 14a can be represented as an LC filter circuit component; FIG. 3 is a schematic three-dimensional view of a basic LC band parallel filter comprising a capacitor and an inductor; FIG. 15b shows how the basic LC band parallel filter of FIG. 15a can be represented as an LC filter circuit component; A schematic 3D view of a low-band parallel Chebyshev filter, and It shows how a low-pass parallel Chebyshev filter can be represented as an LC filter. FIG. 4 is a schematic illustration of a portion of a polymer or composite grid having a socket therein for the chip and further having a through via around the socket; FIG. 4 is a schematic illustration of a panel used to fabricate embedded chips with surrounding through vias and shows how some of the panel IT IS can have sockets for different types of chips; FIG. 18 is a schematic illustration of a portion of the polymer or composite framework of FIG. 17 with a chip in each socket held in place by the polymer or a composite material such as a mold compound; FIG. 4 is a schematic illustration of a cross-section through a portion of the framework showing embedded chips held in each socket by a polymer material, and further showing through vias and pads on both sides of the panel; FIG. 2 is a schematic illustration of a cross section through a die containing embedded chips; FIG. 3 is a schematic illustration of a cross section through a package containing a pair of different dies in adjacent sockets; FIG. 22 is a schematic bottom view of a package such as that shown in FIG. 21; FIG. 2 is a flow diagram illustrating a manufacturing process for making a polymer or composite panel including an array of through vias; 25 is a schematic illustration of an intermediate substructure obtained after each step of flowchart 24; 25 is a schematic illustration of an intermediate substructure obtained after each step of flowchart 24; 25 is a schematic illustration of an intermediate substructure obtained after each step of flowchart 24; 25 is a schematic illustration of an intermediate substructure obtained after each step of flowchart 24; 25 is a schematic illustration of an intermediate substructure obtained after each step of flowchart 24; 25 is a schematic illustration of an intermediate substructure obtained after each step of flowchart 24; 25 is a schematic illustration of an intermediate substructure obtained after each step of flowchart 24; 25 is a schematic illustration of an intermediate substructure obtained after each step of flowchart 24; 25 is a schematic illustration of an intermediate substructure obtained after each step of flowchart 24; 25 is a schematic illustration of an intermediate substructure obtained after each step of flowchart 24; 25 is a schematic illustration of an intermediate substructure obtained after each step of flowchart 24; 25 is a schematic illustration of an intermediate substructure obtained after each step of flowchart 24; 25 is a schematic illustration of an intermediate substructure obtained after each step of flowchart 24; 25 is a schematic illustration of an intermediate substructure obtained after each step of flowchart 24; FIG. 3 is a flow diagram showing how drill fill technology can be used to create plated through holes with stamped sockets; 25 is a schematic illustration of an intermediate substructure obtained after each step of the flowchart 24. 25 is a schematic illustration of an intermediate substructure obtained after each step of the flowchart 24. 25 is a schematic illustration of an intermediate substructure obtained after each step of the flowchart 24. 25 is a schematic illustration of an intermediate substructure obtained after each step of the flowchart 24. 25 is a schematic illustration of an intermediate substructure obtained after each step of the flowchart 24. FIG. 5 is a plan view of a frame with a filter embedded with a socket to the chip.

      It will be understood that the figures are only schematic illustrations and not a fixed ratio. A very thin layer may appear thick. The width of the features may seem to be out of balance with their length.

      In particular, what will be noted is that due to the demand for increasingly more intense miniaturization, equivalent structures can be arranged to have very different spatial arrangements, and therefore somewhat different That may seem like.

      In the following description, a socket structure for embedding a chip is considered. The socket structure consists of metal vias in a dielectric matrix, in particular copper via pillars in a polymer matrix, such as polyimide, epoxy or BT (bismaleimide / triazine) or their blends reinforced by glass fibers. .

The socket structure described below further includes a capacitor incorporated in the frame of the socket. This type of capacitor is typically a lower metal electrode, which can be gold, tantalum or tantalum, and for example Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ or Al ₂ O ₃ is a metal insulator metal (M-I-M) capacitor with an inorganic dielectric layer that can be _three . Capacitors can have a dedicated upper electrode, typically gold, tantalum or tantalum, or vias, typically copper, can be deposited thereon as the upper electrode.

      Since parallel plate capacitors typically have a dielectric material sandwiched between electrodes, which are materials with a very high dielectric constant, the dielectric material used for encapsulation distinguishes it from the capacitor dielectric For this reason, it is referred to below as an encapsulating dielectric.

      The figure is illustrative and no attempt is made to show the scale. In addition, a small number of vias and individual capacitors and filters are shown, while the socket frame can include several capacitors and filters and a large number of vias. In practice, generally a large array of socket frames are produced together.

      Where vias are fabricated by drill and fill techniques, vias generally have a substantially circular cross section because they are fabricated by first drilling a laser hole in the dielectric. Since the encapsulating dielectric is heterogeneous and anisotropic and consists of a polymer matrix and glass fiber reinforcement with an inorganic filler, the circular cross-section of the via is generally rough and slightly rounded and slightly rounded May be distorted. Furthermore, drill and fill vias generally tend to be somewhat tapered and are inverted frustoconical instead of cylindrical.

      Fabricating non-circular vias using the “drill and fill via” approach is prohibitive due to difficulties in cross-section control and geometry. There is also a minimum via size of about 50-60 microns diameter due to laser drilling limitations. These difficulties have been described in detail in the background section above, and among others, via formation due to recess formation and / or hemispherical formation due to the copper via fill electroplating process, laser drilling process. Related to tapering geometry and sidewall roughness, and higher cost due to the use of expensive laser drillers to mill the slots in a “routing” mode that creates grooves in the polymer / glass dielectric.

      In addition to the other limitations of laser drilling described above, via channels differ when different size via channels are drilled and then filled simultaneously with metal to simultaneously produce different size vias. There is an additional limitation of drill and fill technology in that it is difficult to create vias of different diameters in the same layer because of the speed filling. Thus, it is impossible to simultaneously optimize the deposition technique for different sized vias, thus exacerbating the typical problem of recess formation or overfill (hemisphere formation) that characterizes drill and fill technology. Thus, in practical applications, drill and fill vias have a substantially circular cross section, and all vias have a substantially similar cross section, although sometimes somewhat distorted due to the heterogeneous nature of the substrate. Have.

In addition, laser drilled vias in composite dielectric materials such as polyimide / glass or epoxy / glass or BT (bismaleimide / triazine) / glass or their blends with ceramic and / or other filler particles are practical. Is limited to a diameter of about 60 × 10 ⁻⁶ m, and still a significant tapering shape due to the nature of the composite material to be drilled as a result of the required removal process, Suffer from rough side walls.

      As described in (Patent Document 1), (Patent Document 2), and (Patent Document 3) granted to Hurwitz et al. Incorporated here, there is no effective upper limit in the in-plane dimension of the feature. This is a feature of Access photoresist and pattern or panel plating and lamination techniques.

      An alternative, more accurate and flexible manufacturing technique than drill and fill, is to plate both copper via layers and feature layers in patterns developed in photoresist (pattern plating), or panel plating copper layers And then selectively etching away excess material. Both of these routes leave upright via posts and upright features. These upright elements are typically encapsulated by laminating a dielectric over them by placing a layer of dielectric prepreg over the upright features and via posts and then curing the resin of the prepreg. Can.

      A wide range of via shapes and sizes are cost-effective using the flexibility of a bottom-up approach with electroplating on patterned photoresist, followed by stacking (or panel plating, selective etching and stacking) Can be made with. Furthermore, different via shapes and sizes can be fabricated in the same layer. A metal seed layer is deposited first, and then a photoresist material is deposited and a smooth, straight, non-tapered groove is developed in it that is exposed onto the exposed seed layer. This is particularly facilitated when a copper pattern plating approach is used by being able to be subsequently filled by depositing copper in these grooves by pattern plating. In contrast to the drill and fill via approach, via post technology allows grooves in the photoresist layer to be filled to obtain a hemispherical copper connector without a recess. After copper deposition, the photoresist is then stripped to remove the metal seed layer and a permanent, polymer glass composite encapsulant is applied over and around. The “via conductor” structure created in this way can use the process flow described in (Patent Document 1), (Patent Document 2) and (Patent Document 3) given to Hurwitz et al.

      It is a further feature of bottom-up electroplating technology that vias made by electroplating with photoresist can be narrower than vias created by drill and fill. Currently, the narrowest drill and fill via is about 60 microns. By electroplating with a photoresist, resolutions better than 50 microns or even 25 microns can be achieved. It is difficult to connect an IC to this type of substrate. One approach for flip chip bonding is to provide a copper pad that is flush with the surface of the dielectric. This kind of approach is described in (Patent Document 7) given to the inventor of the present invention.

      In addition to via conductors and features, it is possible to fabricate passive elements such as capacitors and filters in structures including via pillar technology using electroplating, PVD and encapsulation molding techniques to create capacitors and filters. It was found that there was.

      Referring to FIG. 1, a polymer-based dielectric frame 1 defining a socket 2 is shown in a schematic isometric view with the front of the frame 1 cut away. The frame 1 has embedded via pillars 5, 6, 7, and at least one of the via pillars 5 includes a thin film capacitor 6. Via pillars produced by electroplating need not be circular, but can extend in one planar direction. The single via pillar shown is an elongated via pillar 7 that can extend in the XY plane and function as an inductor.

FIG. 2 is a schematic cutaway isometric view of a polymer-based dielectric frame 1 defining the socket 2 of FIG. 1, where the socket 2 is one or more embedded components, in this case an additional capacitor 8. , 9 and via pillar 5 with embedded metal insulator metal (MIM) capacitor 6 in frame 1 is connected to embedded capacitors 8, 9 in socket 2 by feature layer features 11, 12. . The embedded capacitor 9 can be fabricated on an insulating substrate 14 such as silicon (Si), silica (SiO ₂ ), glass, AlN, α-alumina or c-plane alumina (sapphire). In addition, a second feature layer is deposited on the filled socket 2 containing the inductor 13. The additional normal via posts 4 shown in FIG. 1 are not included in FIG. 2 or at least as shown in FIG. However, it will be appreciated that the frame 1 of the present invention can include one or more of the normal via pillars 4, via pillars 5 standing on the capacitors 6 and induction via pillars 7.

Both the MIM capacitor in the via 5 in the frame 1 and the MIM capacitors 8, 9 embedded in the socket are lower metal electrodes, which can be gold, tantalum or tantalum, and for example Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ or Al ₂ O ₃ .

Capacitors can have a dedicated upper electrode, typically gold, tantalum or tantalum, or vias 5, typically copper, can be deposited over the dielectric 6 and as such It can function as an upper electrode. Similarly, the embedded capacitors 8, 9 embedded in the frame can be gold, tantalum or tantalum electrodes and Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ or Al ₂ O _3. An inorganic dielectric layer can be provided. Such embedded capacitors 8 and 9 can be fabricated on an inorganic substrate such as c-plane Al ₂ O ₃ (sapphire).

      The capacitor and inductor combination can function as a filter that protects the chip from fluctuation currents and noise. Filters are particularly important for RF telecommunications such as WIFI, Bluetooth, etc. The filter can be useful for isolating parts of the circuit from other elements to prevent interference.

Referring to FIG. 3, a schematic projection of the inductor 40 in the feature layer and the adjacent via post 42 of the via post layer standing on the capacitor 44 connected in series with the inductor 40 is shown. For clarity, the surrounding encapsulating dielectric material is not shown. Only metal structures and capacitors are shown. The structure of FIG. 3 can be made of copper and the capacitor 44 comprises a dielectric material such as Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ or Al ₂ O ₃ , And generally having electrodes of tantalum or another noble metal. In general, via post 42 is encapsulated in a polymer dielectric that can include a filler and can be fabricated using a knitted fiber prepreg. A feature layer that includes the inductor 40 may first be deposited with a capacitor 44 and a via post 42 built thereon. A polymer-based dielectric material, which can be a polymer film or a knitted fiber prepreg, can be laminated over the features 40 and via posts 42. Alternatively, via post 42 and capacitor 44 can be fabricated and laminated with a polymer dielectric, and then inductor 40 in the feature layer can be deposited or shown thereon. 2 can be left unlaminated as a surface trace, such as the inductor 13 of FIG. 2, or can be subsequently laminated with additional via layers possibly not shown. Thus, the inductor 40 is in a feature layer that is part of the frame (1, FIG. 1), or in a surface layer above or below the frame (1, FIG. 1), such as portion 13 of FIG. Can be included. In addition, and with continued reference to FIG. 2, if applied after embedding components 8 and 9 outside the frame 1 and embedded in a polymer dielectric 10 such as a mold compound or prepreg in the cavity 2 For example, the inductor 40 (13) can be partially deposited on the filled cavity.

      It will be appreciated that the feature layer is very thin, typically about 10 microns. The via layer, however, can rather be thicker. FIG. 4 is a schematic projection of an inductor via 56 extending into a via layer connected in series with the capacitor 54 at the base of the via post 52. Capacitor 54 is coupled to inductor via 56 by a trace 58 deposited in the z feature layer or on the surface of the frame, in this case on the bottom surface. Inductor via 56 may have a thickness of about 30 microns and have different characteristics than feature layer inductor 40 of FIG. In general, inductor via 40 is a high Q inductor having an inductance ranging from about 0.1 nH to about 10 nH. As shown, via inductor 56 can be a properly tight coil. However, it will be understood that it can be formed in the frame 1 and can be fully wound around the socket 2 of the frame 1 or it can be together with the socket. It can be embedded in one side of the frame.

      Referring to FIG. 5, it will be appreciated that a filter can be fabricated that includes a pair of inductors; a first inductor 60 in the feature layer and a second inductor 66 in the via post layer. It is. Referring back to FIGS. 1 and 2, the first inductor 60 is surface mounted onto the frame 1 or onto a frame filled onto a cavity 2 filled with polymer 10 such as the inductor 13 of FIG. Or it can be deposited under the filled cavities in the layer containing features 11 and 12, or indeed in subsequent layers. The filter shown in FIG. 5 includes a second inductor 66 in a via layer further comprising a normal via post. The second inductor 66 can be completely fabricated in the framework 1 around the cavity 2. Inductors 60, 66 can be coupled to capacitor 64 in series with each other and at the base of via post 62 in the via layer of via inductor 66.

      It will be appreciated that for some filtering purposes it is required to connect the components in parallel.

      For example, FIG. 6 is a schematic projection of an inductor 70 in a feature layer connected in parallel with a capacitor 74 at the base of a via post 71. Capacitor 74 and inductor 70 are coupled together by via posts 71, 72 and a second, trace 78 in the upper feature layer or on the outside of the multilayer structure. Returning to FIG. 2, the via pillars 71 and 72 are disposed in the frame 1. If the frame is multi-layered, one or more of the inductor 70 and connector 78 can be deposited in the feature layer of the frame or span as much as possible above (or below) the filler 10 in the cavity 2. 2 can be deposited by electroplating the photoresist on the outside of the filled frame 1 of FIG.

      FIG. 7 shows a feature layer (of frame 1) or (on frame 1) and possibly of FIG. 2 coupled in series with inductive via 86, like via 7 in FIGS. 1 and 2, and in parallel with capacitor 84. FIG. 6 is a schematic projection of an inductor 88 in a lower surface layer (deposited onto a filled cavity 2 such as inductor 13). Capacitor 84 and inductive via 86 are coupled together by a trace 88 in the second (upper as drawn) feature layer of the frame, or possibly on the outside of frame 1 that spans cavity 2.

Referring to FIG. 8, a one-layer parallel plate capacitor 20 comprising a dielectric material layer 22 sandwiched between a copper feature layer 24 and a copper post 26 is passed through a substrate 21 (such as frame 1 in FIG. 1). A cross-sectional view is shown. Optionally, a dielectric layer 22 is deposited on the copper feature layer 24 and a copper post 26 is then grown on the dielectric layer 22. The dielectric material can be, for example, Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ or Al ₂ O ₃ and by a physical vapor deposition process such as sputtering or by a chemical vapor deposition process Can be deposited by.

To obtain high quality capacitors, the dielectric can include Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ or Al ₂ O ₃ which can be deposited by a physical vapor process. And may further comprise a layer of aluminum metal previously or subsequently deposited, possibly by sputtering together with a dielectric ceramic. After optional aluminum deposition, the structure can be heated in the presence of oxygen, either in a furnace or oven, or by exposure to infrared radiation. The aluminum is thereby converted in situ into aluminum oxide (alumina Al ₂ O ₃ ). Since Al ₂ O ₃ is not denser than aluminum, it spreads and seals the defects in the ceramic layer, ensuring a high dielectric constant and preventing leakage.

      Copper pillars 26, 28, 30, 32 are encapsulated within encapsulating dielectric material 34. Where the copper pillars 26, 28, 30, 32 are fabricated as via pillars by electroplating on the photoresist (or by panel plating and etching) and then laminated, the encapsulating dielectric material 34 becomes the copper pillars 26, 28, 30, It can be applied as a glass fiber reinforced polymer resin prepreg laminated on 32.

      Using a bottom-up pattern or panel plating, one or more of the copper pillars 28, 32 can be a wide range of inductive via pillars, such as the inductive via pillar 7 of FIGS.

      The copper feature layer 24 can have a thickness of about 15 microns with a tolerance of about + -5 microns. Each via post layer is typically about 40 microns wide, but can be anywhere from 20 microns to 80 microns, for example. The outer feature layers 24, 38, which can be termination pads, are again typically about 15 microns, but can be anywhere from 10 microns to 25 microns, for example.

      As is well known, the capacitance of a capacitor is defined by the dielectric surface area multiplied by the surface area of the capacitor, which is the thickness of the dielectric layer 22 divided by the area of the via post 26.

      Using the simple single layer capacitor of FIG. 8, it is possible to optimize the thickness of the dielectric material 22 and its deposition process. Capacitance is a property of the dielectric constant of the dielectric material 22 and the region of the metal electrode, which in this case is the cross-sectional area of the copper pillar 26.

      In an exemplary embodiment, a noble metal electrode, generally made from tantalum, but optionally made from gold or platinum, is applied to either side of the dielectric layer. The capacitor is therefore incorporated in the via layer at the base of the via pillar. Where the via pillar defines the upper electrode, retaining the thickness and nature of the dielectric layer constant; it can be used to define and fine tune the capacitance.

      As described in more detail below, even where tantalum electrodes are used, the carefully sized via pillar deposition allows plasma etching removal of the capacitor electrodes and dielectric layers, resulting in tantalum and tantalum oxides. Remove the capacitor but leave the capacitor sandwich only by selective etching, such as hydrogen fluoride and oxygen etching, which does not harm the copper. Furthermore, since the via post can be formed by electroplating, it need not be cylindrical, but can have a rectangular or another cross-sectional shape.

      With reference to FIGS. 9 and 9 (i) to 9 (xxxi), one method of fabricating a thin film capacitor under a via post embedded in a polymer dielectric is shown in more detail. It will be appreciated that the illustrated method can be used to deposit an array of via pillars that include thin film capacitors within a framework. Conventional substantially cylindrical via pillars (eg via pillar 4 in FIG. 1) and guide via pillars (eg guide via pillar 7 in FIG. 1) can be deposited in the same via layer. However, to keep the figure simple, additional via posts are not shown and are not associated in the following description.

      The capacitor 248 shown in FIG. 9 (xx) has a dedicated electrode of a different material, typically a noble metal such as gold, platinum or tantalum. Tantalum is generally used because it is cheaper than gold or platinum. However, in an alternative configuration, the upper electrode can be a via post 232 that is electroplated thereon.

      First, the carrier 210 is procured—step 9 (i). Carrier 210 is typically a sacrificial copper substrate. In some embodiments, it can be a copper carrier with a copper quick release thin film added to it.

      A barrier layer 212 is deposited on the copper carrier 210—step 9 (ii). The barrier metal layer 212 can be made of nickel, gold, tin, lead, palladium, silver and combinations thereof. In some embodiments, the barrier metal layer has a thickness in the range of 1 to 10 microns. In general, the barrier layer 212 comprises nickel. A thin barrier layer 212 of nickel can be deposited by a physical vapor deposition process or by a chemical deposition process, which is typically sputtered or electroplated onto a copper carrier 210. For high speed processing, the barrier layer 212 can be electroplated. To ensure planarity and a smooth surface, it can then be planarized, for example by chemical mechanical polishing (CMP) —step 9 (iii) (FIG. 9 (iii) is similar to FIG. 9 (ii). The same).

      A thin layer of copper 214 is then deposited on the barrier layer 212—step 9 (iv). The thickness of the copper layer 214 is typically a few microns and can be fabricated by sputtering or by electroplating.

      The first electrode 216 is then deposited—step 9 (v). By way of example, the first electrode 216 can be made of tantalum by sputtering.

A dielectric layer 218 is then deposited—step 9 (vi). For high performance capacitors, the dielectric layer 218 must be kept as thin as possible without risking failure that allows charge leakage. There are a variety of candidate materials that can be used. These include Ta ₂ O ₅ , BaO ₄ SrTi and TiO ₂ , for example, it can be deposited by sputtering. In general, the thickness of the dielectric layer 218 is in the range of 0.1 to 0.3 microns.

      The second electrode 220 can then be deposited—step 9 (vii). By way of example, the second electrode 220 can be made of tantalum by sputtering.

      In the deformation process, the second noble electrode 220 is not applied. Rather, copper vias are deposited directly on the dielectric and their footprint defines the capacitor's upper electrode and thus the effective area and capacitance.

Furthermore, it is difficult to produce a thin dielectric layer of Ta ₂ O ₅ , BaO ₄ SrTi or TiO ₂ that is free of defects that may lead to charge leakage. To overcome this problem, in some embodiments, an aluminum layer (not shown) is deposited before or after depositing the Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ layer. (See optional step 9 (v) b or optional step 9 (vi) b—see FIG. 9) and by exposing it to heat in an oxygen environment, the aluminum layer is transformed into a high dielectric ceramic alumina (Al ₂ O ₃ ) oxidized to Alumina is less dense than aluminum and expands into adjacent voids. In this way, it is possible to cure the defects and ensure that the continuous thin dielectric separates the electrodes.

      In the main process, a further layer of copper 222 is deposited on the second electrode 220-step 9 (viii). For example, a further layer 222 of copper can be deposited by sputtering or by electroplating. An additional copper layer 222 can be deposited on the patterned photoresist by pattern plating and can be produced, for example, by printing and etching to provide pads, conductors and inductors. A photoresist layer 208 can be applied under the copper carrier 210 and a second photoresist layer 224 is applied over the additional layer 222 of copper and developed into a pattern—step 9 ( ix).

      The areas of the additional layer 222 of copper that are not protected by the patterned photoresist 224 are etched away—step 9 (x). Wet etching can be used. Illustratively, one method of etching away areas of the additional layer 222 of copper that are not protected by the patterned photoresist 224 comprises exposing the sacrificial substrate to a solution of ammonium hydroxide at an elevated temperature. Alternatively, copper chloride or wet iron chloride etching can be used.

The exposed electrode layers 216, 220 and dielectric layer 218 can be removed by dry etching using a plasma etching process—step 9 (xi). For example, hydrogen fluoride and oxygen plasma etching can be used to etch TiO ₂ or Ta ₂ O ₅ , and hydrogen fluoride and argon plasma etching can be used to etch BaO ₄ SrTi (BST). Typical concentration ratios for CF ₄ : O ₂ are in the range between 50:50 and 95: 5, where 95 is the concentration of CF ₄ . A typical concentration ratio for CF ₄ : Ar can be any ratio between 50:50 and 5:95, where 95 is the concentration of Ar.

      In the deformation method, no upper electrode 220 is deposited as described above. Rather, copper vias are fabricated directly on the dielectric material. Patterning the photoresist by stencil or by laser allows for precise control of the cross-sectional size and shape of the via, since it functions as the upper electrode and the capacitance is proportional to the effective area of the via electrode, Specifies the capacity of the capacitor.

      In the main process, the patterned photoresist 224, as well as typically the second photoresist layer 208, is then stripped—step 9 (xii). However, since the second layer 208 of photoresist will soon be replaced by a similar layer of photoresist 228-it can be retained instead.

      A copper seed layer 226 is deposited in step 9 (xiii) over and around the capacitor and exposed copper layer 214. To aid adhesion, a first seed layer of titanium can be deposited first.

      Then moving forward to a different scale with respect to FIG. 9 (xiv), an additional photoresist layer 228 protects the copper substrate (assuming that layer 208 shown in FIG. 9 (xi) has been removed). A thick photoresist layer 230 is deposited and patterned over the seed layer 226 (step 9 (xiv)). Copper interconnect 232 is electroplated into the pattern created by photoresist 230-step 9 (xv).

      Photoresist 228 (208), 230 is then stripped—step 9 (xvi), thereby exposing capacitor 248 which is shorted by seed layer 226 and copper via post 232 interconnect.

      Seed layer 226 is etched away by a rapid etch that minimizes damage to copper layer 214 and via 232, but ensures that copper layer 214 and copper via 232 are isolated from each other by capacitor 248 -step 9 (xvii).

      Many variations of the process are possible. For example, referring to FIG. 9 (xviii), before stacking the polymer-based dielectric material 234 over the copper substrate and vias, the structure is resistant to copper but tantalum and titanium oxide are susceptible to etching. It can be plasma etched by plasma etching such as a mixture of hydrogen fluoride and oxygen—Step 9 (xviii). This reduces the size of the capacitor to that of the via post 232. Since via posts 232 are fabricated by electroplating a photoresist, this provides the possibility to fabricate with high accuracy to virtually any size and shape, and to allow high packaging density Can be square or rectangular instead of circular. Removing excess capacitor material allows for high packaging density between components.

      Capacitor 348 or capacitor 248 is then embedded in polymer-based dielectric material 234 by laminating a layer of polymer-based dielectric material 234 over the copper substrate and via—step 9 (xix). The polymer-based dielectric material 234 is generally polyimide, epoxy or BT (bismaleimide / triazine) or blends thereof and can be reinforced by glass fibers. In some embodiments, a prepreg made of a polymer resin knitted fiber mat can be used. The polymer matrix can include inorganic particulate fillers typically having an average particle size between 0.5 and 30 microns, and the polymer typically contains between 15% and 30% by weight particulates. Including.

Although sometimes referred to as a dielectric, the polymer-based dielectric material 234 is generally compared to that of the dielectric layer 218 of the capacitor 248, which is a more exotic material such as Ta ₂ O ₅ or BaO ₄ SrTi or TiO _2. And has a significantly lower dielectric constant.

      The cured polymer-based dielectric material 234 is then thinned—planarized by step 9 (xx), eg, chemical mechanical polishing (CMP), thereby exposing the end of the copper via 232. A further seed layer 236 of copper is then deposited over the ends of the polymer-based dielectric material 234 and the copper via 232—step 9 (xxi). A photoresist layer 238 is applied over the seed layer 236 and the photoresist layer 238 is patterned—step 9 (xxii). A copper feature layer 240 is electroplated next to the pattern—step 9 (xxiii).

      Photoresist 238 can then be stripped—step 9 (xxiv).

      At this stage, the lower copper layer 214 is coupled to the upper copper layer 240 by the copper interconnect 232 via a capacitor 248 embedded in the copper interconnect 232.

      Additional photoresist layers 242 can be deposited and patterned—step 9 (xxv) and copper vias 244 can be electroplated into the pattern—step 9 (xxvi).

      Photoresist 242 can be stripped, leaving upstanding copper vias 244—step 9 (xxvii), and copper seed layer 236 is then etched away—step 9 (xviii). The copper seed layer can be removed by dry plasma etching or by short-term etching, for example with copper chloride or with ammonium chloride solution.

      Referring to FIG. 9 (xxix), a dielectric material 234 can be stacked over the upstanding via 244.

      The copper carrier 210 can now be etched away, typically using a copper chloride or ammonium chloride solution to do so—step 9 (xxx), (typically nickel) barrier layer 212 being It functions as an etch stop layer.

      The barrier layer 212 can then be removed by a suitable etching technique such as plasma etching or by a specific chemical etchant—step 9 (xxxi). For example, a mixture of nitric acid and hydrogen peroxide can be used to etch away nickel without removing copper. Other alternatives for dissolving nickel that can be used include iron (III) chloride acidified with hydrochloric acid + hydrogen peroxide, hot concentrated sulfuric acid and hydrochloric acid.

      The polymer layer 246 is then thinned and planarized—step 9 (xxxii), exposing the end of the copper via 244. Grinding, polishing or a combined chemical mechanical polishing (CMP) can be used.

      Thus far, it has been shown how an advanced, high performance capacitor 248 can be embedded in a composite structure 250 comprising a copper via layer 232 including a copper via 232 standing on a thin film capacitor 248, but 1, can further include guide vias 7 and normal via posts 4.

      Where frame 1 comprises a single via layer, after step 9 (xx), cavity 2 (FIG. 1) is stamped into the frame and components (eg 8 and 9, FIG. 2) are placed in frame 1 Embedded in or applied as a knitted fiber prepreg with a polymer-based dielectric material 10, which can be a fiber reinforced polymer filler.

      In such cases, feature layer 240 and top via layer 244 can be deposited on a filled frame that is smoothly polished using CMP and processed as a substrate for further buildup. .

      Alternatively, the frame can comprise a feature layer 240 and possibly even a second via layer 244 and additional layers embedded within the polymer-based dielectric matrix 234,246. The cavities can then be punched or cut out from the multilayer frame.

      Since the planar shape of the capacitor plate and dielectric is determined by patterning the photoresist, it will be appreciated that the capacitor can be fabricated in virtually any shape. Capacitors are generally square or rectangular, but can be circular or in fact have virtually any other shape. Capacitors can have 1, 2, 3, or more layers. Since the thickness of the dielectric can be carefully controlled, it is possible to tune the capacitor produced by this process to have virtually any capacitance over a large range and to accurately And can be optimized for a specific operating frequency.

      It should also be noted that the via 244 is not limited to being a simple cylindrical via post because it is not fabricated by drill and fill techniques. By making the pattern in the photoresist 242 using electroplating, the vias 244 can also have substantially any shape and size. Because via 244 can be a wide range of wires in the via layer, via 244 can be an inductor and can be a high-Q inductor with an inductance ranging from about 0.1 nH to about 10 nH.

      It will be appreciated that the combination of capacitor 248 and inductor 244 enables the provision of an RF filter.

      With reference to step 10 (xxxiii) to step 10 (xL) and the corresponding FIG. 10 (xxxiii) to FIG. 10 (xL), techniques for fabricating filter ports will now be described.

      Such ports can be deposited on the frame 1, but generally around the cavity 2 filled by the embedded components 8, 9, and generally around additional layers on both sides It will be understood that it is deposited on a structure comprising one.

      Referring to step 10 (xxxiii), a titanium seed layer 252 is then sputtered over the exposed ends of the matrix 246 and the copper (inductor) via 244. Referring to step 10 (xxxiv), a copper layer 254 is then sputtered onto the titanium layer 252.

      Referring to step 10 (xxxv), a layer of photoresist 256, 258 is placed on each side of the composite structure 250 and patterned. Referring to step 10 (xxxvi), copper 260, 262 is electroplated on patterned photoresist 256, 258 to create ports.

      Referring to step 10 (xxxvii), the layers of photoresist 256, 258 are then stripped, leaving upstanding copper ports 260, 262. Referring to step 10 (xxxviii), the titanium 252 and copper 254 layers are etched away. (The copper pads 260, 262 are slightly damaged by this process.)

      The recess thus formed can be filled with a solder mask 264—step 10 (xxxix) and the copper protected with ENEPIG 266 or other suitable termination technique—step 10 (xL).

      As mentioned above, electroplated vias deposited in photoresist and subsequently laminated using the preferred via pillar technology can have a wide range of shapes and sizes. Further, the frame can include two or more via layers separated by pads.

      Referring to FIG. 11, this flexibility generally allows a copper coil 1200 with via posts to be embedded in a dielectric frame 1202 around the cavity 1204. For example, the illustrated coil 1200 has three layers of extended via pillars 1206, 1207, 1208, possibly via pillars deposited on the feature layer. Layers 1206, 1207, 1208 are connected together by vertical elements 1209, 1210. The vertical elements 1209, 1210 can be via posts or feature layers, or via posts on feature layers.

      A capacitor 1250 can be fabricated below or in the inductor, typically at the base of the via post 1209. Techniques for making capacitors are described above with reference to FIGS. In practice, the copper via post coil 1200 comprises elongate via posts that are generally connected together by feature layers, or elongate feature layers that are connected by via posts. In general, via post layers alternate with feature layers, and coils must be built layer by layer.

      By combining capacitors and inductors, a filter can be provided. Examples of filters are shown in FIGS. 12-16. It will be appreciated that any of these filters or the like can be fabricated in the frame of a chip socket and can be combined with an embedded chip to provide an embedded circuit that includes both the chip and the filter. The substrate can include two or more sockets for two or more chips, eg, for a processor chip and a memory chip. In addition, some layers can be fabricated on the embedded chip, for example, capacitors or inductors in the feature layer can be deposited on the chip.

      Referring to FIG. 12a, which is a three-dimensional representation of the structure of FIG. 10 (xL), FIG. 12b, which is an equivalent circuit diagram, and FIG. 12c, which is a flat schematic diagram of the structure of FIG. 10 (xL). What will be done is that the structure thus created is a basic LC low pass filter 300 consisting essentially of four ports, P1, P2, P3, P4, capacitor C and inductor L. is there.

      Referring to FIG. 12d, in the modified manufacturing technique using the plasma etching step shown in FIG. 9 (xviii), the footprint of via V2 defines the capacitance and size of capacitor C2, where excess material is etched by plasma etching. Removed. Thus, 12d is a schematic cross-section of a basic LC low pass filter equal to FIG. 12a in which via post V2 defines the capacitor electrode and dielectric layer sizes of the structures of FIGS.

      FIG. 12e is a schematic cross-section of yet another basic LC low-pass filter of FIG. 12a, where the top electrode of capacitor C3 is a via column V3 without first depositing a noble metal upper electrode. In making this type of structure, care must be taken to remove all of the copper seed layer from the dielectric.

      It will be appreciated that the techniques detailed in FIGS. 9 and 9 (i) through 9 (xxxii) and 10 (xxxiii) through 10 (xL) have very different characteristics. It can be used to create a wide range of filter circuits. As shown in FIG. 2, many of these can include capacitors 8, 9 embedded in the cavity 2 to protect active elements embedded in the cavity 2.

      For example, with reference to FIGS. 13a and 13b, a basic LC high-pass filter can be fabricated. Referring to FIGS. 14a and 14b, a basic LC series bandpass filter can be fabricated, and similarly, with reference to FIGS. 15a and 15b, a basic LC parallel bandpass filter can be fabricated. With reference to FIGS. 16a and 16b, low-pass parallel Chebyshev filters can be fabricated with appropriate modifications and appropriate modifications.

      Although a single filter has been illustrated, it will be appreciated that in practice a huge array of this type of filter is fabricated together in a large plate that can then be fragmented. is there. Other components can be made with the filter. Filter 260 can be surface mounted to the substrate or embedded in the substrate by depositing additional features and via layers around it.

      As described below, in some embodiments, a filter as described above can be embedded in a substrate, and a socket allows the fabrication of a fully embedded RF circuit that can include, for example, a processor and a filter. In order to accommodate, a chip, such as a processor chip or a memory chip, can be punched through a substrate.

      In general, despite the obvious benefits of embedding to improve integration, it will be understood that if something goes wrong, the components and structures in which it is embedded must be discarded. There are inherent disadvantages due to the embedded components. Sometimes diagnosing the root cause of a problem can be difficult where the components are not isolated and cannot be individually tested. However, due to the expensive (area) demand on the surface of the substrate and the general trend towards miniaturization, embedding filters and other passive elements, as well as active elements such as processors and memories Has significant advantages.

      It is a feature of the present invention that filters and other passive components can be fabricated as stand-alone products for surface mounting. However, once optimized, the process can be integrated into the substrate fabrication process to embed this type of component.

      It will be appreciated that the capacitance of the capacitor depends on the electrode plate area, the dielectric thickness and its dielectric constant. In general, capacitors for RF filters have a capacitance between about 5 and about 15 pF. Using the techniques described here, it is possible to control the capacitance to a narrow range, for example, between 9 and 12 pF, and even between 10 and 11 pF.

      The inductor of the present invention can have an inductance in the nanohenry range. For example, 0.2 nH to 300 nH, but generally 1 nH to about 10 nH.

      Control the inductance of these inductors to a narrow range, such as having a range from about 4 nH to about 8 nH, or where required, for example to a range of less than 1 nanohenry between about 5 nH and about 6 nH. Is possible.

      As described above, the substrate can be fabricated with embedded passive elements. Active devices such as chips can be surface mounted on this type of substrate or embedded in sockets within such a substrate using techniques described more fully below. Embodiments of the present invention propose to fabricate an embedded passive element in a frame around a socket in which a chip such as a memory chip or processor chip can then be embedded.

      This type of frame can be laid out in a large framework around an array of sockets. Each socket in the array can be the same to accommodate the same chip. Alternatively, the array can consist of different sockets with different embedded passive elements in some or all frames around it. For example, the array can include alternating sockets for memory and processing chips. The socket can further accommodate a chip with passive elements such as capacitors or filters. Both passive and active components can be embedded in the socket. For example, a multi-socket frame can include one or more sockets for passive elements and one or more sockets for active elements such as memory chips or processor chips. To facilitate fabrication, this type of chip can be deposited by a robot in a socket and then injected around it with a polymer dielectric that can contain fiber reinforcement. Can be held in place. In some cases, the chip can be held in place by laminating a polymer film thereon.

      All methods for attaching the chip to the interposer are expensive. Wire bonding and flip chip technology are expensive and broken connections result in failure. Embedding the chip rather than surface mounting can reduce manufacturing costs and improve reliability and yield.

      Techniques for making sockets and for embedding chips in such sockets will now be described.

      Referring to FIG. 17, a portion of an array 1010 of chip sockets 1012 defined by a framework comprising a polymer matrix 1016 and an array of metal vias 1014 through the polymer matrix framework 1016 is shown.

      The array 1010 may be part of a panel comprising an array of chip sockets 1012 each surrounded and defined by a polymer matrix framework 1018 comprising a grid of copper vias 1014 through the polymer 1016 of the polymer matrix framework 1018. it can. The polymer matrix 1016 typically includes a glass fiber reinforcement and is most commonly made of a resin-impregnated knitted fiber prepreg.

      Each chip socket 1012 is therefore surrounded by a frame 1018 of a polymer matrix 1016 with a plurality of copper through vias through a frame 1018 disposed around the socket 1012 '.

      The frame 1018 can be made of a polymer applied as a polymer sheet or can be a glass fiber reinforced polymer applied as a prepreg. More details can be found below where the method of fabrication is discussed with reference to FIGS.

      Referring to FIG. 18, Applicant Zhuhai Access panel 1020 is generally in a 2 × 2 array of blocks 1021, 1022, 1023, 1024 separated from each other by a main frame consisting of a horizontal bar 1025, a vertical bar 1026 and an outer frame 1027. Divided. The block comprises an array of chip sockets 1012-FIG. Assuming 5mm x 5mm chip sockets and Access 21 "x 25" panels, this manufacturing method allows 10,000 chips to be packaged on each panel. In contrast, it is noted that fabricating a chip package on a 12 inch wafer, the largest wafer currently used in the industry, allows only 2,500 chips to be processed at a time, The economies of scale when manufacturing with large panels using Zhuhai Access technology will be understood.

      Panels suitable for this technology, however, vary somewhat in size. Generally, the panel is between about 12 inches x 12 inches and about 24 inches x 30 inches. Some standard sizes in current use are 20 inches x 16 inches, 20.3 inches x 16.5 inches and 24.7 inches x 20.5 inches.

      Not all blocks of panel 1020 need have chip sockets 1012 of the same size in them. For example, in the schematic illustration of FIG. 18, the top right block 1022 chip socket 1028 is larger than the other block 1021, 1023, 1024 chip socket 1029. In addition, one or more blocks 1022 can be used with different sized sockets to accommodate different sized chips, but any sub-array of any size produces any particular die package. So that, despite large throughput, small runs of a small number of die packages can be produced, and different die packages can be processed simultaneously for a particular customer or different Allows packages to be made for different customers. Accordingly, the panel 1020 has at least one region 1022 having a socket 1028 with a first set of dimensions for receiving one type of chip and a second set of chips for receiving a second type of chips. A second region 1021 having a socket 1029 with dimensions can be provided.

      Referring to FIG. 17 as described above, each chip socket 1012 (1028, 1029 FIG. 18) is surrounded by a polymer frame 1018 and within each block (1021, 1022, 1023, 1024-FIG. 18) a socket 1028 (1029 ) Is arranged.

      Referring to FIG. 19, a chip 1035 can be placed in each socket 1012 and the space around chip 1035 is the same polymer used to fabricate polymer 1036 or frame 1016? Or it can be filled with polymer-based composites that may not be the same. It can be, for example, a mold compound. In some embodiments, a matrix of filler polymer 1036 and a frame 1016 that is a similar polymer but with different reinforcing fibers can be used. For example, the frame can include reinforcing fibers, while the polymer 1036 used to fill the socket can be fiber free.

      Typical die sizes can be anywhere from about 1.5 mm × 1.5 mm to about 31 mm × 31 mm with slightly larger sockets to accommodate the intended dies at spaced distances. The thickness of the interposer frame must be at least the depth of the die and is preferably 10 to 100 microns. Generally, the depth of the frame is the die thickness plus an additional 20 microns.

      As a result of embedding the chip 1035 in the socket 1012, individual chips are surrounded by a frame 1038 having vias 1014 disposed therethrough around the edge of each die.

      Using Access via pillar technology, vias 1014 can be fabricated as via pillars by pattern plating or by panel plating followed by selective etching, in a polymer film or in a polymer matrix for added stability. Can be subsequently laminated with a dielectric material using a prepreg consisting of a knitted glass fiber bundle. In one embodiment, the dielectric material is Hitachi 705G. In another embodiment, MGC 832 NXA NSFLCA is used. In the third embodiment, Sumitomo GT-K can be used. In another embodiment, Sumitomo LAZ-4785 series film is used. In another embodiment, the Sumitomo LAZ-6785 series is used. For example, alternative materials include Taiyo HBI and Zaristo-125.

      Alternatively, the via can be fabricated using what is known as a drill fill technique. First, a polymer or fiber reinforced polymer matrix is fabricated and then after curing it is drilled by either mechanical drilling or laser drilling. The drill hole can then be filled with copper by electroplating.

      However, there are many advantages in making vias using via posts rather than drill fill techniques. In via pillar technology, all vias can be made simultaneously, so via pillar technology is faster than drill and fill, while holes are drilled individually. Furthermore, the drilled vias are basically cylindrical, while the via posts can have any shape. As a practical matter, all drill fill vias (within tolerance) can have the same diameter, while via posts can have different shapes and sizes. In addition, for increased rigidity, the polymer matrix is preferably a fiber that is generally reinforced by a braided bundle of glass fibers. Where the fiber in the polymer prepreg is placed on an upstanding via post and cured, the post is characterized by smooth vertical sides. However, drill fill vias are generally somewhat tapered and where the composite is pierced; vias generally have a roughness that results in stray inductances that cause noise.

      Generally, vias 1014 range from 40 microns to 500 microns wide. As required for drill fill and, as is often the case with via pillars, for example, in the case of a cylinder, each via can have a diameter in the range of 25 microns to 500 microns.

      Still referring to FIG. 19, after fabricating the polymer matrix framework 1016 with embedded vias, the socket 1012 can be fabricated by CNC or stamping. Alternatively, sacrificial copper blocks can be deposited using either panel plating or pattern plating. If the copper via post 1014 is selectively shielded, for example using photoresist, this type of sacrificial copper block can be etched away to create the socket 1012.

      The polymer framework of the socket array 1038 with vias 1014 in the frame 1038 around each socket 1012 allows for individual chip packages and built-up multilayer chip packages such as multi-chip packages and package “PoP” arrays on the packages. It can be used to create multiple chip packages including.

      Once the chips 1035 are placed in the socket 1012, they can be secured in place using a polymer 1036 such as a mold compound, dry film or prepreg.

      Referring to FIG. 20, copper routing layers 1042, 1043 can be fabricated on one or both sides of the framework 1040 in which the chip 1035 is embedded. In general, the chip 1035 is a flip chip and is connected to a pad 1043 that extends in a fan shape beyond the edge of the chip 1035. Thanks to the through via 1014, the pad 1042 on the upper surface allows to connect additional layers of the chip to PoP packaging or the like. It will be appreciated that basically the upper and lower pads 1042, 1043 allow for the construction of additional via posts and routing layers to create more complex structures.

      A dicing tool 1045 is shown. It will be appreciated that an array of chips 1035 packaged in a panel 1040 can be easily diced into individual chips 1048 as shown in FIG.

      Referring to FIG. 22, in some embodiments, adjacent chip sockets can have different dimensions including different sizes and / or different shapes. For example, the processor chip 1035 can be disposed in one socket and coupled to a memory chip 1055 disposed in an adjacent socket. When the array is diced, adjacent sockets can be held together. Thus, the package can contain multiple chips and possibly different chips, including passive filter chips, but using the techniques described above to fabricate capacitors and filters, It will be noted that they can be manufactured together as part.

      The pads 1042 and 1043 can be connected to the chip via the ball grid array BGA or the land grid array LGA. With current state-of-the-art technology, via posts can be about 130 microns long. Where chips 1035, 1055 are thicker than about 130 microns, it may be necessary to stack one via on top of another. Techniques for stacking vias are known and are discussed, among other things, in the co-continuation (Patent Document 8) and (Patent Document 9) given to Hurwitz et al.

      Referring to FIG. 23, a die package 1048 with a die 1055 in a polymer frame 1016 is shown from below so that the die 1055 is surrounded by the frame 1016 and through vias 1014 pass through the frame 1016 around the periphery of the die 1055. Provided. The die is placed in the socket and held in place by the second polymer 1036. The frame 1016 is generally made of fiber reinforced prepreg for stability. The second polymer 1036 can also be a prepreg, but can also be a polymer film or a mold compound. Generally, as shown, the through vias 1014 are simple cylindrical vias, but they can have different shapes and sizes. A part of the ball grid array of solder balls 1057 on the chip 1055 is connected to the through via 1014 by the pad 1043 in a fan-out configuration. As shown, there can be additional solder balls connected directly to the substrate under the chip. In some embodiments, for communication and data processing, at least one of the through vias is a coaxial via. In other embodiments, at least one via is a transmission line. For example, a technique for manufacturing coaxial vias is given in co-pending (Patent Document 9). A technique for manufacturing a transmission line is shown, for example, in (Patent Document 10).

      In addition to providing contacts for chip stacking, through vias 1014 surrounding the chip can be used to isolate the chip from its surroundings and provide a Faraday shield. This type of shield via can be coupled to a pad that interconnects the shield via on the chip and provides a shield thereto.

      There can be multiple rows of through vias surrounding the chip, the inner row can be used for signals and the outer row can be used for shielding. The outer row can be coupled to a solid copper block fabricated on the chip, which can function as a heat sink to dissipate the heat generated by the chip. Different dies can be packaged in this way. Of particular note is that one or more vias can be a wide range of inductors, as well as capacitors can be fabricated together, and that the inductor and capacitor are embedded in the frame to provide a filter together. It is possible to do.

      The embedded chip technology with a frame having through vias described herein is particularly suitable for analog processing because of the short contacts and the relatively small number of contacts per chip.

      It will be appreciated that the techniques described herein are not limited to packaging IC chips. In some embodiments, the die comprises a component selected from the group consisting of a fuse, a capacitor, an inductor, and a filter. Techniques for making inductors and filters are described in the co-continuation (US Pat. No. 6,057,049) granted to Hurwitz et al.

Referring to FIG. 24 and FIGS. 24 (a) to 24 (l), a method of fabricating an array of chip sockets surrounded by an organic matrix framework includes the following steps:
Obtain a sacrificial carrier 1080-24 (a).

      Optionally, a copper seed layer 1082 is applied onto the copper carrier 1080 -24 (b). An etch resistant layer 1084 is applied over the seed layer 1082 and is deposited by a physical vapor process such as −24 (c), typically made of nickel, and typically sputtering. For example, it can be alternatively deposited by electroplating or electroless plating. Other candidate materials include tantalum, tungsten, titanium, titanium-tungsten alloys, tin, lead, tin-lead alloys, all of which can be sputtered, and tin and lead are further electroplated or It can be electrolessly plated and the barrier metal layer is typically 0.1 to 1 micron thick. (Each candidate barrier layer material is later removed by a suitable solvent or plasma etch conditions). After application of the barrier layer, a further copper seed layer 1086 is applied -24 (d). The copper seed layer is typically about 0.2 to 5 microns thick.

      Steps 24 (b) through 24 (d) are for subsequent removal of the substrate by etching to ensure good adhesion of the barrier layer to the substrate, good adhesion and growth of the via, and without damaging the via. Preferred to make possible. Although the best results include these steps, they are optional, however, one or more may not be used.

      A layer of photoresist 1088 is then applied—step 24 (e), FIG. 24 (e), and patterned with a copper via pattern—24 (f). Copper 1090 is then plated into the pattern -24 (g) and the photoresist 1088 is stripped off -24 (h). Upright copper vias 1090 are laminated −24 (i) with polymer dielectric 1092 which can be a fiber reinforced polymer matrix prepreg. The stacked via array is thinned and planarized to expose the end of the copper vias -24 (j). The carrier is then removed.

      Optionally and preferably, the planarized polymer dielectric with the exposed end of the copper via is etched resistant, such as a photoresist or dielectric film, before the copper carrier 1080 is removed -24 (l). Protected by applying material 1094 -24 (k). Generally, the carrier is a copper carrier 1080 that is removed by dissolving copper. Ammonium-hydroxide or copper chloride can be used to dissolve copper.

      The barrier layer can then be etched away -24 (m) and the etch protection layer 1094 can be removed-step 24 (n).

      Although not described here, it will be understood that upright copper vias are made by panel plating and that excess copper can be selectively etched away to leave the vias. In fact, sockets can alternatively be fabricated by selectively etching away portions of the copper panel, while shielding the vias.

      It will be appreciated that one or more vias 1090 can be the modified via 5 of FIG. 1 including the capacitor 6 therein. Further, one or more vias can be the inductor via 7 of FIG.

      There is a via pillar technology in which only a simple via 1090 is required and not only the modified via 5 of FIG. 1 including the capacitor 6 or the inductor via 7 of FIG. 1 but only a simple cylindrical via is required. Although preferred, drill and fill techniques can also be used.

      With reference to FIG. 25 and FIGS. 25 (a) to 25 (e), in another modification method, a carrier made of a copper clad laminate (CCL) 1100 is obtained −25 (a). CCL has a thickness of tens to hundreds of microns. A typical thickness is 150 microns. A hole 1102 is drilled through CCL-25 (b). The hole 1102 can have a diameter of tens to hundreds of microns. Generally, the hole diameter is 150 microns.

      The through hole is then plated to create a plated through hole 1104 -25 (c).

      The copper clad laminate 1100 is then polished or etched to remove the surface copper layers 1106, 1108 leaving a laminate 1110 with plated through-hole (Pth) copper vias 1104 -25 (d).

      Next, using CNC or stamping, a socket 1112 is made through the laminate to accommodate the chip-25 (e).

      Referring to FIG. 26, a plan view of a frame 2000 with an embedded filter 2002 therein is shown, and various routing vias 2004 have sockets 2006 for housing chips such as processor chips or memory chips. Can be contained. This type of frame 2000 can be fabricated as part of a larger array, such as that shown in FIGS. 17-19, for example. The frame 2000 as shown includes a single socket 2006 for receiving a single chip. However, it will be appreciated that the frame may include more than one socket for receiving more than one chip. This type of socket 2006 can be used to embed a passive chip with a processor chip, a memory chip or a filter embedded therein.

      This specification has described in considerable detail how inductors and capacitors can be fabricated as embedded passive elements in organic substrates. This type of capacitor and inductor combination can provide a filter. The specification then continues to illustrate how polymer frames with embedded vias can be fabricated and how they can be used as sockets for embedded active devices. The combination of these technologies allows for the fabrication of packages with one or more embedded chips and embedded filters for very small highly integrated RF components that include both active and passive components.

      The above description is provided for illustrative purposes only. It will be appreciated that the present invention is capable of many variations.

      Several embodiments of the present invention have been described. Nevertheless, it will be understood that various modifications can be made without departing from the spirit and scope of the invention. Accordingly, other implementations are within the scope of the following claims.

      Accordingly, those skilled in the art will recognize that the present invention is not limited to what has been particularly described above with reference to the figures. Rather, the scope of the present invention is defined by the appended claims, and combinations and subcombinations of the various features described above, as well as variations and modifications that would immediately occur to those skilled in the art upon reading the foregoing description. Includes both changes.

      In the claims, the terms “comprise” and variations thereof, such as “comprises”, “comprising”, etc. include the recited components, but generally others Indicates that it is not an exclusion of

1 Frame 2 Socket Cavity 4 Via Pillar 5 Via Pillar 6 Via Pillar Capacitor Dielectric 7 Via Pillar 8, 9 Capacitor 10 Polymer Dielectric Filler 11, 12 Feature 13 Inductor 14 Substrate 20 Capacitor 21 Substrate 22 Dielectric Layer 24 Feature Layer 26, 28, 30, 32 Copper pillar 34 Encapsulating dielectric material 38 Feature layer 40 Inductor 42 Via pillar 44 Capacitor 52 Via pillar 54 Capacitor 56 Inductor via 58 Trace 60 First inductor 62 Via pillar 64 Capacitor 66 Second inductor 70 Inductor 71 72 Via pillar 74 Capacitor 78 Trace connector 84 Capacitor 86 Inductive via 88 Inductor trace 208 Photoresist layer 210 Carrier 212 Barrier metal layer 214 Copper layer 216 First electrode 218 Dielectric layer 220 1st Two electrodes 222 Copper layer 224 Photoresist layer 226 Seed layer 228 Photoresist layer 230 Photoresist layer 232 Via pillar Interconnect 234 Dielectric material 236 Seed layer 238 Photoresist layer 240 Feature layer Copper layer 242 Photoresist layer 244 Copper via 246 Polymer layer 248 Capacitor 250 Composite structure 252 Titanium seed layer 254 Copper layer 256, 258 Photoresist 260 Copper filter 262 Copper 264 Solder mask 300 Basic LC low-pass filter 348 Capacitor 1010 Array 1012 Chip socket 1012 'Socket 1014 Metal via 1016 Polymer matrix Frame 1018 polymer matrix framework 1020 panel 1021, 1022, 1023, 1024 block 1025 horizontal bar 1026 Straight bar 1027 Outer frame 1028 Chip socket 1029 Chip socket 1035 Chip 1036 Polymer 1038 Frame Socket array 1040 Framework panel 1042 Routing layer pad 1043 Routing layer pad 1045 Dicing tool 1048 Chip die package 1055 Memory chip 1057 Solder ball 1080 Carrier 1082 Seed layer 1084 Etch resistant layer 1086 Seed layer 1088 Photoresist layer 1090 Copper via 1092 Polymer dielectric 1094 Etch resistant material 1100 CCL
1102 Hole 1104 Through-hole 1106, 1108 Copper layer 1110 Laminate 1112 Socket 1200 Coil 1202 Dielectric frame 1204 Cavity 1206, 1207, 1208 Via pillar 1209, 1210 Vertical element 1250 Capacitor 2000 Frame 2002 Embedded filter 2004 Routing via 2006 Socket

Claims (61)

      A chip socket defined by an organic matrix framework, wherein the organic matrix framework includes an upper electrode through which a at least one via contacts a lower electrode, a dielectric layer and a via post through a frame around the socket. A chip socket comprising at least one via post layer including at least one capacitor. The capacitor dielectric comprises at least one of the group consisting of Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO _3, BaO ₄ SrTi and Al ₂ O _3. Item 2. The chip socket according to Item 1.       The chip socket according to claim 1, wherein the lower electrode of the capacitor includes a noble metal.       The chip socket according to claim 1, wherein the lower electrode comprises a metal selected from the group consisting of gold, platinum, and tantalum.       The chip socket according to claim 1, wherein the upper electrode includes a metal selected from the group consisting of gold, platinum, and tantalum.       2. The chip socket according to claim 1, wherein the at least one via stands on the at least one capacitor.       The chip socket according to claim 6, wherein the upper electrode includes the via pillar.       The chip socket of claim 1, wherein the capacitor has a cross-sectional area defined by a cross-sectional area of the via post that is carefully controlled to adjust a capacitance of the capacitor.       The chip socket according to claim 1, wherein the at least one capacitor has a capacitance between 1.5 pF and 300 pF.       The chip socket of claim 1, wherein the at least one capacitor has a capacitance between 5 pF and 45 pF.       The chip socket of claim 1, wherein the framework further comprises at least one feature layer.       The chip socket of claim 1, wherein at least one electronic component is embedded in the socket and electrically connected to the at least one via.       The chip socket according to claim 1, wherein the at least one electronic component includes a second capacitor.       14. The chip socket of claim 13, wherein the second capacitor is a discrete component having a metal termination on at least one end.       The chip socket of claim 13, wherein the second capacitor is a metal-insulator-metal (MIM) capacitor. The metal-insulator-metal (MIM) capacitor is composed of at least one of the group consisting of Ta ₂ O ₅ , TiO ₂ , Ba _x Sr _1-x TiO ₃ , BaTiO ₃ , BaO ₄ SrTi and Al ₂ O _3. The chip socket according to claim 13, further comprising a dielectric layer.       14. The chip socket of claim 13, wherein the lower electrode of the metal-insulator-metal (MIM) capacitor comprises a noble metal.       The chip socket according to claim 13, wherein the lower electrode comprises a metal selected from the group consisting of gold, platinum, and tantalum.       The chip socket of claim 1, wherein the metal-insulator-metal (MIM) upper electrode comprises a metal selected from the group consisting of gold, platinum, and tantalum.       14. The chip socket of claim 13, wherein the metal-insulator-metal (MIM) capacitor is attached to an insulator carrier. Claim wherein the insulating material carrier, silicon (Si), SiO ₂ (silica), characterized glass, AlN, of the group consisting of alumina and c- plane sapphire _Al 2 _O 3 (0001) in that it comprises at least one 14. The chip socket according to 13.       14. The chip socket of claim 13, wherein the metal-insulator-metal (MIM) capacitor plates to be connected are connected to vias by a feature layer.       23. The chip socket of claim 22, wherein the feature layer on one side of the frame and embedded component comprises an inductor.       23. The chip socket of claim 22, wherein an embedded component in at least one feature in the frame, socket, and feature layer provides a filter.       23. The chip socket of claim 22, wherein the filter is selected from the group consisting of a basic LC low pass filter, an LC high pass filter, an LC serial band filter, an LC parallel band filter and a low pass parallel Chebyshev filter. .       The chip socket of claim 1, wherein a chip mounted in the socket is protected from electromagnetic radiation by a Faraday cage with via posts in the frame, thereby minimizing electromagnetic interference.       27. The chip socket of claim 26, wherein at least some of the via posts extend in an XY plane.       A framework comprising a plurality of sockets for receiving a plurality of chips, each socket comprising a frame, and the framework comprising a gridwork of copper via posts and at least one capacitor. work.       29. The framework of claim 28, wherein the processor chip is embedded in one socket and a passive chip comprising at least one capacitor is embedded in the second socket.       A framework comprising a plurality of chip sockets arranged in an array in which each chip socket is surrounded by a frame.       The framework of claim 30, wherein at least one processor chip is embedded in at least one socket.       An array of chip sockets defined by the organic matrix framework of a frame surrounding the socket and further comprising a grid of metal via pillars through the organic matrix framework, wherein the at least one via pillar is at least one capacitor and An array characterized by being connected in series.       The capacitor comprises a lower electrode, a dielectric layer, and is incorporated into the base of the at least one via post such that the at least one via post stands on the at least one capacitor; 33. The array of claim 32.       The arrangement of claim 32, wherein the at least one via post further comprises an upper electrode of the at least one capacitor.       33. The arrangement of claim 32, wherein the frame comprises at least one feature layer, and at least one inductor is formed in the at least one feature layer.       The arrangement of claim 32, wherein the organic matrix framework further comprises a glass fiber bundle.       33. The arrangement of claim 32, wherein each via ranges in width from 25 microns to 500 microns.       33. The array of claim 32, wherein each via is cylindrical and has a diameter in the range of 25 microns to 500 microns.       33. The arrangement of claim 32, wherein the frame around at least one socket comprises alternating via posts and feature layers and comprises at least one via post layer and one feature layer.       The arrangement of claim 32, wherein the grid of metal via posts comprises a plurality of via layers through the organic matrix framework.       33. The arrangement of claim 32, wherein the frame around at least one socket comprises alternating via post and feature layer continuous coils spanning at least one via post layer and one feature layer. .       The arrangement of claim 32, wherein the at least one via post comprises an elongated via post.       The arrangement of claim 32, wherein the elongated via post continuous coil spans multiple via post layers.       33. The arrangement of claim 32, comprising adjacent chip sockets of different dimensions.       44. The arrangement of claim 43, comprising adjacent chip sockets of different sizes.       43. The arrangement of claim 42, comprising adjacent chip sockets of different shapes.       The framework includes at least one feature layer and at least one adjacent via layer, the layer extends in an XY plane and has a height z, and the composite electronic structure has at least one At least one capacitor coupled to the inductor, wherein the at least one via stands on the at least one capacitor and optionally forms an upper electrode. Embedded in a base of a via layer comprising a lower electrode and a dielectric layer and sandwiched between the at least one feature layer and a via post, the via layer embedded in a polymer matrix; and The at least one inductor is formed in at least one of the first feature layer and the adjacent via layer. Sequence according to claim 32,.       The arrangement of claim 32, wherein the at least one capacitor and the at least one inductor are connected in series.       The frame comprises at least a second feature layer on the via layer, and the at least one capacitor and the at least one inductor are connected in parallel via the feature layer. 33. The sequence of claim 32.       50. The arrangement of claim 49, wherein the at least one inductor is fabricated in the feature layer.       The arrangement of claim 32, wherein the at least one inductor is wound in a spiral.       33. The arrangement of claim 32, wherein the inductance of the inductor is at least 0.1 nH.       33. The array of claim 32, wherein the inductance is less than 50 nH.       The arrangement of claim 32, wherein the further inductor is fabricated in the via layer.       55. The arrangement of claim 54, wherein the inductance of the further inductor is at least 0.1 nH.       At least one inductor and the at least one capacitor provide a filter selected from the group consisting of a basic LC low pass filter, an LC high pass filter, an LC series band pass filter, an LC parallel band pass filter and a low pass parallel Chebyshev filter. 33. The array of claim 32.       At least one socket is filled with a chip comprising at least one capacitor in a polymer matrix, and the framework and chip are thinned to expose the end of the via, and the connection and termination are said to be Applied by placing a photoresist on each side of the thinned polymer matrix; and depositing a copper pad on the photoresist pattern, the photoresist is then stripped off, and a solder mask between the copper pads 32. The panel of claim 30, wherein the protective coating is applied as well as a protective coating.       A panel comprising an array of chip sockets, each surrounded and defined by the organic matrix framework comprising a grid of copper via posts through an organic matrix framework, the panel containing one type of chip At least one region having a socket with a first set of dimensions to do and a socket with a second set of dimensions to accommodate a second type of chip, and at least one The via pillar comprises a second region including a thin film capacitor.       59. The panel of claim 58, wherein the at least one via post stands on the thin film capacitor.       59. The panel of claim 58, wherein the at least one via post comprises an upper electrode of the thin film capacitor.       59. The panel of claim 58, comprising a region with two different socket types in close proximity.

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