JP2009055019A - Multi-layered substrate, package substrate for semiconductor integrated circuit, and printed wiring board for semiconductor integrated circuit packaging - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a multilayer substrate including a structure which realizes impedance matching between a longitudinal signal transmission path between an external terminal and a signaling wiring conductor formed on each layer and a ground surrounding it. <P>SOLUTION: A coil structure 110 having inductance which offsets or eases influence of a parasitic capacitance generated around a parasitic capacitance generating part in the longitudinal signal transmission path between a signaling solder ball 1S3 that is an external connection terminal and a signaling wiring conductor 1S51 disposed on a layer other than the layer on which the external connection terminal 1S3 is disposed. The coil structure 110 comprises combinations of a plurality of vias 112 to 119 which connect adjacent two layers and signaling wiring conductors 1S53 and 1S54 disposed on respective layers and connected to the vias through via lands 1S23 and 1S24, for example. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multilayer substrate on which a semiconductor integrated circuit is mounted as a device for realizing a certain function, and more particularly as a package substrate for a semiconductor integrated circuit and a printed wiring board for mounting a semiconductor integrated circuit that enable high-speed transmission of digital signals. The present invention relates to a multilayer substrate suitable for use.

  A multilayer substrate on which a semiconductor integrated circuit as a device for realizing a certain function is mounted is provided with a signal wiring conductor, a via connecting it to a signal external connection terminal, and a via land surrounding each via in each layer, In addition, a ground conductor (plane or wiring), vias connecting the conductors to the ground external connection terminals, and via lands surrounding the vias in each layer are provided.

  By the way, in a package substrate for a semiconductor integrated circuit and a printed wiring board for mounting a semiconductor integrated circuit configured using such a multilayer substrate, when further increasing the speed of a digital signal to be transmitted, an external connection terminal and its external Parasitic capacitance that exists between the vertical signal transmission path between the signal wiring conductors arranged in a layer other than the layer where the connection terminal is arranged and the ground surrounding the vertical signal transmission path, This causes an abrupt impedance change in the vertical signal transmission path, which causes deterioration of transmission characteristics.

  Various proposals have conventionally been made as measures for reducing the parasitic capacitance. For example, in Patent Document 1 and Non-Patent Document 1, as a measure for reducing parasitic capacitance in a package substrate for a semiconductor integrated circuit mounted on a printed wiring board such as a motherboard, vertical signal transmission in the package substrate for the semiconductor integrated circuit is performed. In order to suppress a rapid impedance change in the path, in each layer of the multilayer substrate that is a package substrate for a semiconductor integrated circuit, a non-conductive region is expanded by hollowing out the ground conductor surrounding the via land of the signal transmission path, that is, the conductor layer A method has been proposed in which the region of the dielectric layer between the signal conductor and the GND conductor is expanded.

JP 2002-299502 A “Packaging a 40-Gbps Serial Link Using a Wire-Bonded Plastic Ball Grid Array” IEEE Design & Test of Computers, May-June 2006, pp. 212-219

  However, as in the conventional technique, in each layer of the multilayer substrate, in the method of hollowing out the ground conductor surrounding the periphery of the signal wiring via land and providing the non-conductor region, when the non-conductor region becomes wide, in each layer of the multilayer substrate, A difference in thickness occurs at the boundary between the portion where the ground conductor is cut out and the portion where the ground conductor remains. In the production of a multilayer substrate, this difference in thickness is laminated, so that a step that cannot be ignored appears in the uppermost layer. Then, in the uppermost layer, there is a possibility that the signal wiring straddling the step region is disconnected due to the step.

  In addition, since there is a region in which there is almost no ground conductor around the signal path, there is a possibility that radiation noise increases.

  The present invention has been made in view of the above, and a structure for impedance matching between a vertical signal transmission path between an external connection terminal and a signal wiring conductor provided in each layer and a ground surrounding the signal transmission path. And a printed circuit board for mounting a semiconductor integrated circuit using the multilayer substrate.

  In order to achieve the above-described object, the present invention provides a multilayer substrate on which a semiconductor integrated circuit as a device for realizing a certain function is mounted, except for the external connection terminal of the multilayer substrate and the layer in which the external connection terminal is disposed. There is at least one coil structure having an impedance component that cancels or mitigates the influence of the generated parasitic capacitance in the vicinity of the parasitic capacitance generation location in the vertical signal transmission path between the signal wiring conductor and the signal wiring conductor. It is characterized by being arranged.

  According to the present invention, the coil structure interposed in the vertical signal transmission path between the external connection terminal and the signal wiring conductor provided in each layer cancels out or reduces the influence of the parasitic capacitance. Impedance matching between the path and the ground surrounding it can be achieved. As a result, there is an effect that it is possible to improve the deterioration of the transmission characteristics due to the influence of the parasitic capacitance.

  First, in order to facilitate understanding of the present invention, referring to FIG. 1 to FIG. 5, a configuration example of a multilayer board targeted by the present invention and between external connection terminals and signal wiring conductors provided in each layer Transmission characteristics in the vertical signal transmission path will be described. FIG. 1 shows the layout of each layer of a package substrate for a semiconductor integrated circuit, which is one of the multilayer substrates targeted by the present invention, and a printed wiring board, which is also a multilayer substrate on which the package substrate for the semiconductor integrated circuit is mounted. FIG. FIG. 2 is a cross-sectional view taken along line XZ shown in FIG. 1 (cross-sectional view showing the XZ plane). 3 is a cross-sectional view taken along line YZS shown in FIG. 1 (a cross-sectional view showing a longitudinal signal path on the YZ plane). 4 is a cross-sectional view taken along line YZG shown in FIG. 1 (a cross-sectional view showing a vertical direction GND path on the YZ plane). FIG. 5 is an equivalent circuit diagram of the transmission circuit including the parasitic capacitance generated in the vertical signal transmission path of the multilayer substrate shown in FIG.

  As shown in FIG. 1, a package substrate for a semiconductor integrated circuit (hereinafter simply referred to as “package substrate”) 100 is composed of, for example, four layers. In FIG. 1, from the top to the bottom, the first layer 1L1 to the fourth layer 1L4 are shown. And the printed wiring board 200 which is mounting object is shown under 1L4 of the 4th layer. Here, from the viewpoint of clarifying the problems raised in Patent Document 1 and Non-Patent Document 1, transmission characteristics on the printed wiring board 200 side in the package substrate 100 will be taken up. The illustration of the semiconductor integrated circuit mounted on the upper surface of the first layer 1L1 is omitted. That is, in FIG. 1 to FIG. 4, only the terminals (1S3, 1G3) for connecting to the printed wiring board 200 are shown as the “external connection terminals” in the package substrate 100. The “terminal” includes a terminal for connecting to a semiconductor integrated circuit (not shown) mounted on the upper surface of the first layer 1L1.

  The printed wiring board 200 is also one of the multilayer boards to which the present invention is applied as a printed wiring board for mounting a semiconductor integrated circuit including the package board 100. Here, as described above, the package board is used. Since the transmission characteristics at 100 are taken up, the configuration of the printed wiring board 200 is simplified as shown in FIGS. 2 to 4, the first layer 2L1 and the second layer 2L2 are shown from top to bottom.

  A configuration of the package substrate 100 will be described. 1-4, the code | symbol 101 is a dielectric material layer. The dielectric layer 101 is generally composed of a dielectric layer for a core layer, a dielectric layer for a buildup layer, and a solder resist, but is used without distinction here. Reference numeral 1S1 is a signal via, and reference numeral 1G1 is a GND (ground) via.

  Reference numeral 1S2 is a signal via land. The signal via land 1S2 is provided so as to surround the signal via 1S1 in each layer. Reference numeral 1G2 is a via land for GND. The GND via land 1G2 is provided so as to surround the periphery of the GND via 1G1 in each layer. Reference numeral 1S3 denotes a signal solder ball. The signal solder ball 1S3 is the signal external connection terminal described above. Reference numeral 1G3 denotes a GND solder ball. The GND solder ball 1G3 is the ground external connection terminal described above.

  Reference numeral 1S4 denotes a signal ball pad. The signal ball pad 1S4 is provided so as to surround the periphery of the signal via land 1S2 in the fourth layer 1L4. Reference numeral 1G4 is a ball pad for GND. The GND ball pad 1G4 is provided to surround the GND via land 1G2 in the fourth layer 1L4. Reference numeral 1S5 denotes a signal wiring conductor provided in each layer. Reference numeral 1G6 is a GND plane provided between the layers.

  A configuration of the printed wiring board 200 will be described. 1-4, the code | symbol 201 is a dielectric material layer. The dielectric layer 201 is generally composed of an interlayer dielectric layer and a solder resist, but is used here without distinction. Reference numeral 2G1 is a GND through hole, and reference numeral 2G2 is a GND through hole land. Reference numeral 2S4 is a signal ball pad, and reference numeral 2G4 is a GND ball pad. Reference numeral 2S5 is a signal wiring conductor. The signal wiring conductor 2S5 is connected to the signal ball pad 2S4 in the first layer 2L1. Reference numeral 2G6 is a GND plane provided between the two layers.

  As described above, the package substrate 100 is mounted on the printed wiring board 200 using a ball grid array structure that can shorten the connection terminal length.

  In the above configuration, transmission characteristics of high-speed signals between the package substrate 100 and the printed wiring board 200 will be described. In high-speed serial signal transmission, there is a case where a differential transmission system is used in which a pair of two signals of a normal phase signal and a reverse phase signal is employed. 4, two signal solder balls 1S3 are shown as signal external connection terminals, and two GND solder balls 1G3 are shown as GND external connection terminals. That is, one of the two signal solder balls 1S3 and one of the two GND solder balls 1G3 are used to transmit one of the two system signals, and the other of the two signal solder balls 1S3 and two of the two solder balls 1S3. The other of the two system signals can be transmitted using the other of the solder balls for GND 1G3. However, there may be only one GND ball or three or more solder balls for a differential transmission.

  In the high-speed serial signal output from the package substrate 100 to the printed wiring board 200, each of the two system signals whose high level and low level are opposite to each other is a signal provided in each layer of the package substrate 100 from a semiconductor integrated circuit (not shown). Applied to the corresponding one of the wiring conductors 1S5 for use. The high-speed serial signal applied to the signal wiring conductor 1S5 is transmitted to the signal via land 1S2, the signal via 1S1, the ball pad 1S4, the corresponding signal solder ball 1S3, and the ball pad 2S4 on the printed wiring board 200 provided in each layer. Then, the signal is transmitted to the signal wiring conductor 2S5 on the printed wiring board 200 side. When a high-speed serial signal is input from the printed wiring board 200 to the package substrate 100, the above path is transmitted in the reverse direction.

  Here, the signal wiring conductor 1S5 provided on each layer of the package substrate 100 and the signal wiring conductor 2S5 on the printed wiring board 200 side have a wiring width and an inter-wiring space so that the impedance matches the input / output impedance. The dimensions such as the space between the wiring and the GND plane are designed. For example, in the case of a general differential signal, the wiring differential impedance Zdiff is designed to be 100Ω. The common mode impedance Zcomm is also designed to be within various standards. This matches the input / output impedance of a semiconductor integrated circuit (not shown) mounted on the package substrate 100, suppresses signal reflection, and maintains the signal waveform quality.

  However, in recent years, it has become necessary to respond to requests for further speeding up of transmission signals. The problem in this case is the influence of the parasitic capacitance generated between the vertical signal transmission path and the GND surrounding it. Specifically, this is the influence of parasitic capacitance generated between the signal ball pads 1S4 and 2S4, the signal via land 1S2 and the signal via 1S1, and the peripheral GND solder balls 1G3 and the GND planes 1G6 and 2G6. .

  That is, as shown in FIG. 5, the vertical signal transmission path between the package substrate 100 and the printed wiring board 200 has signal wiring conductors 1S5 provided on each layer of the package substrate 100 and signal wiring on the printed wiring board 200 side. It is equivalently represented as a transmission circuit in which a parasitic capacitance (value Cp1 [pF]) 5C1 exists between the connection end between the wiring conductor 2S5 and GND. In general, parasitic inductance and parasitic inductance are generated at the same time. However, in this case, it is assumed that the influence of the parasitic inductance is smaller than that of the parasitic capacitance.

  When the frequency increases, the parasitic capacitance 5C1 lowers the impedance between the vertical signal transmission path and GND, so that reflection occurs in the vertical signal transmission path and normal signal transmission is not performed. This phenomenon becomes more prominent as the transmission signal becomes faster.

  In order to solve this problem, in Patent Document 1 and Non-Patent Document 1 described above, in the package substrate 100, each layer (first layer to fourth layer) above the signal solder ball 1G3 which is an external connection terminal is defined. The GND plane 1G6 surrounding the periphery of the signal via land 1S2 is cut out with a diameter equal to or larger than that of the signal ball pad 1S4 to widen the area of the dielectric layer 101 in each of the first to fourth layers. A method has been proposed. However, in this method, as described above, there is a risk of disconnection in the signal wiring straddling the step portion generated in the uppermost layer 1L1, and radiation noise is generated by generating a region without GND around the signal path. There can be an increase.

  Therefore, according to the configuration examples shown in FIGS. 1 to 4, the present invention does not widen the area of the dielectric layer 101 around the signal via land 1 </ b> S <b> 2 in each layer of the package substrate 100, but for the signal of the package substrate 100. In the longitudinal signal transmission path between the wiring conductor 1S5 and the signal solder ball 1S3 which is an external connection terminal, a coil structure having an inductance component which cancels or mitigates the influence of the parasitic capacitance generated as described above is interposed. Thus, impedance matching between the vertical signal transmission path and the surrounding GND is achieved to improve high frequency characteristics.

  A preferred embodiment of a multilayer substrate according to the present invention will be described in detail below with reference to the drawings. First, as a first and second embodiment, a coil structure which is a configuration of the present invention is used as a longitudinal signal. The method of interposing in the transmission path and the improvement effect of the high frequency characteristics will be described, and then specific configuration examples of the coil structure will be described as Embodiments 3 to 12. In the first to twelfth embodiments, application examples to the ball grid array type package substrate shown in FIGS. 1 to 4 are shown. However, the package substrate to which the present invention can be applied is limited to this ball grid array type. It is not something.

Embodiments 1 and 2.
FIG. 6 is an equivalent circuit diagram of a transmission circuit for explaining a method (No. 1) of interposing a coil structure according to the present invention in a longitudinal signal transmission path as Embodiment 1 of the present invention. FIG. 7 is an equivalent circuit diagram of a transmission circuit for explaining a method (part 2) of interposing a coil structure according to the present invention in a longitudinal signal transmission path as a second embodiment of the present invention. 6 and 7 are equivalent circuit diagrams in the case where the coil structure according to the present invention having an inductance component that cancels or reduces the influence of the parasitic capacitance is interposed in the transmission circuit shown in FIG.

  First, in FIG. 6, the parasitic capacitance 5C1 (value Cp1 [pF]) shown in FIG. 5 is divided into two parasitic capacitances 5C2 (value Cp2 [pF]) and 5C3 (value Cp3 [pF]). The combined capacitance value “Cp1 + Cp2” of the capacitors 5C2 and 5C3 is substantially equal to the value Cp1 of the parasitic capacitor 5C1, but a configuration in which the coil structure 5L1 is interposed in the signal path between the parasitic capacitors 5C2 and 5C3 is shown.

  The inductance component value Lc1 [nH] of the coil structure 5L1 is a value that can achieve impedance matching with GND by canceling or mitigating the influence of the parasitic capacitances 5C2 and 5C3, that is, the influence of the parasitic capacitance 5C1.

  Next, in FIG. 7, the parasitic capacitance 5C1 (value Cp1 [pF]) shown in FIG. 5 is replaced with the parasitic capacitances 5C4 (value Cp4 [pF]), 5C5 (value Cp5 [pF]), 5C6 (value Cp6 [pF]). ), That is, the combined capacitance value “Cp3 + Cp4 + Cp6” of the parasitic capacitances 5C4, 5C5, and 5C6 is substantially equal to the value Cp1 of the parasitic capacitance 5C1, but in the signal path between the parasitic capacitances 5C3 and 5C4, the coil structure A configuration in which a coil structure 5L3 is interposed in the signal path between the parasitic capacitors 5C5 and 5C6 is shown.

  The value of the inductance component that the coil structure 5L2 has is Lc2 [nH], the value of the inductance component that the coil structure 5L3 has is Lc3 [nH], and the synthesis of the inductance components that the coil structures 5L2 and 5L3 have The value “Lc2 + Lc3” is substantially equal to the inductance component value Lc1 of the coil structure 5L1.

  In other words, in FIG. 7, the generated parasitic capacitance is divided into three, and the coil structure is interposed in the signal path between them to cancel or alleviate the influence of the parasitic capacitance as in FIG. A case of impedance matching is shown.

  Next, the improvement effect of the high frequency characteristic by the structure of this invention which interposes the coil structure which has an inductance component shown in FIG. 6, FIG. 7 with reference to FIG. 8, FIG. 9 is demonstrated. FIG. 8 is a TDR waveform diagram showing a comparison of impedance characteristics of the transmission circuits shown in FIGS. 5 to 7 measured using the TDR method (Time Domain Reflectometry). FIG. 9 is a diagram comparing the passage loss characteristics of the transmission circuits shown in FIGS.

  In FIG. 8, the horizontal axis represents time [ns], and the vertical axis represents impedance Z [Ω]. Reference numeral 5TA denotes a TDR waveform of impedance characteristics in the transmission circuit shown in FIG. Reference numeral 5TB denotes a TDR waveform of impedance characteristics in the transmission circuit shown in FIG. Reference numeral 5TC denotes a TDR waveform of impedance characteristics in the transmission circuit shown in FIG.

  As shown in FIG. 5, when the parasitic capacitance 5C1 is present in the vertical signal transmission path, as shown by the TDR waveform 5TA in FIG. This indicates that a large negative reflection occurs.

  On the other hand, when the coil structure 5L1 is interposed in the longitudinal signal transmission path as shown in FIG. 6, the influence of the parasitic capacitance 5C1 is canceled or alleviated as shown by the TDR waveform 5TB in FIG. However, the fluctuation range is smaller than that of the TDR waveform 5TA.

  Further, when the coil structures 5L2 and 5L3 are interposed in the vertical signal transmission path as shown in FIG. 7, the influence of the parasitic capacitance 5C1 is canceled or reduced as shown by the TDR waveform 5TC in FIG. Although it changes to the higher side, the fluctuation range is smaller than the TDR waveform 5TB.

  Next, in FIG. 9, the horizontal axis represents the frequency [Hz], and the vertical axis represents the passing parameter S21 [dB]. Reference numeral 5FA denotes a passage loss characteristic in the transmission circuit shown in FIG. Reference numeral 5FB denotes a passage loss characteristic in the transmission circuit shown in FIG. Reference numeral 5FC denotes a passage loss characteristic in the transmission circuit shown in FIG.

  As shown in the passage loss characteristic 5FA, in the transmission circuit shown in FIG. 5, the passage loss is larger than the wiring loss from the low frequency stage, and increases almost linearly with a large slope as the frequency increases. Therefore, as the transmission signal becomes faster, normal signal transmission cannot be performed.

  On the other hand, as shown in the passage loss characteristic 5FB, in the transmission circuit shown in FIG. 6, the passage loss recovers from a frequency that can be regarded as direct current to a certain frequency to the same level as the wiring loss. That is, since the frequency at which the passage loss increases rapidly can be shifted to a higher frequency, the high frequency transmission characteristics are improved to be better than the transmission circuit shown in FIG.

  Furthermore, as shown in the passage loss characteristic 5FC, in the transmission circuit shown in FIG. 7, the frequency at which the passage loss rapidly increases can be made higher than the passage loss characteristic 5FB, and the high frequency transmission characteristic is further improved. The

  In this case, as can be understood from the characteristic comparison shown in FIGS. 8 and 9, the value of the generated parasitic capacitance is divided into four or more, and the coil structure is interposed in the signal path between the divided parasitic capacitances. In other words, if three or more coil structures are dispersed and interposed in the longitudinal signal transmission path, a further improvement effect of the high-frequency transmission characteristics can be obtained.

  As described above, according to the first and second embodiments, in the longitudinal signal transmission path in the package substrate 100, the coil structure having an inductance component that cancels or reduces the influence of the parasitic capacitance in the vicinity where the parasitic capacitance exists. By interposing at least one body, impedance matching with surrounding GND can be achieved, and high frequency characteristics can be improved.

  Hereinafter, a specific configuration example of the coil structure according to the present invention will be described. For convenience of explanation, the coil structure disposed on the four-layer package substrate 100 mounted on the printed wiring board 200 shown in FIGS. 1 to 4 is shown. Although described using member names, the coil structure according to the present invention is not limited to a multilayer substrate having a four-layer structure.

Embodiment 3 FIG.
FIG. 10 is a conceptual perspective view showing a configuration example (No. 1) of a coil structure provided in a vertical direction signal transmission path of a multilayer board according to the present invention as Embodiment 3 of the present invention. In FIG. 10, for easy understanding, only the signal path portion where the coil structure in the vertical signal transmission path is provided is shown, and the surrounding GND is omitted.

  10, between the printed wiring board 200 and the package substrate 100, the signal ball pad 2S4 to which the signal wiring conductor 2S5 on the printed wiring board 200 is connected and the fourth layer 1L4 on the package substrate 100 are provided. The signal ball pad 1S4 is connected via a signal solder ball 1S3 as a signal external connection terminal of the package substrate 100.

  The vertical direction signal transmission path in the package substrate 100 is a path from the signal ball pad 1S4 to the signal wiring conductor in each layer in the package substrate 100 (the third layer 1L3 to the uppermost first layer 1L1). In the longitudinal signal transmission path, one coil structure 110 that realizes the coil structure 5L1 shown in FIG. 6 is inserted into the signal path in the vicinity where the parasitic capacitance exists by the method shown in FIG.

  The coil structure 110 is configured by a combination of a plurality of vias that connect a plurality of two layers, and a signal wiring conductor that is disposed in each layer and connected to the vias via via lands. FIG. 10 shows, as an example, a structure example provided in the vertical signal transmission path between the signal ball pad 1S4 and the signal wiring conductor 1S51 in the uppermost first layer 1L1.

  The via 1S1 is a via that connects the fourth layer 1L4 and the first layer 1L1. The first layer 1L1 side end of the via 1S1 is connected to the signal wiring conductor 1S51 via the via land 1S21. The via land 1S22 is connected to the second layer 1L2 of the via 1S1, the via land 1S23 is connected to the third layer 1L3, and the via land 1S24 is connected to the end of the fourth layer 1L4.

  The coil structure 110 shown in FIG. 10 is configured as follows. In FIG. 10, a plurality of vias 112 to 112 connecting the fourth layer 1L4 and the third layer 1L3 to the path between the signal ball pad 1S4 and the via land 1S24 provided on the fourth layer 1L4 side of the via 1S1. Vias 119 are provided in a zigzag shape, and signal ball pads 1S4 are connected to the fourth layer 1L4 side ends of the vias 112 via signal wiring conductors 1S54 and via lands 1S24 provided in the fourth layer 1L4. Between each end of the fourth layer 1L4 of the via 114, between each end of the fourth layer 1L4 of the via 115 and the via 116, between each end of the fourth layer 1L4 of the via 117 and the via 118, and each of the via 119 and the via 1S1 The ends on the fourth layer 1L4 side are connected through signal wiring conductors 1S54 and via lands 1S24 provided on the fourth layer 1L4, respectively. Then, between the via 112 and the via 113 on the side of the third layer 1L3, between the via 114 and the via 115 on the side of the third layer 1L3, between the via 116 and the via 117 on the side of the third layer 1L3, and the via 118. And vias 119 are connected to each other through the signal wiring conductor 1S53 and via land 1S23 provided on the third layer 1L3.

  According to this configuration, when the signal passes through the vertical signal transmission path between the signal ball pad 1S4 and the signal wiring conductor 1S51 connected to the end of the via 1S1 on the first layer 1L1 side, it is provided in the middle. Because of the self-inductance of the coil structure 110, the influence of the parasitic capacitance in the via (1S1) and via land (1S21 to 1S24) existing outside the signal ball pad 1S4 and the coil structure 110 is offset or alleviated. The TDR waveform is improved like the TDR waveform 5TB shown in FIG. 8, and the passing loss is improved like the characteristic 5FB shown in FIG.

  As described above, according to the third embodiment, a plurality of vias connecting the plurality of two layers and the via lands are arranged in the respective layers in the vicinity of the parasitic capacitance generation portion in the middle of the vertical signal transmission path. Since one coil structure 110 composed of a combination with signal wiring conductors connected via the intervening structure is interposed, characteristic degradation due to parasitic capacitance can be improved as described with reference to FIG. Further, there is no need to add parts for improving the characteristics, so there is no increase in cost.

  In FIG. 10, the coil structure 110 is formed using the fourth layer 1L4 and the third layer 1L3. However, the coil structure 110 does not have to be two adjacent layers, and may use two layers that are not adjacent. A combination of two adjacent layers and two non-adjacent layers may be used, and the selection of the two layers to be used is arbitrary.

  FIG. 10 shows the case where the coil structure 110 is formed in a horizontal direction on the two layer surfaces to be used. However, the coil structure 110 is formed in a direction perpendicular to the layer surface by using two or more layers. It may be formed.

  FIG. 10 shows the case where the route to the signal wiring conductor provided in the uppermost first layer 1L1 is targeted, but the route to the signal wiring conductor provided in the second layer 1L2 or the third layer 1L3. The coil structure 110 may be arranged for the target.

Embodiment 4 FIG.
FIG. 11 is a conceptual perspective view showing a configuration example (No. 2) of the coil structure provided in the longitudinal signal transmission path of the multilayer substrate according to the present invention as Embodiment 4 of the present invention. In FIG. 11, for easy understanding, only the signal path portion where the coil structure in the vertical signal transmission path is provided is shown, and the surrounding GND is omitted. For convenience of explanation, the same reference numerals are given to the same or equivalent components as those shown in the first embodiment (FIG. 10). Here, the description will be focused on the portion related to the fourth embodiment.

  As shown in FIG. 11, the coil structure 125a according to the fourth embodiment has a configuration in which curved signal wiring conductors 127 are arranged in a concentric spiral shape (curve spiral shape). In FIG. 11, the number of spiral turns is shown as a plurality of turns, but it may be less than one turn or more than one turn.

  In FIG. 11, as an example, as in the first embodiment (FIG. 10), a structural example provided in the vertical signal transmission path between the signal ball pad 1S4 and the signal wiring conductor 1S51 in the uppermost first layer 1L1. It is shown. In FIG. 11, a via 128 connecting the fourth layer 1L4 and the third layer 1L3 is provided in the vicinity of the signal ball pad 1S4, and the signal ball pad 1S4 is provided at the end of the via 128 on the fourth layer 1L4 side. The signal wiring conductor 1S54 and via land 1S24 provided on the fourth layer 1L4 are connected to each other. The signal wiring conductor 127 arranged in a curvilinear spiral forming the coil structure 125a is provided in the third layer 1L3. That is, one end of the signal wiring conductor 127 arranged in a curvilinear spiral is connected to the via land 1S23 provided at the end of the via 128 on the third layer 1L3 side, and the other end of the signal wiring conductor 127 is the third layer of the via 1S1. It is connected to a via land 1S23 provided on the 1L3 side end.

  According to this configuration, when the signal passes through the vertical signal transmission path between the signal ball pad 1S4 and the signal wiring conductor 1S51 connected to the end of the via 1S1 on the first layer 1L1 side, it is provided in the middle. Because of the self-inductance of the coil structure 125a, the influence of the parasitic capacitance in the via (1S1) and via land (1S21 to 1S24) existing outside the signal ball pad 1S4 and the coil structure 125a is offset or reduced. The TDR waveform is improved like the TDR waveform 5TB shown in FIG. 8, and the passing loss is improved like the characteristic 5FB shown in FIG.

  As described above, according to the fourth embodiment, one coil structure 125a made up of the signal wiring conductor 127 arranged in a curvilinear spiral is interposed in the vicinity of the parasitic capacitance generation location in the middle of the vertical signal transmission path. Therefore, as described with reference to FIG. 6, characteristic deterioration due to parasitic capacitance can be improved. Further, there is no need to add parts for improving the characteristics, so there is no increase in cost.

  In FIG. 11, one coil structure 125a is formed on the third layer 1L3. However, any one of the four layers may be used, and selection of the layer to be used is arbitrary. Further, as a spiral mode, a double-wind mode may be used.

  FIG. 11 shows the case where the route to the signal wiring conductor provided in the uppermost first layer 1L1 is targeted, but the route to the signal wiring conductor provided in the second layer 1L2 or the third layer 1L3. The coil structure 125a may be arranged for the target.

Embodiment 5 FIG.
FIG. 12 is a conceptual perspective view showing a configuration example (No. 3) of the coil structure provided in the longitudinal signal transmission path of the multilayer substrate according to the present invention as Embodiment 5 of the present invention. In FIG. 12, for easy understanding, only the signal path portion where the coil structure is provided in the vertical signal transmission path is shown, and the surrounding GND is omitted. For convenience of explanation, the same reference numerals are given to the same or equivalent components as those shown in the third embodiment (FIG. 10) or the fourth embodiment (FIG. 11). Here, the description will be focused on the portion related to the fifth embodiment.

  As shown in FIG. 12, the coil structure 130 according to the fifth embodiment includes the coil structure 110 shown in the third embodiment (FIG. 10) and the coil structure shown in the fourth embodiment (FIG. 11). 125a is connected in series. In FIG. 12, as an example, similarly to the third embodiment (FIG. 10) and the fourth embodiment (FIG. 11), between the signal ball pad 1S4 and the signal wiring conductor 1S51 in the uppermost first layer 1L1. An example of the structure provided in the vertical signal transmission path is shown.

  The coil structure 130 shown in FIG. 12 is configured as follows. In FIG. 12, a via land 1S24 is arranged between the signal ball pad 1S4 and the end of the fourth layer 1L4 of the via 1S1, and the signal layer has a curved spiral shape that forms the coil structure 125a on the fourth layer 1L4. A wiring conductor 127 is disposed, and a signal ball pad 1S4 is connected to the via land 1S24 via a signal wiring conductor 1S54 provided on the fourth layer 1L4, and one end of the signal wiring conductor 127 having a curved spiral arrangement is connected to the via land 1S24. It is connected. The other end of the curved spiral signal wiring conductor 127 is connected to a via land 1S24 provided on the end side of the fourth layer 1L4 of the via 1S1.

  The coil structure 110 is provided between the via land 1S22 provided on the second layer 1L2 side of the via 1S1 and the signal wiring conductor 1S51 provided on the first layer 1L1. That is, the second layer 1L2 and the first layer 1L1 are connected to the signal path between the via land 1S22 provided on the second layer 1L2 side of the via 1S1 and the signal wiring conductor 1S51 provided on the first layer 1L1. A plurality of vias 132 to 136 are provided in a zigzag shape, and the via land 1S22 provided on the second layer 1L2 side of the via 1S1 is connected to the via 132 via the signal wiring conductor 1S52 and the via land 1S22 provided in the second layer 1L2. Is connected to the end of the second layer 1L2.

  A signal wiring conductor 1S51 and a via land provided in the first layer 1L1 are respectively provided between the via 132 and the via 133 on the first layer 1L1 side end, and between the via 134 and the via 135 on the first layer 1L1 side end. 1S21, and the second layer 1L2 side end of the via 133 and the via 134 and the second layer 1L2 side end of the via 135 and the via 136 are respectively provided in the second layer 1L2. The signal wiring conductor 1S52 and the via land 1S22 are connected to each other, and the signal wiring conductor 1S51 provided on the first layer 1L1 is connected to the via land 1S21 provided on the first layer 1L1 side end of the via 136.

  According to this configuration, when a signal passes through the vertical signal transmission path between the signal ball pad 1S4 and the signal wiring conductor 1S51 disposed on the first layer 1L1, the coil structure 130 provided in the middle is provided. Due to the self-inductance, the influence of the parasitic capacitance in the via (1S1) and via land (1S21 to 1S24) other than the place where the signal ball pad 1S4 and the coil structure 130 are disposed is offset or reduced. In this case, the coil structure 130 has the coil structure 110 and the coil structure 125a connected in series and arranged in a distributed manner as shown in FIG. 7, so that the TDR waveform is the TDR waveform 5TC shown in FIG. Thus, the passage loss is improved like the characteristic 5FC shown in FIG.

  As described above, according to the fifth embodiment, the coil structure 125a made up of the signal wiring conductor 127 arranged in a curvilinear spiral in the vicinity of the parasitic capacitance generation location in the middle of the vertical signal transmission path, and the plurality of two layers A coil structure 130 in which a coil structure 110 composed of a combination of a plurality of vias that connect to each other and a signal wiring conductor that is arranged in each layer and is connected to the via via via lands is interposed Therefore, as described with reference to FIG. 7, the coil structures can be distributed and the characteristic deterioration due to the parasitic capacitance can be further improved. Further, there is no need to add parts for improving the characteristics, so there is no increase in cost.

  FIG. 12 shows the case where the coil structure 125a is provided in the fourth layer 1L4 and the coil structure 110 is configured by using the second layer 1L2 and the first layer 1L1. The order is arbitrary.

  In FIG. 12, the coil structure 110 and the coil structure 125a are used as the coil structures to be distributed and distributed, but either one of the coil structures may be distributed and arranged. For example, a configuration may be adopted in which the coil structure 125a is divided into a plurality of parts by arranging the signal wiring conductors 127 having a curved spiral shape in a plurality of layers and connecting them with vias. In addition, as a distributed arrangement configuration of the coil structure 110, for example, a configuration in which the coil structure 110 is divided into the configuration shown in the third embodiment (FIG. 10) and the coil structure 130 shown in the fifth embodiment (FIG. 12). Also good.

Embodiment 6 FIG.
FIG. 13: is a conceptual perspective view which shows the structural example (the 4) of the coil structure provided in the vertical direction signal transmission path | route of the multilayer substrate concerning this invention as Embodiment 6 of this invention. In FIG. 13, for easy understanding, only the signal path portion where the coil structure in the vertical signal transmission path is provided is shown, and the surrounding GND is omitted.

  In FIG. 13, reference numeral 135 denotes a vertical transmission path for transmitting one signal of the differential pair signal, and reference numeral 136 denotes a vertical transmission path for transmitting the other signal of the differential pair signal. In FIG. 13, the vertical transmission paths 135 and 136 are paths between the signal ball pad 1S4 and the signal wiring conductor 1S51 provided in the first layer 1L1, respectively. As described above, in the package substrate 100 that handles the differential pair signal, characteristic deterioration due to the parasitic capacitance occurs in each of the differential pair signals.

  Therefore, in the sixth embodiment, the coil structures 138 and 139 are arranged in the vertical transmission paths 135 and 136 through which the differential pair signals pass, respectively. As a result, the characteristic degradation can be improved by canceling or mitigating the influence of the parasitic capacitance for each signal of the differential pair signal.

  As the coil structures 138 and 139, FIG. 13 shows the case where the coil structure 110 shown in the third embodiment (FIG. 10) is used, but the coil shown in the fourth embodiment (FIG. 11). The structure 125a and the coil structure 130 shown in Embodiment 5 (FIG. 12) can be used in the same manner.

  As described above, according to the sixth embodiment, when the differential pair signal is handled, the coil structure is disposed in each of the vertical transmission paths through which each signal of the differential pair signal passes. The characteristic deterioration due to the capacity can be improved. Further, there is no need to add parts for improving characteristics, so there is no increase in cost.

Embodiment 7 FIG.
FIG. 14 is a conceptual perspective view showing a configuration example (No. 5) of the coil structure provided in the vertical direction signal transmission path of the multilayer substrate according to the present invention as Embodiment 7 of the present invention. In FIG. 14, for easy understanding, only the signal path portion where the coil structure in the vertical signal transmission path is provided is shown, and the surrounding GND is omitted.

  As shown in FIG. 14, in the multilayer substrate according to the seventh embodiment, in the configuration shown in FIG. 13 (the sixth embodiment), each of the vertical transmission paths 135 and 136 through which each signal of the differential pair signal passes. The coil structure to be arranged is changed from the coil structures 138 and 139 to the coil structures 140 and 141.

  The solder balls 1S3 that are external connection terminals for each signal of the differential pair signal are usually arranged close to each other and the longitudinal transmission paths 135 and 136 are also close to each other. Increases the transmission characteristics of the differential pair signal.

  Therefore, in the seventh embodiment, the coil structures 140 and 141 are formed so that the mutual inductance is positive. As a result, in the differential mode transmission, the inductance decreases, and the differential mode impedance decreases. On the other hand, in the common mode transmission, the inductance increases, so the common mode impedance increases.

  As the coil structures 140 and 141, FIG. 14 shows the case where the coil structure 110 shown in the third embodiment (FIG. 10) is used, but the coil shown in the fourth embodiment (FIG. 11). The structure 125a and the coil structure 130 shown in Embodiment 5 (FIG. 12) can be used in the same manner.

  As described above, according to the seventh embodiment, the coil structure disposed in each of the longitudinal transmission paths through which each signal of the differential pair signal passes can be formed so that the mutual inductance is positive. Therefore, the differential mode impedance can be lowered and the common mode impedance can be increased. Further, there is no need to add parts for improving characteristics, so there is no increase in cost.

Embodiment 8 FIG.
FIG. 15 is a conceptual perspective view showing a configuration example (No. 6) of a coil structure provided in a vertical direction signal transmission path of a multilayer board according to the present invention as Embodiment 8 of the present invention. In FIG. 15, for easy understanding, only the signal path portion where the coil structure in the vertical signal transmission path is provided is shown, and the surrounding GND is omitted.

  As shown in FIG. 15, in the multilayer substrate according to the eighth embodiment, in the configuration shown in FIG. 13 (the sixth embodiment), each of the vertical transmission paths 135 and 136 through which each signal of the differential pair signal passes. The coil structure to be arranged is changed from the coil structures 138 and 139 to the coil structures 142 and 143.

  The solder balls 1S3 that are external connection terminals for each signal of the differential pair signal are usually arranged close to each other and the longitudinal transmission paths 135 and 136 are also close to each other. Increases the transmission characteristics of the differential pair signal.

  Therefore, in the eighth embodiment, the coil structures 142 and 143 are formed so that the mutual inductance is negative. As a result, in differential mode transmission, the inductance increases, so that the differential mode impedance increases. On the other hand, in the transmission in the common mode, the inductance decreases, so the common mode impedance decreases.

  As the coil structures 142 and 143, FIG. 15 shows the case where the coil structure 110 shown in the third embodiment (FIG. 10) is used, but the coil shown in the fourth embodiment (FIG. 11). The structure 125a and the coil structure 130 shown in Embodiment 5 (FIG. 12) can be used in the same manner.

  As described above, according to the eighth embodiment, the coil structure disposed in each of the vertical transmission paths through which each signal of the differential pair signal passes can be formed so that the mutual inductance is negative. Therefore, the differential mode impedance can be increased and the common mode impedance can be decreased. Further, there is no need to add parts for improving characteristics, so there is no increase in cost.

Embodiment 9 FIG.
FIG. 16 is a conceptual perspective view showing a configuration example (No. 7) of a coil structure provided in a vertical direction signal transmission path of a multilayer board according to the present invention as Embodiment 9 of the present invention. In FIG. 16, for easy understanding, only a signal path portion in which a coil structure is provided in the longitudinal signal transmission path and only GND surrounding the periphery of the coil structure are shown.

  As shown in FIG. 16, in the multilayer substrate according to the ninth embodiment, in the configuration shown in FIG. 13 (the sixth embodiment), each of the vertical transmission paths 135 and 136 through which each signal of the differential pair signal passes. The coil structure to be arranged is changed from the coil structures 138 and 139 to the coil structures 144 and 145.

  Since the coil structures 144 and 145 are arranged in the fourth layer 1L4 and the third layer 1L3 in the illustrated example, the GND plane 1G64 of the fourth layer 1L4 and the GND surrounding the coil structures 144 and 145 The GND plane 1G63 of the third layer 1L3 is shown. Reference numeral 1G23 shown between and around the coil structures 144 and 145 is a land provided in a GND via (1G1) connecting the GND plane 1G63 and the GND plane 1G64.

  According to this configuration, since the GND via (1G1) and the via land 1G23 are disposed between and around the coil structures 144 and 145, exchange of magnetic flux between the coil structures 144 and 145 is limited. Thus, the absolute value of the mutual inductance becomes very small, and only the self-inductance of each of the coil structures 144 and 145 increases. That is, the self-inductance of each of the coil structures 144 and 145 increases in any of the differential mode, common mode, and single mode transmissions, so that all of the differential mode impedance, common mode impedance, and characteristic impedance can be increased. .

  As the coil structures 144 and 145, FIG. 16 shows the case where the coil structure 110 shown in the third embodiment (FIG. 10) is used, but the coil shown in the fourth embodiment (FIG. 11). The structure 125a and the coil structure 130 shown in Embodiment 5 (FIG. 12) can be used in the same manner. And the GND plane as GND arrange | positioned between the coil structure 144,145 also becomes a thing according to the coil structure to select.

  As described above, according to the ninth embodiment, the GND for blocking the coupling between the coil structures is arranged between the coil structures arranged in the longitudinal transmission paths through which the signals of the differential pair signal pass. Therefore, the differential mode impedance, common mode impedance, and characteristic impedance can all be increased. Further, there is no need to add parts for improving characteristics, so there is no increase in cost.

  In the sixth to ninth embodiments, a path between the signal ball pad 1S4 and the signal wiring conductor 1S51 provided in the first layer 1L1 is shown as a vertical transmission path through which each signal of the differential pair signal passes. Is a path between the ball pad 1S4 and the signal wiring conductor 1S52 provided on the second layer 1L2, and further a path between the ball pad 1S4 and the signal wiring conductor 1S53 provided on the third layer 1L3. May be.

Embodiment 10 FIG.
FIG. 17: is a conceptual perspective view which shows the structural example (the 8) of the coil structure provided in the vertical direction signal transmission path | route of the multilayer substrate concerning this invention as Embodiment 10 of this invention. In FIG. 17, for easy understanding, only the coil structure is shown, and the surrounding GND is omitted. For convenience of explanation, the same reference numerals are given to the same or equivalent components as those shown in the fourth embodiment (FIG. 11) and the fifth embodiment (FIG. 12). Here, the description will be focused on the portion related to the tenth embodiment.

  As shown in FIG. 17, the coil structure 125b according to the tenth embodiment has a configuration in which a polygonal signal wiring conductor 127 is arranged in a spiral shape (polygonal spiral shape). In FIG. 17, the number of spiral turns is shown as a plurality of turns, but it may be less than one turn or more than one turn.

  In FIG. 17, as an example, as in the fourth embodiment (FIG. 11), a structural example provided in the vertical signal transmission path between the signal ball pad 1S4 and the signal wiring conductor 1S51 in the uppermost first layer 1L1. It is shown. In FIG. 17, a via 128 that connects the fourth layer 1L4 and the third layer 1L3 is provided in the vicinity of the signal ball pad 1S4. The signal wiring conductor 1S54 and via land 1S24 provided on the fourth layer 1L4 are connected to each other. The polygonal spiral arrangement signal wiring conductor 127 constituting the coil structure 125b is provided in the third layer 1L3. That is, one end of the signal wiring conductor 127 having a polygonal spiral arrangement is connected to the via land 1S23 provided on the end of the via 128 on the third layer 1L3 side, and the other end of the signal wiring conductor 127 is connected to the via 1S1. It is connected to via land 1S23 provided at the end of the third layer 1L3.

  According to this configuration, when the signal passes through the vertical signal transmission path between the signal ball pad 1S4 and the signal wiring conductor 1S51 connected to the end of the via 1S1 on the first layer 1L1 side, it is provided in the middle. Because of the self-inductance of the coil structure 125b, the influence of the parasitic capacitance in the via (1S1) and via land (1S21 to 1S24) existing outside the signal ball pad 1S4 and the coil structure 125b is offset or mitigated. The TDR waveform is improved like the TDR waveform 5TB shown in FIG. 8, and the passing loss is improved like the characteristic 5FB shown in FIG.

  At this time, since the polygonal spiral coil structure 125b is configured by the broken line-shaped signal wiring conductor 127, the wiring design in the board design CAD can be designed only by designating the corner position of the polygon. No special functions are required for the board design CAD.

  As described above, according to the tenth embodiment, one coil structure 125b of the signal wiring conductor 127 arranged in a polygonal spiral is interposed in the vicinity of the parasitic capacitance generation location in the middle of the vertical signal transmission path. Therefore, as described with reference to FIG. 6, characteristic deterioration due to parasitic capacitance can be improved. Further, there is no need to add parts for improving the characteristics, so there is no increase in cost. In addition, since the coil structure 125b can be designed only by specifying the polygonal corner position, an expensive board design CAD having a special function is not required.

Embodiment 11 FIG.
FIG. 18 is a conceptual perspective view showing a configuration example (No. 9) of the coil structure provided in the vertical signal transmission path of the multilayer board according to the invention as Embodiment 11 of the invention. In FIG. 18, for easy understanding, only the coil structure is shown, and the surrounding GND is omitted. For convenience of explanation, the same reference numerals are given to the same or equivalent components as those shown in the tenth embodiment (FIG. 17). Here, the description will be focused on the portion related to the eleventh embodiment.

  As shown in FIG. 18, in the coil structure 125c according to the eleventh embodiment, the signal wiring conductor 127 composed of a curved portion and a linear portion bent from the end thereof is arranged in a spiral shape (combined spiral shape). This is the configuration. FIG. 18 shows a case where each of the signal wiring conductors 127 has one curved portion and one straight portion bent from the end portion, and the number of spiral turns is one turn. The case of less than is shown. Of course, the signal wiring conductor 127 may be configured such that a curved portion and a linear portion bent from an end portion thereof are alternately repeated a plurality of times, and the number of spiral turns may be one or more. As described above, when the spiral shape is one or more rounds, the spiral shape of the coil structure 125c according to the eleventh embodiment is clearly a combination of a curved shape and a polygonal shape.

  In FIG. 18, as an example, as in the tenth embodiment (FIG. 17), a structural example provided in the vertical signal transmission path between the signal ball pad 1S4 and the signal wiring conductor 1S51 in the uppermost first layer 1L1. It is shown. In FIG. 18, a via 128 connecting the fourth layer 1L4 and the third layer 1L3 is provided in the vicinity of the signal ball pad 1S4, and the signal ball pad 1S4 is provided at the end of the via 128 on the fourth layer 1L4 side. The signal wiring conductor 1S54 and via land 1S24 provided on the fourth layer 1L4 are connected to each other. The signal wiring conductor 127 of the combined spiral arrangement constituting the coil structure 125c is provided in the third layer 1L3. In other words, one end of the signal wiring conductor 127 in the combined spiral arrangement is connected to the via land 1S23 provided on the third layer 1L3 side end of the via 128, and the other end of the signal wiring conductor 127 is the third of the via 1S1. It is connected to a via land 1S23 provided at the end of the layer 1L3.

  According to this configuration, when the signal passes through the vertical signal transmission path between the signal ball pad 1S4 and the signal wiring conductor 1S51 connected to the end of the via 1S1 on the first layer 1L1 side, it is provided in the middle. Because of the self-inductance of the coil structure 125c, the influence of parasitic capacitance in the via (1S1) and via land (1S21 to 1S24) existing outside the signal ball pad 1S4 and the coil structure 125c is offset or mitigated. The TDR waveform is improved like the TDR waveform 5TB shown in FIG. 8, and the passing loss is improved like the characteristic 5FB shown in FIG. In addition, since a part of the coil structure 125c is constituted by a straight line portion, the wiring work in the board design CAD is entirely curved as in the coil structure 125a shown in the fourth embodiment (FIG. 11). Is also simplified.

  As described above, according to the eleventh embodiment, one signal line conductor 127 arranged in a spiral combination of a curved shape and a polygonal shape is provided in the vicinity of a parasitic capacitance generation location in the middle of the vertical signal transmission path. Since the coil structure 125c is interposed, the characteristic deterioration due to the parasitic capacitance can be improved as described with reference to FIG. Further, there is no need to add parts for improving the characteristics, so there is no increase in cost. In addition, since a part of the coil structure 125c is composed of a straight line portion, wiring work in the board design CAD is facilitated, and cost can be reduced by shortening the work time.

Embodiment 12 FIG.
FIG. 19 is a conceptual perspective view showing a configuration example (No. 10) of a coil structure provided in a vertical direction signal transmission path of a multilayer board according to the present invention as Embodiment 12 of the present invention. In FIG. 19, for easy understanding, only the coil structure is shown, and the surrounding GND is omitted. For convenience of explanation, the same reference numerals are given to the same or equivalent components as those shown in the fourth embodiment (FIG. 11). Here, the description will be focused on the portion related to the twelfth embodiment.

  In FIG. 19, as an example, as in the fourth embodiment (FIG. 11), a structural example provided in the vertical signal transmission path between the signal ball pad 1S4 and the signal wiring conductor 1S51 in the uppermost first layer 1L1. It is shown.

  As shown in FIG. 19, the coil structure 125d according to the twelfth embodiment is configured by a curved spiral signal wiring conductor 127, similar to the coil structure 125a shown in the fourth embodiment (FIG. 11). However, in the twelfth embodiment, the arrangement position is moved to the upper part of the signal ball pad 1S4, for example.

  In FIG. 19, a via 128 connecting the fourth layer 1L4 and the third layer 1L3 is provided in the vicinity of the signal ball pad 1S4, and the signal ball pad 1S4 is provided at the end of the via 128 on the fourth layer 1L4 side. It is connected via a via land 1S24 provided in the fourth layer 1L4. However, in the twelfth embodiment, the via land 1S24 is provided in the signal ball pad 1S4, and is indicated by a dotted line in FIG. For this reason, what corresponds to the signal wiring conductor 1S54 of the fourth layer 1L4 shown in the fourth embodiment (FIG. 11) is not visible in FIG. The signal wiring conductor 127 arranged in a curvilinear spiral forming the coil structure 125d is provided in the third layer 1L3. That is, one end of the signal wiring conductor 127 arranged in a curvilinear spiral is connected to the via land 1S23 provided at the end of the via 128 on the third layer 1L3 side, and the other end of the signal wiring conductor 127 is the third of the via 1S1. It is connected to a via land 1S23 provided at the end of the layer 1L3.

  According to this configuration, since the GND plane cannot enter above the signal ball pad, the capacity between the signal ball pad and the GND plane can be reduced. A coil structure provided in the middle when a signal passes through a vertical signal transmission path between the signal ball pad 1S4 and the signal wiring conductor 1S51 connected to the end of the via 1S1 on the first layer 1L1 side. Due to the self-inductance of 125d, the influence of the parasitic capacitance in the via (1S1) and via land (1S21 to 1S24) existing outside the place where the signal ball pad 1S4 and the coil structure 125d are arranged is canceled or reduced. By these, the TDR waveform is improved like the TDR waveform 5TB shown in FIG. 8, and the passage loss is improved like the characteristic 5FB shown in FIG.

  As described above, according to the twelfth embodiment, one coil is formed by the signal wiring conductor 127 arranged in a curvilinear spiral in the vicinity of the parasitic capacitance generation location in the middle of the vertical signal transmission path above the signal ball pad. Since the structure 125d is interposed, as described with reference to FIG. 6, it is possible to reduce the parasitic capacitance and further improve the characteristic deterioration due to the remaining parasitic capacitance. Further, there is no need to add parts for improving the characteristics, so there is no increase in cost.

  In the twelfth embodiment, the application example to the fourth embodiment is shown, but the present invention can be similarly applied to the tenth and eleventh embodiments.

  Here, in the tenth to twelfth embodiments, one coil structure 125 (b, c, d) is formed in the same layer as the via land 1S23 of the third layer 1L3, but the coil shown in the fourth embodiment is used. Similar to the structure 125a, an arbitrary layer of the four layers may be used, and selection of a layer to be used is arbitrary. Further, as a spiral mode, a double-wind mode may be used.

  Further, it goes without saying that the coil structure 125 (b, c, d) shown in the tenth to twelfth embodiments can be applied to the fifth to ninth embodiments similarly to the coil structure 125a shown in the fourth embodiment. Yes. At that time, when applied to the fifth and sixth embodiments, as in the case of applying the fourth embodiment, not only the route to the signal wiring conductor provided in the uppermost first layer 1L1 is targeted, The coil structure 125 (b, c, d) may be arranged for a route to the signal wiring conductor provided in the second layer 1L2 or the third layer 1L3.

  In each of the first to twelfth embodiments, the configuration for improving the transmission characteristics in the semiconductor integrated circuit package substrate which is a multilayer substrate has been described in detail. The present invention can be similarly applied to the case of improving the transmission characteristics on the side of the semiconductor integrated circuit mounted on the substrate. Also in the printed wiring board for mounting a semiconductor integrated circuit including the semiconductor integrated circuit including the semiconductor integrated circuit package substrate, the transmission characteristics on the semiconductor integrated circuit side including the mounted semiconductor integrated circuit package substrate are improved. The same applies to the case.

  As described above, the multilayer substrate according to the present invention cancels or reduces the influence of the capacitance existing in the vertical signal transmission path between the external connection terminal and the signal wiring conductor of each layer, and the surrounding GND and Because the coil structure is used as a means for impedance matching, there is no need to worry about disconnection of the signal wiring conductor as in the conventional example, and transmission due to the influence of capacitance without causing an increase in radiation noise. The deterioration of characteristics can be improved. Therefore, it is possible to realize a multilayer substrate suitable for use as a package substrate for a semiconductor integrated circuit or a printed wiring board for mounting a semiconductor integrated circuit, which is required to be further increased in speed.

  As described above, the multilayer substrate according to the present invention uses the parasitic capacitance by matching the impedance between the vertical signal transmission path between the external connection terminal and the signal wiring conductor of each layer and the ground surrounding it. It is useful for improving the deterioration of transmission characteristics, and is particularly suitable for use as a package substrate for a semiconductor integrated circuit and a printed wiring board for mounting a semiconductor integrated circuit that require further high-speed transmission of digital signals.

FIG. 2 is an XY plan view showing a layout of each layer in a semiconductor integrated circuit package substrate which is one of the multilayer substrates targeted by the present invention and a printed wiring board which is also a multilayer substrate on which the semiconductor integrated circuit package substrate is mounted. . It is sectional drawing in XZ line shown in FIG. 1 (sectional drawing which shows a XZ plane). FIG. 2 is a cross-sectional view taken along line YZS shown in FIG. 1 (a cross-sectional view showing a longitudinal signal path on a YZ plane). It is sectional drawing in the YZG line | wire shown in FIG. 1 (sectional drawing which shows the vertical direction GND path | route in a YZ plane). FIG. 2 is an equivalent circuit diagram of a transmission circuit including a parasitic capacitance generated in a vertical signal transmission path between the multilayer substrate and the printed wiring board shown in FIG. 1. It is an equivalent circuit diagram of the transmission circuit explaining the method (the 1) which interposes the coil structure by this invention in the vertical direction signal transmission path as Embodiment 1 of this invention. It is an equivalent circuit diagram of the transmission circuit explaining the method (the 2) which interposes the coil structure by this invention in the vertical direction signal transmission path as Embodiment 2 of this invention. FIG. 8 is a TDR waveform diagram showing a comparison of impedance characteristics of the transmission circuits shown in FIGS. 5 to 7 measured using the TDR method. It is a figure which compares and shows the passage loss characteristic of each transmission circuit shown in FIGS. It is a conceptual perspective view which shows the structural example (the 1) of the coil structure provided in the vertical direction signal transmission path | route of the multilayer substrate concerning this invention as Embodiment 3 of this invention. It is a conceptual perspective view which shows the structural example (the 2) of the coil structure provided in the vertical direction signal transmission path | route of the multilayer board | substrate concerning this invention as Embodiment 4 of this invention. It is a conceptual perspective view which shows the structural example (the 3) of the coil structure provided in the longitudinal direction signal transmission path | route of the multilayer substrate concerning this invention as Embodiment 5 of this invention. It is a conceptual perspective view which shows the structure (the 4) of the coil structure provided in the longitudinal direction transmission path of the multilayer substrate concerning this invention as Embodiment 6 of this invention. It is a conceptual perspective view which shows the structural example (the 5) of the coil structure provided in the vertical direction signal transmission path | route of the multilayer substrate concerning this invention as Embodiment 7 of this invention. It is a conceptual perspective view which shows the structural example (the 6) of the coil structure provided in the vertical direction signal transmission path | route of the multilayer board | substrate concerning this invention as Embodiment 8 of this invention. It is a conceptual perspective view which shows the structural example (the 7) of the coil structure provided in the vertical direction signal transmission path | route of the multilayer board | substrate concerning this invention as Embodiment 9 of this invention. It is a conceptual perspective view which shows the structural example (the 8) of the coil structure provided in the vertical direction signal transmission path | route of the multilayer substrate concerning this invention as Embodiment 10 of this invention. It is a conceptual perspective view which shows the structural example (the 9) of the coil structure provided in the vertical direction signal transmission path | route of the multilayer substrate concerning this invention as Embodiment 11 of this invention. It is a conceptual perspective view which shows the structural example (the 10) of the coil structure provided in the vertical direction signal transmission path | route of the multilayer substrate concerning this invention as Embodiment 12 of this invention.

Explanation of symbols

100 Package substrate for semiconductor integrated circuit (package substrate)
200 Printed wiring board 1L1 to 1L4 First layer to fourth layer of package substrate 101 Dielectric layer of package substrate 1S1 Signal via of package substrate 1S2 Land of signal via of package substrate (signal via land)
1S21 to 1S24 Signal via land in the first to fourth layers of the package substrate 1S3 Signal solder ball (signal external connection terminal) of the package substrate
1S4 Package board signal solder ball pad (signal ball pad)
1S5 Signal Wiring Conductor for Package Substrate 1S51 to 1S54 Signal Wiring Conductor for First to Fourth Layers of Package Substrate 1G1 Package Via GND Ground 1G2 Package Substrate GND Via Land 1G3 Package Substrate GND Solder Ball (External connection terminal for GND)
1G4 Solder ball pad for GND on package substrate (GND ball pad)
1G6 GND plane provided in each layer of package substrate 1G63 GND plane provided in third layer of package substrate 1G64 GND plane provided in fourth layer of package substrate 201 Dielectric 2S4 Signal ball pad 2S5 Signal wiring conductor 2G1 For GND Through hole 2G2 GND through hole land 2G4 GND ball pad 2G6 GND plane 5C1 Parasitic capacitance generated in signal transmission path in package substrate 5C2, 5C3 Parasitic capacitance 5C1, 5C5, 5C6 Parasitic capacitance 5C1 5L1, 5L2, 5L3 Coil structure interposed in signal path between parasitic capacitances 110 Coil structure by combination of signal wiring conductor, via and land 112 to 119 Coil structure 1 Vias 125a, 125b, 125c, and 125d constituting the coil structure having a signal wiring conductor formed in a spiral shape 127 A signal wiring conductor formed in a spiral shape 130 A coil in which two coil structures are connected in series Structure 135 Vertical transmission path 136 of one signal of the differential pair signal 136 Vertical transmission path 138, 139 of the other signal of the differential pair signal Coil structure 140 provided in each vertical transmission path of the differential pair signal 140 , 141 Coil structure provided so that the mutual inductance is positive in each longitudinal transmission path of the differential pair signal 142, 144 so that the mutual inductance is negative in each longitudinal transmission path of the differential pair signal Coil structure to be provided 144, 145 Provided in such a manner that GND is interposed in each longitudinal transmission path of the differential pair signal to prevent mutual coupling. Yl structures

Claims (16)

In a multilayer substrate on which a semiconductor integrated circuit is mounted as an apparatus for realizing a certain function,
Occurs in the vicinity of the parasitic capacitance generation location in the vertical signal transmission path between the external connection terminal of the multilayer substrate and the signal wiring conductor disposed in a layer other than the layer in which the external connection terminal is disposed. At least one coil structure having an impedance component that cancels or mitigates the influence of parasitic capacitance is disposed;
A multilayer substrate characterized by that.   The longitudinal signal transmission path includes both a path for transmitting a positive-phase signal and a path for transmitting a reverse-phase signal of a differential pair signal, and at least one coil structure is disposed in each path. The multilayer substrate according to claim 1.   The coil structure interposed in the path for transmitting the positive phase signal and the coil structure interposed in the path for transmitting the negative phase signal are arranged so that mutual inductance has a positive polarity. The multilayer substrate according to claim 2.   The coil structure interposed in the path for transmitting the positive phase signal and the coil structure interposed in the path for transmitting the negative phase signal are arranged so that mutual inductance has a negative polarity. The multilayer substrate according to claim 2.   A ground conductor is disposed between the coil structure interposed in the path for transmitting the positive phase signal and the coil structure interposed in the path for transmitting the negative phase signal. The multilayer substrate according to claim 2, wherein the multilayer substrate is provided.   The coil structure includes a plurality of vias connecting a plurality of two layers composed of one or both of two adjacent layers and two non-adjacent layers, and the vias arranged in the respective layers and connected to the vias via via lands. The multilayer substrate according to claim 1, wherein the multilayer substrate is configured in combination with a signal wiring conductor.   The multilayer structure according to claim 1, wherein the coil structure is configured by arranging signal wiring conductors in one layer in a spiral shape.   The coil structure includes a plurality of vias that connect a plurality of two layers composed of one or both of two adjacent layers and two non-adjacent layers, and are arranged in the respective layers and connected to the vias via via lands. At least one of the coil structures configured in combination with the signal wiring conductor to be arranged and at least one of the coil structures configured by arranging the signal wiring conductor in a spiral on one layer are arranged in series. The multilayer substrate according to claim 1, wherein the multilayer substrate is configured as described above.   The coil structure includes a plurality of vias connecting a plurality of two layers composed of one or both of two adjacent layers and two non-adjacent layers, and the vias arranged in the respective layers and connected to the vias via via lands. The multilayer substrate according to claim 1, wherein a plurality of coil structures configured in combination with signal wiring conductors are arranged in series.   6. The coil structure according to claim 1, wherein the signal wiring conductors arranged in a spiral shape in each of the plurality of layers are connected by vias so as to be arranged in series. A multilayer substrate according to any one of the above.   The multilayer structure according to any one of claims 7, 8, and 10, wherein the spiral shape of the coil structure configured by arranging signal wiring conductors in a spiral shape is a curved shape. substrate.   11. The spiral shape of the coil structure configured by arranging signal wiring conductors in a spiral shape is a polygonal shape, according to claim 7. Multilayer board.   11. The spiral shape of the coil structure configured by arranging signal wiring conductors in a spiral shape is a combined shape of a curved shape and a polygonal shape. The multilayer board | substrate as described in any one.   14. The multilayer substrate according to claim 1, wherein the coil structure is disposed in a vicinity including a position overlapping with a pad of a signal pin.   A package substrate for a semiconductor integrated circuit, comprising the multilayer substrate according to claim 1.   A printed wiring board for mounting a semiconductor integrated circuit, comprising the multilayer substrate according to claim 1.

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