WO2015040727A1 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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Publication number
WO2015040727A1
WO2015040727A1 PCT/JP2013/075403 JP2013075403W WO2015040727A1 WO 2015040727 A1 WO2015040727 A1 WO 2015040727A1 JP 2013075403 W JP2013075403 W JP 2013075403W WO 2015040727 A1 WO2015040727 A1 WO 2015040727A1
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Prior art keywords
substrate
semiconductor chip
signal
semiconductor
integrated circuit
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PCT/JP2013/075403
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French (fr)
Japanese (ja)
Inventor
健治 古後
規雄 中島
高司 川本
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株式会社日立製作所
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Priority to PCT/JP2013/075403 priority Critical patent/WO2015040727A1/en
Publication of WO2015040727A1 publication Critical patent/WO2015040727A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L23/64—Impedance arrangements
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    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2924/11—Device type
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    • H01L2924/141—Analog devices
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a semiconductor integrated circuit device, and more particularly to a package wiring substrate of a semiconductor integrated circuit, a semiconductor integrated device using the wiring substrate, and further to a semiconductor integrated device having a semiconductor chip and a capacitor mounted on the wiring substrate. is there.
  • VDD terminal and the GND terminal may be collectively referred to as a power supply terminal.
  • a semiconductor chip 12 is connected to the center of the PKG wiring board 11 by a bump 15, and a bypass capacitor 13 is disposed on the outer periphery of the semiconductor chip.
  • This bypass capacitor is electrically connected to VDD and GND of the semiconductor chip 11 in the pattern 11 of the PKG wiring board.
  • the PKG wiring board 11 is molded with resin 20 and packaged to form a semiconductor integrated device.
  • This semiconductor device is connected to a printed circuit board (PCB) by a ball grid array (BGA).
  • FIG. 21 shows a model of the power supply wiring impedance when viewed from the circuit side of this mounting structure.
  • the bypass capacitor has a three-stage configuration including a bypass capacitor in the semiconductor chip 12, a bypass capacitor 13 mounted on the PKG substrate, and a bypass capacitor 19 mounted on the PCB substrate.
  • the three-stage bypass capacitors have different electrical distances and capacitance values from the circuit, and different frequency regions corresponding to the respective bypass capacitors.
  • the band above GHz is a bypass capacitor in the semiconductor chip 11 and on the package substrate between the MHz and GHz bands, and the substrate on which the package is mounted is below the MHz band.
  • the capacitors arranged on the package substrate have a 1005 size with a width of 0.5 mm ⁇ a length of 1.0 mm, a 0603 size with a width of 0.3 mm ⁇ a length of 0.6 mm, a width of 0.2 mm ⁇ a length of 0 mm.
  • chip capacitors with different external sizes such as 0402 size of 4 mm.
  • a capacitor with a large external size has a large self-inductance, but can obtain a large capacitance value, and is effective for low frequencies.
  • a capacitor with a small outer size has a small capacitance value but a small self-inductance, and is therefore effective in the high frequency region. Therefore, in high-speed signal transmission having a broadband signal component from several Hz to several tens of GHz, it is necessary to reduce the impedance of the power supply wiring in a wide band by combining a plurality of capacitors.
  • FIG. 22 shows the result of calculating the impedance of the circuit shown in FIG.
  • the impedance of the capacitor is inversely proportional to the frequency, the higher the frequency, the lower the impedance.
  • the part toward the lower right is a part where the capacity appears to be dominant.
  • the portion toward the upper right is a portion where the inductance is dominantly seen. The frequency at which this dominant component switches becomes the antiresonance frequency, and the maximum value of the impedance is generated.
  • FIG. 23 shows a result of plotting the change of the peak value of the power supply wiring impedance when the inductance value which is the distance of the “PKG wiring” shown in FIG. 21 is changed.
  • the impedance dance peak caused by the antiresonance between the PKG wiring and the chip capacitance is the maximum, and it is most effective to suppress this impedance. As described above, this impedance peak is caused by the bypass capacitor capacity in the semiconductor chip 12 and the inductance of the PKG board wiring 11.
  • the semiconductor chip 12 is provided with a bypass capacitor in a portion other than the circuit, and no space is available. Therefore, increasing the capacity of the bypass capacitor in the semiconductor chip 11 requires increasing the chip area and is not actively performed. Therefore, it is important to reduce the inductance of the PKG wiring board 11.
  • Patent Document 1 discloses disposing a bypass capacitor on four sides of a semiconductor chip. However, in this method, since the arrangement of the bypass capacitor overlaps the signal wiring and the four sides, it is extremely difficult to coexist.
  • Non-Patent Document 1 discloses a structure in which a bypass capacitor is disposed on the back surface of the PKG.
  • the BGA cannot be disposed on the back surface of the semiconductor chip, and the number of pins of the PKG is large. Therefore, in order to secure the same number of pins, a larger PKG substrate is required. At the same time, thermal vias cannot be placed directly under the semiconductor chip, thus causing a thermal problem.
  • the bypass capacitor is a high-speed signal (which has the same meaning as a high-frequency signal.
  • the frequency when referred to as a high frequency in this specification is 10 Gbps or more and 100 Gbps or less. The same applies hereinafter.) Therefore, it is necessary to arrange them at positions that are electrically close to the semiconductor chip on the PKG substrate without affecting the wiring.
  • a through hole can be placed directly under the semiconductor chip, so it can be placed in the inner layer of the package with high-speed signal wiring at a position directly under the semiconductor chip, and a bypass capacitor is placed around the semiconductor chip. Is possible.
  • the low inductance of the through hole can be reduced because the layer is thin.
  • the bypass capacitor cannot be disposed in the vicinity of the semiconductor chip, and the inductance of the substrate wiring is large, making it difficult to reduce the power supply wiring impedance.
  • the bias capacitor is disposed between the high-speed signal wirings output from each side of the chip.
  • the position where this bias capacitor is arranged is generally on a straight line connecting the corner of the chip and the corner of the PKG wiring board. That is, for example, as shown in FIG. In FIG. 1, the bias capacitors are denoted by reference numeral 13 and are provided at four locations.
  • the side that provides the input / output end of the high-frequency signal is separated from the side that becomes the input end and the side that becomes the output end. That is, the input / output ends of the high frequency signal are not mixed on the same side. For example, as shown in FIG.
  • the influence of crosstalk can be reduced by arranging the input signals having the same signal amplitude and the output signals separately from each other.
  • a signal input to the semiconductor integrated circuit device shown in FIG. 1 is transmitted over a long distance.
  • the input signal is sufficiently attenuated compared to when it is output from another signal source, and is a minute signal.
  • the signal output from the semiconductor integrated circuit device shown in FIG. 1 assumes an output signal from a normal semiconductor integrated circuit device.
  • the signal amplitude is sufficiently large compared to the input signal.
  • the amplitude voltage of the input signal and the output signal of the present invention are greatly different. For this reason, it is desirable to separate the input signal pad and the output signal pad as much as possible.
  • this high-frequency input / output pad is collected near the center of each side of the semiconductor chip. In this way, the input signal pad and the output signal pad can be separated as much as possible.
  • the input pad group does not include a pad (output terminal) for outputting an output signal.
  • the output pad group generally does not include a pad (input terminal) for applying an input signal.
  • a power supply and a control pad are provided near the end of each side of the semiconductor chip, and a high-frequency signal input / output pad is provided in the center.
  • the area where the power supply and control pad are provided is separated from the area where the input / output pads for high-frequency signals are provided. This also has the effect of reducing the influence of crosstalk by separating the signal pads between the sides.
  • the power supply and control pad may be provided with other than the VDD pad, GND pad, and control pad.
  • FIG. 6 shows an example in which a monitor pad is provided. However, this pad may or may not be present. Since the power supply and control pad of the semiconductor chip are integrated in the four corners of the chip, a bypass capacitor is arranged near the position of the power supply and control pad. As a result, the wiring inductance of the PKG board can be reduced, and the power quality can be improved.
  • the high-frequency signal lines on each side of the semiconductor element are wiring on the PKG substrate on which the semiconductor element is mounted, and the wiring interval increases as the distance from the semiconductor element increases. In such a case, the distance is widened so as to reach the PKG side. At this time, for example, an intersection between the first side and the second side that are orthogonal and adjacent to each other, and one end of the semiconductor element A bypass capacitor is arranged on or near the straight line connecting the two. Thereby, for example, there is an effect that crosstalk between signals between the terminal provided on the first side and the terminal provided on the second side can be reduced.
  • a high-speed semiconductor chip that inputs / outputs a plurality of high-speed signals with a transmission speed of several Gbit / s or more, or 10 Gbps or more per line, has good high-frequency characteristics. Can do. Furthermore, since the bypass capacitor can be placed close to the semiconductor chip, power supply voltage fluctuations can be reduced, and the performance of the semiconductor chip can be fully exploited.
  • 1 is a top view of a semiconductor integrated device according to a first exemplary embodiment of the present invention.
  • 1 is a cross-sectional view of a semiconductor integrated device according to a first embodiment of the present invention at the position of FIG. 1A-A ′.
  • It is a figure which shows the wiring pattern of the 1st layer of the multilayer package board
  • It is a figure which shows the wiring pattern of the 2nd layer of the multilayer package board
  • FIG. 8B is a cross-sectional view of the mounting of the semiconductor integrated device according to the first example of the present invention at the position of FIG. 8B-B ′. It is a figure which shows the wiring pattern of the 1st layer of the multilayer mounting board based on the 1st Example of this invention.
  • FIG. 17 It is sectional drawing of the semiconductor integrated device which concerns on the 4th Example of this invention. It is a top view of the semiconductor chip concerning the 4th example of the present invention. It is another example of the top view of the semiconductor chip which concerns on the 4th Example of this invention. It is a figure which shows an example of the mounting cross-sectional view of a semiconductor integrated device. It is a figure which shows the model of a power supply wiring impedance. It is a figure which shows the relationship between the frequency calculated from the power supply wiring impedance model of FIG. 17, and a power supply wiring impedance. The relationship between the PKG wiring inductance and the relationship between the power supply impedance is shown.
  • a semiconductor integrated circuit device according to the first embodiment of the present invention will be described.
  • FIG. 1 is a top view of the semiconductor integrated device of the present invention.
  • FIG. 2 is a cross-sectional view of the semiconductor integrated device at the position A-A ′.
  • a semiconductor chip 12 On the multilayer package substrate 22, a semiconductor chip 12, high-speed signal (meaning high-frequency signal) wiring 14, a bypass capacitor 13, and a control through-hole area 21 are arranged.
  • high-speed signal input or output ports are arranged on all sides, and high-speed signal wirings 14 are arranged in four directions of the semiconductor chip 12. is doing.
  • the package wiring board 22 on which this component is mounted is covered with resin 20 and molded.
  • a semiconductor chip 12 is arranged in the center of the package wiring board 11 and is flip-chip mounted with bumps 15.
  • FIG. 3 shows the wiring layout of each layer of the multilayer package substrate 22. From the four sides of the semiconductor chip 11, wiring is performed while spreading the high-speed signal wiring 14 toward the four sides of the multilayer package wiring board 22.
  • the high-speed signal wiring is connected to the BGA 16 on the back surface of the package through a high-speed signal through hole 27.
  • This high-speed signal wiring may be a single-phase GSG (GND, Signal, GND) wiring, but it is also possible to increase noise resistance by applying a differential GSSG wiring.
  • the bypass capacitor 13 of the package substrate is arranged between the high-speed signal wirings 14 wired from each side.
  • the inductance of the wiring board can be calculated by Equation 1, and the inductance is proportional to the wiring length. That is, it can be seen that the inductance increases as the wiring length increases.
  • bypass capacitor 13 is disposed as close to the semiconductor chip as possible to reduce the inductance in the package wiring board 11 and shorten the electrical distance from the semiconductor chip 12.
  • FIG. 24 shows the calculation result of the power supply wiring impedance as seen from the circuit when no bypass capacitor is arranged on the PKG board. In this case, a characteristic having a maximum value at a specific frequency is obtained due to anti-resonance between the distance to the capacitor on the PCB and the capacitance in the chip. Therefore, as shown in FIG. 25, by adjusting the frequency to the maximum value by the distance to the PKG capacity and the PKG capacity, and reducing the absolute value of the impedance at the maximum value, the effect of the PKG capacity is further improved. Can be increased.
  • the gain of the amplifier is adjusted to change the waveform equalization amount or the communication data is changed.
  • a control signal that stops the output is necessary to prevent malfunction.
  • FIG. 12 An example of the pad arrangement of the semiconductor chip 12 for inputting the control signal without degrading the characteristics of the high frequency signal is shown in FIG. It is optimal to arrange a high-speed signal input pad or output pad near the center of each side of each semiconductor chip 12 and input power and control signals from four corners. In other words, as shown in this figure, it is a portion described as “signal input pad” and “signal output pad”. That is, power pads are provided at the four corners of the chip 12 and in the vicinity thereof.
  • the “signal input pad” is between the first power supply / control pad and the second power supply / control pad adjacent to the power supply / control pad, and connects the two power supplies / control pads.
  • the “signal output pad” is between the first power supply / control pad and the third power supply / control pad adjacent to the power supply / control pad and connects the two power supplies / control pads.
  • a power source and a control pad are arranged at each of the four corners of the semiconductor chip.
  • the high-frequency pad of the chip is GND, signal (+), signal ( ⁇ ), and GND so that the “signal input pad” and “signal output pad” match the high-speed wiring of the PKG. At this time, the adjacent signal (+) and signal (-) are paired to form a differential signal.
  • the power supply pad is arranged on the high frequency line side, and the control pad and the monitor pad are arranged on the corner side of the chip. This is because the power supply pad is always at a constant voltage, whereas the control and monitor pads are signals whose voltage changes such as a burst signal and a clock when switching to the mode. In order to obtain good high-frequency characteristics, the periphery of the high-frequency line must be kept stable. For this reason, it is desirable to separate the control pad from the high-frequency line.
  • this control wiring is shown in FIG. 5 through the through hole 17 in the vicinity of the semiconductor chip 13 with the wiring route in the first layer minimized. Switch to the inner wiring of the third layer.
  • the bypass capacitor 13 is arranged at a position close to the semiconductor chip 12 on the opposite side of the control through-hole area 21 from the semiconductor chip 12.
  • the multilayer package wiring board 22 having the bypass capacitor 13 and the high-speed signal wiring 14 as shown in FIG. 1 and the BGA of the chip 12 can be smoothly connected.
  • the signal amplitude difference from the adjacent line can be reduced by aligning high-speed signals with only input and only output on each side. Therefore, there is an effect of reducing crosstalk between the input signal and the output signal.
  • each side for example, the signal input pad provided on the first side
  • each side for example, the signal output pad provided on the second side
  • the distance between each side and each side is increased (increased). it can.
  • a bypass capacitor having a height between the wirings on each side signal components that propagate through the space and are coupled can be reduced, which is a countermeasure against crosstalk.
  • FIG. 7 shows the arrangement of the BGA 16 on the back surface of the package wiring board 11.
  • High-speed signals are placed on the outer periphery of the package.
  • GND is arranged around the high-speed signal pad to ensure good high frequency characteristics.
  • a power supply is placed near the center of the package.
  • VDD and GND are arranged in a staggered manner to reduce the impedance of the power supply wiring as a configuration that enhances the mutual of the through hole 17 (mutual, meaning that there is mutual benefit). .
  • control signal through holes is shown in FIGS.
  • the distance between the through holes is determined by the design rules of the multilayer board. Therefore, in order to make the distance between the semiconductor chip 12 and the bypass capacitor 13 close to each other, as shown in FIG. 14, an orthogonal center line (not shown) of the control through-hole area 21 having a right-angled square planar shape is formed. Rather than arranging the semiconductor chips 12 having a right-angled square planar shape vertically and horizontally with respect to two orthogonal center lines, the control through-hole area 21 having a right-angled square planar shape is orthogonal to the two as shown in FIG.
  • center lines are arranged so that they are inclined 45 degrees with respect to the two orthogonal center lines of the semiconductor chip 12 having a right-angled rectangular planar shape, they are arranged closer to each other by 1 / ⁇ 2. be able to.
  • a plurality of through holes 17 are regularly arranged in the control through hole area 21. In addition, if this angle exceeds 0 degree and is an angle of less than 90 degree
  • FIG. 8 shows a top view of the semiconductor integrated device 26 mounted on the package wiring board 22 integrated with the semiconductor chip 12 and molded with the resin 20 mounted on the printed board 24 in FIG.
  • FIG. 9 is a sectional view taken along the line B-B ′ in FIG.
  • the printed circuit board 24 is connected by the BGA 16.
  • the printed circuit board also includes a bypass capacitor 19 and is disposed in the vicinity of the mounted semiconductor integrated device 26.
  • a multilayer substrate is used for the printed circuit board 24, and wiring of each layer is shown in FIG. 10, FIG. 11, FIG. 12, and FIG. A pattern for component placement is created in FIG. 10 of the first layer.
  • the second layer is a GND layer
  • the third layer is a high-speed signal wiring layer
  • the fourth layer is a power supply layer
  • the third-layer high-frequency line is sandwiched between the second and fourth GND and VDD so as to be a strip line.
  • a track is formed.
  • the fifth layer is a signal wiring and arrange VDD or GND on the sixth layer.
  • the connection of the bypass capacitor 19 on the printed circuit board 24 from the semiconductor integrated device 26 cannot be wired in the uppermost layer because the VDD pin is arranged near the center of the semiconductor integrated device 26.
  • the printed circuit board 19 is used as a multilayer board, wired in an intermediate layer through a through hole, and connected to a bypass capacitor arranged on the upper layer of the printed circuit board. Since VDD needs to be connected to a bypass capacitor disposed on the upper layer of the printed circuit board, it is also disposed on the uppermost layer using a through hole.
  • a semiconductor integrated circuit device according to a second embodiment of the present invention will be described.
  • one layer is added to the multilayer substrate as shown in FIG. 16 to form a five-layer multilayer substrate.
  • the inductance L [H] can be expressed by Equation 2 where L VDD is the inductance on the VDD side, L GND is the inductance on the GND side, and M is the mutual inductance of the VDD side inductance and the GND side inductance. That is, it can be seen that increasing M decreases L. Further, M can be expressed by the equation shown in Equation 3, and M increases as the distance (d) between VDD and GND is reduced. (Equation 2)
  • VDD VDD side inductance
  • GND GND inductance
  • M Mutual inductance between VDD side inductance and GND inductance
  • the core layer 23 is provided between the third layer and the fourth layer, and a prepreg layer on the side where the semiconductor chip 12 is mounted is added.
  • the first layer is a high-frequency signal wiring layer
  • the second layer is a GND plane
  • the third layer is a VDD plane
  • the fourth layer is a control wiring
  • the fifth layer is a BGA pattern.
  • the high-speed signal wiring layer of the first layer the high frequency line of the microstrip line is formed with the two layers as the GND plane, the VDD plane is formed as the third layer, and the dielectric between the GND plane is the one layer of the prepreg. . Since the prepreg layer is thinner than the core layer, the GND plane and the VDD plane are closer to each other. Accordingly, the mutual inductance is increased, and the electrical distance between the semiconductor chip 12 and the bypass capacitor 13 can be reduced.
  • FIG. 17 shows an embodiment in which high-speed signals are input / output from two sides from the semiconductor chip 12 and high-speed signals are arranged on four sides from the package wiring board 14.
  • ⁇ Arrange on two sides so that a high-speed signal is input from one side and output from the opposite side. Power supply and control signal input / output are arranged from the other two sides.
  • the semiconductor chip 12 is mounted on the package wiring board 14 if the high-speed signal wiring is 8 lines, half of the 4 lines are input / output from the side of the package wiring board 14 parallel to the input / output side of the semiconductor chip 12, The remaining four lines are input / output from the side of the package wiring board 14 perpendicular to the input / output side of the semiconductor chip 12.
  • the package wiring board 14 has a space, and a bypass capacitor 13 and a control through-hole area are provided at that position. With such an arrangement, a semiconductor integrated device having excellent high frequency characteristics and improved power supply quality is provided.
  • the semiconductor chip is mounted at an angle of 45 ° in FIG. 19, the line length of the high-speed signal wiring 14 can be shortened and the loss can be reduced compared with the case where the semiconductor chip 12 of FIG. A semiconductor integrated device having excellent characteristics and improved power supply quality can be provided.

Abstract

To obtain satisfactory high-speed signal properties in a semiconductor device handling a plurality of high-speed signals, decreasing fluctuations in the power voltage in operation of the semiconductor chip is important, in addition to implementing measures against high-speed signal crosstalk. For this purpose, low impedance for the power wiring is important. In order to prevent a deterioration of high-speed signal properties, high-speed signal wiring (14) is laid as straight lines on a surface parallel to a semiconductor chip (12) and a package wiring substrate (22). When doing so, no high-speed signal wiring is routed in the corner portions of the chip in order to decrease inter-signal crosstalk at each edge. In each of these spaces, a bypass capacitor is disposed, thus allowing for a semiconductor device having excellent high-speed performance and improved power source quality.

Description

半導体集積回路装置Semiconductor integrated circuit device
　本発明は、半導体集積回路装置に関し、特に、半導体集積回路のパッケージ配線基板と，その配線基板を用いた半導体集積装置に関し，さらには半導体チップとコンデンサを配線基板の搭載した半導体集積装置に関するものである。 The present invention relates to a semiconductor integrated circuit device, and more particularly to a package wiring substrate of a semiconductor integrated circuit, a semiconductor integrated device using the wiring substrate, and further to a semiconductor integrated device having a semiconductor chip and a capacitor mounted on the wiring substrate. is there.
　情報通信分野において，インターネット，スマートフォンの普及，クラウド化の進展により，データセンタ内におけるサーバやルータ等の処理するデータ量が飛躍的に増加し，大容量情報処理のニーズが拡大している。このサーバやルータのデータ処理速度を上げるためには，デバイス単体の動作速度の高速化に加え，ＣＰＵ（中央演算処理ユニット）－メモリ間および，デバイス間の信号伝送速度の高速化が必要である。近年，サーバやルータ等の装置では，Ｔｂｉｔ／ｓ　級のスループットが要求されており，この要求を満足するためには，ＣＰＵ－メモリ間等の伝送を，１回線あたり数Ｇｂｉｔ／ｓ級の速度で並列伝送する必要がある。そのため，装置内では，１００回線よりも多くの高速信号回線を取り扱う必要があり，１つの半導体集積チッで複数の高速信号回線を扱うことが求められる。複数の高速信号回線を入出力するためには，特定の辺から信号を入出力するよりも，複数の辺から入出力した方が，同サイズのチップで処理する信号の回線数を増やすことができ，Ｇｂｉｔ／ｓ当りの実装密度を向上させ，サーバやルータに実装する部品の個数を削減することができる。 In the information and communication field, with the spread of the Internet and smartphones, and the development of cloud computing, the amount of data processed by servers and routers in the data center has increased dramatically, and the need for large-capacity information processing is expanding. In order to increase the data processing speed of this server or router, it is necessary to increase the signal transmission speed between the CPU (Central Processing Unit) and the memory and between the devices in addition to increasing the operating speed of the device alone. . In recent years, devices such as servers and routers have required Tbit / s class throughput, and in order to satisfy this requirement, transmission between the CPU and memory, etc., has a speed of several Gbit / s class per line. Need to transmit in parallel. Therefore, it is necessary to handle more than 100 high-speed signal lines in the apparatus, and it is required to handle a plurality of high-speed signal lines with one semiconductor integrated chip. In order to input / output multiple high-speed signal lines, it is possible to increase the number of signal lines processed by a chip of the same size by inputting / outputting from multiple sides rather than inputting / outputting signals from a specific side. It is possible to improve the mounting density per Gbit / s and reduce the number of components mounted on the server or router.
　しかし，複数の高速信号を扱う場合は，信号間の距離が近接されるため，信号間クロストーク対策および，電源電圧の安定化が求められる。信号回線数を増やした場合，半導体集積チップに集積されるトランジスタの数も増加するため，回路動作するために流れる回路電流が増加する。回路電流が増加すると，オームの法則より電源電圧変動も増加することなる。そのため，回路電流が増加した場合において，電源電圧変動量を増加させないためには，電源配線の低インピーダンス化が必要となる。これは，電源電圧に対して，回路に信号を入力して出力するまでの信号の通過時間が変化するような，フィードバック系の無い増幅回路のなどの開回路においては大きな問題となるため，電源電圧安定性を高める必要がある。電源電圧の安定性を高める方法の一つとして，ＶＤＤとグランド（ＧＮＤ）間にバイパスコンデンサを接続する。バイパスコンデンサを配置することで，電源配線を低インピーダンス化することができ，電源安定性を向上させることができる。 However, when handling multiple high-speed signals, the distance between the signals is close, so countermeasures for crosstalk between signals and stabilization of the power supply voltage are required. When the number of signal lines is increased, the number of transistors integrated in the semiconductor integrated chip also increases, so that the circuit current flowing for circuit operation increases. As the circuit current increases, power supply voltage fluctuations also increase according to Ohm's law. For this reason, when the circuit current increases, it is necessary to reduce the impedance of the power supply wiring in order not to increase the power supply voltage fluctuation amount. This is a major problem in open circuits such as an amplifier circuit without a feedback system in which the signal transit time until the signal is input to the circuit and output is changed with respect to the power supply voltage. It is necessary to increase voltage stability. As one method for improving the stability of the power supply voltage, a bypass capacitor is connected between VDD and ground (GND). By arranging a bypass capacitor, the impedance of the power supply wiring can be reduced, and the power supply stability can be improved.
　なお、例えば、VDD端子と、GND端子を合わせて、電源端子ということもある。 Note that, for example, the VDD terminal and the GND terminal may be collectively referred to as a power supply terminal.
　そこで近年では，図２０に示すようにパッケージ（ＰＫＧ）の内部にバイパスコンデンサ１３を配置する方法が行われている。ＰＫＧ配線基板１１の中心に半導体チップ１２をバンプ１５にて接続し，その半導体チップの外周にバイパスコンデンサ１３を配置する。このバイパスコンデンサは，ＰＫＧ配線基板の１１のパターンで，半導体チップ１１のＶＤＤとＧＮＤに電気的に接続されている。 Therefore, in recent years, a method of disposing a bypass capacitor 13 inside a package (PKG) as shown in FIG. A semiconductor chip 12 is connected to the center of the PKG wiring board 11 by a bump 15, and a bypass capacitor 13 is disposed on the outer periphery of the semiconductor chip. This bypass capacitor is electrically connected to VDD and GND of the semiconductor chip 11 in the pattern 11 of the PKG wiring board.
　このＰＫＧ配線基板１１を樹脂２０でモールドしてパッケージングし，半導体集積装置となる。この半導体装置を，ボールグリッドアレイ（ＢＧＡ）にてプリント基板（ＰＣＢ）と接続する。この実装構造の回路側から見た時の電源配線インピーダンスのモデルを図２１に示す。 The PKG wiring board 11 is molded with resin 20 and packaged to form a semiconductor integrated device. This semiconductor device is connected to a printed circuit board (PCB) by a ball grid array (BGA). FIG. 21 shows a model of the power supply wiring impedance when viewed from the circuit side of this mounting structure.
　バイパスコンデンサは，半導体チップ１２内のバイパスコンデンサ，ＰＫＧ基板に実装されてバイパスコンデンサ１３，ＰＣＢ基板に実装されたバイパスコンデンサ１９の３段階構成となっている。この３段のバイパスコンデンサは，回路からの配置される電気的な距離および容量値が異なり，各バイパスコンデンサの対応する周波数領域が異なる。一般的にＧＨｚ以上の帯域は，半導体チップ１１内のバイパスコンデンサ，パッケージ基板上はＭＨｚ～ＧＨｚ帯の間，パッケージを実装する基板がＭＨｚ帯以下と言われている。現在，パッケージ基板上配置するコンデンサには，外形サイズが幅０．５ｍｍ×長さ１．０ｍｍの１００５サイズ，幅０．３ｍｍ×長さ０．６ｍｍの０６０３サイズ，幅０．２ｍｍ×長さ０．４ｍｍの０４０２サイズ等の異なる外形サイズのチップコンデンサがあり，外形サイズの大きいコンデンサは，自己インダクタンスは大きいが，大きな容量値を得る事ができるため，低周波に効果的である。逆に，外形サイズの小さいコンデンサは，容量値は小さいが，自己インダクタンスが小さいため，高周波領域に効果的である。ゆえに，数Hz～数十GHzまでの広帯域の信号成分を有する高速信号伝送においては，複数の容量のコンデンサを組合せることにより，広帯域にて電源配線インピーダンスを低インピーダンス化する必要がある。 The bypass capacitor has a three-stage configuration including a bypass capacitor in the semiconductor chip 12, a bypass capacitor 13 mounted on the PKG substrate, and a bypass capacitor 19 mounted on the PCB substrate. The three-stage bypass capacitors have different electrical distances and capacitance values from the circuit, and different frequency regions corresponding to the respective bypass capacitors. In general, it is said that the band above GHz is a bypass capacitor in the semiconductor chip 11 and on the package substrate between the MHz and GHz bands, and the substrate on which the package is mounted is below the MHz band. Currently, the capacitors arranged on the package substrate have a 1005 size with a width of 0.5 mm × a length of 1.0 mm, a 0603 size with a width of 0.3 mm × a length of 0.6 mm, a width of 0.2 mm × a length of 0 mm. There are chip capacitors with different external sizes such as 0402 size of 4 mm. A capacitor with a large external size has a large self-inductance, but can obtain a large capacitance value, and is effective for low frequencies. Conversely, a capacitor with a small outer size has a small capacitance value but a small self-inductance, and is therefore effective in the high frequency region. Therefore, in high-speed signal transmission having a broadband signal component from several Hz to several tens of GHz, it is necessary to reduce the impedance of the power supply wiring in a wide band by combining a plurality of capacitors.
　図２１に示す回路のインピーダンスを計算した結果を図２２に示す。 FIG. 22 shows the result of calculating the impedance of the circuit shown in FIG.
　コンデンサのインピーダンスは，周波数に反比例するため，周波数が高くなるほどインピーダンスが低くなる。図２２において右下に向かう部分は容量が支配的に見えている部分である。 Since the impedance of the capacitor is inversely proportional to the frequency, the higher the frequency, the lower the impedance. In FIG. 22, the part toward the lower right is a part where the capacity appears to be dominant.
　逆に，配線のインダクタンスのインピーダンスは，周波数に比例するため，高くなるほどインピーダンスが高くなる。図２２において右上に向かう部分はインダクタンスが支配的に見えている部分である。この支配成分が切換る周波数が反共振周波数となり，インピーダンスの極大値が生じている。 Conversely, since the impedance of the wiring inductance is proportional to the frequency, the higher the impedance, the higher the impedance. In FIG. 22, the portion toward the upper right is a portion where the inductance is dominantly seen. The frequency at which this dominant component switches becomes the antiresonance frequency, and the maximum value of the impedance is generated.
　この時，図２１に図示した”ＰＫＧ配線”の距離となるインダクタンス値を変化させた時の電源配線インピーダンスのピーク値の変化をプロットした結果を図２３に示す。 At this time, FIG. 23 shows a result of plotting the change of the peak value of the power supply wiring impedance when the inductance value which is the distance of the “PKG wiring” shown in FIG. 21 is changed.
　この図から明らかなように，ＰＫＧ配線のインダクタンスを低減させると，インピーダンス値が小さくなる。オームの法則より，この電源配線インピーダンスと回路に流れる交流電流を掛けた値が，回路の電源電圧変動となる。そのため，電源電圧変動を抑えるためには，電源配線インピーダンスを低インピーダンス化することが重要となる。このモデルでは，ＰＫＧ配線とチップ容量の反共振で生じるインピーダンスダンスピークが最大であり，このインピーダンスを抑えることが最も効果がある。先にも述べたが，このインピーダンスピークは，半導体チップ１２内のバイパスコンデンサ容量とＰＫＧ基板配線１１のインダクタンスで生じている。 As is clear from this figure, when the inductance of the PKG wiring is reduced, the impedance value becomes smaller. According to Ohm's law, the value obtained by multiplying the power supply wiring impedance by the AC current flowing through the circuit is the power supply voltage fluctuation of the circuit. Therefore, it is important to reduce the power supply wiring impedance in order to suppress fluctuations in the power supply voltage. In this model, the impedance dance peak caused by the antiresonance between the PKG wiring and the chip capacitance is the maximum, and it is most effective to suppress this impedance. As described above, this impedance peak is caused by the bypass capacitor capacity in the semiconductor chip 12 and the inductance of the PKG board wiring 11.
　そこで，このピークを低減させるためには，半導体チップ１１内のバイパスコンデンサ容量の増量もしくは，ＰＫＧ配線基板１１のインダクタンスを低減させることが必要となる。一般的に，半導体チップ１２は，回路以外の部分はバイパスコンデンサを配置されており，スペースが空いていない。そのため，半導体チップ１１内のバイパスコンデンサの容量を増量することは，チップの面積を大きくする必要があり，積極的には行わない。そのため，ＰＫＧ配線基板１１のインダクタンスを低減させることが重要となる。 Therefore, in order to reduce this peak, it is necessary to increase the bypass capacitor capacity in the semiconductor chip 11 or reduce the inductance of the PKG wiring board 11. In general, the semiconductor chip 12 is provided with a bypass capacitor in a portion other than the circuit, and no space is available. Therefore, increasing the capacity of the bypass capacitor in the semiconductor chip 11 requires increasing the chip area and is not actively performed. Therefore, it is important to reduce the inductance of the PKG wiring board 11.
　ＰＫＧ配線基板１１を低インピーダンス化するためには，特許文献１のように基板の表層に配線を設ける方法などが提案されている。本方法は，チップ直下にスルーホールを設けることで，信号配線を内層で配線することが可能であるため，表面層の半導体チップ周辺のＶＤＤ，ＧＮＤ間にバイパスコンデンサを配置することができる。 
　しかし，現在の半導体集積チップは高速性が求められており，パッドの寄生容量を低減させる必要があり，パッドの低面積化が進められている。そのため，ビルドアップの樹脂基板を用いた場合，スルーホールの加工精度の観点から，半導体チップ１１のパッド直下にスルーホールを配置することができない。 In order to reduce the impedance of the PKG wiring board 11, a method of providing wiring on the surface layer of the board as in Patent Document 1 has been proposed. In this method, since the signal wiring can be wired in the inner layer by providing a through hole directly under the chip, a bypass capacitor can be disposed between VDD and GND around the semiconductor chip on the surface layer.
However, the current semiconductor integrated chip is required to have high speed, and it is necessary to reduce the parasitic capacitance of the pad, and the pad area is being reduced. For this reason, when a build-up resin substrate is used, a through hole cannot be disposed directly under the pad of the semiconductor chip 11 from the viewpoint of through hole processing accuracy.
　そのため，表層にて高周波信号を伝達する配線を設ける必要である。特許文献１では、半導体チップの４辺にバイパスコンデンサを配置することが開示されている。しかし，この方法では，信号の配線と４辺にバイパスコンデンサの配置が重なってしまうため，共存することが著しく困難である。 Therefore, it is necessary to provide wiring that transmits high-frequency signals on the surface layer. Patent Document 1 discloses disposing a bypass capacitor on four sides of a semiconductor chip. However, in this method, since the arrangement of the bypass capacitor overlaps the signal wiring and the four sides, it is extremely difficult to coexist.
　また，非特許文献１には，ＰＫＧの裏面にバイパスコンデンサを配置する構造が開示されているが，この方法では，半導体チップの裏面にＢＧＡを配置することができずに，ＰＫＧのピン数が少なくなってしまうため，同じピン数を確保するためには，より大きなＰＫＧ基板が必要となる。同時に半導体チップの真下にサーマルビアを配置することもできないため，熱の問題も生じる。 Non-Patent Document 1 discloses a structure in which a bypass capacitor is disposed on the back surface of the PKG. However, in this method, the BGA cannot be disposed on the back surface of the semiconductor chip, and the number of pins of the PKG is large. Therefore, in order to secure the same number of pins, a larger PKG substrate is required. At the same time, thermal vias cannot be placed directly under the semiconductor chip, thus causing a thermal problem.
　そこで，今回は高周波特性に優れ，かつ電源品質にも優れた半導体集積回路のパッケージ配線基板と，その配線基板を用いた半導体集積装置を提供する。 Therefore, this time, we will provide a semiconductor integrated circuit package wiring board with excellent high-frequency characteristics and power supply quality, and a semiconductor integrated device using the wiring board.
特開２００６－１４７６７６号公報JP 2006-147676 A
　半導体チップの性能引き出すために，高速の信号を劣化せずに入出力が行え，且つ電源電圧を安定化させることが重要である。 In order to extract the performance of the semiconductor chip, it is important to be able to input / output without degrading high-speed signals and to stabilize the power supply voltage.
　そのために，バイパスコンデンサは高速信号（高周波信号と同じ意味である。なお、本明細書でいう高周波というときの周波数は、10 Gbps以上、100 Gbps以下をいうものとする。以下同様である。）の配線に影響を与えずに，ＰＫＧ基板上の半導体チップに電気的に近い位置に配置する必要がある。 Therefore, the bypass capacitor is a high-speed signal (which has the same meaning as a high-frequency signal. Note that the frequency when referred to as a high frequency in this specification is 10 Gbps or more and 100 Gbps or less. The same applies hereinafter.) Therefore, it is necessary to arrange them at positions that are electrically close to the semiconductor chip on the PKG substrate without affecting the wiring.
　セラミック基板を用いた場合は，半導体チップ直下にスルーホールを配置することができるため，半導体チップ直下位置で，高速信号の配線でパッケージの内層に設ける事ができ，半導体チップ外周にバイパスコンデンサを配置することが可能である。 If a ceramic substrate is used, a through hole can be placed directly under the semiconductor chip, so it can be placed in the inner layer of the package with high-speed signal wiring at a position directly under the semiconductor chip, and a bypass capacitor is placed around the semiconductor chip. Is possible.
　しかし，各層厚が厚いため，スルーホールのインダクタンスが大きく，電源配線インピーダンスの低減が困難であった。 However, since the thickness of each layer is large, the inductance of the through hole is large and it is difficult to reduce the impedance of the power supply wiring.
　また，樹脂基板を用いた場合は，層を薄いため，スルーホールの低インダクタンスを低減することが可能である。しかし、スルーホールの加工精度の観点から，半導体直下にスルーホールを配置することが出来ないため，半導体チップ外周に高速信号の配線を設ける必要がある。ゆえに、半導体チップの近傍にバイパスコンデンサを配置できず，基板配線のインダクタンスが大きく電源配線インピーダンスの低減が困難であった。 In addition, when a resin substrate is used, the low inductance of the through hole can be reduced because the layer is thin. However, from the viewpoint of through hole processing accuracy, it is not possible to place a through hole directly under the semiconductor, so it is necessary to provide a high-speed signal wiring around the semiconductor chip. Therefore, the bypass capacitor cannot be disposed in the vicinity of the semiconductor chip, and the inductance of the substrate wiring is large, making it difficult to reduce the power supply wiring impedance.
　そのため，高速で，且つ複数の信号を処理する半導体チップでは，高周波特性を満足したまま，電源品質を向上させることが困難であった。 For this reason, it has been difficult to improve the power supply quality while satisfying the high-frequency characteristics in a semiconductor chip that processes a plurality of signals at high speed.
　上記の課題を解決するため，樹脂基板において，バイアスコンデンサはチップの各辺から出力される高速信号配線の間に配置する。 In order to solve the above problems, on the resin substrate, the bias capacitor is disposed between the high-speed signal wirings output from each side of the chip.
　このバイアスコンデンサを配置する位置は，大体、チップの角とＰＫＧ配線基板の角とを結ぶ直線上とする。即ち、例えば、図１に示す通りである。図１において、バイアスコンデンサは符号13で示され、４か所に設けられている。 The position where this bias capacitor is arranged is generally on a straight line connecting the corner of the chip and the corner of the PKG wiring board. That is, for example, as shown in FIG. In FIG. 1, the bias capacitors are denoted by reference numeral 13 and are provided at four locations.
　複数の高速信号を入出力する半導体チップの場合は，クロストークが問題となる。 In the case of semiconductor chips that input / output multiple high-speed signals, crosstalk becomes a problem.
　そこで，高周波信号（高速信号）の入出力端となる半導体チップの辺において，高周波信号の入出力端を設ける辺は、入力端となる辺と、出力端となる辺とを別個にする。即ち、同一辺に高周波信号の入出力端を混在させないようにする。例えば、図６に示す通りである。 Therefore, in the side of the semiconductor chip that is the input / output end of the high-frequency signal (high-speed signal), the side that provides the input / output end of the high-frequency signal is separated from the side that becomes the input end and the side that becomes the output end. That is, the input / output ends of the high frequency signal are not mixed on the same side. For example, as shown in FIG.
　これは，入力信号と出力信号には信号振幅に差分が生じており，クロストークの影響を増大させる可能性があるためである。即ち、ほぼ同一信号振幅となる入力信号同士と出力信号同士とを分離して配置したほうがクロストークの影響を低減することができる。本発明では、例えば図１に示す半導体集積回路装置に入力される信号は長い距離を伝送されてくることを想定している。長距離伝送の結果、入力される信号は他の信号源から出力される時に比べて、十分に減衰しており、微小な信号となっている。一方、例えば図１に示す半導体集積回路装置から出力される信号は、通常の半導体集積回路装置からの出力信号を想定している。 This is because there is a difference in the signal amplitude between the input signal and the output signal, which may increase the influence of crosstalk. That is, the influence of crosstalk can be reduced by arranging the input signals having the same signal amplitude and the output signals separately from each other. In the present invention, for example, it is assumed that a signal input to the semiconductor integrated circuit device shown in FIG. 1 is transmitted over a long distance. As a result of long-distance transmission, the input signal is sufficiently attenuated compared to when it is output from another signal source, and is a minute signal. On the other hand, for example, the signal output from the semiconductor integrated circuit device shown in FIG. 1 assumes an output signal from a normal semiconductor integrated circuit device.
　このため、入力信号に比べれば、信号振幅は十分に大きい。このように、本発明の入力信号と出力信号とは、その振幅電圧が大きく異なる。このため、入力信号パッドと、出力信号パッドとは、なるべく離間させることが望ましい。 Therefore, the signal amplitude is sufficiently large compared to the input signal. Thus, the amplitude voltage of the input signal and the output signal of the present invention are greatly different. For this reason, it is desirable to separate the input signal pad and the output signal pad as much as possible.
　さらに，この高周波の入出力用のパッドは半導体チップ各辺の中央付近に集める。このようにすることにより、入力信号パッドと、出力信号パッドとをなるべく離間させることが可能となる。入力パッド群の中には、出力信号を出力するためのパッド（出力端子）が含まれないのが一般的である。同様に、出力パッド群の中には、入力信号を印加するためのパッド（入力端子）が含まれないのが一般的である。 Furthermore, this high-frequency input / output pad is collected near the center of each side of the semiconductor chip. In this way, the input signal pad and the output signal pad can be separated as much as possible. In general, the input pad group does not include a pad (output terminal) for outputting an output signal. Similarly, the output pad group generally does not include a pad (input terminal) for applying an input signal.
　同時に，半導体チップの各辺の端部近傍に，電源，制御パッドを設け，中央部分に高周波信号の入出力パッドを設ける。このように構成することにより、電源，制御パッドが設けられるエリアと、高周波信号の入出力パッドが設けられるエリアとを分離する。こうすることで，各辺間の信号パッド間を離間させてクロストークの影響を低減する効果もある。 At the same time, a power supply and a control pad are provided near the end of each side of the semiconductor chip, and a high-frequency signal input / output pad is provided in the center. With this configuration, the area where the power supply and control pad are provided is separated from the area where the input / output pads for high-frequency signals are provided. This also has the effect of reducing the influence of crosstalk by separating the signal pads between the sides.
　図６に示すように、電源，制御パッドには、VDDパッド、GNDパッド、制御パッド以外のものが設けられていてもよい。図６では、その一例として、モニタ用のパッドが設けられているが示されている。但し、このパッドはあっても、無くてもよい。　半導体チップの電源，制御パッドをチップの４角に集約させたので，この電源，制御パッド位置近傍にバイパスコンデンサを配置する。これにより、ＰＫＧ基板の配線インダクタンスを低減でき，電源品質の改善を行うことができる。 As shown in FIG. 6, the power supply and control pad may be provided with other than the VDD pad, GND pad, and control pad. FIG. 6 shows an example in which a monitor pad is provided. However, this pad may or may not be present. Since the power supply and control pad of the semiconductor chip are integrated in the four corners of the chip, a bypass capacitor is arranged near the position of the power supply and control pad. As a result, the wiring inductance of the PKG board can be reduced, and the power quality can be improved.
　また，半導体素子の各辺の高周波信号線は，その半導体素子を搭載したＰＫＧ基板上の配線で、その配線間隔が、半導体素子から遠ざかるに従って拡がる。そのように間隔を広げた上で、ＰＫＧ辺に至るようにする
　この時，例えば、直交し、かつ、隣接する第１の辺と第２の辺との交点と、半導体素子の一の端部とを結ぶ上記直線上またはその近傍にバイパスコンデンサを配置する。これにより、例えば、上記第１の辺上に設けられた端子と上記第２の辺上に設けられた端子との間での信号間のクロストークを低減することができるという効果もある。 The high-frequency signal lines on each side of the semiconductor element are wiring on the PKG substrate on which the semiconductor element is mounted, and the wiring interval increases as the distance from the semiconductor element increases. In such a case, the distance is widened so as to reach the PKG side. At this time, for example, an intersection between the first side and the second side that are orthogonal and adjacent to each other, and one end of the semiconductor element A bypass capacitor is arranged on or near the straight line connecting the two. Thereby, for example, there is an effect that crosstalk between signals between the terminal provided on the first side and the terminal provided on the second side can be reduced.
　本発明を用いれば，１回線あたり，数Ｇｂｉｔ／ｓ以上、若しくは10 Gbps以上伝送速度の高速信号を複数回線分、それぞれ入出力する高速の半導体チップにもおいても良好な高周波特性を有することができる。さらに，バイパスコンデンサも半導体チップに近接させることができるため，電源電圧変動を低減することができ，半導体チップの性能を十分に引き出すことができる。 By using the present invention, a high-speed semiconductor chip that inputs / outputs a plurality of high-speed signals with a transmission speed of several Gbit / s or more, or 10 Gbps or more per line, has good high-frequency characteristics. Can do. Furthermore, since the bypass capacitor can be placed close to the semiconductor chip, power supply voltage fluctuations can be reduced, and the performance of the semiconductor chip can be fully exploited.
本発明の第１の実施例に係る半導体集積装置の上面図である。1 is a top view of a semiconductor integrated device according to a first exemplary embodiment of the present invention. 本発明の第１の実施例に係る半導体集積装置図１Ａ－Ａ’位置での断面図である。1 is a cross-sectional view of a semiconductor integrated device according to a first embodiment of the present invention at the position of FIG. 1A-A ′. 本発明の第１の実施例に係る多層パッケージ基板の第１層の配線パターンを示す図である。It is a figure which shows the wiring pattern of the 1st layer of the multilayer package board | substrate which concerns on the 1st Example of this invention. 本発明の第１の実施例に係る多層パッケージ基板の第２層の配線パターンを示す図である。It is a figure which shows the wiring pattern of the 2nd layer of the multilayer package board | substrate which concerns on 1st Example of this invention. 本発明の第１の実施例に係る多層パッケージ基板の第３層の配線パターンを示す図である。It is a figure which shows the wiring pattern of the 3rd layer of the multilayer package board | substrate which concerns on 1st Example of this invention. 本発明の第一の実施例に係る半導体チップのパッド配置を示す図である。It is a figure which shows the pad arrangement | positioning of the semiconductor chip which concerns on the 1st Example of this invention. 本発明の第１の実施例に係る半導体装置のＢＧＡ配置を示す図である。It is a figure which shows BGA arrangement | positioning of the semiconductor device based on 1st Example of this invention. 本発明の第１の実施例に係る半導体集積装置を多層実装基板に実装した図を示す。1 is a diagram showing a semiconductor integrated device according to a first embodiment of the present invention mounted on a multilayer mounting board. 本発明の第１の実施例に係る半導体集積装置の実装の図８Ｂ-Ｂ’位置での断面図である。FIG. 8B is a cross-sectional view of the mounting of the semiconductor integrated device according to the first example of the present invention at the position of FIG. 8B-B ′. 本発明の第１の実施例に係る多層実装基板の第１層の配線パターンを示す図である。It is a figure which shows the wiring pattern of the 1st layer of the multilayer mounting board based on the 1st Example of this invention. 本発明の第１の実施例に係る多層実装基板の第２層の配線パターンを示す図である。It is a figure which shows the wiring pattern of the 2nd layer of the multilayer mounting board | substrate which concerns on the 1st Example of this invention. 本発明の第１の実施例に係る多層実装基板の第１層の配線パターンを示す図である。It is a figure which shows the wiring pattern of the 1st layer of the multilayer mounting board based on the 1st Example of this invention. 本発明の第１の実施例に係る多層実装基板の第１層の配線パターンを示す図である。It is a figure which shows the wiring pattern of the 1st layer of the multilayer mounting board based on the 1st Example of this invention. 本発明の第２実施例に係る制御ピンエリヤのスルーホール配置１を示す図である。It is a figure which shows the through-hole arrangement | positioning 1 of the control pin area based on 2nd Example of this invention. 本発明の第２の実施例に係る制御ピンエリヤのスルーホール配置２を示す図である。It is a figure which shows the through hole arrangement | positioning 2 of the control pin area which concerns on 2nd Example of this invention. 本発明の第３の実施例に係る半導体集積装置の断面図である。It is sectional drawing of the semiconductor integrated device which concerns on the 3rd Example of this invention. 本発明の第４の実施例に係る半導体集積装置の断面図である。It is sectional drawing of the semiconductor integrated device which concerns on the 4th Example of this invention. 本発明の第４の実施例に係る半導体チップの上面図である。It is a top view of the semiconductor chip concerning the 4th example of the present invention. 本発明の第４の実施例に係る半導体チップの上面図のもう１例である。It is another example of the top view of the semiconductor chip which concerns on the 4th Example of this invention. 半導体集積装置の実装断面図の一例を示す図である。It is a figure which shows an example of the mounting cross-sectional view of a semiconductor integrated device. 電源配線インピーダンスのモデルを示す図である。It is a figure which shows the model of a power supply wiring impedance. 図１７の電源配線インピーダンスモデルから計算したところの、周波数と電源配線インピーダンスとの関係を示す図である。It is a figure which shows the relationship between the frequency calculated from the power supply wiring impedance model of FIG. 17, and a power supply wiring impedance. ＰＫＧ配線インダクタンスと電源インピーダンスとの関係との関係を示す。The relationship between the PKG wiring inductance and the relationship between the power supply impedance is shown. ＰＫＧにバイパスコンデンサを搭載していない時の電源配線インピーダンスモデルから計算したところの、周波数と電源配線インピーダンスとの関係を示す図である。It is a figure which shows the relationship between a frequency and a power supply wiring impedance calculated from the power supply wiring impedance model when no bypass capacitor is mounted in PKG. ＰＫＧにバイパスコンデンサを搭載した時の電源配線インピーダンスモデルから計算したところの、図２４から改善した周波数と電源配線インピーダンスとの関係を示す図である。It is a figure which shows the relationship between the frequency improved from FIG. 24 calculated from the power supply wiring impedance model when a bypass capacitor is mounted in PKG, and power supply wiring impedance.
　以下に、図面を用いて、本発明の実施の形態を詳細に述べる。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
　本発明の第１実施例の半導体集積回路装置について説明する。 A semiconductor integrated circuit device according to the first embodiment of the present invention will be described.
　図１は本発明の半導体集積装置の上面図である。図２は、その半導体集積装置のＡ－Ａ’位置での断面図である。 FIG. 1 is a top view of the semiconductor integrated device of the present invention. FIG. 2 is a cross-sectional view of the semiconductor integrated device at the position A-A ′.
　多層パッケージ基板２２上には，半導体チップ１２，高速信号（高周波信号の意味である。）配線１４，バイパスコンデンサ１３，制御スルーホールエリヤ２１が配置されている。半導体チップは，処理する高速信号の回線数を増加させるため，全ての辺に高速信号の入力または出力のどちらかのポートが配置されており，半導体チップ１２の４方向に高速信号配線１４を配置している。 On the multilayer package substrate 22, a semiconductor chip 12, high-speed signal (meaning high-frequency signal) wiring 14, a bypass capacitor 13, and a control through-hole area 21 are arranged. In order to increase the number of high-speed signal lines to be processed in the semiconductor chip, either high-speed signal input or output ports are arranged on all sides, and high-speed signal wirings 14 are arranged in four directions of the semiconductor chip 12. is doing.
　この部品を実装したパッケージ配線基板２２の上を樹脂２０で覆いモールドしている。パッケージ配線基板１１の中央に半導体チップ１２を配置し，バンプ１５にてフリップチップ実装している。 The package wiring board 22 on which this component is mounted is covered with resin 20 and molded. A semiconductor chip 12 is arranged in the center of the package wiring board 11 and is flip-chip mounted with bumps 15.
　フリップチップ実装は，ワイヤボンディングに比べ，寄生インダクタンスが小さいことからインピーダンスの不整合を小さくでき損失を低減することができる。さらに，ワイヤによる不要放射を低減することができ，クロストークを抑えることができるため，複数のＧｂｉｔ／ｓ級の高速信号を扱うためには必要となる。 Flip chip mounting has smaller parasitic inductance than wire bonding, so impedance mismatch can be reduced and loss can be reduced. Furthermore, unnecessary radiation due to the wire can be reduced, and crosstalk can be suppressed. Therefore, it is necessary to handle a plurality of high-speed signals of the Gbit / s class.
　図3（第１層），図４（第２層），図５（第３，４層）に多層パッケージ基板２２の各層の配線レイアウトを示す。半導体チップ１１の４辺からは，多層パッケージ配線基板２２の４辺に向かって高速信号配線１４を広げながら配線する。この高速信号配線は高速信号用スルーホール２７を介してパッケージ裏面のＢＧＡ１６に接続されている。この高速信号配線は特に単相のＧＳＧ（ＧＮＤ，信号 (Signal)，ＧＮＤ）配線でも問題ないが，差動のＧＳＳＧ配線を適用してノイズ耐性を上げることも可能である。 FIG. 3 (first layer), FIG. 4 (second layer), and FIG. 5 (third and fourth layers) show the wiring layout of each layer of the multilayer package substrate 22. From the four sides of the semiconductor chip 11, wiring is performed while spreading the high-speed signal wiring 14 toward the four sides of the multilayer package wiring board 22. The high-speed signal wiring is connected to the BGA 16 on the back surface of the package through a high-speed signal through hole 27. This high-speed signal wiring may be a single-phase GSG (GND, Signal, GND) wiring, but it is also possible to increase noise resistance by applying a differential GSSG wiring.
　この各辺から配線されている高速信号配線１４の間に，パッケージ基板のバイパスコンデンサ１３を配置している。この時，配線基板のインダクタンスは数式１にて計算することができ，配線長にインダクタンスが比例する。つまり，配線長が長くなるほどインダクタンスが大きくなることが分かる。 The bypass capacitor 13 of the package substrate is arranged between the high-speed signal wirings 14 wired from each side. At this time, the inductance of the wiring board can be calculated by Equation 1, and the inductance is proportional to the wiring length. That is, it can be seen that the inductance increases as the wiring length increases.
　そのため，バイパスコンデンサ１３は，できる限り半導体チップに１２に近い配置し，パッケージ配線基板１１でのインダクタンスを低減して，半導体チップ１２からの電気的な距離を短くする。 Therefore, the bypass capacitor 13 is disposed as close to the semiconductor chip as possible to reduce the inductance in the package wiring board 11 and shorten the electrical distance from the semiconductor chip 12.
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
　　　μ：透磁率
　　　L：インダクタンス
　　　ｄ：ＶＤＤとＧＮＤの距離
　　　ｗ:配線幅
　　　l:配線長
　また，回路からの電気的な距離によりバイパスコンデンサの求められる帯域が異なる。ＰＫＧ基板上には，ＭＨｚ～ＧＨｚ帯の領域の対応が求められるため，幅０．３ｍｍ×長さ０．６ｍｍの０６０３サイズを使用した。また，図２４に，ＰＫＧ基板にバイパスコンデンサを配置しない場合の回路からみた電源配線インピーダンスの計算結果を示す。この場合は，ＰＣＢ上のコンデンサまでの距離とチップ内の容量との反共振により，特定の周波数で極大値を有する特性となる。そこで，図２５に示すように，この極大値となる周波数にＰＫＧ容量までの距離およびＰＫＧ容量で調整し，この極大値となるインピーダンスの絶対値を低減させるようにすると，よりＰＫＧ容量の効果を高めることができる。 μ: Magnetic permeability L: Inductance d: Distance between VDD and GND w: Wiring width l: Wiring length Also, the required band of the bypass capacitor differs depending on the electrical distance from the circuit. On the PKG substrate, since the correspondence of the region from MHz to GHz is required, 0603 size of 0.3 mm width × 0.6 mm length was used. FIG. 24 shows the calculation result of the power supply wiring impedance as seen from the circuit when no bypass capacitor is arranged on the PKG board. In this case, a characteristic having a maximum value at a specific frequency is obtained due to anti-resonance between the distance to the capacitor on the PCB and the capacitance in the chip. Therefore, as shown in FIG. 25, by adjusting the frequency to the maximum value by the distance to the PKG capacity and the PKG capacity, and reducing the absolute value of the impedance at the maximum value, the effect of the PKG capacity is further improved. Can be increased.
　また，半導体チップ１２を動作させるためには，少なくとも，高速信号，ＶＤＤ，ＧＮＤの他に，高速信号の伝送距離を変わると増幅器の利得を調整し波形等化量を変化させたり，通信データが無い時間には，誤動作防止のために出力を停止させたりする制御信号が必要である。 Further, in order to operate the semiconductor chip 12, at least in addition to the high-speed signal, VDD, GND, if the transmission distance of the high-speed signal is changed, the gain of the amplifier is adjusted to change the waveform equalization amount or the communication data is changed. When there is no time, a control signal that stops the output is necessary to prevent malfunction.
　この時，高周波信号の特性を劣化させずに制御信号を入力するための，半導体チップ１２のパッド配置の一例を図６に示す。各半導体チップ１２の各辺の中央付近に高速信号の入力パッドもしくは出力パッドを配置し，４角から電源および制御信号を入力することが最適である。換言すれば、この図に示すように、「信号入力パッド」、「信号出力パッド」と記載されている部分である。即ち、チップ１２の四隅およびその近傍には電源パッドが設けられている。 At this time, an example of the pad arrangement of the semiconductor chip 12 for inputting the control signal without degrading the characteristics of the high frequency signal is shown in FIG. It is optimal to arrange a high-speed signal input pad or output pad near the center of each side of each semiconductor chip 12 and input power and control signals from four corners. In other words, as shown in this figure, it is a portion described as “signal input pad” and “signal output pad”. That is, power pads are provided at the four corners of the chip 12 and in the vicinity thereof.
　「信号入力パッド」は、第１の電源，制御パッドと、その電源，制御パッドに隣接する第２の電源，制御パッドとの間であって、かつ、この２つの電源，制御パッドを結ぶ辺（第１の辺）に沿うように設ける。「信号出力パッド」は、第１の電源，制御パッドと、その電源，制御パッドに隣接する第３の電源，制御パッドとの間であって、かつ、この２つの電源，制御パッドを結ぶ辺（第２の辺）に沿うように設ける。そして，半導体チップの各４角に電源，制御パッドを配置する。
「信号入力パッド」，「信号出力パッド」は，ＰＫＧの高速配線に合わせるように，チップの高周波パッドは，ＧＮＤ，信号(＋)，信号（－），ＧＮＤする。この時，隣接している信号(＋)，信号（-）がペアとなり，差動信号を形成している。 The “signal input pad” is between the first power supply / control pad and the second power supply / control pad adjacent to the power supply / control pad, and connects the two power supplies / control pads. Provided along (first side). The “signal output pad” is between the first power supply / control pad and the third power supply / control pad adjacent to the power supply / control pad and connects the two power supplies / control pads. Provided along (second side). Then, a power source and a control pad are arranged at each of the four corners of the semiconductor chip.
The high-frequency pad of the chip is GND, signal (+), signal (−), and GND so that the “signal input pad” and “signal output pad” match the high-speed wiring of the PKG. At this time, the adjacent signal (+) and signal (-) are paired to form a differential signal.
　さらに，電源，制御パッドの領域においても，高周波線路に与える影響をできる限り低減させるために，高周波線路側に電源パッドを，チップの角側に制御パッドおよび，モニタパッドを配置する。これは，電源パッドは常に一定の電圧であるのに対して，制御，モニタパッドはモードに切り替えの時などに，バースト信号やクロックなど電圧が変化する信号のためである。良好な高周波特性は得るためには，高周波線路の周辺は，安定して状態に保つことが求められる。そのため，制御パッドを高周波線路から，離間させることが望ましいためである。 Furthermore, also in the area of the power supply and control pad, in order to reduce the influence on the high frequency line as much as possible, the power supply pad is arranged on the high frequency line side, and the control pad and the monitor pad are arranged on the corner side of the chip. This is because the power supply pad is always at a constant voltage, whereas the control and monitor pads are signals whose voltage changes such as a burst signal and a clock when switching to the mode. In order to obtain good high-frequency characteristics, the periphery of the high-frequency line must be kept stable. For this reason, it is desirable to separate the control pad from the high-frequency line.
　この制御配線は，図３，図４，図５に示すように第１層での引回し線路は配線を最小限にして，半導体チップ１３の近傍にスルーホール１７を介して，図５に示す第３層の内層配線に切換える。そして，バイパスコンデンサ１３は，その制御スルーホールエリヤ２１の半導体チップ１２とは反対側の半導体チップ１２に近い位置に配置する。 As shown in FIG. 3, FIG. 4 and FIG. 5, this control wiring is shown in FIG. 5 through the through hole 17 in the vicinity of the semiconductor chip 13 with the wiring route in the first layer minimized. Switch to the inner wiring of the third layer. The bypass capacitor 13 is arranged at a position close to the semiconductor chip 12 on the opposite side of the control through-hole area 21 from the semiconductor chip 12.
　このようにすることで，図１に示すような、バイパスコンデンサ１３と高速信号配線１４とを有する多層パッケージ配線基板２２と、チップ１２のBGAとをスムーズに接続することができる。 By doing so, the multilayer package wiring board 22 having the bypass capacitor 13 and the high-speed signal wiring 14 as shown in FIG. 1 and the BGA of the chip 12 can be smoothly connected.
　さらに，高速信号の信号を，各辺で入力のみ，出力のみと揃えることで，隣の回線との信号振幅差を低減することができる。よって、入力信号と、出力信号とのクロストーク低減効果もある。 Furthermore, the signal amplitude difference from the adjacent line can be reduced by aligning high-speed signals with only input and only output on each side. Therefore, there is an effect of reducing crosstalk between the input signal and the output signal.
　さらに，各辺（例えば、第１の辺に設けられた信号入力パッド。）と各辺（例えば、第２の辺に設けられた信号出力パッド。）との距離を離す（大きくする）ことができる。且つパッケージ配線基板では，各辺の配線間に高さのあるバイパスコンデンサを配置することで，空間を伝播して結合する信号成分を低減することができ，クロストーク対策となる。 Furthermore, the distance between each side (for example, the signal input pad provided on the first side) and each side (for example, the signal output pad provided on the second side) is increased (increased). it can. Further, in the package wiring board, by arranging a bypass capacitor having a height between the wirings on each side, signal components that propagate through the space and are coupled can be reduced, which is a countermeasure against crosstalk.
　図７にパッケージ配線基板１１裏面のＢＧＡ１６配置を示す。高速信号はパッケージの外周に配置する。この時，高速信号のパッドには周囲にＧＮＤを配置して良好な高周波特性を確保している。また，パッケージの中央付近には電源を配置する。この時，ＶＤＤとＧＮＤを千鳥配置して，スルーホール１７のミューチャル（mutual。相利的な。相利共生があるという意味である。）を高める構成として電源配線の低インピーダンス化を図っている。 FIG. 7 shows the arrangement of the BGA 16 on the back surface of the package wiring board 11. High-speed signals are placed on the outer periphery of the package. At this time, GND is arranged around the high-speed signal pad to ensure good high frequency characteristics. A power supply is placed near the center of the package. At this time, VDD and GND are arranged in a staggered manner to reduce the impedance of the power supply wiring as a configuration that enhances the mutual of the through hole 17 (mutual, meaning that there is mutual benefit). .
　また，制御信号スルーホール配置を図１４，図１５に示す。スルーホールの間隔は，多層基板のデザインルールによって決められている。そこで，半導体チップ１２とバイパスコンデンサ１３の距離を近接させるためには，図１４に示すように，直角四角形の平面形状を有する制御スルーホールエリア21の直交する中心線（図示していない。）を、直角四角形の平面形状を有する半導体チップ12の２本の直交する中心線に対して垂直，水平に並べるよりも，図１５に示すように直角四角形の平面形状を有する制御スルーホールエリア21の直交する中心線（図示していない。）が、直角四角形の平面形状を有する半導体チップ12の２本の直交する中心線に対して４５度傾くように並べるほうが，1/√2だけ近接に配置することができる。制御スルーホールエリア21内には、複数個のスルーホール17が規則的に配置されている。なお、この角度は、０度を超えて９０度未満の角度であれば、０度または９０度の角度の場合よりも上記近接配置が可能となる。 Also, the arrangement of control signal through holes is shown in FIGS. The distance between the through holes is determined by the design rules of the multilayer board. Therefore, in order to make the distance between the semiconductor chip 12 and the bypass capacitor 13 close to each other, as shown in FIG. 14, an orthogonal center line (not shown) of the control through-hole area 21 having a right-angled square planar shape is formed. Rather than arranging the semiconductor chips 12 having a right-angled square planar shape vertically and horizontally with respect to two orthogonal center lines, the control through-hole area 21 having a right-angled square planar shape is orthogonal to the two as shown in FIG. If the center lines (not shown) are arranged so that they are inclined 45 degrees with respect to the two orthogonal center lines of the semiconductor chip 12 having a right-angled rectangular planar shape, they are arranged closer to each other by 1 / √2. be able to. A plurality of through holes 17 are regularly arranged in the control through hole area 21. In addition, if this angle exceeds 0 degree and is an angle of less than 90 degree | times, the said close arrangement | positioning will be attained rather than the case of an angle of 0 degree or 90 degree | times.
　図８に上記半導体チップ１２を集積したパッケージ配線基板２２に搭載して樹脂２０でモールドした半導体集積装置２６をプリント基板２４実装した上面図を図８に示す。 FIG. 8 shows a top view of the semiconductor integrated device 26 mounted on the package wiring board 22 integrated with the semiconductor chip 12 and molded with the resin 20 mounted on the printed board 24 in FIG.
　また，図９に図８のＢ－Ｂ’位置の断面図を示す。ＢＧＡ１６にてプリント基板２４と接続する。プリント基板にも，バイパスコンデンサ１９を具備し，実装した半導体集積装置２６の近傍に配置している。プリント基板２４にも多層基板を用いて各層の配線を図１０，図１１，図１２，図１３に示す。第１層の図１０には，部品配置用のパターンが作成する。 FIG. 9 is a sectional view taken along the line B-B ′ in FIG. The printed circuit board 24 is connected by the BGA 16. The printed circuit board also includes a bypass capacitor 19 and is disposed in the vicinity of the mounted semiconductor integrated device 26. A multilayer substrate is used for the printed circuit board 24, and wiring of each layer is shown in FIG. 10, FIG. 11, FIG. 12, and FIG. A pattern for component placement is created in FIG. 10 of the first layer.
　また，第２層をＧＮＤ層，第３層を高速信号配線層，第４層を電源層として，第３層の高周波線路を第２，第４のＧＮＤおよびＶＤＤは挟むことでストリップラインとして高周波線路を形成している。また，クロストーク対策等で高周波の配線層を分割したい場合は，第５層を設け信号配線として，第６層にＶＤＤまたはＧＮＤを配置することも可能である。また，半導体集積装置２６から，プリント基板２４上のバイパスコンデンサ１９の接続は，ＶＤＤピンは半導体集積装置２６の中央付近に配置されているため，最上層で配線することはできない。 Further, the second layer is a GND layer, the third layer is a high-speed signal wiring layer, the fourth layer is a power supply layer, and the third-layer high-frequency line is sandwiched between the second and fourth GND and VDD so as to be a strip line. A track is formed. Further, when it is desired to divide the high-frequency wiring layer for crosstalk countermeasures, it is possible to provide the fifth layer as a signal wiring and arrange VDD or GND on the sixth layer. Further, the connection of the bypass capacitor 19 on the printed circuit board 24 from the semiconductor integrated device 26 cannot be wired in the uppermost layer because the VDD pin is arranged near the center of the semiconductor integrated device 26.
　そこで，プリント基板１９を多層基板として，スルーホールを介して中間層にて配線して，プリント基板の上層に配置されたバイパスコンデンサと接続する。ＶＤＤに関しは，プリント基板の上層に配置されたバイパスコンデンサと接続する必要があるため，スルーホールを用いて最上層にも配置する。 Therefore, the printed circuit board 19 is used as a multilayer board, wired in an intermediate layer through a through hole, and connected to a bypass capacitor arranged on the upper layer of the printed circuit board. Since VDD needs to be connected to a bypass capacitor disposed on the upper layer of the printed circuit board, it is also disposed on the uppermost layer using a through hole.
　本発明の第２実施例の半導体集積回路装置について説明する。実施例２の半導体チップ１２とバイパスコンデンサ１３との電気的な距離を近づけるために，図１６のように多層基板に１層追加し，５層の多層基板とする。インダクタンスＬ[Ｈ]は，ＶＤＤ側のインダクタンスをＬＶＤＤ，ＧＮＤ側のインダクタンスをＬＧＮＤ，このＶＤＤ側のインダクタンスとＧＮＤ側のインダクタンスのミューチャルインダクタンスをＭとすると，数２で表すことができる。つまり，Ｍを大きくすると，Ｌを小さくなることが分かる。また，Ｍは数３に示す式で表すことができ，ＶＤＤとＧＮＤの距離（ｄ）を近づけて小さくすれば，Ｍが大きくなる。
（数２）
Figure JPOXMLDOC01-appb-I000002
A semiconductor integrated circuit device according to a second embodiment of the present invention will be described. In order to reduce the electrical distance between the semiconductor chip 12 and the bypass capacitor 13 of the second embodiment, one layer is added to the multilayer substrate as shown in FIG. 16 to form a five-layer multilayer substrate. The inductance L [H] can be expressed by Equation 2 where L VDD is the inductance on the VDD side, L GND is the inductance on the GND side, and M is the mutual inductance of the VDD side inductance and the GND side inductance. That is, it can be seen that increasing M decreases L. Further, M can be expressed by the equation shown in Equation 3, and M increases as the distance (d) between VDD and GND is reduced.
(Equation 2)
Figure JPOXMLDOC01-appb-I000002
　
　ＬＶＤＤ:ＶＤＤ側インダクタンス
　ＬＧＮＤ:ＧＮＤインダクタンス
　Ｍ：ＶＤＤ側インダクタンスとＧＮＤインダクタンス間のミューチャルインダクタンス
　
L VDD : VDD side inductance L GND : GND inductance M: Mutual inductance between VDD side inductance and GND inductance
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000003
Ｍ：ミューチャルインダクタンス
μ：透磁率
ｄ：ＶＤＤとＧＮＤの距離
ｗ:配線幅
l:配線長
　そこで，コア層２３を第３層と第４層の間に設け，半導体チップ１２を搭載する側のプリプレグ層を追加する。第１層を高周波信号配線層，第２層をＧＮＤプレーン，第３層をＶＤＤプレーン，第４層を制御配線，第５層をＢＧＡパターンとする。そして，第１層の高速信号配線層として，２層をＧＮＤプレーンでマイクロストリップ線路の高周波線路を形成し，第３層にＶＤＤプレーンとして，ＧＮＤプレーンとの間の誘電体をプリプレグ１層とする。コア層に比べ，プリプレグ層の厚さは，薄いためＧＮＤプレーンとＶＤＤプレーンが近づく。従って，ミューチャルインダクタンスが大きくなり，半導体チップ１２とバイパスコンデンサ１３との電気的な距離を近づけることができる。 M: Mutual inductance μ: Magnetic permeability d: Distance between VDD and GND w: Wiring width
l: Wiring length Therefore, the core layer 23 is provided between the third layer and the fourth layer, and a prepreg layer on the side where the semiconductor chip 12 is mounted is added. The first layer is a high-frequency signal wiring layer, the second layer is a GND plane, the third layer is a VDD plane, the fourth layer is a control wiring, and the fifth layer is a BGA pattern. Then, as the high-speed signal wiring layer of the first layer, the high frequency line of the microstrip line is formed with the two layers as the GND plane, the VDD plane is formed as the third layer, and the dielectric between the GND plane is the one layer of the prepreg. . Since the prepreg layer is thinner than the core layer, the GND plane and the VDD plane are closer to each other. Accordingly, the mutual inductance is increased, and the electrical distance between the semiconductor chip 12 and the bypass capacitor 13 can be reduced.
　本発明の第３実施例の半導体集積回路装置について説明する。図１7は，半導体チップ１２からは，高速信号が２辺からの入出力，パッケージ配線基板１４からは４辺に高速信号が配置される場合の実施例である。 A semiconductor integrated circuit device according to a third embodiment of the present invention will be described. FIG. 17 shows an embodiment in which high-speed signals are input / output from two sides from the semiconductor chip 12 and high-speed signals are arranged on four sides from the package wiring board 14.
　半導体チップは，動作速度が速くなると，特性を安定させるためにトランジスタのゲートの方向を揃える必要がある。しかし，パッケージのＢＧＡ１６は，４辺から入出力した方がプリント基板２４の配線引き回しが簡単となる。この時の半導体チップのパッドパターンを図１８に示す。 As the operation speed of a semiconductor chip increases, it is necessary to align the direction of the gate of the transistor in order to stabilize the characteristics. However, when the BGA 16 of the package is input / output from four sides, the wiring of the printed circuit board 24 becomes easier. The pad pattern of the semiconductor chip at this time is shown in FIG.
　高速の信号を１辺から入力して，対辺から信号出力するような，２辺に配置する。他の２辺から電源および制御信号の入出力を配置する。この半導体チップ１２をパッケージ配線基板１４に搭載した場合，高速信号配線を８回線とすると，半分の４回線を半導体チップ１２の入出力辺と平行なパッケージ配線基板１４の辺から入出力を行い，残りの４回線を，半導体チップ１２の入出力辺と垂直なパッケージ配線基板１４の辺から入出力を行う。 配置 Arrange on two sides so that a high-speed signal is input from one side and output from the opposite side. Power supply and control signal input / output are arranged from the other two sides. When the semiconductor chip 12 is mounted on the package wiring board 14, if the high-speed signal wiring is 8 lines, half of the 4 lines are input / output from the side of the package wiring board 14 parallel to the input / output side of the semiconductor chip 12, The remaining four lines are input / output from the side of the package wiring board 14 perpendicular to the input / output side of the semiconductor chip 12.
　この時，２辺から入出力される信号には，振幅差が生じている可能性があり，クロストークの影響を考慮して，近接で引回しを行わない。この場合，パッケージ配線基板１４にスペースがあり，その位置にバイパスコンデンサ１３および，制御スルーホールエリヤを設ける。このような配置とすることで，高周波特性に優れ，電源品質を向上させた半導体集積装置を提供する。 At this time, there is a possibility that an amplitude difference is generated between the signals input and output from the two sides, and in consideration of the influence of crosstalk, the signals are not routed close to each other. In this case, the package wiring board 14 has a space, and a bypass capacitor 13 and a control through-hole area are provided at that position. With such an arrangement, a semiconductor integrated device having excellent high frequency characteristics and improved power supply quality is provided.
　さらに，図１9に半導体チップを４５°傾けて搭載すると，図１７の半導体チップ１２を傾けない場合に比べ，高速信号配線１４の線路長を短くでき，損失を低減することができるため，より高周波特性に優れた，電源品質を向上させた半導体集積装置を提供することができる。 Furthermore, if the semiconductor chip is mounted at an angle of 45 ° in FIG. 19, the line length of the high-speed signal wiring 14 can be shortened and the loss can be reduced compared with the case where the semiconductor chip 12 of FIG. A semiconductor integrated device having excellent characteristics and improved power supply quality can be provided.
　１１　パッケージ配線基板
　１２　半導体チップ
　１３　パッケージ配線基板のバイパスコンデンサ
　１４　高速信号配線
　１５　バンプ
　１６　ボールグリッドアレイ（ＢＧＡ）
　１７　スルーホール
　１８　パッケージ配線基板の高速信号エリヤ
　１９　プリント基板のバイパスコンデンサ
　２０　ＰＫＧ基板のモールド樹脂
　２１　制御スルーホールエリヤ
　２２　多層パッケージ配線基板
　２３　多層パッケージ配線基板のコア層
　２４　プリント基板
　２５　パッケージ配線基板の電源，制御パッドエリヤ
　２６　半導体集積装置
　２７　高速信号用スルーホール DESCRIPTION OF SYMBOLS 11 Package wiring board 12 Semiconductor chip 13 Bypass capacitor of package wiring board 14 High-speed signal wiring 15 Bump 16 Ball grid array (BGA)
DESCRIPTION OF SYMBOLS 17 Through hole 18 High-speed signal area of package wiring board 19 Bypass capacitor of printed circuit board 20 Mold resin of PKG board 21 Control through-hole area 22 Multilayer package wiring board 23 Core layer of multilayer package wiring board 24 Printed board 25 Power supply of package wiring board , Control pad area 26 Semiconductor integrated device 27 Through hole for high-speed signal

Claims (16)

  1. 　その一の面に半導体チップを実装するための基板を有し、
    　前記基板は多層基板であり、
    　前記基板に設けられた導体からなる配線パターンは、電源電圧を供給するための電源電圧電位供給配線パターン、接地電位を供給するための接地電位供給配線パターン、その外部から前記半導体チップの内部への入力信号を供給するか、又は前記半導体チップの内部からの出力信号をその外部へ出力信号を供給するための、複数本の、信号配線パターンおよび前記半導体チップを制御するための制御信号を供給するための制御配線パターンを有し、
    　前記半導体チップの表面の平面形状は実質的に第1の直角四角形であり、
    　前記基板の表面の平面形状は実質的に第２の直角四角形であり、
    　前記半導体チップは第１～第４の辺を有する前記第1の直角四角形であり、かつ、前記第１の辺と前記第３の辺とは実質的に並行であり、前記第２の辺と前記第４の辺とは実質的に並行であり、
    　前記基板は第１～第４の辺を有する前記第２の直角四角形であり、かつ、前記第１の辺と前記第３の辺とは実質的に並行であり、前記第２の辺と前記第４の辺とは実質的に並行であり、
    　前記半導体チップは、前記多層基板のうちの一の表面基板上の実質的な中央部分にフリップチップ実装され、前記半導体チップの各バンプと、前記多層基板のうちの一の表面基板上のメタル層とが電気的に接続され、
    　前記半導体チップの前記第１の辺と前記基板の前記第１の辺とは実質的に並行であり、前記半導体チップの前記第２の辺と前記基板の前記第２の辺とは実質的に並行であり、前記半導体チップの前記第３の辺と前記基板の前記第３の辺とは実質的に並行であり、前記半導体チップの前記第４の辺と前記基板の前記第４の辺とは実質的に並行であり、
    　前記半導体チップの前記第１の辺と前記第２の辺の第１の交点と、前記基板の前記第１の辺と前記第２の辺の第２の交点とを結ぶ第１の線の上に第１のバイパスコンデンサが設けられ、
    　前記半導体チップの前記第２の辺と前記第３の辺の第３の交点と、前記基板の前記第２の辺と前記第３の辺の第４の交点とを結ぶ第２の線の上に第２のバイパスコンデンサが設けられ、
    　前記半導体チップの前記第３の辺と前記第４の辺の第５の交点と、前記基板の前記第３の辺と前記第４の辺の第６の交点とを結ぶ第３の線の上に第３のバイパスコンデンサが設けられ、
    　前記半導体チップの前記第４の辺と前記第１の辺の第７の交点と、前記基板の前記第４の辺と前記第１の辺の第８の交点とを結ぶ第４の線の上に第４のバイパスコンデンサが設けられ、
    　前記第１～第４のバイパスコンデンサのそれぞれ一端は、前記多層基板に設けられたスルーホールおよび前記一の表面基板上よりも下層の基板を介して、前記チップの角部にそれぞれ位置する前記チップの制御端子と電気的に接続されていることを特徴とする半導体集積回路装置。     It has a substrate for mounting a semiconductor chip on its one surface,
    The substrate is a multilayer substrate;
    A wiring pattern made of a conductor provided on the substrate includes a power supply voltage potential supply wiring pattern for supplying a power supply voltage, a ground potential supply wiring pattern for supplying a ground potential, and the outside to the inside of the semiconductor chip. A plurality of signal wiring patterns and a control signal for controlling the semiconductor chip are supplied to supply an input signal or to supply an output signal from the inside of the semiconductor chip to the outside. Control wiring pattern for
    The planar shape of the surface of the semiconductor chip is substantially a first right-angled square,
    The planar shape of the surface of the substrate is substantially a second right-angled square;
    The semiconductor chip is the first right-angled quadrilateral having first to fourth sides, and the first side and the third side are substantially parallel to each other, and The fourth side is substantially parallel to the fourth side;
    The substrate is the second right-angled quadrilateral having first to fourth sides, and the first side and the third side are substantially parallel, and the second side and the side Substantially parallel to the fourth side,
    The semiconductor chip is flip-chip mounted on a substantial central portion on one surface substrate of the multilayer substrate, and each bump of the semiconductor chip and a metal layer on one surface substrate of the multilayer substrate And are electrically connected,
    The first side of the semiconductor chip and the first side of the substrate are substantially parallel, and the second side of the semiconductor chip and the second side of the substrate are substantially The third side of the semiconductor chip and the third side of the substrate are substantially parallel, and the fourth side of the semiconductor chip and the fourth side of the substrate Are substantially parallel,
    On a first line connecting a first intersection of the first side and the second side of the semiconductor chip and a second intersection of the first side and the second side of the substrate Is provided with a first bypass capacitor,
    On a second line connecting the third intersection of the second side and the third side of the semiconductor chip and the fourth intersection of the second side and the third side of the substrate Is provided with a second bypass capacitor,
    On a third line connecting the fifth intersection of the third side and the fourth side of the semiconductor chip and the sixth intersection of the third side and the fourth side of the substrate Is provided with a third bypass capacitor,
    On the fourth line connecting the fourth side of the semiconductor chip and the seventh intersection of the first side and the fourth side of the substrate and the eighth intersection of the first side Is provided with a fourth bypass capacitor,
    One end of each of the first to fourth bypass capacitors is located at a corner of the chip via a through hole provided in the multilayer substrate and a substrate lower than the first surface substrate. A semiconductor integrated circuit device characterized in that it is electrically connected to the control terminal.
  2. 　前記基板は、樹脂基板であることを特徴とする請求項１記載の半導体集積回路装置。 2. The semiconductor integrated circuit device according to claim 1, wherein the substrate is a resin substrate.
  3. 　前記入力信号および前記出力信号の動作周波数は、10Gbps以上、100Gbps以下であることを特徴とする請求項１記載の半導体集積回路装置。 2. The semiconductor integrated circuit device according to claim 1, wherein operating frequencies of the input signal and the output signal are 10 Gbps or more and 100 Gbps or less.
  4. 　前記第１～第４のバイパスコンデンサは、前記半導体チップに近接して設けられていることを特徴とする請求項１記載の半導体集積回路装置。 2. The semiconductor integrated circuit device according to claim 1, wherein the first to fourth bypass capacitors are provided close to the semiconductor chip.
  5. 　前記半導体チップの前記第１の辺および前記第３の辺の中央部分には信号入力パッドが集中的に配置され、
    　前記半導体チップの前記第２の辺および前記第４の辺の中央部分には信号出力パッドが集中的に配置され、
    　前記半導体チップの前記第１～第４の辺の端部およびその近傍には、それぞれ電源パッドおよび制御信号パッドが集中的に配置されていることを特徴とする請求項１記載の半導体集積回路装置。     The signal input pads are intensively arranged in the central part of the first side and the third side of the semiconductor chip,
    The signal output pads are intensively arranged in the central part of the second side and the fourth side of the semiconductor chip,
    2. The semiconductor integrated circuit device according to claim 1, wherein power supply pads and control signal pads are intensively arranged at and near the ends of the first to fourth sides of the semiconductor chip, respectively. .
  6. 　前記第1～第４のバイパスコンデンサのそれぞれ一端と、前記半導体チップの前記第１、第３、第５および第７の交点とを結ぶ前記第１、第２、第３および第４の線に対して、その長手方向の中心線が０度を超え９０度未満の交差角または４５度の交差角で交差する、直角四角形の平面形状を有する制御スルーホールエリアを有し、
    　前記制御スルーホールエリア内には複数個のスルーホールが規則的に配置され、
    　前記制御スルーホールエリア内の前記スルーホールを介して、前記前記第1～第４のバイパスコンデンサのそれぞれと、前記チップの角部にそれぞれ位置する前記チップの制御端子とが電気的に接続されていることを特徴とする請求項１記載の半導体集積回路装置。     The first, second, third and fourth lines connecting one end of each of the first to fourth bypass capacitors and the first, third, fifth and seventh intersections of the semiconductor chip. On the other hand, it has a control through-hole area having a right-angled square planar shape whose longitudinal centerline intersects at an intersection angle greater than 0 degrees and less than 90 degrees or an intersection angle of 45 degrees,
    A plurality of through holes are regularly arranged in the control through hole area,
    Each of the first to fourth bypass capacitors and a control terminal of the chip located at a corner of the chip are electrically connected via the through hole in the control through hole area. 2. The semiconductor integrated circuit device according to claim 1, wherein:
  7. 　前記多層基板は、相対的に層の厚さが厚い厚層の基板と、相対的に層の厚さが薄い薄層の基板とを有し、一の厚層の基板の一の面に第１の薄層の基板が設けられ、前記一の厚層の基板の他の面に第２の薄層の基板が設けられ、前記半導体チップは薄い薄層の基板上に設けられていることを特徴とする請求項１記載の半導体集積回路装置。 The multilayer substrate includes a thick substrate having a relatively thick layer and a thin substrate having a relatively thin layer, and is formed on one surface of the one thick substrate. One thin layer substrate is provided, a second thin layer substrate is provided on the other surface of the one thick layer substrate, and the semiconductor chip is provided on the thin thin layer substrate. 2. The semiconductor integrated circuit device according to claim 1, wherein:
  8. 　その一の面に半導体チップを実装するための基板を有し、
    　前記基板は多層基板であり、
    　前記基板に設けられた導体からなる配線パターンは、電源電圧を供給するための電源電圧電位供給配線パターン、接地電位を供給するための接地電位供給配線パターン、その外部から前記半導体チップの内部への入力信号を供給するか、又は前記半導体チップの内部からの出力信号をその外部へ出力信号を供給するための、複数本の、信号配線パターンおよび前記半導体チップを制御するための制御信号を供給するための制御配線パターンを有し、
    　前記半導体チップの表面の平面形状は実質的に第1の直角四角形であり、
    　前記基板の表面の平面形状は実質的に第２の直角四角形であり、
    　前記半導体チップは第１～第４の辺を有する前記第1の直角四角形であり、かつ、前記第１の辺と前記第３の辺とは実質的に並行であり、前記第２の辺と前記第４の辺とは実質的に並行であり、
    　前記基板は第１～第４の辺を有する前記第２の直角四角形であり、かつ、前記第１の辺と前記第３の辺とは実質的に並行であり、前記第２の辺と前記第４の辺とは実質的に並行であり、
    　前記半導体チップは、前記多層基板のうちの一の表面基板上の実質的な中央部分にフリップチップ実装され、前記半導体チップの各バンプと、前記多層基板のうちの一の表面基板上のメタル層とが電気的に接続され、
    　前記半導体チップの前記第１の辺と前記基板の前記第１の辺とは実質的に並行であり、前記半導体チップの前記第２の辺と前記基板の前記第２の辺とは実質的に並行であり、前記半導体チップの前記第３の辺と前記基板の前記第３の辺とは実質的に並行であり、前記半導体チップの前記第４の辺と前記基板の前記第４の辺とは実質的に並行であり、
    　前記半導体チップの前記第１の辺と前記第２の辺の第１の交点と、前記基板の前記第１の辺と前記第２の辺の第２の交点とを結ぶ第１の線の上に第１のバイパスコンデンサが設けられ、
    　前記半導体チップの前記第３の辺と前記第４の辺の第３の交点と、前記基板の前記第３の辺と前記第４の辺の第４の交点とを結ぶ第２の線の上に第２のバイパスコンデンサが設けられ、
    　前記第１～第２のバイパスコンデンサのそれぞれ一端は、前記多層基板に設けられたスルーホールおよび前記一の表面基板上よりも下層の基板を介して、前記チップの角部にそれぞれ位置する前記チップの制御端子と電気的に接続されていることを特徴とする半導体集積回路装置。     It has a substrate for mounting a semiconductor chip on its one surface,
    The substrate is a multilayer substrate;
    A wiring pattern made of a conductor provided on the substrate includes a power supply voltage potential supply wiring pattern for supplying a power supply voltage, a ground potential supply wiring pattern for supplying a ground potential, and the outside to the inside of the semiconductor chip. A plurality of signal wiring patterns and a control signal for controlling the semiconductor chip are supplied to supply an input signal or to supply an output signal from the inside of the semiconductor chip to the outside. Control wiring pattern for
    The planar shape of the surface of the semiconductor chip is substantially a first right-angled square,
    The planar shape of the surface of the substrate is substantially a second right-angled square;
    The semiconductor chip is the first right-angled quadrilateral having first to fourth sides, and the first side and the third side are substantially parallel to each other, and The fourth side is substantially parallel to the fourth side;
    The substrate is the second right-angled quadrilateral having first to fourth sides, and the first side and the third side are substantially parallel, and the second side and the side Substantially parallel to the fourth side,
    The semiconductor chip is flip-chip mounted on a substantial central portion on one surface substrate of the multilayer substrate, and each bump of the semiconductor chip and a metal layer on one surface substrate of the multilayer substrate And are electrically connected,
    The first side of the semiconductor chip and the first side of the substrate are substantially parallel, and the second side of the semiconductor chip and the second side of the substrate are substantially The third side of the semiconductor chip and the third side of the substrate are substantially parallel, and the fourth side of the semiconductor chip and the fourth side of the substrate Are substantially parallel,
    On a first line connecting a first intersection of the first side and the second side of the semiconductor chip and a second intersection of the first side and the second side of the substrate Is provided with a first bypass capacitor,
    On a second line connecting the third intersection of the third side and the fourth side of the semiconductor chip and the fourth intersection of the third side and the fourth side of the substrate Is provided with a second bypass capacitor,
    One end of each of the first to second bypass capacitors is located at a corner of the chip via a through hole provided in the multilayer substrate and a substrate lower than the first surface substrate. A semiconductor integrated circuit device characterized in that it is electrically connected to the control terminal.
  9. 　前記基板は、樹脂基板であることを特徴とする請求項８記載の半導体集積回路装置。 9. The semiconductor integrated circuit device according to claim 8, wherein the substrate is a resin substrate.
  10. 　前記入力信号および前記出力信号の動作周波数は、10Gbps以上、100Gbps以下であることを特徴とする請求項８記載の半導体集積回路装置。 The semiconductor integrated circuit device according to claim 8, wherein operating frequencies of the input signal and the output signal are 10 Gbps or more and 100 Gbps or less.
  11. 　前記第１～第２のバイパスコンデンサは、前記半導体チップに接して、又は近接して設けられていることを特徴とする請求項８記載の半導体集積回路装置。 9. The semiconductor integrated circuit device according to claim 8, wherein the first and second bypass capacitors are provided in contact with or in proximity to the semiconductor chip.
  12. 　前記半導体チップの前記第１の辺上には信号入力パッドが集中的に配置され、
    　前記半導体チップの前記第２の辺上には信号出力パッドが集中的に配置され、
    　前記半導体チップの前記第３～第４の辺上の中央部分には、それぞれ電源パッドおよび制御信号パッドが集中的に配置されていることを特徴とする請求項８記載の半導体集積回路装置。     Signal input pads are intensively arranged on the first side of the semiconductor chip,
    Signal output pads are intensively arranged on the second side of the semiconductor chip,
    9. The semiconductor integrated circuit device according to claim 8, wherein power supply pads and control signal pads are intensively arranged at the central portions on the third to fourth sides of the semiconductor chip.
  13. 　その一の面に半導体チップを実装するための基板を有し、
    　前記基板は多層基板であり、
    　前記基板に設けられた導体からなる配線パターンは、電源電圧を供給するための電源電圧電位供給配線パターン、接地電位を供給するための接地電位供給配線パターン、その外部から前記半導体チップの内部への入力信号を供給するか、又は前記半導体チップの内部からの出力信号をその外部へ出力信号を供給するための、複数本の、信号配線パターンおよび前記半導体チップを制御するための制御信号を供給するための制御配線パターンを有し、
    　前記半導体チップの表面の平面形状は実質的に長方形であり、
    　前記基板の表面の平面形状は実質的に正方形または直角四角形であり、
    　前記半導体チップは第１～第４の辺を有する前記長方形であり、かつ、前記第１の辺と前記第３の辺とは実質的に並行であり、前記第２の辺と前記第４の辺とは実質的に並行であり、
    　前記基板は第１～第４の辺を有する前記正方形または直角四角形であり、かつ、前記第１の辺と前記第３の辺とは実質的に並行であり、前記第２の辺と前記第４の辺とは実質的に並行であり、
    　前記半導体チップは、前記多層基板のうちの一の表面基板上の実質的な中央部分にフリップチップ実装され、前記半導体チップの各バンプと、前記多層基板のうちの一の表面基板上のメタル層とが電気的に接続され、
    　前記半導体チップの前記第１の辺の延長線と前記基板の前記第１の辺の延長線とは実質的に４５度の傾きで交差しており、前記半導体チップの前記第２の辺の延長線と前記基板の前記第２の辺の延長線とは実質的に４５度の傾きで交差しており、前記半導体チップの前記第３の辺の延長線と前記基板の前記第３の辺の延長線とは実質的に４５度の傾きで交差しており、前記半導体チップの前記第４の辺の延長線と前記基板の前記第４の辺の延長線とは実質的に４５度の傾きで交差しており、
    　前記半導体チップの前記第１および第３の辺に比べて、相対的に短い辺である、前記半導体チップの前記第２の辺に隣接配置された第１の制御スルーホールエリアの端部近傍に、第１のバイパスコンデンサが設けられ、
    　前記半導体チップの前記第１および第３の辺に比べて、相対的に短い辺である、前記半導体チップの前記第４の辺に隣接配置された第２の制御スルーホールエリアの端部近傍に、第２のバイパスコンデンサが設けられていることを特徴とする半導体集積回路装置。     It has a substrate for mounting a semiconductor chip on its one surface,
    The substrate is a multilayer substrate;
    A wiring pattern made of a conductor provided on the substrate includes a power supply voltage potential supply wiring pattern for supplying a power supply voltage, a ground potential supply wiring pattern for supplying a ground potential, and the outside to the inside of the semiconductor chip. A plurality of signal wiring patterns and a control signal for controlling the semiconductor chip are supplied to supply an input signal or to supply an output signal from the inside of the semiconductor chip to the outside. Control wiring pattern for
    The planar shape of the surface of the semiconductor chip is substantially rectangular,
    The planar shape of the surface of the substrate is substantially square or right-angled square,
    The semiconductor chip is the rectangle having first to fourth sides, and the first side and the third side are substantially parallel, and the second side and the fourth side Is substantially parallel to the edge,
    The substrate is the square having the first to fourth sides or the right-angled quadrangle, and the first side and the third side are substantially parallel, and the second side and the second side The side of 4 is substantially parallel,
    The semiconductor chip is flip-chip mounted on a substantial central portion on one surface substrate of the multilayer substrate, and each bump of the semiconductor chip and a metal layer on one surface substrate of the multilayer substrate And are electrically connected,
    The extension line of the first side of the semiconductor chip and the extension line of the first side of the substrate intersect with each other with an inclination of substantially 45 degrees, and the extension of the second side of the semiconductor chip. The line and the extension line of the second side of the substrate substantially intersect at an inclination of 45 degrees, and the extension line of the third side of the semiconductor chip and the third side of the substrate The extension line intersects with an inclination of substantially 45 degrees, and the extension line of the fourth side of the semiconductor chip and the extension line of the fourth side of the substrate have an inclination of substantially 45 degrees. Crossed at
    In the vicinity of the end of the first control through-hole area disposed adjacent to the second side of the semiconductor chip, which is a relatively short side compared to the first and third sides of the semiconductor chip. A first bypass capacitor is provided;
    In the vicinity of the end of the second control through-hole area disposed adjacent to the fourth side of the semiconductor chip, which is a relatively short side compared to the first and third sides of the semiconductor chip A semiconductor integrated circuit device, wherein a second bypass capacitor is provided.
  14. 　前記基板は、樹脂基板であることを特徴とする請求項１３記載の半導体集積回路装置。 14. The semiconductor integrated circuit device according to claim 13, wherein the substrate is a resin substrate.
  15. 　前記入力信号および前記出力信号の動作周波数は、10Gbps以上、100Gbps以下であることを特徴とする請求項１３記載の半導体集積回路装置。 14. The semiconductor integrated circuit device according to claim 13, wherein operating frequencies of the input signal and the output signal are 10 Gbps or more and 100 Gbps or less.
  16. 　前記半導体チップの前記第１の辺上には信号入力パッドが集中的に配置され、
    　前記半導体チップの前記第２の辺上には信号出力パッドが集中的に配置され、
    　前記半導体チップの前記第３～第４の辺上の中央部分には、それぞれ電源パッドおよび制御信号パッドが集中的に配置されていることを特徴とする請求項１３記載の半導体集積回路装置。     Signal input pads are intensively arranged on the first side of the semiconductor chip,
    Signal output pads are intensively arranged on the second side of the semiconductor chip,
    14. The semiconductor integrated circuit device according to claim 13, wherein power supply pads and control signal pads are intensively arranged at the central portions on the third to fourth sides of the semiconductor chip.
PCT/JP2013/075403 2013-09-20 2013-09-20 Semiconductor integrated circuit device WO2015040727A1 (en)

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