WO2015040727A1 - Dispositif de circuit intégré à semi-conducteur - Google Patents

Dispositif de circuit intégré à semi-conducteur Download PDF

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Publication number
WO2015040727A1
WO2015040727A1 PCT/JP2013/075403 JP2013075403W WO2015040727A1 WO 2015040727 A1 WO2015040727 A1 WO 2015040727A1 JP 2013075403 W JP2013075403 W JP 2013075403W WO 2015040727 A1 WO2015040727 A1 WO 2015040727A1
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Prior art keywords
substrate
semiconductor chip
signal
semiconductor
integrated circuit
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PCT/JP2013/075403
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English (en)
Japanese (ja)
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健治 古後
規雄 中島
高司 川本
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株式会社日立製作所
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Priority to PCT/JP2013/075403 priority Critical patent/WO2015040727A1/fr
Publication of WO2015040727A1 publication Critical patent/WO2015040727A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
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    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a semiconductor integrated circuit device, and more particularly to a package wiring substrate of a semiconductor integrated circuit, a semiconductor integrated device using the wiring substrate, and further to a semiconductor integrated device having a semiconductor chip and a capacitor mounted on the wiring substrate. is there.
  • VDD terminal and the GND terminal may be collectively referred to as a power supply terminal.
  • a semiconductor chip 12 is connected to the center of the PKG wiring board 11 by a bump 15, and a bypass capacitor 13 is disposed on the outer periphery of the semiconductor chip.
  • This bypass capacitor is electrically connected to VDD and GND of the semiconductor chip 11 in the pattern 11 of the PKG wiring board.
  • the PKG wiring board 11 is molded with resin 20 and packaged to form a semiconductor integrated device.
  • This semiconductor device is connected to a printed circuit board (PCB) by a ball grid array (BGA).
  • FIG. 21 shows a model of the power supply wiring impedance when viewed from the circuit side of this mounting structure.
  • the bypass capacitor has a three-stage configuration including a bypass capacitor in the semiconductor chip 12, a bypass capacitor 13 mounted on the PKG substrate, and a bypass capacitor 19 mounted on the PCB substrate.
  • the three-stage bypass capacitors have different electrical distances and capacitance values from the circuit, and different frequency regions corresponding to the respective bypass capacitors.
  • the band above GHz is a bypass capacitor in the semiconductor chip 11 and on the package substrate between the MHz and GHz bands, and the substrate on which the package is mounted is below the MHz band.
  • the capacitors arranged on the package substrate have a 1005 size with a width of 0.5 mm ⁇ a length of 1.0 mm, a 0603 size with a width of 0.3 mm ⁇ a length of 0.6 mm, a width of 0.2 mm ⁇ a length of 0 mm.
  • chip capacitors with different external sizes such as 0402 size of 4 mm.
  • a capacitor with a large external size has a large self-inductance, but can obtain a large capacitance value, and is effective for low frequencies.
  • a capacitor with a small outer size has a small capacitance value but a small self-inductance, and is therefore effective in the high frequency region. Therefore, in high-speed signal transmission having a broadband signal component from several Hz to several tens of GHz, it is necessary to reduce the impedance of the power supply wiring in a wide band by combining a plurality of capacitors.
  • FIG. 22 shows the result of calculating the impedance of the circuit shown in FIG.
  • the impedance of the capacitor is inversely proportional to the frequency, the higher the frequency, the lower the impedance.
  • the part toward the lower right is a part where the capacity appears to be dominant.
  • the portion toward the upper right is a portion where the inductance is dominantly seen. The frequency at which this dominant component switches becomes the antiresonance frequency, and the maximum value of the impedance is generated.
  • FIG. 23 shows a result of plotting the change of the peak value of the power supply wiring impedance when the inductance value which is the distance of the “PKG wiring” shown in FIG. 21 is changed.
  • the impedance dance peak caused by the antiresonance between the PKG wiring and the chip capacitance is the maximum, and it is most effective to suppress this impedance. As described above, this impedance peak is caused by the bypass capacitor capacity in the semiconductor chip 12 and the inductance of the PKG board wiring 11.
  • the semiconductor chip 12 is provided with a bypass capacitor in a portion other than the circuit, and no space is available. Therefore, increasing the capacity of the bypass capacitor in the semiconductor chip 11 requires increasing the chip area and is not actively performed. Therefore, it is important to reduce the inductance of the PKG wiring board 11.
  • Patent Document 1 discloses disposing a bypass capacitor on four sides of a semiconductor chip. However, in this method, since the arrangement of the bypass capacitor overlaps the signal wiring and the four sides, it is extremely difficult to coexist.
  • Non-Patent Document 1 discloses a structure in which a bypass capacitor is disposed on the back surface of the PKG.
  • the BGA cannot be disposed on the back surface of the semiconductor chip, and the number of pins of the PKG is large. Therefore, in order to secure the same number of pins, a larger PKG substrate is required. At the same time, thermal vias cannot be placed directly under the semiconductor chip, thus causing a thermal problem.
  • the bypass capacitor is a high-speed signal (which has the same meaning as a high-frequency signal.
  • the frequency when referred to as a high frequency in this specification is 10 Gbps or more and 100 Gbps or less. The same applies hereinafter.) Therefore, it is necessary to arrange them at positions that are electrically close to the semiconductor chip on the PKG substrate without affecting the wiring.
  • a through hole can be placed directly under the semiconductor chip, so it can be placed in the inner layer of the package with high-speed signal wiring at a position directly under the semiconductor chip, and a bypass capacitor is placed around the semiconductor chip. Is possible.
  • the low inductance of the through hole can be reduced because the layer is thin.
  • the bypass capacitor cannot be disposed in the vicinity of the semiconductor chip, and the inductance of the substrate wiring is large, making it difficult to reduce the power supply wiring impedance.
  • the bias capacitor is disposed between the high-speed signal wirings output from each side of the chip.
  • the position where this bias capacitor is arranged is generally on a straight line connecting the corner of the chip and the corner of the PKG wiring board. That is, for example, as shown in FIG. In FIG. 1, the bias capacitors are denoted by reference numeral 13 and are provided at four locations.
  • the side that provides the input / output end of the high-frequency signal is separated from the side that becomes the input end and the side that becomes the output end. That is, the input / output ends of the high frequency signal are not mixed on the same side. For example, as shown in FIG.
  • the influence of crosstalk can be reduced by arranging the input signals having the same signal amplitude and the output signals separately from each other.
  • a signal input to the semiconductor integrated circuit device shown in FIG. 1 is transmitted over a long distance.
  • the input signal is sufficiently attenuated compared to when it is output from another signal source, and is a minute signal.
  • the signal output from the semiconductor integrated circuit device shown in FIG. 1 assumes an output signal from a normal semiconductor integrated circuit device.
  • the signal amplitude is sufficiently large compared to the input signal.
  • the amplitude voltage of the input signal and the output signal of the present invention are greatly different. For this reason, it is desirable to separate the input signal pad and the output signal pad as much as possible.
  • this high-frequency input / output pad is collected near the center of each side of the semiconductor chip. In this way, the input signal pad and the output signal pad can be separated as much as possible.
  • the input pad group does not include a pad (output terminal) for outputting an output signal.
  • the output pad group generally does not include a pad (input terminal) for applying an input signal.
  • a power supply and a control pad are provided near the end of each side of the semiconductor chip, and a high-frequency signal input / output pad is provided in the center.
  • the area where the power supply and control pad are provided is separated from the area where the input / output pads for high-frequency signals are provided. This also has the effect of reducing the influence of crosstalk by separating the signal pads between the sides.
  • the power supply and control pad may be provided with other than the VDD pad, GND pad, and control pad.
  • FIG. 6 shows an example in which a monitor pad is provided. However, this pad may or may not be present. Since the power supply and control pad of the semiconductor chip are integrated in the four corners of the chip, a bypass capacitor is arranged near the position of the power supply and control pad. As a result, the wiring inductance of the PKG board can be reduced, and the power quality can be improved.
  • the high-frequency signal lines on each side of the semiconductor element are wiring on the PKG substrate on which the semiconductor element is mounted, and the wiring interval increases as the distance from the semiconductor element increases. In such a case, the distance is widened so as to reach the PKG side. At this time, for example, an intersection between the first side and the second side that are orthogonal and adjacent to each other, and one end of the semiconductor element A bypass capacitor is arranged on or near the straight line connecting the two. Thereby, for example, there is an effect that crosstalk between signals between the terminal provided on the first side and the terminal provided on the second side can be reduced.
  • a high-speed semiconductor chip that inputs / outputs a plurality of high-speed signals with a transmission speed of several Gbit / s or more, or 10 Gbps or more per line, has good high-frequency characteristics. Can do. Furthermore, since the bypass capacitor can be placed close to the semiconductor chip, power supply voltage fluctuations can be reduced, and the performance of the semiconductor chip can be fully exploited.
  • 1 is a top view of a semiconductor integrated device according to a first exemplary embodiment of the present invention.
  • 1 is a cross-sectional view of a semiconductor integrated device according to a first embodiment of the present invention at the position of FIG. 1A-A ′.
  • It is a figure which shows the wiring pattern of the 1st layer of the multilayer package board
  • It is a figure which shows the wiring pattern of the 2nd layer of the multilayer package board
  • FIG. 8B is a cross-sectional view of the mounting of the semiconductor integrated device according to the first example of the present invention at the position of FIG. 8B-B ′. It is a figure which shows the wiring pattern of the 1st layer of the multilayer mounting board based on the 1st Example of this invention.
  • FIG. 17 It is sectional drawing of the semiconductor integrated device which concerns on the 4th Example of this invention. It is a top view of the semiconductor chip concerning the 4th example of the present invention. It is another example of the top view of the semiconductor chip which concerns on the 4th Example of this invention. It is a figure which shows an example of the mounting cross-sectional view of a semiconductor integrated device. It is a figure which shows the model of a power supply wiring impedance. It is a figure which shows the relationship between the frequency calculated from the power supply wiring impedance model of FIG. 17, and a power supply wiring impedance. The relationship between the PKG wiring inductance and the relationship between the power supply impedance is shown.
  • a semiconductor integrated circuit device according to the first embodiment of the present invention will be described.
  • FIG. 1 is a top view of the semiconductor integrated device of the present invention.
  • FIG. 2 is a cross-sectional view of the semiconductor integrated device at the position A-A ′.
  • a semiconductor chip 12 On the multilayer package substrate 22, a semiconductor chip 12, high-speed signal (meaning high-frequency signal) wiring 14, a bypass capacitor 13, and a control through-hole area 21 are arranged.
  • high-speed signal input or output ports are arranged on all sides, and high-speed signal wirings 14 are arranged in four directions of the semiconductor chip 12. is doing.
  • the package wiring board 22 on which this component is mounted is covered with resin 20 and molded.
  • a semiconductor chip 12 is arranged in the center of the package wiring board 11 and is flip-chip mounted with bumps 15.
  • FIG. 3 shows the wiring layout of each layer of the multilayer package substrate 22. From the four sides of the semiconductor chip 11, wiring is performed while spreading the high-speed signal wiring 14 toward the four sides of the multilayer package wiring board 22.
  • the high-speed signal wiring is connected to the BGA 16 on the back surface of the package through a high-speed signal through hole 27.
  • This high-speed signal wiring may be a single-phase GSG (GND, Signal, GND) wiring, but it is also possible to increase noise resistance by applying a differential GSSG wiring.
  • the bypass capacitor 13 of the package substrate is arranged between the high-speed signal wirings 14 wired from each side.
  • the inductance of the wiring board can be calculated by Equation 1, and the inductance is proportional to the wiring length. That is, it can be seen that the inductance increases as the wiring length increases.
  • bypass capacitor 13 is disposed as close to the semiconductor chip as possible to reduce the inductance in the package wiring board 11 and shorten the electrical distance from the semiconductor chip 12.
  • FIG. 24 shows the calculation result of the power supply wiring impedance as seen from the circuit when no bypass capacitor is arranged on the PKG board. In this case, a characteristic having a maximum value at a specific frequency is obtained due to anti-resonance between the distance to the capacitor on the PCB and the capacitance in the chip. Therefore, as shown in FIG. 25, by adjusting the frequency to the maximum value by the distance to the PKG capacity and the PKG capacity, and reducing the absolute value of the impedance at the maximum value, the effect of the PKG capacity is further improved. Can be increased.
  • the gain of the amplifier is adjusted to change the waveform equalization amount or the communication data is changed.
  • a control signal that stops the output is necessary to prevent malfunction.
  • FIG. 12 An example of the pad arrangement of the semiconductor chip 12 for inputting the control signal without degrading the characteristics of the high frequency signal is shown in FIG. It is optimal to arrange a high-speed signal input pad or output pad near the center of each side of each semiconductor chip 12 and input power and control signals from four corners. In other words, as shown in this figure, it is a portion described as “signal input pad” and “signal output pad”. That is, power pads are provided at the four corners of the chip 12 and in the vicinity thereof.
  • the “signal input pad” is between the first power supply / control pad and the second power supply / control pad adjacent to the power supply / control pad, and connects the two power supplies / control pads.
  • the “signal output pad” is between the first power supply / control pad and the third power supply / control pad adjacent to the power supply / control pad and connects the two power supplies / control pads.
  • a power source and a control pad are arranged at each of the four corners of the semiconductor chip.
  • the high-frequency pad of the chip is GND, signal (+), signal ( ⁇ ), and GND so that the “signal input pad” and “signal output pad” match the high-speed wiring of the PKG. At this time, the adjacent signal (+) and signal (-) are paired to form a differential signal.
  • the power supply pad is arranged on the high frequency line side, and the control pad and the monitor pad are arranged on the corner side of the chip. This is because the power supply pad is always at a constant voltage, whereas the control and monitor pads are signals whose voltage changes such as a burst signal and a clock when switching to the mode. In order to obtain good high-frequency characteristics, the periphery of the high-frequency line must be kept stable. For this reason, it is desirable to separate the control pad from the high-frequency line.
  • this control wiring is shown in FIG. 5 through the through hole 17 in the vicinity of the semiconductor chip 13 with the wiring route in the first layer minimized. Switch to the inner wiring of the third layer.
  • the bypass capacitor 13 is arranged at a position close to the semiconductor chip 12 on the opposite side of the control through-hole area 21 from the semiconductor chip 12.
  • the multilayer package wiring board 22 having the bypass capacitor 13 and the high-speed signal wiring 14 as shown in FIG. 1 and the BGA of the chip 12 can be smoothly connected.
  • the signal amplitude difference from the adjacent line can be reduced by aligning high-speed signals with only input and only output on each side. Therefore, there is an effect of reducing crosstalk between the input signal and the output signal.
  • each side for example, the signal input pad provided on the first side
  • each side for example, the signal output pad provided on the second side
  • the distance between each side and each side is increased (increased). it can.
  • a bypass capacitor having a height between the wirings on each side signal components that propagate through the space and are coupled can be reduced, which is a countermeasure against crosstalk.
  • FIG. 7 shows the arrangement of the BGA 16 on the back surface of the package wiring board 11.
  • High-speed signals are placed on the outer periphery of the package.
  • GND is arranged around the high-speed signal pad to ensure good high frequency characteristics.
  • a power supply is placed near the center of the package.
  • VDD and GND are arranged in a staggered manner to reduce the impedance of the power supply wiring as a configuration that enhances the mutual of the through hole 17 (mutual, meaning that there is mutual benefit). .
  • control signal through holes is shown in FIGS.
  • the distance between the through holes is determined by the design rules of the multilayer board. Therefore, in order to make the distance between the semiconductor chip 12 and the bypass capacitor 13 close to each other, as shown in FIG. 14, an orthogonal center line (not shown) of the control through-hole area 21 having a right-angled square planar shape is formed. Rather than arranging the semiconductor chips 12 having a right-angled square planar shape vertically and horizontally with respect to two orthogonal center lines, the control through-hole area 21 having a right-angled square planar shape is orthogonal to the two as shown in FIG.
  • center lines are arranged so that they are inclined 45 degrees with respect to the two orthogonal center lines of the semiconductor chip 12 having a right-angled rectangular planar shape, they are arranged closer to each other by 1 / ⁇ 2. be able to.
  • a plurality of through holes 17 are regularly arranged in the control through hole area 21. In addition, if this angle exceeds 0 degree and is an angle of less than 90 degree
  • FIG. 8 shows a top view of the semiconductor integrated device 26 mounted on the package wiring board 22 integrated with the semiconductor chip 12 and molded with the resin 20 mounted on the printed board 24 in FIG.
  • FIG. 9 is a sectional view taken along the line B-B ′ in FIG.
  • the printed circuit board 24 is connected by the BGA 16.
  • the printed circuit board also includes a bypass capacitor 19 and is disposed in the vicinity of the mounted semiconductor integrated device 26.
  • a multilayer substrate is used for the printed circuit board 24, and wiring of each layer is shown in FIG. 10, FIG. 11, FIG. 12, and FIG. A pattern for component placement is created in FIG. 10 of the first layer.
  • the second layer is a GND layer
  • the third layer is a high-speed signal wiring layer
  • the fourth layer is a power supply layer
  • the third-layer high-frequency line is sandwiched between the second and fourth GND and VDD so as to be a strip line.
  • a track is formed.
  • the fifth layer is a signal wiring and arrange VDD or GND on the sixth layer.
  • the connection of the bypass capacitor 19 on the printed circuit board 24 from the semiconductor integrated device 26 cannot be wired in the uppermost layer because the VDD pin is arranged near the center of the semiconductor integrated device 26.
  • the printed circuit board 19 is used as a multilayer board, wired in an intermediate layer through a through hole, and connected to a bypass capacitor arranged on the upper layer of the printed circuit board. Since VDD needs to be connected to a bypass capacitor disposed on the upper layer of the printed circuit board, it is also disposed on the uppermost layer using a through hole.
  • a semiconductor integrated circuit device according to a second embodiment of the present invention will be described.
  • one layer is added to the multilayer substrate as shown in FIG. 16 to form a five-layer multilayer substrate.
  • the inductance L [H] can be expressed by Equation 2 where L VDD is the inductance on the VDD side, L GND is the inductance on the GND side, and M is the mutual inductance of the VDD side inductance and the GND side inductance. That is, it can be seen that increasing M decreases L. Further, M can be expressed by the equation shown in Equation 3, and M increases as the distance (d) between VDD and GND is reduced. (Equation 2)
  • VDD VDD side inductance
  • GND GND inductance
  • M Mutual inductance between VDD side inductance and GND inductance
  • the core layer 23 is provided between the third layer and the fourth layer, and a prepreg layer on the side where the semiconductor chip 12 is mounted is added.
  • the first layer is a high-frequency signal wiring layer
  • the second layer is a GND plane
  • the third layer is a VDD plane
  • the fourth layer is a control wiring
  • the fifth layer is a BGA pattern.
  • the high-speed signal wiring layer of the first layer the high frequency line of the microstrip line is formed with the two layers as the GND plane, the VDD plane is formed as the third layer, and the dielectric between the GND plane is the one layer of the prepreg. . Since the prepreg layer is thinner than the core layer, the GND plane and the VDD plane are closer to each other. Accordingly, the mutual inductance is increased, and the electrical distance between the semiconductor chip 12 and the bypass capacitor 13 can be reduced.
  • FIG. 17 shows an embodiment in which high-speed signals are input / output from two sides from the semiconductor chip 12 and high-speed signals are arranged on four sides from the package wiring board 14.
  • ⁇ Arrange on two sides so that a high-speed signal is input from one side and output from the opposite side. Power supply and control signal input / output are arranged from the other two sides.
  • the semiconductor chip 12 is mounted on the package wiring board 14 if the high-speed signal wiring is 8 lines, half of the 4 lines are input / output from the side of the package wiring board 14 parallel to the input / output side of the semiconductor chip 12, The remaining four lines are input / output from the side of the package wiring board 14 perpendicular to the input / output side of the semiconductor chip 12.
  • the package wiring board 14 has a space, and a bypass capacitor 13 and a control through-hole area are provided at that position. With such an arrangement, a semiconductor integrated device having excellent high frequency characteristics and improved power supply quality is provided.
  • the semiconductor chip is mounted at an angle of 45 ° in FIG. 19, the line length of the high-speed signal wiring 14 can be shortened and the loss can be reduced compared with the case where the semiconductor chip 12 of FIG. A semiconductor integrated device having excellent characteristics and improved power supply quality can be provided.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne, pour obtenir des propriétés de signal grande vitesse satisfaisantes dans un dispositif à semi-conducteur gérant une pluralité de signaux grande vitesse, la diminution des fluctuations dans la tension d'alimentation électrique en fonctionnement de la puce semi-conductrice, en plus de l'implémentation de mesures contre la diaphonie de signal grande vitesse. A cette fin, une faible impédance pour le câblage électrique est importante. Afin d'empêcher une détérioration de propriétés de signal grande vitesse, un câblage de signal grande vitesse (14) est posé sous la forme de lignes droites sur une surface parallèle à une puce semi-conductrice (12) et à un substrat de câblage de boîtier (22). Ce faisant, aucun câblage de signal grande vitesse est acheminé dans les parties de coin de la puce afin de diminuer la diaphonie inter-signal au niveau de chaque bord. Dans chacun de ces espaces, un condensateur de dérivation est disposé, obtenant ainsi un dispositif à semi-conducteur ayant une excellente performance grande vitesse et une qualité de source d'alimentation électrique améliorée.
PCT/JP2013/075403 2013-09-20 2013-09-20 Dispositif de circuit intégré à semi-conducteur WO2015040727A1 (fr)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6352556B1 (ja) * 2017-06-19 2018-07-04 新電元工業株式会社 半導体装置
JP6352555B1 (ja) * 2017-06-19 2018-07-04 新電元工業株式会社 半導体装置
CN109003972A (zh) * 2018-09-03 2018-12-14 董志良 一种电力电子组件集成结构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001144205A (ja) * 1999-11-10 2001-05-25 Canon Inc 多端子素子及びプリント配線板
JP2001308222A (ja) * 2000-04-21 2001-11-02 Hitachi Ltd 実装基板
JP2003282781A (ja) * 2002-03-27 2003-10-03 Minolta Co Ltd 回路基板
WO2008098060A2 (fr) * 2007-02-06 2008-08-14 Sanmina-Sci Corporation Capacité distributive localisée améliorée pour circuits imprimés

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001144205A (ja) * 1999-11-10 2001-05-25 Canon Inc 多端子素子及びプリント配線板
JP2001308222A (ja) * 2000-04-21 2001-11-02 Hitachi Ltd 実装基板
JP2003282781A (ja) * 2002-03-27 2003-10-03 Minolta Co Ltd 回路基板
WO2008098060A2 (fr) * 2007-02-06 2008-08-14 Sanmina-Sci Corporation Capacité distributive localisée améliorée pour circuits imprimés

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6352556B1 (ja) * 2017-06-19 2018-07-04 新電元工業株式会社 半導体装置
JP6352555B1 (ja) * 2017-06-19 2018-07-04 新電元工業株式会社 半導体装置
WO2018235135A1 (fr) * 2017-06-19 2018-12-27 新電元工業株式会社 Dispositif à semi-conducteur
WO2018235137A1 (fr) * 2017-06-19 2018-12-27 新電元工業株式会社 Dispositif à semi-conducteur
US10199486B2 (en) 2017-06-19 2019-02-05 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device
KR101950131B1 (ko) * 2017-06-19 2019-02-19 신덴겐코교 가부시키가이샤 반도체 장치
US10243477B2 (en) 2017-06-19 2019-03-26 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device having a bypass capacitor
KR20190087686A (ko) * 2017-06-19 2019-07-25 신덴겐코교 가부시키가이샤 반도체 장치
KR102009590B1 (ko) 2017-06-19 2019-08-09 신덴겐코교 가부시키가이샤 반도체 장치
CN109003972A (zh) * 2018-09-03 2018-12-14 董志良 一种电力电子组件集成结构
CN109003972B (zh) * 2018-09-03 2024-05-28 董志良 一种电力电子组件集成结构

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