CN111769096A - A universal substrate and preparation method based on three-dimensional capacitance and inductance - Google Patents

Abstract

The invention belongs to the technical field of semiconductor packaging, and particularly relates to a universal substrate based on a three-dimensional capacitor inductor and a preparation method thereof. The universal substrate provided by the invention is provided with the three-dimensional capacitance inductor which is simultaneously integrated in the silicon through hole, and the three-dimensional capacitance inductor value can be adjusted. Because the electrodes of the capacitance inductor are separately prepared, the capacitance inductors on the substrate can be connected in series or in parallel through wire bonding or rewiring, and different inductance and capacitance layouts are obtained. The universal substrate with the passive devices provided by the invention does not need to design the substrate and the passive devices independently when each system is integrated. In addition, the substrate effectively increases the values of capacitance and inductance in the integrated system, can integrate the capacitance and the inductance near a chip in three-dimensional integration, can also improve the function density of TSV in the three-dimensional integration, and improves the utilization rate of silicon in the system integration. Compared with discrete capacitance and inductance on other organic PCBs, the integration level is greatly improved.

Description

A universal substrate and preparation method based on three-dimensional capacitance and inductance

technical field

The invention belongs to the technical field of semiconductor packaging, and in particular relates to a general substrate based on three-dimensional capacitance and inductance and a preparation method.

Background technique

With the advent of the era of intelligence, people's demand for integrated circuits is constantly increasing, but the feature size of devices is close to the physical limit. In order to further improve the performance and integration, some researchers can greatly improve the functional density of the chip by systematically integrating the chip in the three-dimensional direction. However, the requirements for the substrate of 3D system integration are much higher than those of ordinary packaged substrates, because with the increase of chip density in system integration, signal coupling becomes extremely serious, and more and more decoupling capacitors and inductances are required. Only relying on discrete capacitors and inductors on the PCB board cannot meet the requirements in chip integration, because the value of capacitors and inductors is too small, the number is too large, and the distance from the active area of the chip is far. Therefore, the substrate (interchange board) with higher capacitance and inductance value can greatly improve the integration degree and reduce the number of capacitance and inductance. The passive network is directly arranged near or directly under the active components, which can make up for the weakness of the passive network on the PCB board and is of great significance for three-dimensional integration.

At present, the packaging substrates required for 3D system integration are individually customized according to requirements, which are not only expensive, but also have a long design and production cycle. Therefore, a general-purpose substrate with 3D capacitors and inductors has great research and commercial prospects.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a three-dimensional capacitor-inductor-based universal substrate with high TSV function density and high system integration and a preparation method thereof.

The general substrate based on three-dimensional capacitance and inductance provided by the present invention has three-dimensional capacitance and inductance simultaneously integrated in silicon through holes on the substrate, and the value of three-dimensional capacitance and inductance can be adjusted. Combine or re-wire the capacitors and inductors on the substrate in series or parallel to obtain different inductors and capacitor layouts, wherein the three-dimensional capacitors and inductors include:

a substrate, formed with through-silicon vias;

A three-dimensional capacitor is formed on the sidewall of the through silicon via, and includes a first metal layer, a second insulating layer and a second metal layer in sequence;

The three-dimensional inductor is composed of the center filling metal of the through-silicon via and the re-wiring of the planar thick metal;

Wherein, a first insulating layer is provided between the sidewall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is provided between the three-dimensional capacitor and the three-dimensional inductor.

In the universal substrate of the present invention, preferably, the second insulating layer is a high-K dielectric material.

In the universal substrate of the present invention, preferably, the first metal layer and the second metal layer are Cu, TiN, or Cr.

In the general substrate of the present invention, preferably, the substrate is high-resistance silicon, glass, BT resin or a flexible substrate.

In the universal substrate of the present invention, preferably, the first insulating layer and the third insulating layer are silicon oxide or silicon nitride.

The present invention also provides a general substrate preparation method based on three-dimensional capacitance and inductance, comprising the following steps:

Etching to form blind holes on the substrate;

forming a first insulating layer in the blind hole and on the surface of the substrate;

Forming each layer of the three-dimensional capacitor on the first insulating layer includes sequentially depositing a first metal layer, a second insulating layer and a second metal layer, and removing the redundant second insulating layer and second metal layer by photolithography and etching layer to expose part of the surface of the first metal layer, and then remove the redundant first metal layer by photolithography to expose part of the surface of the first insulating layer;

forming a third insulating layer to cover the second metal layer, the first metal layer and the first insulating layer;

Electroplating metal, and removing excess metal by chemical mechanical polishing and dry etching, leaving only the center filling metal in the blind hole as a part of the three-dimensional inductor;

respectively opening windows on the first metal layer and the second metal layer to make test or connection pads;

Filling the metal surface in the center of the blind hole to make a three-dimensional inductance test or connection pad;

Temporarily bonding and protecting the front pattern of the substrate, performing mechanical grinding, polishing and dry etching on the back of the substrate to expose the backside TSVs, and dry etching to remove part of the first insulating layer, the TSVs at the bottom of the TSVs the first metal layer, the second insulating layer and the second metal layer until the center filling metal is exposed;

Perform back insulation and photolithography etching to open the window, then deposit thick metal and etch to form interconnection, forming the plane thick metal rewiring part of the three-dimensional inductor;

Temporary bonding is removed to obtain a universal substrate based on three-dimensional capacitance-inductance.

In the preparation method of the present invention, preferably, the second insulating layer is a high-K dielectric material.

In the preparation method of the present invention, preferably, the first metal layer and the second metal layer are Cu, TiN or Cr.

In the preparation method of the present invention, preferably, the substrate is high-resistance silicon, glass, BT resin or a flexible substrate.

In the preparation method of the present invention, preferably, the center filling metal is Cu or W.

The present invention provides a universal substrate with passive devices, and does not require separate design of the substrate and passive devices for each system integration. In addition, this kind of substrate can effectively increase the value of capacitance and inductance in the integrated system, and can integrate the capacitance and inductance near the chip in the three-dimensional integration. It can also improve the functional density of the TSV in the three-dimensional integration and improve the utilization rate of silicon in the system integration. . Compared with discrete capacitor inductors on other organic PCB boards, the level of integration is greatly improved.

Description of drawings

FIG. 1 is a flow chart of a method for preparing a universal substrate based on three-dimensional capacitance and inductance of the present invention.

Figures 2 to 14 show the structural schematic diagrams of each step of a general substrate based on three-dimensional capacitance and inductance.

15 to 16 are schematic diagrams of two three-dimensional capacitance-inductance unit wirings based on a three-dimensional capacitance-inductance general substrate.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It should be understood that the specific The embodiments are only used to explain the present invention, and are not intended to limit the present invention. The described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for convenience The invention is described and simplified without indicating or implying that the device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

Furthermore, numerous specific details of the present invention are described below, such as device structures, materials, dimensions, processing techniques and techniques, in order to provide a clearer understanding of the present invention. However, as can be understood by one skilled in the art, the present invention may be practiced without these specific details. Unless specifically indicated below, various parts of the device may be constructed of materials known to those skilled in the art, or materials developed in the future with similar functions may be employed.

The universal substrate based on the three-dimensional capacitance and inductance of the present invention has the three-dimensional capacitance and inductance simultaneously integrated in the silicon through hole, and the three-dimensional capacitance and inductance value can be adjusted. Since the electrodes of the capacitance and inductance are separated, the capacitance and inductance of the substrate can be connected in series or parallel by wire bonding or rewiring to obtain different inductance and capacitance layouts.

The technical solutions of the present invention are further described below with reference to FIGS. 1 to 14 , taking the method for preparing a general substrate based on three-dimensional capacitance and inductance on a high-resistance silicon substrate as an example. FIG. 1 is a flow chart of a method for preparing a universal substrate based on three-dimensional capacitance and inductance, and FIGS. 2 to 14 show schematic structural diagrams of each step of a universal substrate based on three-dimensional capacitance and inductance.

In step S1, blind holes are formed by etching on the substrate. Specifically, high-resistance silicon is selected as the substrate 200, and a standard optical lithography process is used on the substrate to expose a pattern as the original alignment pattern for lithography. A through-silicon hole pattern is produced by thin-resist photolithography, and a blind hole 201 with a thickness of 200 microns and a diameter of 50 microns is etched by deep silicon etching. The obtained structure is shown in FIG. 2 .

In step S2, on the above structure, a thermal oxidation method is used to form silicon dioxide as the first insulating layer 202, and the obtained structure is shown in FIG. 3 . The thickness of the silicon dioxide is preferably 500 nm, and a thicker insulating layer can effectively reduce the capacitance and inductance brought by the substrate. Then, 200nm silicon nitride is deposited by chemical vapor deposition (PECVD) method to relieve the stress of silicon dioxide. Of course, other stress relief methods can also be used.

Step S3 , as shown in FIGS. 4 to 5 , each layer of the three-dimensional capacitor is formed on the first insulating layer, including sequentially depositing the first metal layer 203 , the second insulating layer 204 and the second metal layer 205 , and performing photolithography and etching. The redundant second insulating layer 204 and the second metal layer 205 are removed by etching, so that part of the surface of the first metal layer 203 is exposed, and the photoresist is removed. Then, the redundant first metal layer 203 is removed by photolithography, so that part of the surface of the first insulating layer 202 is exposed, and the photoresist is removed. The first metal layer and the second metal layer are preferably metals such as Cu, TiN, and Cr. The second insulating layer is preferably a high-K dielectric material such as HfO ₂ . The first metal layer, the second metal layer, and the second insulating layer may be prepared by methods such as atomic layer deposition (ALD), sputtering, and the like.

In step S4 , the third insulating layer 206 is formed to cover the second metal layer 205 , the first metal layer 203 and the first insulating layer 202 , and the obtained structure is shown in FIG. 6 .

Step S5 , depositing a seed layer and electroplating metal 207 , as shown in FIG. 7 . Then chemical mechanical polishing removes most of the metal Cu, then annealing to remove the stress between Cu and silicon dioxide, and then dry etching is performed to remove the residual Cu and the protruding Cu in the hole, leaving only the center filling metal in the blind hole 207. As part of the three-dimensional inductor, the resulting structure is shown in FIG. 8 .

In step S6, windows are opened on the first metal layer 203 and the second metal layer 205 respectively, and test or connection pads 208 and 209 are fabricated. The obtained structure is shown in FIG. 9 .

In step S7, a three-dimensional inductance test or connection pad 210 is formed on the surface of the metal 207 in the center of the blind hole.

In step S8 , the transparent glass 212 and the front surface of the substrate 200 are temporarily bonded by the temporary bonding glue 211 to protect the front surface pattern, and the obtained structure is shown in FIG. 10 . The back of the substrate 200 is mechanically ground and polished to remove 300 microns of silicon (the total thickness of the silicon substrate is 525 microns), and stops at a distance of 25 microns from the bottom of the blind hole. The resulting structure is shown in FIG. 11 . Then, the backside TSVs are exposed by dry etching, and part of the first insulating layer 202 , the first metal layer 203 , the second insulating layer 204 and the second metal layer 205 at the bottom of the TSVs are removed by dry etching until they are exposed. The center is filled with metal 207, and the resulting structure is shown in FIG. 12 .

In step S9 , back insulation is performed, and windows are etched by photolithography, thick metal is deposited and etched to form interconnections, and a planar thick metal re-wiring portion 213 of the three-dimensional inductor is formed. The obtained structure is shown in FIG. 13 .

In step S10, the temporary bonding is removed, and the general silicon substrate is formed, and the resulting structure is shown in FIG. 14 .

As shown in FIG. 14 , the universal substrate based on three-dimensional capacitance and inductance of the present invention has three-dimensional capacitance and inductance simultaneously integrated in through silicon vias, and the value of three-dimensional capacitance and inductance can be adjusted. Since the electrodes of the capacitance and inductance of the substrate are separated, the capacitance and inductance of the substrate can be connected in series or parallel by wire bonding or rewiring to obtain different inductance and capacitance layouts.

The three-dimensional capacitor and inductor include: a substrate 200 formed with through-silicon vias; and a three-dimensional capacitor formed on the sidewalls of the through-silicon vias, including a first metal layer 203 , a second insulating layer 204 and a second metal layer 205 in sequence. The three-dimensional inductor is composed of the center filling metal 207 of the TSV and the planar thick metal re-wiring 213; wherein, a first insulating layer 202 is provided between the sidewall of the TSV and the three-dimensional capacitor, and a first insulating layer 202 is provided between the three-dimensional capacitor and the three-dimensional inductor. There is a third insulating layer 206 .

Preferably, the second insulating layer is a high-K dielectric material, such as HfO ₂ or the like. The first metal layer and the second metal layer are metals such as Cu, TiN, and Cr. The substrate can be selected from high-resistance silicon, glass, bismaleimide triazine (BT) resin, flexible substrate, etc. The first insulating layer and the third insulating layer may be silicon oxide, silicon nitride, or the like. The center filler metal is preferably Cu, W, or the like.

Figures 15 and 16 show schematic diagrams of two three-dimensional capacitance-inductance unit wirings based on a three-dimensional capacitance-inductance general substrate. The electrode wirings of all capacitors on the universal substrate are separated or connected, so as to form three-dimensional capacitors with different capacitance values. Some capacitors can be wire-bonded to achieve the desired capacitance value. Inductors on common substrates all have thick metal traces, resulting in coil resistors of different inductance values. The required inductance value can be obtained by connecting electrodes by wire bonding or rewiring to change the number of coils and the wiring method of the coils.

The invention cleverly utilizes TSV to prepare three-dimensional capacitance and inductance on the substrate, integrates the capacitance and the inductance in the through silicon via (TSV) at the same time, but separates the electrodes of the capacitance and the inductance to form a universal substrate. The capacitance and inductance on the substrate are connected in series or in parallel through external wire bonding or rewiring to obtain the required capacitance and inductance. The present invention can provide a universal substrate, and does not require a separate design of the substrate for each system integration. In addition, this kind of substrate can effectively increase the value of capacitance and inductance in the integrated system, and can integrate the capacitance and inductance near the chip in the three-dimensional integration. It can also improve the functional density of the TSV in the three-dimensional integration and improve the utilization rate of silicon in the system integration. . Compared with discrete capacitor inductors on other organic PCB boards, the level of integration is greatly improved.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. All should be covered within the protection scope of the present invention.

Claims (10)

1. A universal substrate based on three-dimensional capacitance and inductance, characterized in that it has three-dimensional capacitance and inductance simultaneously integrated in through-silicon vias, and the value of the three-dimensional capacitance and inductance can be adjusted; the electrodes of the three-dimensional capacitance and inductance are separated and can be Wire bonding or rerouting of capacitors and inductors on the substrate in series or parallel to obtain different inductor and capacitor layouts, where: The three-dimensional capacitance-inductor includes: a substrate formed with through-silicon vias; A three-dimensional capacitor is formed on the sidewall of the through silicon via, and includes a first metal layer, a second insulating layer and a second metal layer in sequence; The three-dimensional inductor is composed of the center filling metal of the through-silicon via and the re-wiring of the planar thick metal; A first insulating layer is provided between the sidewall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is provided between the three-dimensional capacitor and the three-dimensional inductor. 2 . The universal substrate based on three-dimensional capacitance and inductance according to claim 1 , wherein the second insulating layer is a high-K dielectric material. 3 . 3 . The universal substrate based on three-dimensional capacitance and inductor according to claim 1 , wherein the first metal layer and the second metal layer are Cu, TiN or Cr. 4 . 4 . The universal substrate based on three-dimensional capacitance and inductor according to claim 1 , wherein the substrate is high-resistance silicon, glass, BT resin or a flexible substrate. 5 . 5 . The universal substrate based on three-dimensional capacitor and inductor according to claim 1 , wherein the first insulating layer and the third insulating layer are silicon oxide or silicon nitride. 6 . 6. A general substrate preparation method based on three-dimensional capacitance inductance, characterized in that the specific steps are: Etching to form blind holes on the substrate; forming a first insulating layer in the blind hole and on the surface of the substrate; Forming each layer of the three-dimensional capacitor on the first insulating layer includes sequentially depositing a first metal layer, a second insulating layer and a second metal layer, and removing the redundant second insulating layer and second metal layer by photolithography and etching layer to expose part of the surface of the first metal layer, and then remove the redundant first metal layer by photolithography to expose part of the surface of the first insulating layer; forming a third insulating layer to cover the second metal layer, the first metal layer and the first insulating layer; Electroplating metal, and removing excess metal by chemical mechanical polishing and dry etching, leaving only the center filling metal in the blind hole as a part of the three-dimensional inductor; respectively opening windows on the first metal layer and the second metal layer to make test or connection pads; Filling the metal surface in the center of the blind hole to make a three-dimensional inductance test or connection pad; Temporarily bonding and protecting the front pattern of the substrate, performing mechanical grinding, polishing and dry etching on the back of the substrate to expose the backside TSVs, and dry etching to remove part of the first insulating layer, the TSVs at the bottom of the TSVs the first metal layer, the second insulating layer and the second metal layer until the center filling metal is exposed; Perform back insulation and photolithography etching to open the window, then deposit thick metal and etch to form interconnection, forming the plane thick metal rewiring part of the three-dimensional inductor; Temporary bonding is removed to obtain a universal substrate based on three-dimensional capacitance-inductance. 7 . The method for preparing a universal substrate based on three-dimensional capacitance and inductance according to claim 6 , wherein the second insulating layer is a high-K dielectric material. 8 . 8 . The method for preparing a universal substrate based on three-dimensional capacitance and inductance according to claim 6 , wherein the first metal layer and the second metal layer are Cu, TiN or Cr. 9 . 9 . The method for preparing a universal substrate based on three-dimensional capacitance and inductance according to claim 6 , wherein the substrate is high-resistance silicon, glass, BT resin or a flexible substrate. 10 . 10 . The method for preparing a universal substrate based on three-dimensional capacitance and inductance according to claim 6 , wherein the center filling metal is Cu or W. 11 .

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