CN111769096A - Universal substrate based on three-dimensional capacitance and inductance and preparation method - Google Patents
Universal substrate based on three-dimensional capacitance and inductance and preparation method Download PDFInfo
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- CN111769096A CN111769096A CN202010561677.8A CN202010561677A CN111769096A CN 111769096 A CN111769096 A CN 111769096A CN 202010561677 A CN202010561677 A CN 202010561677A CN 111769096 A CN111769096 A CN 111769096A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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Abstract
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a universal substrate based on a three-dimensional capacitor inductor and a preparation method thereof. The universal substrate provided by the invention is provided with the three-dimensional capacitance inductor which is simultaneously integrated in the silicon through hole, and the three-dimensional capacitance inductor value can be adjusted. Because the electrodes of the capacitance inductor are separately prepared, the capacitance inductors on the substrate can be connected in series or in parallel through wire bonding or rewiring, and different inductance and capacitance layouts are obtained. The universal substrate with the passive devices provided by the invention does not need to design the substrate and the passive devices independently when each system is integrated. In addition, the substrate effectively increases the values of capacitance and inductance in the integrated system, can integrate the capacitance and the inductance near a chip in three-dimensional integration, can also improve the function density of TSV in the three-dimensional integration, and improves the utilization rate of silicon in the system integration. Compared with discrete capacitance and inductance on other organic PCBs, the integration level is greatly improved.
Description
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a universal substrate based on a three-dimensional capacitor inductor and a preparation method thereof.
Background
With the advent of the intelligent age, the demand for integration of integrated circuits has increased, but the feature size of devices has approached physical limits. To further improve performance and integration, some researchers have integrated chips in a three-dimensional system to greatly improve the functional density of the chips. However, the substrate requirements for three-dimensional system integration are much higher than those for ordinary packaging, because as the chip density in system integration increases, signal coupling becomes very severe and more decoupling capacitors and inductors are required. Relying solely on discrete capacitive inductors on a PCB board does not meet the requirements in chip integration because the capacitive inductors are too small in value, too numerous in number and far from the chip active area. Therefore, the substrate (adapter plate) with higher capacitance inductance value can greatly improve the integration level and reduce the capacitance inductance quantity, and meanwhile, the passive network can be directly arranged near or under the active element by the methods of the substrate embedding active element technology, narrow-pitch bump-free bonding and the like, so that the weakness of the passive network on the PCB board is well compensated, and the three-dimensional integration is of great significance.
At present, the packaging substrates required by three-dimensional system integration are individually customized according to requirements, and not only are the price high, but also the design and manufacturing period is long, so that the universal substrate with the three-dimensional capacitance inductor has great research and commercial prospects.
Disclosure of Invention
The invention aims to provide a general substrate based on a three-dimensional capacitor inductor and a preparation method thereof, wherein the general substrate has high TSV function density and high system integration level.
The invention provides a three-dimensional capacitor inductor-based universal substrate, which is provided with a three-dimensional capacitor inductor integrated in a silicon through hole at the same time, wherein the three-dimensional capacitor inductor can be adjusted, electrodes of the three-dimensional capacitor inductor are separated, and the capacitor inductor on the substrate can be connected in series or in parallel through lead bonding or rewiring to obtain different inductor and capacitor layouts, wherein the three-dimensional capacitor inductor comprises:
a substrate formed with a through-silicon via;
the three-dimensional capacitor is formed on the side wall of the silicon through hole and sequentially comprises a first metal layer, a second insulating layer and a second metal layer;
the three-dimensional inductor is formed by rewiring of center filling metal and plane thick metal of the silicon through hole;
a first insulating layer is arranged between the side wall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is arranged between the three-dimensional capacitor and the three-dimensional inductor.
In the universal substrate of the present invention, preferably, the second insulating layer is a high-K dielectric material.
In the universal substrate according to the present invention, preferably, the first metal layer and the second metal layer are Cu, TiN, or Cr.
In the universal base plate of the present invention, preferably, the substrate is made of high-resistance silicon, glass, BT resin, or a flexible base plate.
In the universal substrate according to the present invention, it is preferable that the first insulating layer and the third insulating layer are silicon oxide or silicon nitride.
The invention also provides a preparation method of the universal substrate based on the three-dimensional capacitance and inductance, which comprises the following steps:
etching a substrate to form a blind hole;
forming a first insulating layer in the blind holes and on the surface of the substrate;
forming each layer of the three-dimensional capacitor on the first insulating layer, wherein the steps of depositing a first metal layer, a second insulating layer and a second metal layer in sequence, removing redundant second insulating layers and redundant second metal layers through photoetching and etching to expose partial surfaces of the first metal layers, and removing redundant first metal layers through photoetching and etching to expose partial surfaces of the first insulating layers;
forming a third insulating layer so as to cover the second metal layer, the first metal layer and the first insulating layer;
electroplating metal, removing redundant metal by chemical mechanical polishing and dry etching, and only keeping the center filling metal in the blind hole as a part of the three-dimensional inductor;
respectively windowing the first metal layer and the second metal layer, and manufacturing a test or connection bonding pad;
manufacturing a test or connection bonding pad of the three-dimensional inductor on the surface of the metal filled in the center of the blind hole;
temporarily bonding the front pattern of the protective substrate, carrying out mechanical grinding, polishing and dry etching on the back of the substrate to expose a back silicon through hole, and removing part of the first insulating layer, the first metal layer, the second insulating layer and the second metal layer at the bottom of the silicon through hole by dry etching until the center filling metal is exposed;
carrying out back insulation, photoetching and windowing, then depositing thick metal and etching to form interconnection, and forming a planar thick metal rewiring part of the three-dimensional inductor;
and removing the temporary bonding to obtain the universal substrate based on the three-dimensional capacitance inductor.
In the preparation method of the present invention, preferably, the second insulating layer is a high-K dielectric material.
In the preparation method of the present invention, preferably, the first metal layer and the second metal layer are Cu, TiN, or Cr.
In the preparation method of the invention, preferably, the substrate is high-resistance silicon, glass, BT resin or flexible substrate.
In the preparation method of the present invention, preferably, the center-filling metal is Cu or W.
The invention provides a universal substrate with passive devices, and the substrate and the passive devices are not required to be designed independently when each system is integrated. In addition, the substrate effectively increases the values of capacitance and inductance in the integrated system, can integrate the capacitance and the inductance near a chip in three-dimensional integration, can also improve the function density of TSV in the three-dimensional integration, and improves the utilization rate of silicon in the system integration. Compared with discrete capacitance and inductance on other organic PCBs, the integration level is greatly improved.
Drawings
Fig. 1 is a flow chart of a general substrate preparation method based on three-dimensional capacitance and inductance of the present invention.
FIGS. 2 to 14 show the structural diagrams of the steps of the general substrate based on the three-dimensional capacitance and inductance.
Fig. 15 to 16 are schematic diagrams of two types of three-dimensional capacitive-inductor unit wiring of a three-dimensional capacitive-inductor based general substrate.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly and completely understood, the technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Furthermore, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details. Unless otherwise specified below, each part in the device may be formed of a material known to those skilled in the art, or a material having a similar function developed in the future may be used.
The universal substrate based on the three-dimensional capacitance inductor has the three-dimensional capacitance inductor which is simultaneously integrated in the silicon through hole, and the inductance value of the three-dimensional capacitance inductor can be adjusted. Because the electrodes of the capacitance inductors are separated, the capacitance inductors of the substrate can be connected in series or in parallel through wire bonding or rewiring, and different inductance and capacitance layouts are obtained.
The technical scheme of the present invention is further described below with reference to fig. 1 to 14, taking a method for preparing a three-dimensional capacitance and inductance based universal substrate on a high-resistance silicon substrate as an example. Fig. 1 is a flowchart of a method for manufacturing a three-dimensional capacitive-inductor-based universal substrate, and fig. 2 to 14 are schematic structural diagrams of steps of the three-dimensional capacitive-inductor-based universal substrate.
Step S1, forming blind vias by etching on the substrate. Specifically, high-resistance silicon is selected as the substrate 200, and a pattern is exposed thereon as a lithography original alignment pattern by using a standard optical lithography process. And (3) photoetching the thin photoresist to manufacture a through silicon via pattern, and etching a blind hole 201 with the thickness of 200 microns and the diameter of 50 microns by using a deep silicon etching method to obtain the structure shown in figure 2.
In step S2, silicon dioxide is formed as the first insulating layer 202 on the above structure by thermal oxidation, and the resulting structure is as shown in fig. 3. The thickness of the silicon dioxide is preferably 500nm, and the thicker insulating layer can effectively reduce the capacitance and the inductance brought by the substrate. Then, 200nm silicon nitride is deposited by chemical vapor deposition (PECVD) to relieve the stress of the silicon dioxide, although other methods of relieving the stress may be used.
Step S3, as shown in fig. 4 to 5, forming each layer of the three-dimensional capacitor on the first insulating layer, including depositing the first metal layer 203, the second insulating layer 204 and the second metal layer 205 in sequence, and removing the redundant second insulating layer 204 and the redundant second insulating layer 205 by photolithography and etchingAnd the second metal layer 205, exposing part of the surface of the first metal layer 203, and removing the photoresist. And then, removing the redundant first metal layer 203 by photoetching, exposing part of the surface of the first insulating layer 202, and removing the photoresist. The first metal layer and the second metal layer are preferably metals such as Cu, TiN, and Cr. The second insulating layer is preferably HfO2And high-K dielectric materials. The first metal layer, the second metal layer and the second insulating layer can be prepared by Atomic Layer Deposition (ALD), sputtering and the like.
In step S4, a third insulating layer 206 is formed to cover the second metal layer 205, the first metal layer 203 and the first insulating layer 202, and the resulting structure is shown in fig. 6.
Step S5, deposit a seed layer and plate metal 207, as shown in fig. 7. Then, the chemical mechanical polishing is performed to remove most of the metal Cu, then, the annealing is performed to remove the stress between the Cu and the silicon dioxide, then, the dry etching is performed to remove the residual Cu and the protruding Cu in the hole, only the center filling metal 207 in the blind hole is remained to be used as a part of the three-dimensional inductor, and the obtained structure is shown in fig. 8.
In step S6, windows are opened in the first metal layer 203 and the second metal layer 205, respectively, to form test or connection pads 208 and 209, and the resulting structure is shown in fig. 9.
Step S7, a test or connection pad 210 of the three-dimensional inductor is fabricated on the surface of the metal 207 filled in the center of the blind via.
In step S8, the transparent glass 212 is temporarily bonded to the front surface of the substrate 200 by the temporary bonding paste 211, so as to protect the front surface pattern, and the resulting structure is shown in fig. 10. The back of the substrate 200 was mechanically ground and polished to remove 300 microns thick silicon (the total thickness of the silicon substrate was 525 microns), stopping at 25 microns from the bottom of the blind via, resulting in the structure shown in fig. 11. Then, dry etching is performed to expose the back silicon through hole, and dry etching is performed to remove a part of the first insulating layer 202, the first metal layer 203, the second insulating layer 204 and the second metal layer 205 at the bottom of the silicon through hole until the center filling metal 207 is exposed, so that the structure is shown in fig. 12.
Step S9, performing back insulation, performing photolithography and etching to form a window, depositing thick metal, and etching to form an interconnection, thereby forming a planar thick metal rewiring portion 213 of the three-dimensional inductor, and the resulting structure is shown in fig. 13.
Step S10, removing the temporary bond, and molding the common silicon substrate, the structure is shown in fig. 14.
As shown in fig. 14, the three-dimensional capacitor inductor-based universal substrate of the present invention has a three-dimensional capacitor inductor integrated in a silicon via at the same time, and the three-dimensional capacitor inductor value can be adjusted. Because the electrodes of the capacitance inductance of the substrate are separated, the capacitance inductance of the substrate can be connected in series or in parallel through wire bonding or rewiring to obtain different inductance and capacitance layouts,
wherein, three-dimensional capacitive inductance includes: a substrate 200 formed with through-silicon vias; and the three-dimensional capacitor is formed on the side wall of the through silicon via and sequentially comprises a first metal layer 203, a second insulating layer 204 and a second metal layer 205. A three-dimensional inductor, which is composed of a center filling metal 207 of a through silicon via and a plane thick metal rewiring 213; a first insulating layer 202 is disposed between the sidewall of the through-silicon via and the three-dimensional capacitor, and a third insulating layer 206 is disposed between the three-dimensional capacitor and the three-dimensional inductor.
Preferably, the second insulating layer is a high-K dielectric material, such as HfO2And the like. The first metal layer and the second metal layer are made of Cu, TiN, Cr and other metals. The substrate can be made of high-resistance silicon, glass, Bismaleimide Triazine (BT) resin, flexible substrate and the like. The first insulating layer and the third insulating layer may be silicon oxide, silicon nitride, or the like. The center-fill metal is preferably Cu, W, or the like.
Fig. 15 and 16 show schematic diagrams of two types of three-dimensional capacitive-inductor cell wirings of a three-dimensional capacitive-inductor-based general-purpose substrate. The electrode wiring of all capacitors on the universal substrate is separated and connected, so that three-dimensional capacitors with different capacitance values are combined. Some capacitance may be attached by wire bonding to achieve the desired capacitance value. The inductors on the common substrate are all provided with thick metal wiring, thereby forming coil resistors with different inductance values. The number of coils and the wiring pattern of the coils can be changed by connecting the electrodes by wire bonding or rewiring, etc., so that a desired inductance value can be obtained.
The invention skillfully utilizes the TSV to prepare the three-dimensional capacitor inductor on the substrate, integrates the capacitor and the inductor in the Through Silicon Via (TSV) at the same time, and separates the electrodes of the capacitor and the inductor to form the universal substrate. And the capacitance inductors on the substrate are connected in series or in parallel through external lead bonding or rewiring to obtain the required capacitance inductors. The invention can provide a universal substrate without requiring a separate design substrate for each system integration. In addition, the substrate effectively increases the values of capacitance and inductance in the integrated system, can integrate the capacitance and the inductance near a chip in three-dimensional integration, can also improve the function density of TSV in the three-dimensional integration, and improves the utilization rate of silicon in the system integration. Compared with discrete capacitance and inductance on other organic PCBs, the integration level is greatly improved.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (10)
1. A general substrate based on three-dimensional capacitance inductance is characterized by comprising three-dimensional capacitance inductances which are simultaneously integrated in silicon through holes, and the three-dimensional capacitance inductances can be adjusted; the electrodes of the three-dimensional capacitance inductor are separated, and the capacitance inductors on the substrate can be connected in series or in parallel through lead bonding or rewiring to obtain different inductance and capacitance layouts, wherein:
the three-dimensional capacitive inductor comprises: a substrate formed with a through-silicon via;
the three-dimensional capacitor is formed on the side wall of the silicon through hole and sequentially comprises a first metal layer, a second insulating layer and a second metal layer;
the three-dimensional inductor is formed by rewiring of center filling metal and plane thick metal of the silicon through hole;
a first insulating layer is arranged between the side wall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is arranged between the three-dimensional capacitor and the three-dimensional inductor.
2. The three-dimensional capacitive-inductor based universal substrate of claim 1, wherein the second insulating layer is a high-K dielectric material.
3. The three-dimensional capacitive-inductor based universal substrate of claim 1, wherein the first metal layer and the second metal layer are Cu, TiN or Cr.
4. The three-dimensional capacitive-inductor based universal base plate of claim 1, wherein the substrate is a high-resistance silicon, glass, BT resin or flexible base plate.
5. The three-dimensional capacitive inductor based universal substrate of claim 1, wherein the first insulating layer and the third insulating layer are silicon oxide or silicon nitride.
6. A preparation method of a universal substrate based on a three-dimensional capacitance inductor is characterized by comprising the following specific steps:
etching a substrate to form a blind hole;
forming a first insulating layer in the blind holes and on the surface of the substrate;
forming each layer of the three-dimensional capacitor on the first insulating layer, wherein the steps of depositing a first metal layer, a second insulating layer and a second metal layer in sequence, removing redundant second insulating layers and redundant second metal layers through photoetching and etching to expose partial surfaces of the first metal layers, and removing redundant first metal layers through photoetching and etching to expose partial surfaces of the first insulating layers;
forming a third insulating layer so as to cover the second metal layer, the first metal layer and the first insulating layer;
electroplating metal, removing redundant metal by chemical mechanical polishing and dry etching, and only keeping the center filling metal in the blind hole as a part of the three-dimensional inductor;
respectively windowing the first metal layer and the second metal layer, and manufacturing a test or connection bonding pad;
manufacturing a test or connection bonding pad of the three-dimensional inductor on the surface of the metal filled in the center of the blind hole;
temporarily bonding the front pattern of the protective substrate, carrying out mechanical grinding, polishing and dry etching on the back of the substrate to expose a back silicon through hole, and removing part of the first insulating layer, the first metal layer, the second insulating layer and the second metal layer at the bottom of the silicon through hole by dry etching until the center filling metal is exposed;
carrying out back insulation, photoetching and windowing, then depositing thick metal and etching to form interconnection, and forming a planar thick metal rewiring part of the three-dimensional inductor;
and removing the temporary bonding to obtain the universal substrate based on the three-dimensional capacitance inductor.
7. The method for preparing the three-dimensional capacitor and inductor based universal substrate according to claim 6, wherein the second insulating layer is a high-K dielectric material.
8. The method for preparing the three-dimensional capacitor and inductor based universal substrate according to claim 6, wherein the first metal layer and the second metal layer are Cu, TiN or Cr.
9. The method for preparing the three-dimensional capacitance and inductance based universal base plate according to claim 6, wherein the substrate is high-resistance silicon, glass, BT resin or flexible base plate.
10. The method for preparing the three-dimensional capacitor and inductor based universal substrate according to claim 6, wherein the center-filling metal is Cu or W.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114695339A (en) * | 2020-12-25 | 2022-07-01 | 京东方科技集团股份有限公司 | Substrate integrated with passive device and preparation method thereof |
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| CN102800647A (en) * | 2012-08-22 | 2012-11-28 | 上海宏力半导体制造有限公司 | Three-dimensional spiral inductor and forming method thereof |
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2020
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| CN102800647A (en) * | 2012-08-22 | 2012-11-28 | 上海宏力半导体制造有限公司 | Three-dimensional spiral inductor and forming method thereof |
| CN105655316A (en) * | 2014-11-27 | 2016-06-08 | 珠海越亚封装基板技术股份有限公司 | Chip-use polymer frame being connected with capacitor in series and having at least one hole |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114695339A (en) * | 2020-12-25 | 2022-07-01 | 京东方科技集团股份有限公司 | Substrate integrated with passive device and preparation method thereof |
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