CN104766806B - The method of wafer three-dimensional integration - Google Patents
The method of wafer three-dimensional integration Download PDFInfo
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- CN104766806B CN104766806B CN201510148865.7A CN201510148865A CN104766806B CN 104766806 B CN104766806 B CN 104766806B CN 201510148865 A CN201510148865 A CN 201510148865A CN 104766806 B CN104766806 B CN 104766806B
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 230000010354 integration Effects 0.000 title claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 115
- 239000002184 metal Substances 0.000 claims abstract description 115
- 239000011241 protective layer Substances 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 103
- 238000005530 etching Methods 0.000 claims description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 16
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 11
- 239000007769 metal material Substances 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 239000011135 tin Substances 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 230000008569 process Effects 0.000 abstract description 8
- 206010037660 Pyrexia Diseases 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 66
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000000872 buffer Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
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- 230000009467 reduction Effects 0.000 description 2
- 238000011946 reduction process Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to field of semiconductor manufacture more particularly to a kind of methods of wafer three-dimensional integration.The wafer of the chip comprising different process, different function can be integrated in a heterogeneous three-dimensional structure of wafer scale by the method for the present invention; while chip volume is maintained; the extensive function of improving chip; the metal interconnection between each functional chip has been greatly shortened; reduce fever, power consumption, with postponing; the bandwidth between each function module is improved, the process conditions of thicker protective layer are needed suitable for chip.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of methods of wafer three-dimensional integration.
Background technology
Integrated level is continuously improved in continuous reduce of integrated circuit device, can on chip area every square centimeter at present
More than 1,000,000,000 transistors are integrated, and the total length of metal interconnecting wires is even more to have reached tens kilometers.This not only causes wiring to become
Obtain complex, it is often more important that delay, power consumption, noise of metal interconnection etc. all constantly increase with the reduction of characteristic size
Add, particularly globally interconnected RC (resistance capacitance) delays have seriously affected the performance of integrated circuit.In addition, dynamic power consumption with
The load capacitance value of circuit is directly proportional, at present in the dynamic power consumption of mainstream high performance microprocessor, has more than half all by interconnecting
Caused by line.The method for solving interconnection delay at present is to increase a series of buffers on globally interconnected line, and due to a large amount of
The addition of buffer, the power consumption of circuit increase considerably, i.e., exchange speed for using power consumption.The use of copper-connection and bottom K media makes
Series resistance and parasitic capacitance decrease, and make that technique develops to 90nm by 130nm and overall performance increases, and introduce
Super low-K dielectric can only also maintain technological development to 65nm nodes.Therefore, it is integrated as determining to be substituted transistor for metal interconnection
The principal element of circuit performance.
Chip system (SoC, System on a Chip) technology wishes to realize the repertoire of system on a single chip, such as
Array, simulation, radio frequency, photoelectricity and MEMS (Microelectromechanical Systems, MEMS), SoC hair
Maximum difficulty is different process compatible problems in exhibition, for example, realize SoC may need standard COMS, RF, Bipolar and
The techniques such as MEMS, the substrate material of these manufacturing process are all different, as a consequence it is hardly possible to by its Integrated manufacture on a chip is led to.
Even if the identical module of substrate material will also consider the manufacture feasibility of each circuit module during manufacturing.This aspect cannot be right
The manufacture feasibility of each circuit module.This aspect cannot adequately optimize each circuit module, on the other hand be
It in one plane realizes multiple modules, needs to increase mask plate quantity, arrange mutually to limit during process sequence, certainly will increase
The cost of circuit manufacture, the raising of limiting performance.Therefore, the chip of multifunction module remains discrete at present, and SoC's is each
Kind advantage still rests on the stage of imagination due to the limitation of manufacture.
Three-dimensional interconnection is the collection for realizing multilayer device in one single chip using the third dimension on the basis of planar circuit
Into, i.e., a big planar circuit is divided into several logically related function modules and is distributed in multiple adjacent chip layers,
Then multilayer chiop is integrated by penetrating the three-dimensional perpendicular interconnection of substrate.Three-dimensional interconnection can realize different functions, difference
Globally interconnected length is greatly lowered in the Vertical collection of the multi-chip of technique, so as to which interconnection delay be greatly lowered, improve collection
Into the power consumption of circuit speed, reduction chip.Three-dimensional interconnection can be with integrated multi-layer different process or the integrated electricity of various substrates material
Road, the SoC for heterogeneous chip provide good solution.Three-dimensional interconnection is all physical interconnections, and it is different can to solve multi-chip
Matter integrates, high-bandwidth communication and the problems such as interconnection delay.
But existing three-dimensional integration technology passes through RDL between the first wafer 11 and the second wafer 12
(Redietribution Layer redistribute interconnection layer) layer 14, TSV (Though Silicon ViA regions, silicon perforation) knots
The modes such as structure 13 and tin ball 16 are connected inside and out three-dimensionally integrated, mainly in package level (pA regions ckA regions ge
Level it) carries out.Structure as depicted in figs. 1 and 2 it is difficult to be realized in wafer scale (wA regions fer level), hinders SoC into one
The development of integrated level is walked, this is that those skilled in the art are unwilling to see.
Invention content
In view of the above problems, the present invention provides a kind of method of wafer three-dimensional integration.
The technical proposal for solving the technical problem of the invention is：
A kind of method of wafer three-dimensional integration, wherein, including：
The one bonding wafer for being provided with interconnection area and lead areas is provided, metal connecting line is provided in above-mentioned bonding wafer
The metal layer of mutually insulated is electrically connected by structure and metal layer, above-mentioned metal connection structure, and above-mentioned metal connection structure
Part surface be exposed to the upper surface of above-mentioned bonding wafer；
Above-mentioned interconnection area includes at least an above-mentioned metal connection structure, and above-mentioned lead areas is above-mentioned including at least two
Metal connection structure；
In preparing one first protective layer on above-mentioned bonding wafer, it is sudden and violent that above-mentioned first protective layer covers above-mentioned metal connection structure
The surface of dew；
Part first protective layer is removed, the surface of the above-mentioned metal connection structure in above-mentioned lead areas will be located at
It is exposed；
Metal lead wire is prepared to be electrically connected adjacent above-mentioned metal connection structure in above-mentioned lead areas.
The method of above-mentioned wafer three-dimensional integration, wherein, above-mentioned bonding wafer includes the first wafer and the second wafer, above-mentioned
First wafer includes the first silicon substrate layer and the first BEOL dielectric layers；Second wafer includes the second silicon substrate layer and the 2nd BEOL is situated between
Matter layer, above-mentioned 2nd BEOL dielectric layers cover the upper surface of the first BEOL dielectric layers.
The method of above-mentioned wafer three-dimensional integration, wherein, any of the above-described metal connection structure is electrically connected two above-mentioned gold
Belong to layer.
The method of above-mentioned wafer three-dimensional integration, wherein, any of the above-described metal connection structure is electrically connected two above-mentioned gold
Belong to layer, respectively in above-mentioned first BEOL dielectric layers and in the 2nd BEOL dielectric layers.
The method of above-mentioned wafer three-dimensional integration, wherein, the preparation process of above-mentioned metal connection structure is：Ditch after first through-hole
The etching technics of through-hole after the etching technics of slot or first groove.
The method of above-mentioned wafer three-dimensional integration, wherein, the etching technics of groove includes after above-mentioned elder generation's through-hole：
Etch second silicon substrate layer, above-mentioned 2nd BEOL dielectric layers and above-mentioned first BEOL dielectric layers, with formed by
Above-mentioned layer on surface of metal gives exposed through-hole；
On the basis of above-mentioned through-hole, etching, which is located at any two, needs what is be electrically connected by above-mentioned metal connection structure
Second silicon substrate layer of metal layer, to form above-mentioned groove.
The method of above-mentioned wafer three-dimensional integration, wherein, the etching technics of through-hole includes after above-mentioned elder generation's groove：
Etching is located at the second silicon substrate that any two needs the metal layer being electrically connected by above-mentioned metal connection structure
Bottom, to form groove；
On the basis of above-mentioned groove, etching is positioned at the 2nd BEOL dielectric layers and first of any of the above-described metal layer
BEOL dielectric layers, to form above-mentioned groove.
The method of above-mentioned wafer three-dimensional integration, wherein, after above-mentioned elder generation's through-hole after the etching technics of groove or first groove
The etching technics of through-hole further includes：
After forming above-mentioned groove, in filling metal material in above-mentioned groove.
The method of above-mentioned wafer three-dimensional integration, wherein, the material of above-mentioned metal material is copper, aluminium, tin or tungsten.
The method of above-mentioned wafer three-dimensional integration, wherein, the material of above-mentioned metal lead wire is metal or metal and metal nitrogen
The mixing material of compound.
The method of above-mentioned wafer three-dimensional integration, wherein, the material of above-mentioned first protective layer is nitride or oxide.
The method of above-mentioned wafer three-dimensional integration, wherein, it further includes：
In above-mentioned metal lead wire and first the second protective layer of protective layer disposed thereon, and etch above-mentioned second protective layer and make
State the exposure of metal lead wire part.
Above-mentioned technical proposal has the following advantages that or advantageous effect：
The wafer of chip comprising different process, different function can be integrated in by the method for the present invention by a wafer
In the heterogeneous three-dimensional structure of grade, while chip volume is maintained, the function of chip is improved on a large scale.Also, it significantly contracts
Metal interconnection between short each functional chip, so reduce the fever of chip, power consumption, with delay, improve each work(
Bandwidth between energy module.
Description of the drawings
With reference to appended attached drawing, more fully to describe the embodiment of the present invention.However, appended attached drawing be merely to illustrate and
It illustrates, and is not meant to limit the scope of the invention.
Fig. 1 is the structure diagram of three-dimensional TSV integrated morphologies in background of invention；
Fig. 2 is the structure diagram of tin ball packaged type in background of invention；
Fig. 3-12 is the corresponding structure diagram of each step in the method for the present invention.
Specific embodiment
The present invention provides a kind of method of wafer three-dimensional integration.Suitable for being bonded on-chip lead region and the three-dimensional of wafer
Interconnection area needs separated situation.
The core concept of the present invention is to face each other placement, then will by the way that two panels to have been completed to the wafer of integrated circuit preparation
Above-mentioned two panels wafer bonding, then by setting TSV between wafer, realize different function between different wafers chip it
Between interconnection, and the protective layer that thickness is higher than metal interconnecting layer is formed by using the deposition of multiple protective layer, so as to protect
Protect the metal interconnecting layer structure of chip.
The method of the present invention is described in detail below in conjunction with the accompanying drawings, but not as a limitation of the invention.
First, a bonding wafer for being provided with interconnection area 1 and lead areas 2 is provided, is bonded in wafer and is provided with metal
The metal layer of mutually insulated is electrically connected by connecting line construction 28 and metal layer, metal connection structure, and metal connection structure
Part surface is exposed to the upper surface of bonding wafer.
Interconnection area includes at least a metal connection structure, and lead areas includes at least two metal connection structures；
In preparing one first protective layer 29 on bonding wafer, the first protective layer 29 covers the table of metal connection structure exposure
Face.
The first protective layer of part 29 is removed, the surface of metal connection structure 28 being located in lead areas is given cruelly
Dew.
Metal lead wire 210 is prepared " to give the adjacent metal connection structure 28 ＇ and 28 in the lead areas
Electrical connection.
In the following, a specific embodiment is lifted to be described in further detail to the present invention.
First, the first wafer and the second wafer for having completed integrated circuit preparation are provided, above-mentioned first wafer includes the
One silicon substrate layer 21 and 22 structure of the first BEOL dielectric layers, above-mentioned second wafer include the second silicon substrate layer 24 and the 2nd BEOL
25 structure of dielectric layer.
Wherein, the first BEOL dielectric layers 22 and the 2nd BEOL dielectric layers 25 include several metal layers, and hair is done for ease of illustrating
Bright purpose only shows metal layer at six.
The first i.e. above-mentioned BEOL dielectric layers have further included the first metal layer 23,23 ＇ of third metal layer and fifth metal layer
23 ", the 2nd BEOL dielectric layers 25 have further included second metal layer 26,26 ＇ of the 4th metal layer and the 6th metal layer 26 ".
Wherein, metal interconnection layer of the first metal layer for integrated circuit on the first wafer, with integrated circuit in the first wafer
Interior each function element electrical connection.Part-structure of the second metal layer for the metal interconnection layer of integrated circuit on the second wafer,
It is electrically connected with each function element in the second wafer in integrated circuit.
Then, the second integrated circuit layer covers the upper surface of first integrated circuit layer, and structure is tied as shown in Figure 3
Structure.Bonding technology is carried out to the first wafer for completing to stack and the second wafer again, it is made to be connected as entirety, then to completing to be bonded work
The wafer of skill carries out reduction process, the first silicon substrate layer 21 and the second silicon substrate layer 24 is thinned, to facilitate subsequently to the first silicon
The etching technics of 21 and second silicon substrate layer 24 of basal layer completes the chip interconnection between wafer.
Wherein, any one process program of the prior art can be used (such as machinery with reduction process in above-mentioned bonding technology
Polishing process, chemical mechanical milling tech).
Then, the first lithographic etching technics is carried out to the first wafer and the second wafer, i.e., to the first metal layer and the second gold medal
Belong to 24 part of the second silicon substrate layer above layer and perform etching technique, etching technics to above-mentioned 2nd BEOL dielectric layers, 25 upper surface
Stop, structure as shown in Figure 4.Then at the second silicon substrate layer 24 and the 2nd BEOL dielectric layers 25 disposed thereon, one layer of separation layer 27,
The second silicon substrate layer 24 and the 2nd BEOL dielectric layers 25 to be protected not to be destroyed in subsequent technique.
Wherein, the material of separation layer 27 is preferably oxide or nitride.
Later, the second lithographic etching technics is carried out to the first wafer and the second wafer, i.e., to the above the first metal layer
Two BEOL dielectric layers, 25 part performs etching technique, and etching technics to the first metal layer upper surface stops, structure as shown in Figure 5.
Then, third lithographic etching technics is carried out to above-mentioned first wafer and the second wafer, i.e., to above second metal layer
25 part of the 2nd BEOL dielectric layers perform etching technique, etching technics to above-mentioned second metal layer upper surface stops, such as Fig. 6 institutes
Show structure.
Then, in the groove formed to respectively walking etching technics in first, second, and third lithographic etching technics, filling gold
Belong to material, form the first metal connection structure 28,28 ＇ of the second metal connection structure and third metal connection structure 28 ", and remove
First separation layer 27, structure as shown in Figure 7.
Wherein, metal material is preferably copper, aluminium, tin or tungsten.
Then, in the second silicon base 24, the first metal connection structure 28,28 ＇ of the second metal connection structure and third metal
Connecting line construction 28 " upper surface deposit one layer of first protective layer 29, with protect the second silicon base 24, the first metal connection structure 28,
It is existing that second metal connection structure, 28 ＇ and third metal connection structure 28 " in subsequent technique is not destroyed or occurs metal diffusion
As leading to short circuit, structure as shown in Figure 8.
Wherein, the material of the first protective layer 29 is preferably oxide or nitride.
Then, the 4th lithographic etching technics is carried out to the first wafer and the second wafer, i.e., to 23 ＇ of third metal layer, the 4th
29 part of the first protective layer above 26 ＇ of metal layer, fifth metal layer 23 " and the 6th metal layer 26 " performs etching technique, etches
To 28 ＇ of the second metal connection structure and third metal connection structure 28, " interior filling metal material upper surface stops technique.Then at
Filling metal material upper surface deposition one in one protective layer 29,28 ＇ of the second metal connection structure and third metal connection structure 28 "
Layer metallic film 210, structure as shown in Figure 9.
Wherein, the material of metallic film 210 is preferably the mixing material of metal or metal and metal nitride.
Then, the 5th lithographic etching technics is carried out to the first wafer and the second wafer, i.e., metallic film 210 is performed etching
210 ＇ of metal lead wire of technique, to form electrical connection 28 ＇ of the second metal connection structure and third metal connection structure 28 ", etching
Technique to 29 upper surface of the first protective layer stops, structure as shown in Figure 10.
Then, one layer of second protective layer 211 is deposited in the first protective layer 29 and 210 ＇ upper surfaces of metal lead wire, such as Figure 11 institutes
Show structure.
Finally, the 6th lithographic etching technics is carried out to the first wafer and the second wafer, i.e., to 210 ＇ of metal lead wire above
Second protective layer, 211 part performs etching, and is etched to the stopping of 210 ＇ upper surfaces of metal interconnecting layer, structure as shown in figure 12.
Above-mentioned first is only the present embodiment narration to third lithographic etching technics and sets number, does not form to this implementation
Example limitation, processing step can be adjusted correspondingly according to the needs of actual product.
In conclusion the method for the wafer three-dimensional integration of the present invention can will include different works by the method for the present invention
Skill, different function the wafer of chip be integrated in a heterogeneous three-dimensional structure of wafer scale, for needing lead areas and three
Tieing up interconnection region needs separated process conditions, while chip volume is maintained, the extensive function of improving chip, substantially
Degree shortens the metal interconnection between each functional chip, reduces fever, power consumption, with postponing, improves each function module
Between bandwidth.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly will be evident.
Therefore, appended claims should regard the whole variations and modifications of true intention and range for covering the present invention as.It is weighing
The range and content of any and all equivalence, are all considered as still belonging to the intent and scope of the invention in the range of sharp claim.
Claims (12)
- A kind of 1. method of wafer three-dimensional integration, which is characterized in that including：The one bonding wafer for being provided with interconnection area and lead areas is provided, metal connection structure is provided in the bonding wafer And the metal layer of mutually insulated is electrically connected by metal layer, the metal connection structure, and the portion of the metal connection structure Point surface is exposed to the upper surface of the bonding wafer；The interconnection area includes at least a metal connection structure, and the lead areas includes at least two metals Connecting line construction；In preparing one first protective layer on the bonding wafer, first protective layer covers the metal connection structure exposure Surface；Part first protective layer is removed, the surface for the metal connection structure being located in the lead areas is given Exposure；Metal lead wire is prepared to be electrically connected the adjacent metal connection structure in the lead areas.
- 2. the method for wafer three-dimensional integration as described in claim 1, which is characterized in that the bonding wafer includes the first wafer With the second wafer, first wafer includes the first silicon substrate layer and the first BEOL dielectric layers；Second wafer includes the second silicon substrate Bottom and the 2nd BEOL dielectric layers, second wafer cover the upper surface of first wafer.
- 3. the method for wafer three-dimensional integration as described in claim 1, which is characterized in that the arbitrary metal connection structure is electric Connect two metal layers.
- 4. the method for wafer three-dimensional integration as claimed in claim 2, which is characterized in that arbitrary metal connection structure institute electricity Two metal layers are connected, respectively in the first BEOL dielectric layers and in the 2nd BEOL dielectric layers.
- 5. the method for wafer three-dimensional integration as claimed in claim 2, which is characterized in that the preparation work of the metal connection structure Skill is：After first through-hole after the etching technics of groove or first groove through-hole etching technics.
- 6. the method for wafer three-dimensional integration as claimed in claim 5, which is characterized in that the etching work of groove after elder generation's through-hole Skill includes：Second silicon substrate layer, the 2nd BEOL dielectric layers and the first BEOL dielectric layers are etched, to be formed by described in Layer on surface of metal gives exposed through-hole；On the basis of the through-hole, etching, which is located at any two, needs the metal being electrically connected by the metal connection structure Second silicon substrate layer of layer top, to form the groove.
- 7. the method for wafer three-dimensional integration as claimed in claim 5, which is characterized in that the etching work of through-hole after elder generation's groove Skill includes：Etching is located at the second silicon substrate layer that any two needs the metal layer being electrically connected by the metal connection structure, To form groove；On the basis of the groove, etching is located at the 2nd BEOL dielectric layers and the first BEOL of the arbitrary metal layer Dielectric layer, to form the groove.
- 8. the method for wafer three-dimensional integration as claimed in claims 6 or 7, which is characterized in that the quarter of groove after elder generation's through-hole The etching technics of through-hole further includes after etching technique or first groove：After forming the groove, in filling metal material in the groove.
- 9. the method for wafer three-dimensional integration as claimed in claim 8, which is characterized in that the material of the metal material for copper, Aluminium, tin or tungsten.
- 10. the method for wafer three-dimensional integration as described in claim 1, which is characterized in that the material of the metal lead wire is gold Category or the mixing material of metal and metal nitride.
- 11. the method for wafer three-dimensional integration as described in claim 1, which is characterized in that the material of first protective layer is Nitride or oxide.
- 12. the method for wafer three-dimensional integration as described in claim 1, which is characterized in that further include：In the metal lead wire and first the second protective layer of protective layer disposed thereon, and etch second protective layer and make the gold Belong to lead portion exposure.
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| CN105742197B (en) * | 2016-03-11 | 2018-08-24 | 武汉新芯集成电路制造有限公司 | A kind of bonding crystal circle structure and preparation method thereof |
| CN105977236B (en) * | 2016-05-30 | 2018-09-21 | 武汉新芯集成电路制造有限公司 | It is bonded crystal circle structure and preparation method thereof |
| CN106356365A (en) * | 2016-10-10 | 2017-01-25 | 武汉新芯集成电路制造有限公司 | Semiconductor device and preparation method thereof |
| CN109166820B (en) * | 2018-08-28 | 2020-01-24 | 武汉新芯集成电路制造有限公司 | Semiconductor device manufacturing method and semiconductor device |
| CN112364598B (en) * | 2020-11-10 | 2024-06-25 | 西安紫光国芯半导体有限公司 | Three-dimensional chip, three-dimensional chip integrated verification method, verification device and electronic equipment |
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