JP2009170669A - Wiring board, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the via fracture of a filled stack via which is caused by the stress applied to a wiring board comprising a multi-layer built-up board, etc., with respect to the wiring board and a semiconductor device. <P>SOLUTION: The wiring board has a conductor layer, a first recessed portion formed in the surface of the conductor layer, a first insulating layer formed on the conductor layer, a first opening portion formed in the first insulating layer and exposing the first recessed portion to the external, a first filled via disposed in the first opening portion and at least whose one portion is embedded in the first recessed portion, a second insulating layer formed on the first insulating layer and the first filled via, a second opening portion formed in the second insulating layer and exposing the first filled via to the external, and a second filled via disposed in the second opening portion and connected with the first filled via. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring board, a semiconductor device multilayer buildup board, and a flip chip package, and more particularly, a configuration for increasing the bonding strength of a filled stack via provided in the wiring board of the multilayer buildup board and the wiring board. The present invention relates to a semiconductor device.

Conventionally, a flip chip package is known as a semiconductor device mounting structure, and will be described with reference to FIGS.
See FIG.
FIG. 34 is a diagram for explaining the configuration of a conventional flip chip package, FIG. 34 (a) is a schematic plan view, and FIG. 34 (b) is a schematic diagram along the alternate long and short dash line connecting AA 'in the plan view. FIG.
A conventional flip chip package includes a semiconductor element 201, bumps 202 formed of solder or the like on a surface electrode (not shown) of the semiconductor element 201, wiring on the surface, and paired with the bumps 202 of the semiconductor element 201. In order to protect the semiconductor element 201, the gap between the semiconductor element 201 and the multilayer buildup board 210 is provided in order to protect the semiconductor element 201. The underfill resin 203 is filled with solder balls 216 which serve as connection terminals when the flip chip package is mounted on the mother board.
Reference numeral 204 denotes a polyimide resin coat layer.

See FIG.
FIG. 35 is an enlarged view showing a filled stack via structure. As the multilayer buildup substrate 210, a buildup multilayer substrate having 6 to 8 layers is generally used.
This build-up multilayer substrate 210 has a through-through hole 212 and is laminated with a build-up resin 213 on a core substrate 211 on which wiring has been made in advance on the front and back sides. Each layer is connected with filled vias.

Conventionally, filled vias provided in each layer are connected by spiral vias 217 in which the positions of stacked filled vias are offset as shown in FIG.
However, as the density and density of semiconductors in recent years have increased, the wiring density of the substrate has increased. As a result, it is difficult to route wiring with spiral vias. Filled stack vias 218 connected to the top are becoming mainstream.

In a multilayer build-up substrate using a conventional filled stack via, stress is concentrated at the bottom of the filled stack via due to the stress due to the difference in thermal expansion coefficient between the semiconductor element and the substrate.
In particular, in the case of all-layer filled stack vias, stress concentrates on the connection with the substrate core layer, and there is a problem of breakage of the via joint due to a temperature cycle or the like. Refer to FIG. 36 for this situation. I will explain.

See FIG.
As shown in FIG. 36 (a), when a stress is applied due to a difference in thermal expansion coefficient between the semiconductor element and the substrate, the whole layer filled stack via acts as a single rigid body. Since stress concentrates on the lowermost filled stack via 218 in contact with the core substrate 211 serving as an action point, a via fracture portion 219 is likely to occur in the lowermost filled stack via 218 as shown in FIG. Become.

  Therefore, in order to prevent via breakage, it has been proposed to increase the adhesive strength by making the size of the lowermost filled stack via larger than the size of the filled stack via provided thereon (see, for example, Patent Document 1). .

  Alternatively, the interlayer insulating film for one layer is composed of two layers of dry films having different characteristics, and after forming a forward tapered via hole in the two layers of dry film by laser irradiation, the lower layer is formed by wet etching. It has been proposed to form a constricted portion at the center of a filled stack via by enlarging a via hole provided with a dry film (see, for example, Patent Document 2).

In this case, the stress generated by the difference in thermal expansion coefficient between the semiconductor element and the substrate is concentrated on the constricted portion, so that the stress applied to the portion in contact with the core layer is reduced and the via fracture is avoided.
JP 2006-216713 A JP 2006-253189 A

However, as in Patent Document 1 described above, there is a problem that if the size of the upper filled stack via is reduced, alignment becomes difficult.
On the other hand, if the size of the upper layer filled stack via is made the same as the conventional size, the size of the lowermost filled stack via needs to be larger than that, which hinders high integration.

On the other hand, in the case of the above-mentioned Patent Document 2, since two types of dry films are required, there is a risk of increasing the manufacturing cost.
In addition, since the cross-sectional shape of the via hole filled with plating becomes a drum shape with a constriction in the middle portion, air or the like is involved, and plating is poor, voids are likely to occur on the lower layer side, and the manufacturing yield may be reduced.

  Accordingly, it is an object of the present invention to prevent via breakage of a filled stack via due to stress applied to the wiring board in a wiring board having a filled stack via.

  The wiring board is formed on the conductor layer, the first recess formed on the surface of the conductor layer, the first insulating layer formed on the conductor layer, and the first insulating layer, A first opening that exposes the first recess; a first filled via that is disposed in the first opening and at least partially embedded in the first recess; the first insulating film; A second insulating layer formed on the first filled via, a second opening formed in the second insulating layer and exposing the first filled via, and disposed in the second opening And a second filled via connected to the first filled via.

  From another viewpoint, the wiring board includes a conductor layer, a first protrusion formed on a surface of the conductor layer, a first insulating layer formed on the conductor layer, and the first A first opening that is formed in the insulating layer and exposes the first protrusion, and a first filled via that is disposed in the first opening and in which the first protrusion is embedded in the bottom, A second insulating layer formed on the first insulating film and the first filled via; a second opening formed in the second insulating layer; and a second opening formed in the second opening. And a second filled via connected to the first filled via.

  From another viewpoint, the semiconductor device is required to have a semiconductor element mounted on any of the above-described various wiring boards.

  According to the disclosed wiring board, the bottom surface of the bottommost filled stack via where stress is most concentrated has a via structure that incorporates a recess or protrusion pattern provided in a conductor pattern in contact therewith, and the contact area of the bottom surface of the filled stack via 3 is expanded and enlarged three-dimensionally, the adhesive strength is increased, and via breakage can be effectively suppressed.

Here, a first embodiment of the present invention will be described with reference to FIG.
See Fig. 1 (a)
At least when filling filled vias 15 are formed on the core substrate 11 having the through-holes with the Cu plating layer 12 formed on the inner wall surface and filled with the resin 13 and the predetermined wiring patterns 14 formed on the front and back surfaces, the filled stack vias 15 ₁ of the bottom of the lower layer, the same contact conductor patterns are typically formed so as to fill the recess formed on the wiring pattern 14.

Embedment depth d if see FIG. 1 (b) This is, 5 [mu] m or more, or 1/3 or more of any of the conditions of the thickness t of the wiring pattern 14 in which the bottom portion of the filled stack vias 15 ₁ the lowermost is embedded To satisfy.
Incidentally, the thickness t of the wiring pattern 14 is about 15 to 20 μm.

Thus, by making the filled stack via 15 ₁ into the buried via structure, the bonding area of the filled stack via 15 ₁ is increased and the bonding strength is increased.
In this case, the filled stack vias 15 ₂ and 15 _{3 to} be sequentially stacked may have a buried via structure as shown in the drawing, or may have a conventional non-buried via structure.

Further, the diameters a ₁ , a ₂ , and a ₃ of the filled stack vias are basically the same via diameter, that is, a ₁ = a ₂ without intentionally changing the size as in Patent Document 1 described above. = and a _3.
In this case, the cross-sectional shape of each filled stack via is such that the width of the bottom is the width of the top, that is, the diameter a ₁ when the thickness of the filled stack via is 30 to 40 μm in accordance with the opening formation by laser irradiation. , A ₂ and a ₃ are 80% to 90% inversely tapered.
The filling depth is basically the same depth for each filled stack via, but may be different for each filled stack via.

  In order to obtain such a buried via structure, when the filled stack via 15 is formed, a recess is formed in the conductive pattern located immediately below the filled stack via, that is, the wiring pattern 14 by etching or the like. The filled stack via 15 is formed so as to fill the recess.

Further, as shown in FIG. 1A, after bonding the semiconductor chip 21 onto the wiring substrate 10 with solder bumps 22, an underfill resin 23 is filled between the semiconductor chip 21 and the wiring substrate 10. A flip chip package is configured.
Reference numerals 16, 17, and 24 in the figure denote an interlayer insulating film, a solder resist, and a polyimide resin coating layer, respectively, made of dry film.

In this kind of flip-chip packages, since the lowermost layer of the filled stack vias 15 ₁ exerted concentrated least stress and buried via structures, without via fracture of the filled stack vias 15 ₁ occurs, reliability High flip chip package can be realized.

Next, a second embodiment of the present invention will be described with reference to FIG.
See Fig. 2 (a)
At least when filling filled vias 18 are formed in the core substrate 11 in which the through-holes in which the Cu plating layer 12 is formed on the inner wall surface are filled with the resin 13 and the predetermined wiring pattern 14 is formed on the front and back surfaces, The bottom portion of the lower filled stack via 18 ₁ is formed so as to wrap the protrusion 19 provided by electrolytic plating on the surface of the conductor pattern, typically the wiring pattern 14 in contact therewith.

See FIG. 2B. The height h of the protrusion 19 in this case is 5 μm or more and satisfies the condition of 1/3 or less of the thickness of the filled stack via 18 ₁ .

Thus, by making the filled stack via 18 ₁ into the encapsulated via structure, the bonding area of the filled stack via 18 ₁ is increased and the bonding strength is increased.
In this case, the filled stacked vias 18 ₂ and 18 _{3 to} be sequentially stacked may have a buried via structure as shown in the drawing, or may have a conventional non-buried via structure.

Further, the diameter of each filled stack via is basically the same via diameter without intentionally changing the size as in Patent Document 1 described above.
The heights h ₁ , h ₂ , and h ₃ of the protrusions 19 are basically the same in each filled stack via, but may be different in each filled stack via.

  In order to obtain such an embedded via structure, when the filled stack via 18 is formed, a predetermined opening is formed on the surface of the conductor pattern, i.e., the wiring pattern 14 that is located immediately below the filled stack via. The dried film is attached as a plating frame, and the projections 19 are formed by electrolytic plating. Then, the filled stack via 18 is formed so as to enclose the projections 19.

  Further, as shown in FIG. 2A, after the semiconductor chip 21 is bonded to the wiring board 10 by the solder bumps 22, an underfill resin 23 is filled between the semiconductor chip 21 and the wiring board 10. A flip chip package is configured.

In such a flip-chip package, since the lowermost filled stack via 18 ₁ to which stress is concentrated is applied has an encapsulated via structure, via fracture of the filled stack via 18 ₁ does not occur and reliability is improved. High flip chip package can be realized.

Next, with reference to FIGS. 3 to 5, the manufacturing process of the multilayer build-up substrate according to the first embodiment of the present invention will be described.
Refer to FIG.
First, the core substrate 30 in which the through via 31 is provided and the Cu pattern 32 is formed on the inner wall surface and the main surface of the through via 31 is prepared.

Refer to FIG.
Next, for example, an epoxy resin is embedded in the through via 31 to form a via filling resin layer 33.
At this time, the epoxy resin is applied a plurality of times so that the surface of the via filling resin layer 33 is not recessed with respect to the main surface of the core substrate 30.

Next, after forming a Cu plating seed layer (not shown) by electroless plating on the entire surface, a Cu plating layer 34 having a thickness of, for example, 10 to 20 μm is formed by performing electroplating. To do.
The thickness at this time includes the Cu plating seed layer.
In the following steps and other examples, description of the plating seed layer is omitted.

Refer to FIG.
Next, a resist pattern 35 corresponding to the position of the through via 31 and having an opening 36 at the center is provided, and the Cu plating layer 34 is etched using the resist pattern 35 as a mask to form a wiring pattern 37.
The diameter of the opening 36 at this time is set to a size that matches the tapered shape of the via hole formed in the interlayer insulating film thereafter, and the bottom of the recess 38 formed in the wiring pattern 37 reaches the via filling resin 33. .

Next, after removing the resist pattern 35, for example, a dry film having a thickness of 30 to 40 μm is attached to form the interlayer insulating film 39.
Although this step is performed on the front and back of the core substrate 30, only one surface will be described for the sake of simplicity of illustration and description.

Refer to FIG.
Next, a via hole 41 is formed in the interlayer insulating film 39 by irradiating the laser beam 40. See Fig. 4 (g)
Next, a Cu plating layer 42 is formed on the entire surface.
At this time, polishing is performed so that the surface becomes flat.
In the following steps and other examples, the planarization process is performed when the concave portion is embedded with the Cu plating layer, but the description thereof is omitted.

Refer to FIG. 4 (h)
Next, a resist pattern 43 is provided, and etching is performed using the resist pattern 43 as a mask, so that a filled stack via 44 integrated with the wiring pattern 45 is formed.
At this time, the bottom of the filled stack via 44 has a buried via structure buried by the thickness of the wiring pattern 37, so that the junction area increases and the strength increases.

Refer to FIG.
Next, after removing the resist pattern 43, for example, a dry film having a thickness of 30 to 40 μm is pasted again to form the interlayer insulating film 46.
Refer to FIG.
Next, a via hole 48 is formed in the interlayer insulating film 46 by irradiating a laser beam 47.

Refer to FIG.
Thereafter, the filled stack via 49 integrated with the second-layer wiring pattern 50 is formed by performing the steps of FIGS. 4G and 5I.
By repeating this interlayer insulating film forming process, via hole forming process by laser irradiation, Cu plating process, and etching process for the required number of layers, the multilayer buildup substrate of Example 1 of the present invention is completed.
FIG. 5K shows a three-layer structure, and reference numerals 51, 52, and 53 denote wiring patterns formed integrally with the interlayer insulating film, the filled stack via, and the filled stack via 52, respectively. is there.

  As described above, in the first embodiment of the present invention, the recess is formed in the wiring layer in contact with the core substrate by etching, and the lowermost filled stack via is formed so as to fill the bottom in the recess. The occurrence of breakage can be prevented.

Next, with reference to FIGS. 6 to 8, the manufacturing process of the multilayer buildup substrate according to the second embodiment of the present invention will be described.
See Fig. 6 (a)
First, in the same manner as in the first embodiment, the core substrate 30 in which the through via 31 is provided and the Cu pattern 32 is formed on the inner wall surface and the main surface of the through via 31 is prepared.

See Fig. 6 (b)
Next, for example, an epoxy resin is embedded in the through via 31 to form a via filling resin layer 33.
At this time, the epoxy resin is applied a plurality of times so that the surface of the via filling resin layer 33 is not recessed with respect to the main surface of the core substrate 30.

Next, for example, a Cu plating layer 34 of 10 to 20 μm is formed.
Refer to FIG.
Next, a resist pattern 35 corresponding to the position of the through via 31 and having an opening 36 at the center is provided, and the Cu plating layer 34 is etched using the resist pattern 35 as a mask to form a wiring pattern 37.
The diameter of the opening 36 at this time is set to a size that matches the tapered shape of the via hole formed in the interlayer insulating film thereafter, and the bottom of the recess 38 formed in the wiring pattern 37 reaches the via filling resin 33. .

Next, after removing the resist pattern 35, for example, a dry film having a thickness of 30 to 40 μm is pasted to form the interlayer insulating film 39.
Although this step is performed on the front and back of the core substrate 30, only one surface will be described for the sake of simplicity of illustration and description.

Refer to FIG.
Next, a via hole 41 is formed in the interlayer insulating film 39 by irradiating the laser beam 40. See Fig. 7 (g)
Next, a Cu plating layer 42 is formed on the entire surface.

Refer to FIG.
Next, a resist pattern 54 having an opening 55 at the center is provided, and etching is performed using the resist pattern 54 as a mask, so that a filled stack via 56 integrated with the wiring pattern 57 is formed.

At this time, the bottom of the filled stack via 56 has a buried via structure buried by the thickness of the wiring pattern 37, so that the junction area increases and the strength increases.
At the same time, a recess 58 is also formed on the surface of the wiring pattern 57 formed integrally with the filled stack via 56.
The depth of the recess 58 is equal to or greater than the thickness of the wiring pattern 57.
Incidentally, the thickness of the wiring pattern 57 is about 12 μm.

See Fig. 8 (i)
Next, after removing the resist pattern 54, again, for example, a dry film having a thickness of 30 to 40 μm is pasted to form the interlayer insulating film 46.
Refer to FIG.
Next, a via hole 48 is formed in the interlayer insulating film 46 by irradiating a laser beam 47.

Refer to FIG.
Thereafter, the filled stack via 59 integrated with the second-layer wiring pattern 60 is formed by performing the steps of FIGS. 7G and 8I.
At this time, since the bottom of the filled stack via 59 has a buried via structure embedded in the recess 58 formed in the wiring pattern 57, the junction area increases and the strength increases.
At the same time, a recess 61 is also formed on the surface of the wiring pattern 60 formed integrally with the filled stack via 59.

By repeating this interlayer insulating film forming step, via hole forming step by laser irradiation, Cu plating step, and etching step for the required number of layers, the multilayer buildup substrate of Example 2 of the present invention is completed.
FIG. 8K shows a three-layer structure, and reference numerals 62 and 63 denote a filled stack via and a wiring pattern formed integrally with the filled stack via 62.

  As described above, in Example 2 of the present invention, not only the lowermost filled stack via but also all filled stacked vias have the buried via structure, so that the bonding strength is further increased and the resistance to via breakage is further increased. Rise.

Next, with reference to FIGS. 9 to 11, a manufacturing process of the multilayer buildup substrate according to the third embodiment of the present invention will be described.
See Fig. 9 (a)
First, in the same manner as in the first embodiment, the core substrate 30 in which the through via 31 is provided and the Cu pattern 32 is formed on the inner wall surface and the main surface of the through via 31 is prepared.

Refer to FIG. 9B.
Next, for example, an epoxy resin is embedded in the through via 31 to form a via filling resin layer 33.
At this time, the recess 64 can be formed in the via filling resin layer 33 by performing the epoxy resin coating process once.

Next, refer to FIG. 9C. The Cu plating layer 65 is formed so that the thickness of the flat portion is, for example, 10 to 20 μm.
Refer to FIG.
Next, a resist pattern 35 corresponding to the position of the through via 31 and having an opening 36 at the center is provided, and the Cu plating layer 65 is etched using the resist pattern 35 as a mask to form a wiring pattern 66. A recess 67 is formed in the pattern 66.

Note that the diameter of the opening 36 at this time is set to a size that matches the tapered shape of the via hole formed in the interlayer insulating film thereafter.
The depth of the recess 67 is equal to or greater than the thickness of the wiring pattern 66.
Incidentally, the thickness of the wiring pattern 66 is about 12 μm.

Next, after removing the resist pattern 35, for example, a dry film having a thickness of 30 to 40 μm is pasted to form the interlayer insulating film 39.
Although this step is performed on the front and back of the core substrate 30, only one surface will be described for the sake of simplicity of illustration and description.

Refer to FIG.
Next, a via hole 41 is formed in the interlayer insulating film 39 by irradiating the laser beam 40. See Fig. 10 (g)
Next, a Cu plating layer 68 is formed on the entire surface.

Refer to FIG.
Next, a resist pattern 43 is provided, and etching is performed using the resist pattern 43 as a mask, so that a filled stack via 69 integrated with the wiring pattern 70 is formed.
At this time, the bottom of the filled stack via 69 has a buried via structure embedded in the recess 67 formed in the wiring pattern 66, so that the junction area increases and the strength increases.

Refer to FIG.
Next, after removing the resist pattern 43, for example, a dry film having a thickness of 30 to 40 μm is pasted again to form the interlayer insulating film 46. Refer to FIG.
Next, a via hole 48 is formed in the interlayer insulating film 46 by irradiating a laser beam 47.

Refer to FIG.
Thereafter, the filled stack via 71 integrated with the second-layer wiring pattern 72 is formed by performing the steps of FIG. 10G and FIG. 11I.
By repeating this interlayer insulating film forming step, via hole forming step by laser irradiation, Cu plating step, and etching step for the required number of layers, the multilayer buildup substrate of Example 3 of the present invention is completed.
FIG. 11K shows a three-layer structure, and reference numerals 73 and 74 denote a filled stack via and a wiring pattern formed integrally with the filled stack via 73.

  As described above, in Example 3 of the present invention, the lowermost filled stack via has a buried via structure using the recess formed in the via filling resin, and the entire joint surface with the bottom of the filled stack via is formed. Since this becomes a Cu layer, the bonding strength is increased and the occurrence of via fracture can be prevented.

  Moreover, since the depth of the recess can be controlled by the filling amount of the via filling resin, it is possible to increase the depth of the recess incorporated into the bottom of the filled stack via, and thereby the bonding area with the bottom of the filled stack via. Can be further increased.

Next, with reference to FIG.12 and FIG.13, the manufacturing process of the multilayer buildup board | substrate of Example 4 of this invention is demonstrated.
Refer to FIG.
First, in the same manner as in the third embodiment, the core substrate 30 in which the through via 31 is provided and the Cu pattern 32 is formed on the inner wall surface and the main surface of the through via 31 is prepared.

Refer to FIG.
Next, for example, an epoxy resin is embedded in the through via 31 to form a via filling resin layer 33.
At this time, the recess 64 can be formed in the via filling resin layer 33 by performing the epoxy resin coating process once.

Next, refer to FIG. 12C. Next, a Cu plating layer 75 having a thickness of, for example, 10 to 20 μm is formed on the entire surface.
At this time, since the Cu plating layer 75 is curved along the recess 64, the recess 76 is formed.
Refer to FIG.
Next, a resist pattern 77 is provided corresponding to the position of the through via 31, and the Cu plating layer 75 is etched using the resist pattern 77 as a mask to form a wiring pattern 78.

Next, after removing the resist pattern 77, for example, a dry film having a thickness of 30 to 40 μm is pasted to form the interlayer insulating film 39.
Although this step is performed on the front and back of the core substrate 30, only one surface will be described for the sake of simplicity of illustration and description.

Refer to FIG.
Next, a via hole 41 is formed in the interlayer insulating film 39 by irradiating the laser beam 40. See Fig. 13 (g)
Next, a Cu plating layer 68 is formed on the entire surface.
See FIG. 13 (h)
Thereafter, the steps shown in FIGS. 10 (h) to 11 (k) in the third embodiment are sequentially performed to complete a multilayer buildup substrate having a three-layer filled stack via.

  In the fourth embodiment of the present invention, when the Cu plating layer is formed on the core substrate, the concave portion 64 formed in the via filling resin layer 33 is not buried, so that the buried via structure is formed. The recess etching process is not required, and the manufacturing process is simplified.

Next, with reference to FIGS. 14 to 16, a manufacturing process of the multilayer buildup substrate according to the fifth embodiment of the present invention will be described.
See Fig. 14 (a)
First, in the same manner as in the third embodiment, the core substrate 30 in which the through via 31 is provided and the Cu pattern 32 is formed on the inner wall surface and the main surface of the through via 31 is prepared.

See FIG. 14 (b)
Next, for example, an epoxy resin is embedded in the through via 31 to form a via filling resin layer 33.
At this time, the recess 64 can be formed in the via filling resin layer 33 by performing the epoxy resin coating process once.

Next, refer to FIG. 14C. The Cu plating layer 65 is formed so that the thickness of the flat portion is, for example, 10 to 20 μm.
Refer to FIG.
Next, a resist pattern 35 corresponding to the position of the through via 31 and having an opening 36 at the center is provided, and the Cu plating layer 65 is etched using the resist pattern 35 as a mask to form a wiring pattern 66. A recess 67 is formed in the pattern 66.

Note that the diameter of the opening 36 at this time is set to a size that matches the tapered shape of the via hole formed in the interlayer insulating film thereafter.
The depth of the recess 67 is equal to or greater than the thickness of the wiring pattern 66.
Incidentally, the thickness of the wiring pattern 66 is about 12 μm.

Next, after removing the resist pattern 35, for example, a dry film having a thickness of 30 to 40 μm is pasted to form the interlayer insulating film 39.
Although this step is performed on the front and back of the core substrate 30, only one surface will be described for the sake of simplicity of illustration and description.

Refer to FIG.
Next, a via hole 41 is formed in the interlayer insulating film 39 by irradiating the laser beam 40. Refer to FIG.
Next, a Cu plating layer 68 is formed on the entire surface.

Refer to FIG. 15 (h)
Next, similarly to Example 2, a resist pattern 79 having an opening 80 at the center is provided, and etching is performed using the resist pattern 79 as a mask, so that a filled stack via 81 integrated with the wiring pattern 82 is formed. The

At this time, since the bottom of the filled stack via 81 has a buried via structure buried by the thickness of the recess 67, the junction area is increased and the strength is increased.
At the same time, a recess 83 is also formed on the surface of the wiring pattern 82 formed integrally with the filled stack via 81.
The depth of the recess 83 is equal to or greater than the thickness of the wiring pattern 82.

Refer to FIG.
Next, after removing the resist pattern 79, for example, a dry film having a thickness of 30 to 40 μm is pasted again to form the interlayer insulating film 46.
Refer to FIG.
Next, a via hole 48 is formed in the interlayer insulating film 46 by irradiating a laser beam 47.

Refer to FIG.
Thereafter, the filled stack via 84 integrated with the second-layer wiring pattern 85 is formed by performing the steps of FIGS. 7G and 8I.
At this time, the bottom of the filled stack via 84 has a buried via structure in which the concave portion 83 formed in the wiring pattern 82 is buried, so that the bonding area increases and the strength increases.
At the same time, a recess is also formed on the surface of the wiring pattern 85 formed integrally with the filled stack via 84.

By repeating this interlayer insulating film forming step, via hole forming step by laser irradiation, Cu plating step, and etching step for the required number of layers, the multilayer buildup substrate of Example 2 of the present invention is completed.
FIG. 16K shows a three-layer structure, and reference numerals 86 and 87 denote a filled stack via and a wiring pattern formed integrally with the filled stack via 86.

As described above, in the fifth embodiment of the present invention, since all filled stack vias have a buried via structure as in the second embodiment, the via fracture resistance is increased.
Similarly to the third embodiment, the lowermost filled stack via has a buried via structure using a recess formed in the via filling resin, and the entire bonding surface with the bottom of the filled stack via is the Cu layer. Therefore, the bonding strength is increased and the occurrence of via fracture can be prevented.

Next, with reference to FIGS. 17 to 19, the manufacturing process of the multilayer buildup substrate according to the sixth embodiment of the present invention will be described.
Refer to FIG.
First, in the same manner as in the first embodiment, a core substrate 30 in which the through via 31 is provided and the Cu pattern 32 is formed on the inner wall surface and the main surface of the through via 31 is prepared.

Refer to FIG.
Next, for example, an epoxy resin is embedded in the through via 31 to form a via filling resin layer 33.
At this time, the epoxy resin is applied a plurality of times so that the surface of the via filling resin layer 33 is not recessed with respect to the main surface of the core substrate 30.

Next, refer to FIG. 17C. Next, a Cu plating layer 34 having a thickness of, for example, 10 to 20 μm is formed on the entire surface.
Refer to FIG.
Next, a resist pattern 88 is provided corresponding to the position of the through via 31, and the Cu plating layer 34 is etched using the resist pattern 88 as a mask to form a wiring pattern 89.

Next, after removing the resist pattern 88, for example, a dry film resist 90 having a thickness of 10 to 30 μm is pasted, and, for example, an opening having a diameter of 20 μm is formed, and then the opening is electrolyzed. Cu protrusions 91 are formed by Cu plating.
Although this step is performed on the front and back of the core substrate 30, only one surface will be described for the sake of simplicity of illustration and description.

Refer to FIG.
Next, after removing the dry film resist 90, for example, a dry film having a thickness of 30 to 40 μm is attached to form the interlayer insulating film 39.
Refer to FIG.
Next, a via hole 41 is formed in the interlayer insulating film 39 by irradiating the laser beam 40.

Refer to FIG.
Next, a Cu plating layer 42 is formed on the entire surface.
At this time, polishing is performed so that the surface becomes flat.

See FIG. 19 (i)
Next, a resist pattern 43 is provided, and etching is performed using the resist pattern 43 as a mask, so that a filled stack via 92 integrated with the wiring pattern 93 is formed.
At this time, the bottom of the filled stack via 92 has an embedded via structure that encloses the Cu protrusion 91, so that the bonding area increases and the strength increases.

See FIG. 19 (j)
Next, after removing the resist pattern 43, for example, a dry film having a thickness of 30 to 40 μm is pasted again to form the interlayer insulating film 46.
See FIG. 19 (k)
Thereafter, as in the first embodiment, the via hole forming process by laser irradiation, the Cu plating process, the etching process, and the interlayer insulating film forming process are repeated for the required number of layers. 6 multilayer build-up substrates are completed.

  As described above, in Example 6 of the present invention, the Cu protrusion is provided by electrolytic plating on the surface of the wiring pattern, and the lowermost filled stack via is formed so that the bottom of the Cu protrusion is wrapped. Therefore, the occurrence of via rupture can be prevented.

Next, with reference to FIGS. 20-22, the manufacturing process of the multilayer buildup board | substrate of Example 7 of this invention is demonstrated.
Refer to FIG.
First, as in the sixth embodiment, a core substrate 30 is prepared in which a through via 31 is provided and a Cu pattern 32 is formed on the inner wall surface and main surface of the through via 31.

Refer to FIG.
Next, for example, an epoxy resin is embedded in the through via 31 to form a via filling resin layer 33.
At this time, the epoxy resin is applied a plurality of times so that the surface of the via filling resin layer 33 is not recessed with respect to the main surface of the core substrate 30.

Next, refer to FIG. 20C. Next, a Cu plating layer 34 having a thickness of, for example, 10 to 20 μm is formed on the entire surface.
See FIG. 20 (d).
Next, a resist pattern 88 is provided corresponding to the position of the through via 31, and the Cu plating layer 34 is etched using the resist pattern 88 as a mask to form a wiring pattern 89.

Next, after removing the resist pattern 88, for example, a dry film resist 90 having a thickness of 10 to 30 μm is pasted, and, for example, an opening having a diameter of 20 μm is formed, and then the opening is electrolyzed. Cu protrusions 91 are formed by Cu plating.
Although this step is performed on the front and back of the core substrate 30, only one surface will be described for the sake of simplicity of illustration and description.

Refer to FIG.
Next, after removing the dry film resist 90, for example, a dry film having a thickness of 30 to 40 μm is attached to form the interlayer insulating film 39.
Refer to FIG. 21 (g).
Next, a via hole 41 is formed in the interlayer insulating film 39 by irradiating the laser beam 40.

Refer to FIG. 21 (h)
Next, a Cu plating layer 42 is formed on the entire surface.
At this time, polishing is performed so that the surface becomes flat.

See FIG. 22 (i)
Next, a resist pattern 43 is provided, and etching is performed using the resist pattern 43 as a mask, so that a filled stack via 92 integrated with the wiring pattern 93 is formed.
At this time, the bottom of the filled stack via 92 has an embedded via structure that encloses the Cu protrusion 91, so that the bonding area increases and the strength increases.

Refer to FIG.
Next, after removing the resist pattern 43, for example, a dry film resist 94 having a thickness of 10 to 30 μm is pasted again. For example, after forming an opening having a diameter of 20 μm, the opening is subjected to electrolytic Cu plating. Thus, the Cu protrusion 95 is formed.

Refer to FIG. 22 (k).
Next, the dry film resist 94 is removed, and thereafter, the number of layers requiring an interlayer insulating film forming process, a via hole forming process by laser irradiation, a Cu plating process, an etching process, and a Cu protrusion forming process. The multilayer buildup substrate according to the seventh embodiment of the present invention is completed by repeating the process only.
22 (k) shows a three-layer structure, reference numerals 96 and 99 are filled stack vias, and reference numerals 97 and 100 are wiring patterns formed integrally with the filled stack vias 96 and 99, respectively. Reference numeral 98 denotes a Cu protrusion.

  Thus, in Example 7 of this invention, since all the filled stack vias are made into the inclusion via structure, via fracture resistance increases.

Next, with reference to FIGS. 23 to 25, a manufacturing process of the multilayer buildup substrate according to the eighth embodiment of the present invention will be described.
Refer to FIG.
First, as in the sixth embodiment, a core substrate 30 is prepared in which a through via 31 is provided and a Cu pattern 32 is formed on the inner wall surface and main surface of the through via 31.

Refer to FIG.
Next, for example, an epoxy resin is embedded in the through via 31 to form a via filling resin layer 33.
At this time, the epoxy resin is applied a plurality of times so that the surface of the via filling resin layer 33 is not recessed with respect to the main surface of the core substrate 30.
Next, a Cu plating layer 34 having a thickness of, for example, 10 to 20 μm is formed on the entire surface.

Refer to FIG.
Next, a resist pattern 88 is provided corresponding to the position of the through via 31, and the Cu plating layer 34 is etched using the resist pattern 88 as a mask to form a wiring pattern 89.

Next, after removing the resist pattern 88, a resin protrusion 101 made of an epoxy resin having a diameter of 20 μm and a thickness of 5 to 20 μm is formed on the wiring pattern 89 by a screen printing method, for example. To do.

Refer to FIG.
Next, for example, a dry film having a thickness of 30 to 40 μm is attached to form the interlayer insulating film 39.
See FIG. 24 (g).
Next, a via hole 41 is formed in the interlayer insulating film 39 by irradiating the laser beam 40.

See FIG. 24 (h)
Next, a Cu plating layer 42 is formed on the entire surface.
At this time, polishing is performed so that the surface becomes flat.
Refer to FIG. 25 (i)
Next, a resist pattern 43 is provided, and etching is performed using the resist pattern 43 as a mask, so that a filled stack via 92 integrated with the wiring pattern 93 is formed.
At this time, the bottom of the filled stack via 92 has an embedded via structure that encloses the resin protrusion 101, so that the bonding area increases and the strength increases.

Refer to FIG. 25 (j).
Next, after removing the resist pattern 43, for example, a dry film having a thickness of 30 to 40 μm is pasted again to form the interlayer insulating film 46. Refer to FIG. 25 (k).
Thereafter, as in the first embodiment, the via hole forming process by laser irradiation, the Cu plating process, the etching process, and the interlayer insulating film forming process are repeated for the required number of layers. 8 multilayer build-up substrates are completed.

Next, with reference to FIG. 26, the flip-chip package of Example 9 of this invention is demonstrated.
See FIG.
FIG. 26 (a) is a schematic cross-sectional view of a flip chip package of Example 9 of the present invention, and FIG. 26 (b) is an enlarged view of a main part, and the multilayer buildup substrate of Example 1 described above. A semiconductor element is mounted on the board.
The semiconductor element 110 is connected to a Cu wiring layer formed on the uppermost layer of the multilayer buildup substrate 29, that is, a pad via a solder bump 111 formed on a surface electrode (not shown) of the semiconductor element 110. ing.

  A polyimide resin coat layer 112 is provided on the electrode formation surface of the semiconductor element 110, and an underfill resin 113 is filled in a gap between the multilayer buildup substrate 29 and the semiconductor element 110.

  Also, solder balls 114 serving as connection terminals when the flip chip package is mounted on the mother board are provided on the back surface of the multilayer buildup substrate 29, and a solder resist 115 is provided on the side connected to the solder bumps 111. Is provided.

  As described above, in the ninth embodiment of the present invention, the multilayer buildup substrate in which the lowermost filled stack via shown in the first embodiment has a buried via structure is used. When a flip chip package is configured by mounting the via breakage, via breakage does not occur because the via breakage resistance is increased even when stress due to the difference in thermal expansion coefficient is applied.

Next, a flip chip package of Example 10 of the present invention will be described with reference to FIG. 27. Since the basic configuration is the same as that of Example 9, here, an enlarged main part showing a filled stack via structure is shown. Only the figure is shown.
See FIG.
FIG. 27 is an enlarged view of a main part of the flip chip package of Example 10 of the present invention, in which a semiconductor element is mounted on the multilayer buildup substrate of Example 2 described above.

  As described above, in the tenth embodiment of the present invention, the multilayer buildup substrate in which the filled stack vias shown in the second embodiment have a buried via structure is used. When a flip chip package is configured by mounting the via breakage, via breakage does not occur because the via breakage resistance is further increased even when stress due to the difference in thermal expansion coefficient is applied.

Next, the flip chip package of Example 11 of the present invention will be described with reference to FIG. 28. Since the basic configuration is the same as that of Example 9, here, an enlarged main part showing a filled stack via structure is shown. Only the figure is shown.
See FIG.
FIG. 28 is an enlarged view of a main part of the flip chip package of Example 11 of the present invention, in which a semiconductor element is mounted on the multilayer buildup substrate of Example 3 described above.

As described above, in Example 11 of the present invention, a multilayer build-up substrate having a buried via structure in which the lowermost filled stack via shown in Example 3 is buried using a recess provided in via-filling resin is used. Since the flip chip package is configured by mounting a semiconductor element on this multilayer build-up board, even if stress due to the difference in thermal expansion coefficient is applied, the via fracture resistance is further increased. There is no via breakage.
Note that the same structure can be obtained even when the multilayer buildup substrate of Example 4 is used.

Next, the flip chip package of the twelfth embodiment of the present invention will be described with reference to FIG. 29. Since the basic configuration is the same as that of the ninth embodiment, here, an enlarged main part showing a filled stack via structure is shown. Only the figure is shown.
See FIG.
FIG. 29 is an enlarged view of a main part of the flip chip package of Example 12 of the present invention, in which a semiconductor element is mounted on the multilayer buildup substrate of Example 5 described above.

  As described above, in the twelfth embodiment of the present invention, the lowermost filled stack via shown in the fifth embodiment is formed by using the recessed portion provided in the via filling resin, and the buried via structure is formed thereon. Since the filled stack via also uses a multilayer buildup substrate with a buried via structure, when a flip chip package is configured by mounting a semiconductor element on this multilayer buildup substrate, the stress caused by the difference in thermal expansion coefficient is Even if added, the via fracture is not generated because the via fracture resistance is further increased.

Next, the flip-chip package of the thirteenth embodiment of the present invention will be described with reference to FIG. 30. Since the basic configuration is the same as that of the ninth embodiment, here, an enlarged main part showing a filled stack via structure is shown. Only the figure is shown.
See FIG.
FIG. 30 is an enlarged view of a main part of the flip chip package of Example 13 of the present invention, in which a semiconductor element is mounted on the multilayer buildup substrate of Example 6 described above.

  As described above, in the thirteenth embodiment of the present invention, the multilayer buildup substrate having the embedded via structure of the bottom layer filled stack via shown in the sixth embodiment is used. When a flip chip package is configured by mounting the via breakage, via breakage does not occur because the via breakage resistance is increased even when stress due to the difference in thermal expansion coefficient is applied.

Next, a flip-chip package of Example 14 of the present invention will be described with reference to FIG. 31. Since the basic configuration is the same as that of Example 9, here, an enlarged main part showing a filled stack via structure is shown. Only the figure is shown.
See FIG.
FIG. 31 is an enlarged view of a main part of the flip chip package of Example 14 of the present invention, in which a semiconductor element is mounted on the multilayer buildup substrate of Example 7 described above.

  As described above, in the fourteenth embodiment of the present invention, the multi-layer buildup substrate having the filled via structure of all the layers shown in the seventh embodiment and having the embedded via structure is used. When a flip chip package is configured by mounting the via breakage, via breakage does not occur because the via breakage resistance is further increased even when stress due to the difference in thermal expansion coefficient is applied.

Next, the flip chip package of the fifteenth embodiment of the present invention will be described with reference to FIG. 32. Since the basic configuration is the same as that of the ninth embodiment, here, an enlarged main part showing a filled stack via structure is shown. Only the figure is shown.
See FIG.
FIG. 32 is an enlarged view of a main part of the flip chip package of Example 15 of the present invention, in which a semiconductor element is mounted on the multilayer buildup substrate of Example 8 described above.

  As described above, in the fifteenth embodiment of the present invention, since the bottom layer filled stack via shown in the eighth embodiment uses a multilayer buildup substrate having an encapsulated via structure using a resin protrusion, this multilayer When a flip-chip package is configured by mounting a semiconductor element on a build-up board, via rupture resistance is increased even when stress due to the difference in thermal expansion coefficient is applied, so via rupture occurs even with an inexpensive configuration There is nothing to do.

Next, with reference to FIG. 33, the multilayer buildup board | substrate of Example 16 of this invention is demonstrated.
See Figure 33
FIG. 33 (a) is a conceptual plan view of a multilayer buildup substrate according to Embodiment 16 of the present invention, and FIG. 33 (b) is a cross-sectional view of the principal part along the alternate long and short dash line connecting AA 'in the plan view. FIG.
As shown in the figure, in the multilayer buildup substrate of Example 16, the filled stack via in the peripheral portion where stress is applied is the buried via structure 116 shown in Example 1, and the internal filled stack via is used as a conventional flat. The filled stack via structure 117 is used.

In this case, as shown in the figure, the outer three rows of filled stack vias have the buried via structure 116 shown in the first embodiment.
In the case of a 2000-pin class multilayer buildup board, it is desirable that the outer three rows to the fifth row be buried via structures 116.
Such a selective arrangement of the via structure is similarly applied to the second to eighth embodiments.

As mentioned above, although embodiment and each Example of this invention were described, this invention is not restricted to the numerical value, material, or process shown in embodiment and each Example, A various change is possible. is there.
For example, in each of the above-described embodiments, the number of stacked layers is a total of 6 multilayer buildup boards with 3 layers on one side. However, the number of stacked layers is 4 layers or more on one side, resulting in a total of 8 or more layers. Also good.

It is explanatory drawing of the buried via structure of the 1st Embodiment of this invention. It is explanatory drawing of the enclosure via structure of the 2nd Embodiment of this invention. It is explanatory drawing to the middle of the manufacturing process of the multilayer buildup board | substrate of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 3 of the manufacturing process of the multilayer buildup board | substrate of Example 1 of this invention. It is explanatory drawing after FIG. 4 of the manufacturing process of the multilayer buildup board | substrate of Example 1 of this invention. It is explanatory drawing to the middle of the manufacturing process of the multilayer buildup board | substrate of Example 2 of this invention. It is explanatory drawing to the middle after FIG. 6 of the manufacturing process of the multilayer buildup board | substrate of Example 2 of this invention. It is explanatory drawing after FIG. 7 of the manufacturing process of the multilayer buildup board | substrate of Example 2 of this invention. It is explanatory drawing to the middle of the manufacturing process of the multilayer buildup board | substrate of Example 3 of this invention. It is explanatory drawing to the middle after FIG. 9 of the manufacturing process of the multilayer buildup board | substrate of Example 3 of this invention. It is explanatory drawing after FIG. 10 of the manufacturing process of the multilayer buildup board | substrate of Example 3 of this invention. It is explanatory drawing to the middle of the manufacturing process of the multilayer buildup board | substrate of Example 4 of this invention. It is explanatory drawing after FIG. 12 of the manufacturing process of the multilayer buildup board | substrate of Example 4 of this invention. It is explanatory drawing to the middle of the manufacturing process of the multilayer buildup board | substrate of Example 5 of this invention. It is explanatory drawing to the middle after FIG. 14 of the manufacturing process of the multilayer buildup board | substrate of Example 5 of this invention. It is explanatory drawing after FIG. 15 of the manufacturing process of the multilayer buildup board | substrate of Example 5 of this invention. It is explanatory drawing to the middle of the manufacturing process of the multilayer buildup board | substrate of Example 6 of this invention. It is explanatory drawing to the middle after FIG. 17 of the manufacturing process of the multilayer buildup board | substrate of Example 6 of this invention. It is explanatory drawing after FIG. 18 of the manufacturing process of the multilayer buildup board | substrate of Example 6 of this invention. It is explanatory drawing to the middle of the manufacturing process of the multilayer buildup board | substrate of Example 7 of this invention. It is explanatory drawing to the middle after FIG. 20 of the manufacturing process of the multilayer buildup board | substrate of Example 7 of this invention. It is explanatory drawing after FIG. 21 of the manufacturing process of the multilayer buildup board | substrate of Example 7 of this invention. It is explanatory drawing to the middle of the manufacturing process of the multilayer buildup board | substrate of Example 8 of this invention. It is explanatory drawing to the middle after FIG. 23 of the manufacturing process of the multilayer buildup board | substrate of Example 8 of this invention. It is explanatory drawing after FIG. 24 of the manufacturing process of the multilayer buildup board | substrate of Example 8 of this invention. It is structure explanatory drawing of the flip-chip package of Example 9 of this invention. It is a principal part enlarged view of the flip chip package of Example 10 of this invention. It is a principal part enlarged view of the flip chip package of Example 11 of this invention. It is a principal part enlarged view of the flip chip package of Example 12 of this invention. It is a principal part enlarged view of the flip chip package of Example 13 of this invention. It is a principal part enlarged view of the flip chip package of Example 14 of this invention. It is a principal part enlarged view of the flip chip package of Example 15 of this invention. It is composition explanatory drawing of the multilayer buildup board | substrate of Example 16 of this invention. It is structure explanatory drawing of the conventional flip chip package. It is an enlarged view showing a filled stack via structure. It is explanatory drawing of a via fracture | rupture.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Wiring board 11 Core board 12 Cu plating layer 13 Resin 14 Wiring patterns 15, 15 ₁ , 15 ₂ , 15 ₃ Filled stack via 16 Interlayer insulating film 17 Solder resist 18, 18 ₁ , 18 ₂ , 18 ₃ Filled stack via 19 Protrusion Part 21 Semiconductor chip 22 Solder bump 23 Underfill resin 24 Polyimide resin coating layer 29 Multilayer buildup substrate 30 Core substrate 31 Through via 32 Cu pattern 33 Via filling resin layer 34 Cu plating layer 35 Resist pattern 36 Opening 37 Wiring pattern 38 Recess 39, 46, 51 Interlayer insulating film 40, 47 Laser beam 41, 48 Via hole 42 Cu plating layer 43 Resist pattern 44, 49, 52 Filled stack via 45, 50, 53 Wiring pattern 54 Resist pattern 55 Openings 56, 59, 62 F Wire stack 58, 60, 63 Wiring pattern 58, 61 Recess 64 Recess 65 Cu plating layer 66 Wiring pattern 67 Recess 68 Cu plating layer 69, 71, 73 Filled stack via 70, 72, 74 Wiring pattern 75 Cu plating layer 76 Recess 77 Resist pattern 78 Wiring pattern 79 Resist pattern 80 Opening 81, 84, 86 Filled stack vias 82, 85, 87 Wiring pattern 83 Recess 88 Resist pattern 89 Wiring pattern 90, 94 Dry film resist 91, 95, 98 Cu protrusion 92 , 96, 99 Filled stack vias 93, 97, 100 Wiring pattern 101 Resin protrusion 110 Semiconductor element 111 Solder bump 112 Polyimide resin coating layer 113 Underfill resin 114 Solder ball 115 Solder resist 16 embedded via structure 117 flat via structure 201 semiconductor element 202 bump 203 underfill resin 204 polyimide resin coat layer 210 multilayer buildup substrate 211 core substrate 212 through-through hole 213 buildup resin 214 filled via 215 solder resist 216 solder ball 217 spiral Via 218 Filled stack via 219 Via fracture

Claims (6)

A conductor layer;
A first recess formed on the surface of the conductor layer;
A first insulating layer formed on the conductor layer;
A first opening formed in the first insulating layer and exposing the first recess;
A first filled via disposed in the first opening and at least partially embedded in the first recess;
A second insulating layer formed on the first insulating film and the first filled via;
A second opening formed in the second insulating layer and exposing the first filled via; a second filled via disposed in the second opening and connected to the first filled via;
A wiring board comprising: The wiring board according to claim 1,
The wiring board further comprising a second recess formed on a surface of the first filled via and in which at least a part of the second filled via is embedded. In the wiring board according to claim 1 or 2,
A substrate disposed under the conductor layer;
A through hole formed in the substrate;
Resin filled in the through hole to a position lower than the main surface of the substrate;
Further comprising
The wiring board, wherein the conductor layer is formed from a main surface of the substrate to a surface of the resin. A conductor layer;
A first protrusion formed on the surface of the conductor layer;
A first insulating layer formed on the conductor layer;
A first opening formed in the first insulating layer and exposing the first protrusion;
A first filled via disposed in the first opening and having the first protrusion embedded in a bottom;
A second insulating layer formed on the first insulating film and the first filled via;
A second opening formed in the second insulating layer;
A second filled via disposed in the second opening and connected to the first filled via;
A wiring board comprising: The wiring board according to claim 4,
The wiring board further comprising a second convex portion formed on a surface of the first filled via and embedded in a bottom portion of the second filled via.   A semiconductor device comprising a semiconductor substrate mounted on the wiring board according to claim 1.

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