JP5454605B2 - Wiring substrate and semiconductor device - Google Patents

Description

  The present invention relates to a wiring board and a semiconductor device, and more particularly to a configuration for increasing the bonding strength of a filled stack via provided in a wiring board of a multilayer buildup board and a semiconductor device using the wiring board.

  Conventionally, a flip chip package is known as a semiconductor device mounting structure, and will be described with reference to FIGS. 18A and 18B are explanatory views of the configuration of a conventional flip chip package. FIG. 18A is a schematic plan view, and FIG. 18B is a schematic diagram along a dashed line connecting A-A 'in the plan view. FIG. A conventional flip chip package includes a semiconductor element 201, bumps 202 formed of solder or the like on a surface electrode (not shown) of the semiconductor element 201, wiring on the surface, and paired with the bumps 202 of the semiconductor element 201. In order to protect the semiconductor element 201, the gap between the semiconductor element 201 and the multilayer buildup board 210 is provided in order to protect the semiconductor element 201. The underfill resin 203 is filled with solder balls 216 which serve as connection terminals when the flip chip package is mounted on the mother board. Reference numeral 204 denotes a polyimide resin coat layer.

  FIG. 19 is an enlarged view showing a filled stack via structure. As the multilayer buildup substrate 210, a buildup multilayer substrate having 6 to 8 layers is generally used. This build-up multilayer substrate 210 has a through-through hole 212 and is laminated with a build-up resin 213 on a core substrate 211 on which wiring has been made in advance on the front and back sides. Each layer is connected with filled vias.

  Conventionally, filled vias provided in each layer are connected by spiral vias 217 in which the positions of stacked filled vias are offset as shown in FIG. However, as the density and density of semiconductors in recent years have increased, the wiring density of the substrate has increased. As a result, it is difficult to route wiring with spiral vias. Filled stack vias 218 connected to the top are becoming mainstream.

  In a multilayer build-up substrate using a conventional filled stack via, stress is concentrated at the bottom of the filled stack via due to the stress due to the difference in thermal expansion coefficient between the semiconductor element and the substrate. In particular, in the case of all-layer filled stack vias, stress concentrates on the connection part with the substrate core layer, and there is a problem that the via joint part breaks due to a temperature cycle or the like. I will explain.

  As shown in FIG. 20 (a), when a stress is applied due to a difference in thermal expansion coefficient between the semiconductor element and the substrate, the entire layer filled stack via acts as a single rigid body. Since stress concentrates on the lowermost filled stack via 218 in contact with the core substrate 211 serving as an action point, the via fracture portion 219 is likely to occur in the lowermost filled stack via 218 as shown in FIG. Become.

  Therefore, in order to prevent via breakage, it has been proposed to increase the adhesive strength by making the size of the lowermost filled stack via larger than the size of the filled stack via provided thereon (see, for example, Patent Document 1). .

  Alternatively, the interlayer insulating film for one layer is composed of two layers of dry films having different characteristics, and after forming a forward tapered via hole in the two layers of dry film by laser irradiation, the lower layer is formed by wet etching. It has been proposed to form a constricted portion at the center of a filled stack via by enlarging a via hole provided in a dry film (see, for example, Patent Document 2).

  In this case, the stress generated by the difference in thermal expansion coefficient between the semiconductor element and the substrate is concentrated on the constricted portion, so that the stress applied to the portion in contact with the core layer is reduced and the via fracture is avoided.

JP 2006-216713 A JP 2006-253189 A

  However, as in Patent Document 1 described above, there is a problem that if the size of the upper filled stack via is reduced, alignment becomes difficult. On the other hand, if the size of the upper layer filled stack via is made the same as the conventional size, the size of the lowermost filled stack via needs to be larger than that, which hinders high integration.

  On the other hand, in the case of the above-mentioned Patent Document 2, since two types of dry films are required, there is a risk of increasing the manufacturing cost. In addition, since the cross-sectional shape of the via hole filled with plating becomes a drum shape with a constriction in the middle portion, air or the like is involved, and plating is poor, voids are likely to occur on the lower layer side, and the manufacturing yield may be reduced.

  Accordingly, it is an object of the present invention to prevent via breakage of a filled stack via due to stress applied to the wiring board in a wiring board having a filled stack via.

The wiring substrate includes a substrate having a first region and a second region located surrounding the first region, and a first portion having no protrusion formed in the first region of the substrate. 1 of the conductor layer, a second conductive layer having a first protrusion on the second region formed in the surface of said substrate, formed on the first conductive layer and the second conductive layer The first insulating layer formed, the first opening formed in the first insulating layer in the first region and reaching the upper surface of the first conductor layer, and the first region in the second region. A second opening that is formed in one insulating layer and reaches the first protrusion, and a first filled via that is disposed in the first opening and has a bottom face that is in contact with the first conductor layer. , A second filled via disposed in the second opening and covering the first convex portion, the first insulating film , the first filled via, and the front A second insulating layer formed on the second filled via; a third opening formed in the second insulating layer in the first region and reaching the first filled via; and the second A fourth opening that is formed in the second insulating layer in the region and reaches the second filled via, and a third filled via that is disposed in the third opening and connected to the first filled via And a fourth filled via disposed in the fourth opening and connected to the second filled via .

From another point of view, the semiconductor device is required to have a semiconductor element mounted on the wiring board.

  According to the disclosed wiring board, the bottom surface of the bottommost filled stack via where stress is most concentrated has a via structure in which the bottom surface of the filled stack via is incorporated with the protrusion pattern provided on the conductor pattern in contact with the bottom surface. Since it is originally expanded and enlarged, the adhesive strength is increased and via breakage can be effectively suppressed.

It is explanatory drawing of the enclosure via structure of embodiment of this invention. It is explanatory drawing to the middle of the manufacturing process of the multilayer buildup board | substrate of the reference example 1 of this invention. It is explanatory drawing to the middle after FIG. 2 of the manufacturing process of the multilayer buildup board | substrate of the reference example 1 of this invention. It is explanatory drawing after FIG. 3 of the manufacturing process of the multilayer buildup board | substrate of the reference example 1 of this invention. It is explanatory drawing to the middle of the manufacturing process of the multilayer buildup board | substrate of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 5 of the manufacturing process of the multilayer buildup board | substrate of Example 1 of this invention. It is explanatory drawing after FIG. 6 of the manufacturing process of the multilayer buildup board | substrate of Example 1 of this invention. It is explanatory drawing to the middle of the manufacturing process of the multilayer buildup board | substrate of Example 2 of this invention. It is explanatory drawing to the middle after FIG. 8 of the manufacturing process of the multilayer buildup board | substrate of Example 2 of this invention. It is explanatory drawing after FIG. 9 of the manufacturing process of the multilayer buildup board | substrate of Example 2 of this invention. It is explanatory drawing to the middle of the manufacturing process of the multilayer buildup board | substrate of Example 3 of this invention. It is explanatory drawing to the middle after FIG. 11 of the manufacturing process of the multilayer buildup board | substrate of Example 3 of this invention. It is explanatory drawing after FIG. 12 of the manufacturing process of the multilayer buildup board | substrate of Example 3 of this invention. It is structure explanatory drawing of the flip chip package of Example 4 of this invention. It is a principal part enlarged view of the flip chip package of Example 5 of this invention. It is a principal part enlarged view of the flip chip package of Example 6 of this invention. It is structure explanatory drawing of the multilayer buildup board | substrate of Example 7 of this invention. It is structure explanatory drawing of the conventional flip chip package. It is an enlarged view showing a filled stack via structure. It is explanatory drawing of a via fracture | rupture.

Here, a first embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1 (a), filled through vias are filled in a core substrate 11 in which a through hole having a Cu plating layer 12 formed on the inner wall surface is filled with a resin 13 and a predetermined wiring pattern 14 is formed on both sides. in forming the 18, at least, formed to the bottom of the lowermost filled stacked vias _181, therewith contacting conductive pattern, typically wrap the protrusion 19 provided by electrolytic plating on the surface of the wiring pattern 14 To do.

As shown in FIG. 1 (b), the height h of the projection 19 in this case, at 5μm or more, 1/3 or less of the condition is satisfied in the thickness of the filled stack vias 18 _1.

Thus, by making the filled stack via 18 ₁ into the encapsulated via structure, the bonding area of the filled stack via 18 ₁ increases and the bonding strength increases. In this case, the filled stack vias 18 ₂ and 18 _{3 to} be sequentially stacked may have a buried via structure as shown in the drawing, or may have a conventional non-buried via structure.

Further, the diameter of each filled stack via is basically the same via diameter without intentionally changing the size as in Patent Document 1 described above. The heights h ₁ , h ₂ , and h ₃ of the protrusions 19 are basically the same in each filled stack via, but may be different in each filled stack via.

  In order to obtain such an embedded via structure, when the filled stack via 18 is formed, a predetermined opening is formed on the surface of the conductor pattern, i.e., the wiring pattern 14 that is located immediately below the filled stack via. The dried film is attached as a plating frame, and the projections 19 are formed by electrolytic plating. Then, the filled stack via 18 is formed so as to enclose the projections 19.

  Further, as shown in FIG. 1A, after bonding the semiconductor chip 21 onto the wiring substrate 10 with solder bumps 22, an underfill resin 23 is filled between the semiconductor chip 21 and the wiring substrate 10. A flip chip package is configured.

In this kind of flip-chip packages, since the lowermost layer of the filled stack vias 18 ₁ exerted concentrated least stress and wrapping via structure, without via fracture of the filled stack vias 18 ₁ occurs, reliability High flip chip package can be realized.

  Next, before explaining the first embodiment of the present invention, the manufacturing process of the multilayer build-up substrate of the reference example 1 which is a premise of the present invention will be described with reference to FIGS. First, as shown in FIG. 2A, a core substrate 30 having a through via 31 and a Cu pattern 32 formed on the inner wall surface and main surface of the through via 31 is prepared.

  Next, as shown in FIG. 2B, for example, an epoxy resin is embedded in the through via 31 to form a via filling resin layer 33. At this time, the epoxy resin is applied a plurality of times so that the surface of the via filling resin layer 33 is not recessed with respect to the main surface of the core substrate 30.

  Next, as shown in FIG. 2C, a Cu plating seed layer (not shown) is formed on the entire surface by electroless plating, and then electrolytic plating is performed to form a Cu plating having a thickness of, for example, 10 to 20 μm. Layer 34 is formed. The thickness at this time includes the Cu plating seed layer. In the following steps and other examples, description of the plating seed layer is omitted.

  Next, as shown in FIG. 2D, a resist pattern 35 corresponding to the position of the through via 31 and having an opening 36 in the center is provided, and the Cu plating layer 34 is etched using the resist pattern 35 as a mask. Then, the wiring pattern 37 is formed. The diameter of the opening 36 at this time is set to a size that matches the tapered shape of the via hole formed in the interlayer insulating film thereafter, and the bottom of the recess 38 formed in the wiring pattern 37 reaches the via filling resin 33. .

  Next, as shown in FIG. 3E, after removing the resist pattern 35, for example, a dry film with a thickness of 30 to 40 μm is attached to form the interlayer insulating film 39. Although this step is performed on the front and back of the core substrate 30, only one surface will be described for the sake of simplicity of illustration and description.

  Next, as shown in FIG. 3F, a via hole 41 is formed in the interlayer insulating film 39 by irradiating the laser beam 40. Next, as shown in FIG. 3G, a Cu plating layer 42 is formed on the entire surface. At this time, polishing is performed so that the surface becomes flat. In the following steps and other examples, the planarization process is performed when the concave portion is embedded with the Cu plating layer, but the description thereof is omitted.

  Next, as shown in FIG. 3H, a resist pattern 43 is provided, and etching is performed using the resist pattern 43 as a mask, so that a filled stack via 44 integrated with the wiring pattern 45 is formed. At this time, the bottom of the filled stack via 44 has a buried via structure buried by the thickness of the wiring pattern 37, so that the junction area increases and the strength increases.

  Next, as shown in FIG. 4I, after removing the resist pattern 43, for example, a dry film having a thickness of 30 to 40 μm is pasted again to form the interlayer insulating film 46. Next, as shown in FIG. 4 (j), a via hole 48 is formed in the interlayer insulating film 46 by irradiating a laser beam 47.

  Thereafter, by performing the steps of FIG. 3G and FIG. 4I, a filled stack via 49 integrated with the second-layer wiring pattern 50 is formed as shown in FIG. 4K. . By repeating this interlayer insulating film forming step, via hole forming step by laser irradiation, Cu plating step, and etching step for the required number of layers, the multilayer buildup substrate of Reference Example 1 of the present invention is completed. FIG. 4K shows a three-layer structure, and reference numerals 51, 52, and 53 denote wiring patterns formed integrally with the interlayer insulating film, the filled stack via, and the filled stack via 52, respectively. is there.

  As described above, in Reference Example 1 of the present invention, the recess is formed in the wiring layer in contact with the core substrate by etching, and the lowermost filled stack via is formed so as to bury the bottom in the recess. The occurrence of breakage can be prevented.

  Based on the above, next, the manufacturing process of the multilayer buildup substrate according to the first embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 5A, a core substrate 30 in which a through via 31 is provided and a Cu pattern 32 is formed on the inner wall surface and the main surface of the through via 31 is prepared as in the first reference example.

  Next, as shown in FIG. 5B, for example, an epoxy resin is embedded in the through via 31 to form a via filling resin layer 33. At this time, the epoxy resin is applied a plurality of times so that the surface of the via filling resin layer 33 is not recessed with respect to the main surface of the core substrate 30.

  Next, as illustrated in FIG. 5C, a Cu plating layer 34 having a thickness of, for example, 10 to 20 μm is formed on the entire surface. Next, as shown in FIG. 5D, a resist pattern 88 is provided corresponding to the position of the through via 31, and the Cu plating layer 34 is etched using the resist pattern 88 as a mask to form a wiring pattern 89.

  Next, as shown in FIG. 6 (e), after removing the resist pattern 88, for example, a dry film resist 90 having a thickness of 10 to 30 μm is pasted, and for example, an opening having a diameter of 20 μm is formed. Cu protrusions 91 are formed by electrolytic Cu plating of the openings. Although this step is performed on the front and back of the core substrate 30, only one surface will be described for the sake of simplicity of illustration and description.

  Next, as shown in FIG. 6 (f), after removing the dry film resist 90, for example, a dry film with a thickness of 30 to 40 μm is attached to form an interlayer insulating film 39. Next, as shown in FIG. 6G, a via hole 41 is formed in the interlayer insulating film 39 by irradiating the laser beam 40.

  Next, as shown in FIG. 6H, a Cu plating layer 42 is formed on the entire surface. At this time, polishing is performed so that the surface becomes flat.

  Next, as shown in FIG. 7I, a resist pattern 43 is provided, and etching is performed using the resist pattern 43 as a mask, so that a filled stack via 92 integrated with the wiring pattern 93 is formed. At this time, the bottom of the filled stack via 92 has an embedded via structure that encloses the Cu protrusion 91, so that the bonding area increases and the strength increases.

  Next, as shown in FIG. 7 (j), after removing the resist pattern 43, for example, a dry film with a thickness of 30 to 40 μm is pasted again to form the interlayer insulating film 46. Thereafter, as shown in FIG. 7 (k), in the same manner as in Reference Example 1 described above, a layer requiring a via hole forming step by laser irradiation, a Cu plating step, an etching step, and an interlayer insulating film forming step. The multilayer build-up substrate according to the first embodiment of the present invention is completed by repeating a number of times.

  As described above, in Example 1 of the present invention, the Cu protrusion is provided on the surface of the wiring pattern by electrolytic plating, and the lowermost filled stack via is formed so that the bottom of the Cu protrusion is wrapped. Therefore, the occurrence of via rupture can be prevented.

  Next, with reference to FIGS. 8 to 10, the manufacturing process of the multilayer build-up substrate according to the second embodiment of the present invention will be described. First, as shown in FIG. 8A, a core substrate 30 is prepared in which a through via 31 is provided and a Cu pattern 32 is formed on the inner wall surface and main surface of the through via 31 as in the first embodiment.

  Next, as shown in FIG. 8B, for example, an epoxy resin is embedded in the through via 31 to form a via filling resin layer 33. At this time, the epoxy resin is applied a plurality of times so that the surface of the via filling resin layer 33 is not recessed with respect to the main surface of the core substrate 30.

  Next, as shown in FIG. 8C, a Cu plating layer 34 having a thickness of, for example, 10 to 20 μm is formed on the entire surface. Next, as shown in FIG. 8D, a resist pattern 88 is provided corresponding to the position of the through via 31, and the Cu plating layer 34 is etched using the resist pattern 88 as a mask to form a wiring pattern 89.

  Next, as shown in FIG. 9 (e), after removing the resist pattern 88, for example, a dry film resist 90 having a thickness of 10 to 30 μm is pasted, for example, after forming an opening having a diameter of 20 μm, Cu protrusions 91 are formed by electrolytic Cu plating of the openings. Although this step is performed on the front and back of the core substrate 30, only one surface will be described for the sake of simplicity of illustration and description.

  Next, as shown in FIG. 9 (f), after removing the dry film resist 90, for example, a dry film with a thickness of 30 to 40 μm is attached to form the interlayer insulating film 39. Next, as shown in FIG. 9G, a via hole 41 is formed in the interlayer insulating film 39 by irradiating the laser beam 40.

  Next, as shown in FIG. 9H, a Cu plating layer 42 is formed. At this time, polishing is performed so that the surface becomes flat.

  Next, as shown in FIG. 10I, a resist pattern 43 is provided, and etching is performed using the resist pattern 43 as a mask, so that a filled stack via 92 integrated with the wiring pattern 93 is formed. At this time, the bottom of the filled stack via 92 has an embedded via structure that encloses the Cu protrusion 91, so that the bonding area increases and the strength increases.

  Next, as shown in FIG. 10 (j), after removing the resist pattern 43, for example, a dry film resist 94 having a thickness of 10 to 30 μm is pasted again to form an opening having a diameter of 20 μm, for example. Thereafter, the Cu protrusion 95 is formed by electrolytic Cu plating of the opening.

  Next, as shown in FIG. 10 (k), the dry film resist 94 is removed, and thereafter, the interlayer insulating film forming step, the via hole forming step by laser irradiation, the Cu plating step, the etching step, and the Cu protrusions. The multilayer build-up substrate according to the second embodiment of the present invention is completed by repeating the formation process and the number of layers required. FIG. 10 (k) shows a three-layer structure. Reference numerals 96 and 99 denote filled stack vias, and reference numerals 97 and 100 denote wiring patterns formed integrally with the filled stack vias 96 and 99, respectively. Reference numeral 98 denotes a Cu protrusion.

  Thus, in Example 2 of the present invention, all filled stack vias have an embedded via structure, so the via fracture resistance is increased.

  Next, with reference to FIGS. 11 to 13, a manufacturing process of the multilayer buildup substrate according to the third embodiment of the present invention will be described. First, as shown in FIG. 11A, a core substrate 30 is prepared in which a through via 31 is provided and a Cu pattern 32 is formed on the inner wall surface and the main surface of the through via 31 as in the first embodiment.

  Next, as shown in FIG. 11B, for example, an epoxy resin is embedded in the through via 31 to form a via filling resin layer 33. At this time, the epoxy resin is applied a plurality of times so that the surface of the via filling resin layer 33 is not recessed with respect to the main surface of the core substrate 30. Next, as shown in FIG. 11C, a Cu plating layer 34 having a thickness of, for example, 10 to 20 μm is formed on the entire surface.

  Next, as shown in FIG. 11C, a resist pattern 88 is provided corresponding to the position of the through via 31, and the Cu plating layer 34 is etched using the resist pattern 88 as a mask to form a wiring pattern 89.

  Next, as shown in FIG. 12E, after removing the resist pattern 88, a resin made of epoxy resin having a diameter of 20 μm and a thickness of 5 to 20 μm is formed on the wiring pattern 89 by a screen printing method. A protrusion 101 is formed.

  Next, as illustrated in FIG. 12F, for example, a dry film having a thickness of 30 to 40 μm is attached to form the interlayer insulating film 39. Next, as shown in FIG. 12G, a via hole 41 is formed in the interlayer insulating film 39 by irradiating a laser beam 40.

  Next, as shown in FIG. 12H, a Cu plating layer 42 is formed on the entire surface. At this time, polishing is performed so that the surface becomes flat. Next, as shown in FIG. 13I, a resist pattern 43 is provided, and etching is performed using the resist pattern 43 as a mask, so that a filled stack via 92 integrated with the wiring pattern 93 is formed. At this time, the bottom of the filled stack via 92 has an embedded via structure that encloses the resin protrusion 101, so that the bonding area increases and the strength increases.

  Next, as shown in FIG. 13 (j), after removing the resist pattern 43, for example, a dry film having a thickness of 30 to 40 μm is pasted again to form the interlayer insulating film 46. Thereafter, as shown in FIG. 13 (k), in the same manner as in Reference Example 1 described above, a layer requiring a via hole forming step by laser irradiation, a Cu plating step, an etching step, and an interlayer insulating film forming step. The multilayer build-up substrate according to the third embodiment of the present invention is completed by repeating a number of times.

  Next, with reference to FIG. 14, the flip-chip package of Example 4 of this invention is demonstrated. FIG. 14A is a schematic cross-sectional view of a flip chip package according to a fourth embodiment of the present invention, and FIG. 14B is an enlarged view of a main part, and the multilayer buildup substrate according to the first embodiment described above. A semiconductor element is mounted on the board. The semiconductor element 110 is connected to a Cu wiring layer formed on the uppermost layer of the multilayer buildup substrate 29, that is, a pad via a solder bump 111 formed on a surface electrode (not shown) of the semiconductor element 110. ing.

  A polyimide resin coat layer 112 is provided on the electrode formation surface of the semiconductor element 110, and an underfill resin 113 is filled in a gap between the multilayer buildup substrate 29 and the semiconductor element 110.

  Also, solder balls 114 serving as connection terminals when the flip chip package is mounted on the mother board are provided on the back surface of the multilayer buildup substrate 29, and a solder resist 115 is provided on the side connected to the solder bumps 111. Is provided.

  As described above, in the fourth embodiment of the present invention, since the multilayer buildup substrate having the embedded via structure of the lowermost filled stack via shown in the first embodiment is used, a semiconductor element is used as the multilayer buildup substrate. When a flip chip package is configured by mounting the via breakage, via breakage does not occur because the via breakage resistance is increased even when stress due to the difference in thermal expansion coefficient is applied.

  Next, the flip-chip package of the fifth embodiment of the present invention will be described with reference to FIG. 15. Since the basic configuration is the same as that of the fourth embodiment, here, an enlarged main part showing a filled stack via structure is shown. Only the figure is shown. FIG. 15 is an enlarged view of a main part of a flip chip package of Example 5 of the present invention, in which a semiconductor element is mounted on the multilayer buildup substrate of Example 2 described above.

  As described above, in the fifth embodiment of the present invention, since the multilayer buildup substrate having the embedded via structure of the full-layer filled stack via shown in the second embodiment is used, a semiconductor element is used as the multilayer buildup substrate. When a flip chip package is configured by mounting the via breakage, via breakage does not occur because the via breakage resistance is further increased even when stress due to the difference in thermal expansion coefficient is applied.

  Next, a flip chip package according to a sixth embodiment of the present invention will be described with reference to FIG. 16. Since the basic configuration is the same as that of the fourth embodiment, here, an enlarged main part showing a filled stack via structure is shown. Only the figure is shown. FIG. 16 is an enlarged view of a main part of a flip chip package of Example 6 of the present invention, in which a semiconductor element is mounted on the multilayer buildup substrate of Example 3 described above.

  As described above, in the sixth embodiment of the present invention, since the lowermost filled stack via shown in the third embodiment uses a multilayer buildup substrate having an embedded via structure using a resin protrusion, this multilayer When a flip-chip package is configured by mounting a semiconductor element on a build-up board, via rupture resistance is increased even when stress due to the difference in thermal expansion coefficient is applied. There is nothing to do.

  Next, with reference to FIG. 17, the multilayer buildup board | substrate of Example 7 of this invention is demonstrated. FIG. 17A is a conceptual plan view of a multilayer buildup substrate according to Embodiment 7 of the present invention, and FIG. 17B is a cross-sectional view of the main part along the one-dot chain line connecting AA ′ in the plan view. Although it is a figure, here, for convenience of explanation, the filled stack via of Reference Example 1 is illustrated and described. As shown in the figure, in the multilayer build-up substrate of Example 7, the filled stack via in the stressed peripheral portion is used as a buried via structure 116, and the internal filled stack via is replaced with a conventional flat filled stack via structure 117. It is a thing.

  Here, as shown in the figure, the filled stack vias in the three outer rows of filled stack vias are formed as buried via structures 116. In the case of a 2000-pin class multilayer buildup board, it is desirable that the outer three rows to the fifth row be buried via structures 116. Such a selective arrangement of the via structure is applied to the first to third embodiments.

  As mentioned above, although embodiment and each Example of this invention were described, this invention is not restricted to the numerical value, material, or process shown in embodiment and each Example, A various change is possible. is there. For example, in each of the above-described embodiments, the number of stacked layers is a total of 6 multilayer buildup boards with 3 layers on one side. However, the number of stacked layers is 4 layers or more on one side, resulting in a multilayer buildup board with a total of 8 layers or more. Also good.

DESCRIPTION OF SYMBOLS 10 Wiring board 11 Core board 12 Cu plating layer 13 Resin 14 Wiring pattern 16 Interlayer insulating film 17 Solder resist 18, 18 ₁ , 18 ₂ , 18 ₃ Filled stack via 19 Protrusion 21 Semiconductor chip 22 Solder bump 23 Underfill resin 24 Polyimide Resin coat layer 29 Multilayer build-up substrate 30 Core substrate 31 Through via 32 Cu pattern 33 Via filling resin layer 34 Cu plating layer 35 Resist pattern 36 Opening 37 Wiring pattern 38 Recess 39, 46, 51 Interlayer insulating film 40, 47 Laser light 41, 48 Via hole 42 Cu plating layer 43 Resist pattern 44, 49, 52 Filled stack via 45, 50, 53 Wiring pattern 88 Resist pattern 89 Wiring pattern 90, 94 Dry film resist 91, 95, 98 Cu protrusion Portions 92, 96, 99 Filled stack vias 93, 97, 100 Wiring pattern 101 Resin protrusion 110 Semiconductor element 111 Solder bump 112 Polyimide resin coating layer 113 Underfill resin 114 Solder ball 115 Solder resist 116 Embedded via structure 117 Flat filled stack Via structure 201 Semiconductor element 202 Bump 203 Underfill resin 204 Polyimide resin coating layer 210 Multilayer buildup substrate 211 Core substrate 212 Through-through hole 213 Buildup resin 214 Filled via 215 Solder resist 216 Solder ball 217 Spiral via 218 Filled stack via 219 Via fracture Part

Claims (3)

A substrate having a first region and a second region located surrounding the first region;
A first conductor layer having no protrusion formed in the first region of the substrate ;
A second conductor layer having a first protrusion on the surface formed in the second region of the substrate ;
A first insulating layer formed on the first conductor layer and the second conductor layer;
A first opening formed in the first insulating layer of the first region and reaching an upper surface of the first conductor layer;
A second opening formed in the first insulating layer of the second region and reaching the first protrusion;
A first filled via disposed in the first opening and having the entire bottom surface in contact with the first conductor layer;
A second filled via disposed in the second opening and covering the first protrusion;
Said first insulating film, over the first filled via, and a second insulating layer formed on the second filled via,
A third opening formed in the second insulating layer of the first region and reaching the first filled via ;
A fourth opening formed in the second insulating layer of the second region and reaching the second filled via ;
A third filled via disposed in the third opening and connected to the first filled via ;
A fourth filled via disposed in the fourth opening and connected to the second filled via ;
A wiring board comprising: The wiring board according to claim 1,
Having a second protrusion on the surface of the second filled via;
The wiring board, wherein the fourth filled via covers the second convex portion.   A semiconductor device having a semiconductor element mounted on the wiring board according to claim 1.

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