CN108573881A - A kind of semiconductor devices and its manufacturing method and electronic device - Google Patents
A kind of semiconductor devices and its manufacturing method and electronic device Download PDFInfo
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- CN108573881A CN108573881A CN201710131567.6A CN201710131567A CN108573881A CN 108573881 A CN108573881 A CN 108573881A CN 201710131567 A CN201710131567 A CN 201710131567A CN 108573881 A CN108573881 A CN 108573881A
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- 239000010949 copper Substances 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 12
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
- H01L2224/091—Disposition
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacturing method and electronic devices.The method includes：The first wafer is provided, first wafer includes the first surface and second surface being oppositely arranged, and alignment mark and the image sensor element positioned at the alignment mark side are formed in the first surface；There is provided the second wafer, and by the first surface of first wafer and second wafer bonding；The second surface of first wafer is thinned to exposing the alignment mark.The method forms readily identified alignment mark, can further increase the performance and yield of the semiconductor devices in the case where ensureing to be bonded quality.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacturing method and electronics
Device.
Background technology
In general, imaging sensor is the semiconductor devices that optical imagery is converted into electric signal.Imaging sensor includes electricity
Lotus coupled apparatus (CCD) and complementary metal oxide semiconductor (CMOS) imaging sensor.
Since cmos image sensor (CMOS image sensor, CIS) has improved manufacturing technology and characteristic, because
This semiconductor fabrication everyway concentrates on exploitation cmos image sensor.Cmos image sensor utilizes CMOS technology system
It makes, and there is lower power consumption, it is easier to it realizes highly integrated, produces smaller device, therefore, cmos image sensing
Device is widely used in various products, such as digital camera and digital camera etc..
3D CIS make it occupy unique status in imaging sensor market the promotion for being imaged integrated level.Generally use
The back-illuminated type 3D CIS of Cu-Cu bondings, because of the particularity of its bonding technology, the alignment mark region for being used for back side photoetching is usual
Because not being bonded, and generate the risk of silicon explosion.And the practice for increasing Cu bonding dummy patterns can form jamming pattern, greatly
Ground influences the quality of alignment mark.
Therefore, it is necessary to propose a kind of manufacturing method of semiconductor devices, above-mentioned technical problem is solved.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, the method includes：
The first wafer is provided, first wafer includes the first surface and second surface being oppositely arranged, described first
Alignment mark and the image sensor element positioned at the alignment mark side are formed in surface；
There is provided the second wafer, and by the first surface of first wafer and second wafer bonding；
The second surface of first wafer is thinned to exposing the alignment mark.
Optionally, the bonding method includes：
Dielectric layer is formed on the alignment mark and the image sensor element, is formed and is protruded in the dielectric layer
Several the first spaced metal columns；
Second wafer is provided, several the second spaced metal columns are formed on second wafer；
First metal column and second metal column are bonded.
Optionally, the method still further comprises after exposing the alignment mark：
The alignment mark exposed is etched, to form recess；
Functional film layer is formed on the surface of the second surface and the recess.
Optionally, the method for forming the alignment mark includes：
The first surface is patterned, to form several spaced grooves on the first surface；
The groove is filled using marker material and covers the first surface；
The marker material is etched to the first surface or hereinafter, to form the alignment mark.
Optionally, the depth of the groove is 2um~2.5um, and the width of the groove is 0.7um~2.5um.
Optionally, it is formed between the first metal column described in the dielectric layer and the image sensor element and institute
State the interconnection structure of the first metal column and image sensor element electrical connection.
Optionally, it is isolator formed with and blocks between the first metal column and the alignment mark described in the dielectric layer
The barrier bed of the alignment mark.
Optionally, first metal column is uniformly scattered in the entire dielectric layer.
The present invention also provides a kind of semiconductor devices, the semiconductor devices includes：
First wafer, first wafer include the first surface and second surface being oppositely arranged, in the first surface
It is formed with alignment mark and the image sensor element positioned at the alignment mark side, wherein the alignment mark runs through institute
It states the first wafer and is exposed to the second surface；
Second wafer, the first surface of first wafer are mutually bonded with second wafer.
Optionally, the semiconductor devices further includes：
Dielectric layer is located at the first surface, covers the alignment mark and image sensor element；
First metal column, the surface being set in the dielectric layer and protrude from the dielectric layer at interval；
Second wafer is formed with several the second spaced metal columns, wherein described first on second wafer
Metal column and second metal column are mutually bonded.
Optionally, on the second surface, the height of the alignment mark is less than the second surface, and then is formed recessed
It falls into.
Optionally, it is formed with functional film layer on the surface of the second surface and the recess.
Optionally, it is formed between the first metal column described in the dielectric layer and the image sensor element and institute
State the interconnection structure of the first metal column and image sensor element electrical connection.
Optionally, it is isolator formed with and blocks between the first metal column and the alignment mark described in the dielectric layer
The barrier bed of the alignment mark.
The present invention also provides a kind of electronic device, the electronic device includes above-mentioned semiconductor devices.
In conclusion the semiconductor devices of the present invention designs the alignment mark in the figure in preparation process
The side of shape sensor element, and no longer it is upper and lower position relationship, and also the alignment mark runs through first wafer, cruelly
It is exposed on the second surface, in the case where ensureing to be bonded quality, forms readily identified alignment mark, can further carry
The performance and yield of the high semiconductor devices.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A-Fig. 1 I are obtained by the correlation step of the manufacturing method according to the semiconductor devices of one embodiment of the present invention
The structural schematic diagram of the device obtained；
Fig. 2 is the process flow chart according to the manufacturing method of the semiconductor devices of one embodiment of the present invention；
Fig. 3 shows the schematic diagram of the electronic device in one embodiment of the invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further includes making
With the different orientation with the device in operation.For example, if the device in attached drawing is overturn, then, it is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the variation of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but include due to for example manufacturing caused shape
Shape deviation.For example, be shown as the injection region of rectangle its edge usually there is circle or bending features and/or implantation concentration ladder
Degree, rather than the binary from injection region to non-injection regions changes.Equally, the disposal area can be led to by injecting the disposal area formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
The preparation method of the semiconductor devices including alignment mark includes the following steps at present：It is brilliant that first is provided first
Circle, wherein first wafer is device wafers, and various functions device, such as image are initially formed in the device wafers
Then senser element re-forms alignment mark on the wafer, the usual alignment mark is formed in device area, such as shape
Top on the vertical direction of function element described in Cheng Yu, and metal column is formed in the outside of the alignment mark, then carry
For the second wafer, it is also formed with metal column on second wafer, then passes through first wafer and second wafer
The metal column is mutually bonded, and after bonding, alignment mark region is not usually because being bonded, therefore the meeting between the metal column
Cavity is formed, when carrying out back technique to first wafer, the limited pressure that first wafer is born, and it is quick-fried to generate silicon
The risk split.In order to solve this problem, usually virtual gold can be formed in the alignment mark region on the inside of the metal column
Belong to column, is used to support first wafer, to increase the stress that first wafer is born, but so virtual gold
Jamming pattern, the greatly quality to influencing fiducial mark note can be formed again by belonging to column.
Therefore, the present invention to solve the above-mentioned problems, provides a kind of manufacturing method of semiconductor devices, the method packet
It includes：
The first wafer is provided, first wafer includes the first surface and second surface being oppositely arranged, first table
Alignment mark and the image sensor element positioned at the alignment mark side are formed in face；
There is provided the second wafer, and by the first surface of first wafer and second wafer bonding；
The second surface of first wafer is thinned to exposing the alignment mark.
The semiconductor devices of the present invention designs the alignment mark in the image sensor in preparation process
The side of element, and no longer it is upper and lower position relationship, and also the alignment mark runs through first wafer, is exposed to described
On second surface, in the case where ensureing to be bonded quality, readily identified alignment mark is formed, described half can be further increased
The performance and yield of conductor device.
Embodiment one
In the following, the manufacturing method of the semiconductor devices of the present invention is described in detail with reference to figure 1A- Fig. 1 I and Fig. 2,
In, Figure 1A-Fig. 1 I is are obtained according to the correlation step of the manufacturing method of the semiconductor devices of one embodiment of the present invention
The structural schematic diagram of device, Fig. 2 are the technological process according to the manufacturing method of the semiconductor devices of one embodiment of the present invention
Figure.
As shown in Fig. 2, the manufacturing method of the semiconductor devices specifically includes following steps：
Step S1：The first wafer is provided, first wafer includes the first surface and second surface being oppositely arranged, in institute
It states and is formed with alignment mark and the image sensor element positioned at the alignment mark side in first surface；
Step S2：There is provided the second wafer, and by the first surface of first wafer and second wafer bonding；
Step S3：The second surface of first wafer is thinned to exposing the alignment mark.
First, it executes step 1 and provides the first wafer 100, first wafer includes being oppositely arranged as shown in Figure 1A
First surface and second surface are formed with alignment mark 1011 and the figure positioned at the alignment mark side in the first surface
Shape sensor element 102.
Specifically, first wafer 100 can be following at least one of the material being previously mentioned：On silicon, insulator
Silicon (SSOI), stacking SiGe (S-SiGeOI), germanium on insulator SiClx on insulator are laminated on silicon (SOI), insulator
(SiGeOI) and germanium on insulator (GeOI) etc..
Wherein could be formed with various logic device in first wafer 100, for example, be formed with various cmos devices with
And passive device etc., it is illustrated so that the second wafer is cmos image sensor (CIS) wafer as an example here, specially back-illuminated type
CIS.
In the present embodiment, the constituent material of first wafer 100 selects monocrystalline silicon.
First wafer 100 is device wafers, wherein master of the device wafers for realizing predetermined integrated chip
Circuit function is wanted, for example, central processing unit, substantially rectangular shape, central processing unit can be by many active electricals such as MOSFET
Circuit component is constituted.
First wafer 100 includes the first surface and second surface being oppositely arranged, wherein determines the first surface
Justice is front, the second surface is defined as the back side, unless otherwise specified with reference to the explanation.
Wherein, the first surface of first wafer can be divided into marked region and device region in the present invention
Domain to which alignment mark and image sensor element are formed in different regions, rather than is formed in technique same at present
Region.
For example, the first surface includes the marked region and device area being disposed adjacent in the present invention, wherein described
Alignment mark is formed in the marked region, and image sensor element is formed in device area.
Optionally, the device area can be arranged in the region of crystal circle center, and the marked region is arranged in marginal zone
The division in domain, certain marked region and device area is to better illustrate, and there is no apparent on the first wafer
Boundary.
Wherein, the method for forming the alignment mark includes：
Step 1：The first surface is patterned, to form several spaced grooves on the first surface；
Step 2：The groove is filled using marker material and covers the first surface；
Step 3：Marker material is etched to the first surface or the first surface hereinafter, to form the alignment mark
1011。
It is formed and mask layer and is patterned on the first surface of first wafer in the step 1, with described the
One surface forms several spaced grooves, as shown in Figure 1A.
Wherein, the groove can have larger depth-to-width ratio, such as column construction elongated in shape.
Optionally, the depth of the groove is 2um~2.5um, and the width of the groove is 0.7um~2.5um.
The method of deep reaction ion etching (DRIE) is selected to form the groove in this step, such as in the deep reaction
Gas hexa-fluoride (SF is selected in ion etching (DRIE) step6) it is used as process gas, apply radio-frequency power supply so that lithium
Pasc reaction air inlet forms high ionization, and control operating pressure is 20mTorr-8Torr, power 600W, frequency in the etching step
Rate is 13.5MHz, Dc bias can the continuous control in -500V-1000V, ensure the needs of anisotropic etching, select deep
Reactive ion etching (DRIE) can keep very high etching photoresist selection ratio.Deep reaction ion etching (DRIE) system
It can select the common equipment of ability, it is not limited to a certain model.
In the step 2, deposition marker material 101 fills the groove and covers the first surface, wherein described
Marker material 101 can select the material for having larger etching selectivity with first wafer, such as can select dielectric material
Material, such as SiO2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc..
Optionally, the marker material 101 selects SiO in this embodiment2。
Wherein, in order to adequately fill the groove, deposition can be continued after having filled the groove to covering institute
The certain thickness of first surface is stated, as shown in Figure 1B.
To completely remove the SiO of first surface in the step 32And SiO in reservation groove as much as possible2For
Preferably, as shown in Figure 1 C, and then alignment mark 1011 is formed.
Then CIS processing steps are executed in the device area of the first surface, with the shape in the device area
At image sensor element 102.Wherein, the specific type and forming method of the image sensor element 102 are referred to
Method commonly used in the art, it is not limited to which a certain, details are not described herein.
Step 2 is executed, dielectric layer 103 is formed on the alignment mark and the image sensor element, is being given an account of
Form the interconnection structure that be electrically connected with the image sensor element in electric layer, while in the dielectric layer described in formation is blocked
The barrier bed of alignment mark.
Specifically, as shown in figure iD, wherein the interconnection structure 104 includes several metal layers positioned at different layers, in gold
Through-hole is set between category layer, and then forms the interconnection structure that metal layer and through-hole alternately connect.
And in the alignment mark region, the barrier bed is not contacted with the alignment mark, as shown in figure iD.
Wherein, the barrier bed can be metal layer, can be formed simultaneously with the metal layer in interconnection structure, Er Qieke
To be located at same layer with the arbitrary metal layer in the interconnection structure, you can to select and the arbitrary metal layer one in interconnection structure
It rises and is formed, as referring to figure 1E.
Wherein, the forming method of the interconnection structure can select conventional manufacturing method, such as form dielectric layer, then
The dielectric layer is patterned, to form opening and conductive material is selected to fill the opening, sequentially forms each metal
Layer and through-hole, to form the interconnection structure, the further depositing second dielectric layer 105 after forming the metal layer at top,
To cover the metal layer at top and planarize.
Step 3 is executed, forms several the first spaced metal columns outstanding in second dielectric layer 105
106。
Specifically, as referring to figure 1E, several described metal columns 106 interval is formed in dielectric layer in this step, institute
Such as SiO can be used by giving an account of electric layer2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc..
Illustratively, the material of the first metal column 106 can use any suitable metal material, can be used have from
The one or more conductive materials and metallic compound selected in Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al.
In the present embodiment, the material of the first metal column 106 includes Cu.
Further, the top of first metal column 106 is exposed from the dielectric layer, and then forms outstanding first
Metal column, as referring to figure 1E.
Step 4 is executed, the second wafer 200 is provided, several the second spaced metals are formed on second wafer
Column 202；First metal column 106 and second metal column 202 are bonded.
Specifically, as shown in fig. 1F, second wafer 200 can be following at least one of the material being previously mentioned：
Silicon, silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, stacking SiGe (S-SiGeOI) on insulator, on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc..
Wherein described second wafer 200 is logic wafer, and various logic device, example are formed in second wafer 200
Such as it is formed with various cmos devices and passive device.
As an example, functional component 201 can also be formed in the second wafer 200, for example, transistor, interconnection structure and
Radio-frequency devices.In the present embodiment, for transistor for constituting various circuits, radio-frequency devices are used to form radio frequency component or module.
Wherein, transistor can be normal transistor, high-k/metal gate transistors, fin transistor or other are suitable
Transistor.Interconnection structure may include metal layer (such as layers of copper or aluminium layer), metal plug etc..Radio-frequency devices may include inductance
(inductor) devices such as.
In addition to including transistor, radio-frequency devices and interconnection structure, cmos device can also include other various feasible groups
Part, such as resistance, capacitance, MEMS device etc., are not defined herein.
Wherein, the concrete structure and forming method of the various components in cmos device, those skilled in the art can roots
It is selected with reference to the prior art according to actual needs, details are not described herein again.
The second metal column 202 is formed on second wafer, the material of second metal column 202, which can use, appoints
The suitable metal material of meaning can be used one or more with being selected from Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al
Conductive material and metallic compound.
In the present embodiment, the material of the second metal column 202 includes Cu.
Further, the top of second metal column 202 is exposed from the dielectric layer, and then forms outstanding second
Metal column, as referring to figure 1E.
Then first metal column and the second metal column are bonded, to engage the first wafer and the second wafer.
Illustratively, when the material of the first metal column and the second metal column is copper metal, Cu-Cu bondings are carried out, optionally,
The bonding pressure is 20kN~50kN, and preferably 30kN~40kN, bonding temperature is 300 DEG C~450 DEG C, bonding time 20
Minute~60 minutes.
Wherein, first metal column and second metal column are uniformly distributed in first wafer and the second wafer
In, therefore the metal column can undertake the stress that the first wafer is born in the subsequent process after bonding.
Step 5 is executed, the second surface of first wafer is thinned to exposing the alignment mark 1011.
Specifically, as shown in Figure 1 G, the thining method can select method commonly used in the art, it is not limited to a certain
Kind, details are not described herein.
The second surface of first wafer is ground to the top of the alignment mark in this step, described in exposing
Alignment mark.
The alignment mark runs through first wafer after exposing the alignment mark in the present invention, is exposed to institute
It states on second surface, in the case where ensureing to be bonded quality, forms readily identified alignment mark, can further increase described
The performance and yield of semiconductor devices.
Step 6 is executed, the alignment mark of exposing is etched, to form recess；In the second surface and the recess
Middle formation low light transmission or lighttight film layer.
Specifically, as shown in fig. 1H, the alignment mark that etch-back is exposed in this step, to form recess, in turn
Rough structure is formed in the second surface.
When the first layer at the back side define film layer be low light transmission or opaque film when (such as Al), be thinned after carry out a step oxidation
The etching of silicon forms rough shape, forms pattern label after low light transmission or opaque film preparation, still can be formed
The pattern of higher quality marks, as shown in Figure 1 I.
So far, the introduction for preparing the semiconductor gas device of the embodiment of the present invention is completed.After the above step, also
May include other correlation steps, details are not described herein again.Also, in addition to the foregoing steps, the manufacturing method of the present embodiment is also
Can include other steps among above-mentioned each step or between different steps, these steps can pass through current technique
In various techniques realize that details are not described herein again.
The semiconductor devices of the present invention designs the alignment mark in the image sensor in preparation process
The side of element, and no longer it is upper and lower position relationship, and also the alignment mark runs through first wafer, is exposed to described
On second surface, in the case where ensureing to be bonded quality, readily identified alignment mark is formed, described half can be further increased
The performance and yield of conductor device.
Embodiment two
The present invention also provides a kind of semiconductor devices that the manufacturing method using previous embodiment one prepares, specifically
Ground is described in detail the semiconductor devices of the present invention with reference to figure 1I.
The semiconductor devices includes：
First wafer, first wafer include the first surface and second surface being oppositely arranged, in the first surface
It is formed with alignment mark and the image sensor element positioned at the alignment mark side, wherein the alignment mark runs through institute
It states the first wafer and is exposed to the second surface；
Second wafer, the first surface of first wafer and second wafer are mutually bonded.
Wherein, on the second surface, the height of the alignment mark is less than the second surface, and then is formed recessed
It falls into.
Wherein, low light transmission or lighttight film layer are formed in the second surface and the groove.
Wherein, be formed between the first metal column described in the dielectric layer and the image sensor element with it is described
The interconnection structure of first metal column and image sensor element electrical connection.
Wherein, it is isolator formed between the first metal column and the alignment mark described in the dielectric layer and blocks institute
State the barrier bed of alignment mark.
Optionally, as shown in Figure 1 I, first wafer includes the first surface and second surface being oppositely arranged, and described
Alignment mark 1011 and the image sensor element 102 positioned at the alignment mark side are formed in one surface.
Specifically, first wafer 100 can be following at least one of the material being previously mentioned：On silicon, insulator
Silicon (SSOI), stacking SiGe (S-SiGeOI), germanium on insulator SiClx on insulator are laminated on silicon (SOI), insulator
(SiGeOI) and germanium on insulator (GeOI) etc..
Wherein could be formed with various logic device in first wafer 100, for example, be formed with various cmos devices with
And passive device etc., it is illustrated so that the second wafer is cmos image sensor (CIS) wafer as an example here, specially back-illuminated type
CIS.
In the present embodiment, the constituent material of first wafer 100 selects monocrystalline silicon.
First wafer 100 is device wafers, wherein master of the device wafers for realizing predetermined integrated chip
Circuit function is wanted, for example, central processing unit, substantially rectangular shape, central processing unit can be by many active electricals such as MOSFET
Circuit component is constituted.
First wafer 100 includes the first surface and second surface being oppositely arranged, wherein determines the first surface
Justice is front, the second surface is defined as the back side, unless otherwise specified with reference to the explanation.
Wherein, the first surface of first wafer can be divided into marked region and device region in the present invention
Domain to which alignment mark and image sensor element are formed in different regions, rather than is formed in technique same at present
Region.
For example, the first surface includes the marked region and device area being disposed adjacent in the present invention, wherein described
Alignment mark is formed in the marked region, and image sensor element is formed in device area.
Optionally, the device area can be arranged in the region of crystal circle center, and the marked region is arranged in marginal zone
The division in domain, certain marked region and device area is to better illustrate, and there is no apparent on the first wafer
Boundary.
Optionally, the depth of the alignment mark is 2um~2.5um, the width of the alignment mark be 0.7um~
2.5um。
It is formed with dielectric layer 103 on the alignment mark and the image sensor element, the shape in the dielectric layer
At the interconnection structure being electrically connected with the image sensor element, while being formed in the dielectric layer and blocking the alignment mark
Barrier bed.
Wherein, the interconnection structure 104 includes several metal layers positioned at different layers, and through-hole is arranged between metal layer,
And then form the interconnection structure that metal layer and through-hole alternately connect.
And in the alignment mark region, the barrier bed is not contacted with the alignment mark.
Wherein, the barrier bed can be metal layer, can be formed simultaneously with the metal layer in interconnection structure, Er Qieke
To be located at same layer with the arbitrary metal layer in the interconnection structure, you can to select and the arbitrary metal layer one in interconnection structure
It rises and is formed.
Several the first spaced metal columns 106 outstanding are formed in the dielectric layer.
Several described described intervals of first metal column 106 are formed in dielectric layer, and the dielectric layer can use for example
SiO2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc..
Illustratively, the material of the first metal column 106 can use any suitable metal material, can be used have from
The one or more conductive materials and metallic compound selected in Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al.
In the present embodiment, the material of the first metal column 106 includes Cu.
Further, the top of first metal column 106 is exposed from the dielectric layer, and then forms outstanding first
Metal column.
Second wafer 200 can be following at least one of the material being previously mentioned：Silicon, silicon-on-insulator (SOI),
Be laminated on insulator silicon (SSOI), stacking SiGe (S-SiGeOI) on insulator, germanium on insulator SiClx (SiGeOI) and
Germanium on insulator (GeOI) etc..
Wherein described second wafer 200 is logic wafer, and various logic device, example are formed in second wafer 200
Such as it is formed with various cmos devices and passive device.
As an example, functional component 201 can also be formed in the second wafer 200, for example, transistor, interconnection structure and
Radio-frequency devices.In the present embodiment, for transistor for constituting various circuits, radio-frequency devices are used to form radio frequency component or module.
Wherein, transistor can be normal transistor, high-k/metal gate transistors, fin transistor or other are suitable
Transistor.Interconnection structure may include metal layer (such as layers of copper or aluminium layer), metal plug etc..Radio-frequency devices may include inductance
(inductor) devices such as.
In addition to including transistor, radio-frequency devices and interconnection structure, cmos device can also include other various feasible groups
Part, such as resistance, capacitance, MEMS device etc., are not defined herein.
Wherein, the concrete structure and forming method of the various components in cmos device, those skilled in the art can roots
It is selected with reference to the prior art according to actual needs, details are not described herein again.
The second metal column 202 is formed on second wafer, the material of second metal column 202, which can use, appoints
The suitable metal material of meaning can be used one or more with being selected from Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al
Conductive material and metallic compound.
In the present embodiment, the material of the second metal column 202 includes Cu.
Further, the top of second metal column 202 is exposed from the dielectric layer, and then forms outstanding second
Metal column.
The alignment mark runs through first wafer in the present invention, is exposed on the second surface, is ensureing key
In the case of closing quality, readily identified alignment mark is formed, the performance of the semiconductor devices and good can be further increased
Rate.
The height of the alignment mark is less than the second surface, and then forms recess, in the second surface and described
Low light transmission or lighttight film layer are formed in recess.
Specifically, the alignment mark that etch-back is exposed in this step, to form recess, and then in second table
Face forms rough structure.
When the first layer at the back side define film layer be low light transmission or opaque film when (such as Al), be thinned after carry out a step oxidation
The etching of silicon forms rough shape, after low or opaque film preparation formed pattern label, still can be formed compared with
The pattern of high-quality marks, as shown in Figure 1 I.
Since the semiconductor devices of the present invention is prepared using the method in previous embodiment one, also have identical
The advantages of.
Embodiment three
The present invention also provides a kind of electronic device, including the semiconductor devices described in embodiment two, the semiconductor devices
Part is prepared according to one the method for embodiment.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP is set
Standby or any intermediate products for including circuit.The electronic device of the embodiment of the present invention, due to the use of above-mentioned semiconductor
Device, thus there is better performance.
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loud speaker 305, microphone 306 etc..
The wherein described mobile phone handsets include the semiconductor devices described in embodiment two, and the semiconductor devices includes：
First wafer, first wafer include the first surface and second surface being oppositely arranged, in the first surface
It is formed with alignment mark and the image sensor element positioned at the alignment mark side, wherein the alignment mark runs through institute
It states the first wafer and is exposed to the second surface；
Second wafer, the first surface of first wafer and second wafer are mutually bonded.
The electronic device of the embodiment of the present invention due to the use of above-mentioned semiconductor devices, thus has better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (15)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that the method includes：
The first wafer is provided, first wafer includes the first surface and second surface being oppositely arranged, in the first surface
In be formed with alignment mark and the image sensor element positioned at the alignment mark side；
There is provided the second wafer, and by the first surface of first wafer and second wafer bonding；
The second surface of first wafer is thinned to exposing the alignment mark.
2. according to the method described in claim 1, it is characterized in that, the bonding method includes：
Dielectric layer is formed on the alignment mark and the image sensor element, if being formed in the dielectric layer outstanding
Dry the first spaced metal column；
Second wafer is provided, several the second spaced metal columns are formed on second wafer；
First metal column and second metal column are bonded.
3. according to the method described in claim 1, it is characterized in that, the method is also into one after exposing the alignment mark
Step includes：
The alignment mark exposed is etched, to form recess；
Functional film layer is formed on the surface of the second surface and the recess.
4. according to the method described in claim 1, it is characterized in that, the method for forming the alignment mark includes：
The first surface is patterned, to form several spaced grooves on the first surface；
The groove is filled using marker material and covers the first surface；
The marker material is etched to the first surface or hereinafter, to form the alignment mark.
5. according to the method described in claim 4, it is characterized in that, the depth of the groove be 2um~2.5um, the groove
Width be 0.7um~2.5um.
6. according to the method described in claim 1, it is characterized in that, the first metal column described in the dielectric layer and the figure
The interconnection structure being electrically connected with first metal column and the image sensor element is formed between shape sensor element.
7. according to the method described in claim 1, it is characterized in that, the first metal column described in the dielectric layer and described right
It is isolator formed with the barrier bed for blocking the alignment mark between fiducial mark note.
8. according to the method described in claim 1, it is characterized in that, first metal column is uniformly scattered in and is entirely given an account of
In electric layer.
9. a kind of semiconductor devices, which is characterized in that the semiconductor devices includes：
First wafer, first wafer include the first surface and second surface being oppositely arranged, and are formed in the first surface
There are alignment mark and the image sensor element positioned at the alignment mark side, wherein the alignment mark is through described the
One wafer is simultaneously exposed to the second surface；
Second wafer, the first surface of first wafer are mutually bonded with second wafer.
10. semiconductor devices according to claim 9, which is characterized in that the semiconductor devices further includes：
Dielectric layer is located at the first surface, covers the alignment mark and image sensor element；
First metal column, the surface being set in the dielectric layer and protrude from the dielectric layer at interval；
Second wafer is formed with several the second spaced metal columns, wherein first metal on second wafer
Column and second metal column are mutually bonded.
11. semiconductor devices according to claim 9, which is characterized in that on the second surface, the alignment mark
Height be less than the second surface, and then formed recess.
12. semiconductor devices according to claim 11, which is characterized in that in the table of the second surface and the recess
Face is formed with functional film layer.
13. semiconductor devices according to claim 10, which is characterized in that the first metal column described in the dielectric layer
Be formed between the image sensor element be electrically connected with first metal column and the image sensor element it is mutual
Link structure.
14. semiconductor devices according to claim 10, which is characterized in that the first metal column described in the dielectric layer
The barrier bed for blocking the alignment mark is isolator formed between the alignment mark.
15. a kind of electronic device, which is characterized in that the electronic device includes the semiconductor described in one of claim 9 to 14
Device.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110854053A (en) * | 2019-11-19 | 2020-02-28 | 上海华力微电子有限公司 | Preparation method of bonding mark, wafer bonding method, bonding mark and semiconductor device |
| CN111293100A (en) * | 2018-12-07 | 2020-06-16 | 南亚科技股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN111834385A (en) * | 2020-08-18 | 2020-10-27 | 上海华力微电子有限公司 | Backside illuminated image sensor and manufacturing method thereof |
| CN112510017A (en) * | 2020-12-15 | 2021-03-16 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258832A (en) * | 2012-02-17 | 2013-08-21 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
| CN104701334A (en) * | 2015-02-15 | 2015-06-10 | 格科微电子（上海）有限公司 | Deep-groove isolated stacked image sensor manufacturing method |
| CN104981907A (en) * | 2013-02-14 | 2015-10-14 | 奥林巴斯株式会社 | Semiconductor substrate, image pickup element, and image pickup apparatus |
| CN105448748A (en) * | 2014-07-30 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof and electronic device |
| CN106365108A (en) * | 2015-07-23 | 2017-02-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof, and electronic apparatus |
| US20170062495A1 (en) * | 2015-08-26 | 2017-03-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned back side deep trench isolation structure |
-
2017
- 2017-03-07 CN CN201710131567.6A patent/CN108573881A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258832A (en) * | 2012-02-17 | 2013-08-21 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
| CN104981907A (en) * | 2013-02-14 | 2015-10-14 | 奥林巴斯株式会社 | Semiconductor substrate, image pickup element, and image pickup apparatus |
| CN105448748A (en) * | 2014-07-30 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof and electronic device |
| CN104701334A (en) * | 2015-02-15 | 2015-06-10 | 格科微电子（上海）有限公司 | Deep-groove isolated stacked image sensor manufacturing method |
| CN106365108A (en) * | 2015-07-23 | 2017-02-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof, and electronic apparatus |
| US20170062495A1 (en) * | 2015-08-26 | 2017-03-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned back side deep trench isolation structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111293100A (en) * | 2018-12-07 | 2020-06-16 | 南亚科技股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN110854053A (en) * | 2019-11-19 | 2020-02-28 | 上海华力微电子有限公司 | Preparation method of bonding mark, wafer bonding method, bonding mark and semiconductor device |
| CN111834385A (en) * | 2020-08-18 | 2020-10-27 | 上海华力微电子有限公司 | Backside illuminated image sensor and manufacturing method thereof |
| CN111834385B (en) * | 2020-08-18 | 2022-10-25 | 上海华力微电子有限公司 | Backside illuminated image sensor and manufacturing method thereof |
| CN112510017A (en) * | 2020-12-15 | 2021-03-16 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
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