CN110854053A - Preparation method of bonding mark, wafer bonding method, bonding mark and semiconductor device - Google Patents
Preparation method of bonding mark, wafer bonding method, bonding mark and semiconductor device Download PDFInfo
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- CN110854053A CN110854053A CN201911136266.8A CN201911136266A CN110854053A CN 110854053 A CN110854053 A CN 110854053A CN 201911136266 A CN201911136266 A CN 201911136266A CN 110854053 A CN110854053 A CN 110854053A
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000002360 preparation method Methods 0.000 title abstract description 13
- 235000012431 wafers Nutrition 0.000 claims abstract description 154
- 229910052751 metal Inorganic materials 0.000 claims abstract description 51
- 239000002184 metal Substances 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 7
- 230000004927 fusion Effects 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 description 11
- 230000003287 optical effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/682—Mask-wafer alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention provides a preparation method of a bonding mark, which comprises the following steps: step S1: forming a groove on the bearing wafer through etching; step S2: filling metal in the groove; step S3: and removing the metal on the surface of the carrier wafer to reserve the metal filled in the groove, thereby forming a bonding mark on the carrier wafer. According to the preparation method of the bonding mark, after the groove is formed through etching, the identification of the mark surface is improved through depositing metal in the groove, the risk of bonding gaps caused by the groove is reduced, and the bonding quality is improved. Furthermore, the invention also provides the bonding mark prepared based on the method, the bonding mark has a clear boundary, is easy to identify, reduces the failure rate of identification, can reduce the rejection rate of wafers, and improves the productivity. Still further, the invention also provides a wafer bonding method and a semiconductor device prepared based on the wafer bonding method.
Description
Technical Field
The invention belongs to the field of semiconductors, and particularly relates to a preparation method of a bonding mark, a wafer bonding method, the bonding mark and a semiconductor device.
Background
With the rapid development of Semiconductor technology, Complementary Metal Oxide Semiconductor (CMOS) and Micro Electro Mechanical Systems (MEMS) devices become the most mainstream technologies in the markets of various sensor products, and with the continuous progress of the technologies, such products will be developed toward smaller size, higher electrical performance and lower loss.
The CMOS image sensor is a core component of an image pickup apparatus, and realizes an image pickup function by converting an optical signal into an electric signal. It has been widely used in various fields because of its advantages of low power consumption and high signal-to-noise ratio.
Taking a BackSide Illumination CMOS Image Sensors (CIS BSI for short) as an example, in an existing manufacturing process, a device wafer is first formed, a pixel device, a logic device and a metal interconnection structure are formed in the device wafer, a carrier wafer is then bonded to the device wafer, a back of the device wafer is then thinned, and finally a subsequent process of forming a CMOS Image sensor (CIS for short) on a back of the device wafer is performed.
Wafer bonding related to the CIS BSI process in the prior art is that the CIS device wafer and the bearing wafer are subjected to fusion bonding, the wafer is turned over through the fusion bonding, and light can enter from the substrate of the CIS device wafer to perform photoelectric reaction. After fusion bonding, identifying special overlay alignment marks (OVL marks) of an upper wafer and a lower wafer by an infrared optical measurement method, and then performing alignment test. A dry etching process is required to etch a 100nm deep trench on the carrier wafer as a bonding mark (i.e., an alignment mark for bonding alignment and alignment test on the upper wafer). But the bonding mark will interfere with the profile of the wafer surface, causing infrared optical recognition to fail. On the other hand, increasing the trench etching depth can improve the mark surface definition, but at the same time, the risk of bonding voids is increased, which affects the bonding quality.
Therefore, there is a need for an improved method of making bonding marks, which improves the definition of the boundaries of the bonding marks, improves the recognition of the surface, and reduces the risk of bonding voids due to grooves.
Disclosure of Invention
The invention aims to provide a preparation method of a bonding mark, which aims to improve the identification of the surface of the bonding mark and solve the problem of the risk of bonding gaps caused by grooves.
In order to achieve the above object, the present invention provides a method for preparing a bonding mark, comprising:
step S1: forming a groove on the bearing wafer through etching;
step S2: filling metal in the groove;
step S3: and removing the metal on the surface of the carrier wafer to reserve the metal filled in the groove, thereby forming a bonding mark on the carrier wafer.
Optionally, in the method for manufacturing a bonding mark, the depth of the trench in step S1 is 80nm to 120 nm.
Optionally, in the method for preparing the bonding mark, the etching in step S1 is dry etching.
Optionally, in the method for preparing a bonding mark, the metal is filled in the step S2 to fill the trench.
To achieve the above and other related objects, the present invention further provides a wafer bonding method, including:
forming a bonding mark on a bearing wafer by adopting the preparation method of the bonding mark;
forming an interface bonding layer to cover the bearing wafer and the surface of the bonding mark;
and providing a device wafer, aligning the device wafer and the bearing wafer according to the bonding marks, and bonding the device wafer to the interface bonding layer.
Optionally, in the wafer bonding method, the device wafer is bonded to the interface bonding layer through a fusion bonding process.
Optionally, in the wafer bonding method, the carrier wafer and the device wafer are both silicon wafers, and the interface bonding layer is silicon dioxide.
Optionally, in the wafer bonding method, after the device wafer is bonded to the interfacial bonding layer, the method further includes: and thinning the surface of the device wafer, which faces away from the bearing wafer.
In order to achieve the above objects and other related objects, the present invention further provides a bonding mark prepared based on the above method for preparing a bonding mark.
In order to achieve the above objects and other related objects, the present invention further provides a semiconductor device manufactured by the wafer bonding method.
In summary, the present invention provides a method for preparing a bonding mark, including: step S1: forming a groove on the bearing wafer through etching; step S2: filling metal in the groove; step S3: and removing the metal on the surface of the carrier wafer to reserve the metal filled in the groove, thereby forming a bonding mark on the carrier wafer. According to the invention, after the groove is formed by etching, the identification of the mark surface is improved by the method of filling metal in the groove, the risk problem of bonding gaps caused by the groove is solved, and the bonding quality is improved.
Further, the invention also provides a wafer bonding method, which comprises the following steps: forming a bonding mark on a bearing wafer by adopting the preparation method of the bonding mark; then forming an interface bonding layer to cover the bearing wafer and the surface of the bonding mark; and finally, providing a device wafer, aligning the device wafer and the bearing wafer according to the bonding mark, and bonding the device wafer to the interface bonding layer.
Still further, the invention also provides a bonding mark prepared by the preparation method of the bonding mark and a semiconductor device prepared by the wafer bonding method. The bonding mark has a clear boundary, is easy to identify, reduces the failure rate of identification, reduces the rejection rate of wafers and improves the productivity.
Drawings
FIGS. 1A-1C are process diagrams of wafer bonding alignment;
FIG. 2 is a schematic view of a carrier wafer structure;
FIG. 3 is a schematic diagram of the structure of the carrier wafer of FIG. 2 for forming bonding marks;
FIG. 4 is an identification schematic of the bonding mark formed in FIG. 3;
FIG. 5 is a schematic view of a carrier wafer structure according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram formed after step S1 in accordance with an embodiment of the present invention;
FIG. 7 is a schematic structural diagram formed after step S2 in accordance with an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a bonding mark formed in an embodiment of the present invention.
Wherein, in FIGS. 1-4:
10-pad oxide layer, 20-silicon substrate, 30-groove, 40-bonding mark boundary, 50-upper wafer, 60-lower wafer, and 70-alignment mark;
in FIGS. 5-8:
01-pad oxide, 02-substrate, 03-trench, 04-metal, 05-interfacial bonding layer.
Detailed Description
FIGS. 1A-1C illustrate a wafer bonding alignment process, where an upper target is first used to locate the marked locations of a lower wafer 60 (i.e., a device wafer), and the locations are digitized and saved; then, the lower target is used to adjust the position of the upper wafer 50 (i.e. the carrier wafer) and to perform digital imaging; finally, the lower wafer 60 is repositioned and brought into contact with the upper wafer 50 to form the overlay alignment mark 70.
As shown in fig. 2 and 3, a dry etching process is first used to etch a 100nm deep trench on a carrier wafer (i.e., an upper wafer) as a bonding mark (i.e., an alignment mark for bonding alignment and alignment test on the upper wafer). The carrier wafer is preferably a silicon wafer, and may include a silicon substrate 20 and a pad oxide layer 10 thereon, that is, a trench 30 with a depth of 100nm is etched on the pad oxide layer 10 and the silicon substrate 20 by dry etching, and the trench 30 with a depth of 100nm is used as a wafer bonding mark. Since the depth of the trench is 100nm, the profile of the wafer surface is disturbed, which causes the boundary of the trench 30, i.e. the bonding mark boundary 40 (see fig. 4), to be unclear, thereby easily causing the infrared optical recognition failure, increasing the wafer scrap rate, and reducing the production capacity. It has been found that the mark surface definition can be improved by increasing the trench etching depth, but as the trench depth increases, the risk of bonding voids increases, affecting the bonding quality.
The invention provides a preparation method of a bonding mark, which aims to improve the identification of the surface of the bonding mark and solve the risk problem of bonding gaps caused by grooves.
The following provides a more detailed description of the method for producing a bonding mark according to the present invention with reference to the accompanying drawings and specific examples. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 5 to 7, the method for preparing the bonding mark (bonding mark) includes:
step S1: forming a groove 03 on the bearing wafer through etching;
step S2: filling metal 04 in the groove 03;
step S3: and removing the metal on the surface of the carrier wafer to reserve the metal filled in the groove 03, thereby forming a bonding mark on the carrier wafer.
In step S1, trenches 03 are formed on the carrier wafer by etching. Wherein the structure of the carrier wafer is shown in fig. 5. The carrier wafer (carrier wafer) is preferably a silicon wafer, and the structure of the carrier wafer may include a substrate 02 and a Pad Oxide layer (Pad Oxide)01 thereon.
Referring to fig. 6, a trench 03 is formed on the carrier wafer by etching. The etching may be dry etching or wet etching, and is preferably dry etching. The depth of the groove 03 is preferably 80nm to 200nm, and more preferably 100nm, which is consistent with the depth of the prior art. Because the too shallow etching depth of the groove 03 can cause the unclear edge of the groove 03 and influence subsequent infrared optical identification, and the increased etching depth of the groove 03 can improve the surface definition of the bonding mark, but can increase the risk of bonding gaps and influence the bonding quality, the scale depth of the groove 03 is preferably 80 nm-200 nm. At this time, the pad oxide layer 01 of the carrier wafer is etched through, and the silicon substrate 02 is also etched by a partial depth, so as to finally form the trench 03.
Referring to fig. 7, in step S2, the trench 03 is filled with metal 04. The metal 04 may be tungsten, gold, or copper metal, but is not limited to the above materials. The metal 04 may be filled in the trench 03 by a Physical Vapor Deposition (PVD) method or an electroplating method.
In step S3, the metal 04 on the surface of the carrier wafer is removed to leave the metal 04 filled in the trench 03, so as to form a bonding mark (not shown) on the carrier wafer. Since the metal 04 needs to fill the trench 03, the surface of the carrier wafer (i.e. the upper surface of the pad oxide layer 01) is also covered with the metal 04 during the filling process, and the metal 04 covered on the surface of the carrier wafer affects the formation of the subsequent interfacial bonding layer 05, thereby affecting the quality of wafer bonding, so that the metal on the surface of the carrier wafer, i.e. the metal covered on the upper surface of the pad oxide layer 01, needs to be removed. The method for removing the metal covering the upper surface of the pad oxide layer 01 may be a Chemical Mechanical Polishing (CMP) method or an etching method, and the specific method type may be adjusted according to the material type of the metal 04. For example, when the metal 04 is tungsten, a chemical mechanical polishing method may be used to remove the tungsten metal on the surface of the carrier wafer; when the metal 04 is other metals, the metal 04 on the surface of the carrier wafer can also be removed by using a non-pattern etching method.
After removing the metal on the surface of the carrier wafer, the substrate 02 and the metal 04 in the groove 03 form a bonding mark. On the surface of the carrier wafer, the substrate 02 and the metal 04 in the trench 03 and the pad oxide layer 01 around the substrate have a clear boundary, which is easy to identify. Therefore, the bonding mark can be formed by filling metal in the trench 03 to have a clear boundary with the surrounding surface of the carrier wafer, so that the recognition result of the bonding mark is improved, and the risk of bonding voids (bonding void) caused by using the trench 03 not filled with any material as the bonding mark can be solved because the upper surface of the bonding mark is flush or substantially flush with the upper surface of the surrounding carrier wafer.
The embodiment also provides a wafer bonding method, which includes:
firstly, forming a bonding mark on a bearing wafer by adopting the preparation method of the bonding mark;
then, forming an interface bonding layer 05 to cover the surfaces of the bearing wafer and the bonding mark;
then, a device wafer is provided, the device wafer and the carrier wafer are aligned according to the bonding marks, and the device wafer is bonded to the interface bonding layer 05.
Referring to fig. 8, first, the bonding mark is formed on a carrier wafer by the above-mentioned method for preparing the bonding mark, that is, the step S1: forming a groove 03 on the bearing wafer through etching; step S2: filling a metal layer 04 in the groove 03; step S3: and removing the metal 04 on the surface of the carrier wafer to reserve the metal 04 filled in the groove, thereby forming a bonding mark on the carrier wafer.
And then, depositing an interface bonding layer 05 on the surface of the bearing wafer to be used as an interface bonded with the device wafer. After removing the metal 04 on the surface of the carrier wafer and retaining the metal 04 in the groove 03, after depositing an interfacial bonding layer 05 on the surface of the carrier wafer, the interfacial bonding layer 05 covers the upper surface of the pad oxide layer 01 and the upper surface of the bonding mark. The interface bonding layer 05 is used as an interface bonded with a device wafer, the material of the interface bonding layer 05 can be silicon dioxide or silicon nitride, and the like, so long as the interface bonding layer 05 is compact and stable, is not easy to damage, and can protect the bonding mark.
Next, a device wafer, preferably a silicon wafer, is provided, and then the position of the bonding mark may be monitored by means of an infrared optical measurement device to achieve alignment of the device wafer and the carrier wafer, after which the device wafer is bonded to the interfacial bonding layer 05 by a suitable wafer bonding process. The wafer bonding process may be a fusion bonding process, that is, after a device wafer and a carrier wafer are aligned, the device wafer is bonded to the interface bonding layer 05 through the fusion bonding process. After the device wafer is bonded to the interfacial bonding layer 05, the surface of the device wafer, which faces away from the carrier wafer, may be thinned, and subsequent processes, such as plastic encapsulation, through silicon vias, wire bonding, etc., may be performed.
The invention also provides a bonding mark, which is prepared by the preparation method of the bonding mark. Compared with the bonding mark in the prior art, the metal 04 is filled in the groove 03 by a Physical Vapor Deposition (PVD) method or an electroplating method in the preparation process of the bonding mark, the metal on the surface of the carrier wafer is removed by a Chemical Mechanical Polishing (CMP) method or a blank etch method, the bonding mark is composed of the substrate 02 and the metal in the groove 03, and the boundary of the surface of the bonding mark is clear and easy to identify, so that the probability of infrared optical identification failure can be effectively reduced, the production line is smoother, the wafer rejection rate can be reduced, and the productivity is improved.
The invention also provides a semiconductor device prepared based on the wafer bonding method.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A method for preparing a bonding mark, the method comprising:
step S1: forming a groove on the bearing wafer through etching;
step S2: filling metal in the groove;
step S3: and removing the metal on the surface of the carrier wafer to reserve the metal filled in the groove, thereby forming a bonding mark on the carrier wafer.
2. The method for preparing a bonding mark according to claim 1, wherein the depth of the trench in step S1 is 80nm to 200 nm.
3. The method for preparing a bonding mark according to claim 1, wherein the etching in step S1 is dry etching.
4. The method for preparing a bonding mark according to claim 1, wherein the step S2 is performed by filling the metal into the trench.
5. A wafer bonding method, comprising:
forming a bonding mark on a carrier wafer by using the method for manufacturing a bonding mark according to any one of claims 1 to 4;
forming an interface bonding layer to cover the bearing wafer and the surface of the bonding mark;
and providing a device wafer, aligning the device wafer and the bearing wafer according to the bonding marks, and bonding the device wafer to the interface bonding layer.
6. The wafer bonding method of claim 5, wherein the device wafer is bonded to the interfacial bonding layer by a fusion bonding process.
7. The wafer bonding method of claim 5, wherein the carrier wafer and the device wafer are both silicon wafers, and the interfacial bonding layer is silicon dioxide.
8. The wafer bonding method of claim 5, further comprising, after bonding the device wafer to the interfacial bonding layer: and thinning the surface of the device wafer, which faces away from the bearing wafer.
9. A bonding label produced based on the production method of a bonding label according to any one of claims 1 to 4.
10. A semiconductor device prepared based on the wafer bonding method of any one of claims 5 to 8.
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| CN201911136266.8A CN110854053A (en) | 2019-11-19 | 2019-11-19 | Preparation method of bonding mark, wafer bonding method, bonding mark and semiconductor device |
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Cited By (1)
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