CN102760710A - Through-silicon via structure and formation method thereof - Google Patents
Through-silicon via structure and formation method thereof Download PDFInfo
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- CN102760710A CN102760710A CN201110105754XA CN201110105754A CN102760710A CN 102760710 A CN102760710 A CN 102760710A CN 201110105754X A CN201110105754X A CN 201110105754XA CN 201110105754 A CN201110105754 A CN 201110105754A CN 102760710 A CN102760710 A CN 102760710A
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Abstract
The invention discloses a through-silicon via structure and a formation method thereof. The through-silicon via structure comprises a through hole communicating a first surface of a chip with a second surface of the chip, a conducting layer filled in the through hole, a through hole dielectric ring that is in direct contact with and encloses the conducting layer, a first conducting ring that is in direct contact with and encloses the through hole dielectric ring, and a first dielectric ring which is in directly contact with and encloses the first conducting ring and is enclosed by the chip.
Description
Technical field
The present invention relates to a kind of silicon perforation structure, and the method that forms the silicon perforation structure.The present invention particularly relates to a kind of silicon perforation structure with double-deck ring, is used for reducing in conductive substrates and the silicon perforation structure in the wafer bad electric coupling problem between electric conducting material.
Background technology
Silicon puncturing technique (TSV) is a kind of semiconductor technology of novelty.Silicon through electrode technology mainly is to solve the problem of chip chamber interconnection, belongs to the three-dimensional encapsulation technology of a kind of new three dimensions.Hot silicon puncturing technique more meets light, thin, short, little market demand product through three-dimensionally piling up, producing via the silicon perforating wound, provides wafer-class encapsulation such as MEMS (MEMS), photoelectricity and electronic component required packaging technology technology.
The silicon puncturing technique is on wafer, to hole with the mode of etching or laser, again electric conducting material such as copper, polysilicon, tungsten etc. is inserted the raceway groove (promptly connecting inside and outside joint circuit) that guide hole (Via) forms conduction.Then wafer or tube core (die) thinning are piled up, combine (bonding) more at last, and become three-dimensional piling IC (3D IC).Thus, just can remove lead-in wire and link (wire bonding) mode.Change with the mode of etching or laser hole (Via) and conduction electrode, not only can save the lead-in wire space, also can dwindle the usable floor area of circuit board and the volume of packaging part.
Owing to adopt the structure dress interior bonds distance of silicon puncturing technique; Be wafer or the thickness of tube core after the thinning; The traditional stack encapsulation that links compared to taking to go between; The inside access path of three dimensions piling IC is shorter, can make the transmission resistance of chip chamber littler relatively, speed is faster, noise is littler, usefulness is better.Especially at central processing unit (CPU) and memory cache, and on the transfer of data in the memory card applications, more can highlight the usefulness advantage that the short distance interior bonds path of silicon puncturing technique is brought.In addition, the size after the encapsulation of three dimensions piling IC is equal to die-size.In emphasical multi-functional, undersized portable electronic product field, the miniaturization characteristic of three dimensions piling IC is the primary factor of market importing especially.
With the sequencing of the technology and the technology of present exploitation, the silicon puncturing technique can be divided into first boring (via first) and back boring (via last) two big examples.Wherein boring technology can be divided into (before CMOS) and (after CMOS) two kinds of variations behind metal-oxide semiconductor (MOS) before metal-oxide semiconductor (MOS) again earlier.The processing step of boring earlier before metal-oxide semiconductor (MOS) is before carrying out metal oxide semiconductor processing, on silicon wafer substrate, forms silicon perforation raceway groove in advance, and inserts electric conducting material.For taking the high-temperature technology in the follow-up metal-oxide semiconductor (MOS) step into account, the selection of electric conducting material is main with the polysilicon that can bear follow-up metal-oxide semiconductor (MOS) high-temperature technology at present.And the better metals such as copper of conductivity then can influence its resistance because of conducting metal (thermal process) after accepting high-temperature technology repeatedly, and cause the problem of resistance deterioration (pumping).As a complete unit; Consider insert electric conducting material after during the degree of difficulty of wafer thinning technology; The processing step of boring earlier that these carry out before metal-oxide semiconductor (MOS); Higher with the degree of integration and the compatible degree of conventional semiconductor processing techniques, pollute the deficiency that must bear follow-up metal-oxide semiconductor (MOS) high-temperature technology with electric conducting material but have copper.
And the processing step of boring earlier behind metal-oxide semiconductor (MOS) then is after accomplishing metal oxide semiconductor processing, just begins to carry out the forming technology of guide hole and inserts conducting metal.The conductive metallic material that adopts at present is many with the good copper of conductive characteristic.And because copper is easy to generate the bottom and does not fill up but the phenomenon that sealed at the top when filling perforation, cause cavity (void) occurring in the raceway groove and lost efficacy, therefore intermediate manufacturer also being arranged is electric conducting material with tungsten (W) metal.On the whole; The processing step of boring earlier behind metal-oxide semiconductor (MOS); Because metal-oxide semiconductor (MOS) is accomplished; Copper is inserted the flatening process difficulty especially behind the guide hole, and the copper pollution problems is arranged, can increase these processing steps and conventional semiconductor processing techniques like this and integrate and compatible degree of difficulty.
In addition, core conductive layer in the silicon perforation structure and substrate be because all be conductor, so in element operation the time, the core conductive layer can produce bad electric coupling reaction with substrate, and influences the performance of element.Therefore, still need a kind of silicon perforation structure of novelty, and the method for making the silicon perforation structure, can reduce or eliminate the problem that core conductive layer and substrate produce bad electric coupling reaction.
Summary of the invention
So the present invention proposes a kind of silicon perforation structure of novelty, and the method for making the silicon perforation structure.The complex loop that the novel silicon perforation structure of the present invention has particular design can reduce or eliminate the problem that core conductive layer and substrate produce bad electric coupling reaction.
The present invention at first provides a kind of silicon perforation structure of novelty.Silicon perforation structure of the present invention comprise wafer, piercing hole, conductive layer, piercing hole dielectric collar, first conducting ring or the first substrate ring, with first dielectric collar.Wafer comprises first and second, and piercing hole promptly is used for being communicated with first and second.Conductive layer fills up in the piercing hole, and the piercing hole dielectric collar is then around also direct contact conductive layer.One of them centers on also directly contact piercing hole dielectric collar first conducting ring or the first substrate ring.First dielectric collar is centered on by wafer again around also directly contacting first conducting ring.
Secondly the present invention proposes a kind of method that forms the silicon perforation structure.At first, wafer is provided, it comprise substrate, first with second.Secondly, in wafer, form compound circulus.Compound circulus comprises core substrate post, piercing hole dielectric collar, the first substrate ring and first dielectric collar.The piercing hole dielectric collar comprises dielectric material, centers on and directly contacts core substrate post.The first substrate ring is around also directly contacting the piercing hole dielectric collar.First dielectric collar is centered on by wafer again around also directly contacting the first substrate ring.Afterwards, expose compound circulus via second chip thinning.Continue, form second dielectric layer, be used for covering second and exposed composite circulus.Come again, remove the substrate in the compound circulus fully, make core substrate post become piercing hole, and be communicated with first and second.Then, use the core electric conducting material to fill up piercing hole and obtain the silicon perforation structure.
In embodiments of the present invention, can also the while remove the first substrate ring fully and become first cavity ring, re-use first electric conducting material and fill up first cavity ring, make the substrate ring of winning become first conducting ring.In another exemplifying embodiment of the present invention, can or carry out semiconductor technology afterwards before forming the silicon perforation structure.(in yet another embodiment of the invention, can also form multi-layer metal structure, it is positioned at first and goes up and comprise first conductive structure, second conductive structure and the 3rd conductive structure.The first conducting ring lower extension by first conductive structure constitute, extension is made up of the 3rd conductive structure on first conducting ring, the conductive layer extension then is made up of second conductive structure.Thus, make the conducting ring lower extension extension on first conducting ring of winning, the conductive layer extension is inserted and put wherein, in order to the reciprocation between screening conductive layer extension and wafer.In the another exemplifying embodiment of the present invention, the conductive layer extension can also have bending structure.
Description of drawings
Fig. 1-6 illustrates the sketch map that the present invention forms silicon perforation structure method.
Fig. 7-10C and the multiple different exemplifying embodiment of Figure 12 illustration silicon perforation structure of the present invention.
Figure 11 illustration lowers even blocks the coupling effect between core electric conducting material and substrate.
Description of reference numerals
101 first of 100 silicon perforation structures
102 second 103 wafer/semiconductor substrates
110 compound circulus 111 core substrate posts
112 piercing hole dielectric collar, dielectric material post 113 first substrate rings
114 first dielectric collar, 116 first cavity ring
117 second dielectric collar, 120 semiconductor elements
122 drain electrodes of 121 source electrodes
123 grids, 124 interlayer dielectric layers
125 internal connection-wire structures, 126 contact plungers
140 second dielectric layers, 150 core electric conducting materials
151 first electric conducting materials/first conducting ring, 152 second conducting rings
160 multi-layer metal structures, 161 first conductive structures
162 second conductive structures 163 the 3rd conductive structure
164 first conducting ring lower extension, 165 conductive layer extensions
Embodiment
The present invention at first provides a kind of novel method that forms the silicon perforation structure.Novel method of the present invention can special form the complex loop structure, is used for reducing or eliminating the problem that the bad electric coupling of generation reacts between core conductive layer and substrate.
Please refer to Fig. 1-10, illustrate the sketch map that the present invention forms silicon perforation structure method.At first, please refer to Fig. 1, wafer 103 at first is provided.Wafer 103 will be used to form the silicon perforation structure; Itself comprise the semiconductor-based end 103; And have relative first 101 and second 102; Wherein first 101 is the front at the semiconductor-based end 103, is used for preparing various semiconductor element and metal interconnecting, and second 102 then is the bottom surface at the semiconductor-based end 103.The semiconductor-based end 103, can be silicon.
Secondly, in wafer 103, form compound circulus 110.Compound circulus 110 comprises core substrate post 111, piercing hole dielectric collar 112, the first substrate ring 113 and first dielectric collar 114 at least.Piercing hole dielectric collar 112 comprises dielectric material, centers on and directly contacts core substrate post 111.The first substrate ring 113 is positioned at the outside of piercing hole dielectric collar 112, so can be around also directly contacting piercing hole dielectric collar 112.First dielectric collar 114 is positioned at the outside of the first substrate ring 113, so can also can be centered on by the semiconductor-based end 103 in the wafer 103 simultaneously around also directly contacting the first substrate ring 113.
Then, please refer to Fig. 2, carry out semiconductor technology depending on the circumstances or the needs of the situation.These semiconductor technologies can be any suitable semiconductor technology; For example; On first 101, form semiconductor element 120 through semiconductor technology thus; And on semiconductor element 120, form to cover the interlayer dielectric layer 124 of semiconductor element 120, and be positioned on the interlayer dielectric layer 124 and the internal connection-wire structure 125 that is electrically connected with semiconductor element 120.Semiconductor technology depending on the circumstances or the needs of the situation can be carried out before or after obtaining the silicon perforation structure, and Fig. 2 illustration semiconductor technology is carried out before the silicon perforation structure obtaining.
In the present embodiment, semiconductor element 120 can comprise grid 123 and source electrode that is positioned at grid 123 both sides 121 and drain electrode 122 etc.Depending on the circumstances or the needs of the situation, can also on semiconductor element 120, form etching stopping layer or stressor layers, and then form interlayer dielectric layer 124.Internal connection-wire structure 125 is promptly via contact plunger 126, pass interlayer dielectric layer 124 and respectively be positioned at that corresponding grid 123, source electrode 121 are electrically connected with drain electrode 122 on first 101.Interlayer dielectric layer 124 can comprise a kind of to multiple dielectric material, for example silica, silicon nitride, low dielectric constant dielectric materials, silicon oxynitride, carborundum etc. or its combination in any.Internal connection-wire structure 125 can comprise barrier layer, copper crystal seed layer and copper layer for via inlaying the formed copper damascene conductive of step structure.Contact plunger 126 can comprise tungsten usually and be used as the titanium and the titanium nitride of barrier layer.
Next; Please refer to Fig. 3; Treat to accomplish for first 101 required various semiconductor element and metal interconnecting (among Fig. 3 with internal connection-wire structure 125 and contact plunger 126 representative of metal interconnecting as a whole) afterwards; Then carry out wafer thinning technology, to expose core substrate post 111, piercing hole dielectric collar 112, the first substrate ring 113 and first dielectric collar 114 in the compound circulus 110 via second 102 chip thinning 103.The mode that it can use grinding etc. removes the wafer 103 of part and exposes compound circulus 110.For example, can use organic material, similarly be viscose glue (figure do not show), and first 101 of wafer 103 fitted with carrier (figure does not show), carries out grinding steps again, removes the wafer 103 of part and expose compound circulus 110.Core substrate post 111, piercing hole dielectric collar 112, the first substrate ring 113 and first dielectric collar 114.Can all be concentric structure.
Subsequently, please refer to Fig. 4, form second dielectric layer 140.Second dielectric layer 140 not only can cover second 102, and exposes compound circulus 110 simultaneously.The step that forms second dielectric layer 140 can be; Use dielectric material earlier, for example silicon nitride or silica cover second 102 comprehensively; And then use photoetching to cooperate the dielectric material of etching step selective removal part, purpose is to expose compound circulus 110 accurately.Fig. 4 illustration semiconductor technology is not carried out as yet.
Come again, remove the substrate 103 of core substrate post 111 in the compound circulus 110 fully, make core substrate post 111 become piercing hole 115.And piercing hole 115 can be communicated with first 101 and second 102.Can use suitable etching method, for example dry ecthing and/or wet etching cooperate photoresist to remove the substrate 103 of core substrate post 111.
Then, please refer to Fig. 5, use core electric conducting material 150 fills up piercing hole 115 and obtains silicon perforation structure 100.For example, use the mode of deposition, core electric conducting material 150 is filled up among the piercing hole 115, and directly or indirectly be electrically connected with internal connection-wire structure 125.Core electric conducting material 150 generally includes low-resistance electric conducting material, for example copper.The core electric conducting material 150 that constitutes silicon perforation structure 100 can be about the column construction of 5-20 micron for diameter.
Depending on the circumstances or the needs of the situation, before core electric conducting material 150 fills up piercing hole 115, can be on the inwall of piercing hole dielectric collar 112 form wherein at least one of barrier layer (figure does not show) and crystal seed layer (figure does not show) earlier, and cover the surface of piercing hole dielectric collar 112.When core electric conducting material 150 was copper, barrier layer (figure does not show) can be avoided the bad diffusion of copper atom.Crystal seed layer (figure does not show) then is the deposition that can induce core electric conducting material 150.
Depending on the circumstances or the needs of the situation, please refer to Fig. 6, in removing compound circulus 110, in the substrate 103 of core substrate post 111, can also remove the substrate 103 in the first substrate ring 113 in the lump fully, and become first cavity ring 116.Afterwards, please refer to Fig. 7, it is general to fill up piercing hole 115 as core electric conducting material 150, uses first electric conducting material 151 to fill up first cavity ring 116, becomes first conducting ring 151.Core electric conducting material 150 can be identical with first electric conducting material 151, also can be different.If core substrate post 111 first substrate rings 113 remove simultaneously, can use the same conductive backfill.If core substrate post 111 first substrate rings 113 remove respectively, then can use different electric conducting materials to separate backfill.
Depending on the circumstances or the needs of the situation, please refer to Fig. 8, can also form concentric at least one group of conducting ring and dielectric collar in the periphery of first dielectric collar 114.For example, form second conducting ring 152 and second dielectric collar 117.Second conducting ring 152 can be around also directly contacting first dielectric collar 114.117 of second dielectric collar can be centered on by wafer 113 again around also directly contacting second conducting ring 152.Form the concentric conducting ring and the method for dielectric collar, can not add to give unnecessary details in this event with reference to aforesaid explanation.
In embodiment of the present invention, the core electric conducting material 150 at silicon perforation structure 100 centers can made with one side (for example first 101 or second 102) with outer field conducting ring (for example the illustration person of institute is second conducting ring 152 among Fig. 8).Or, earlier at first the 101 core electric conducting material 150 of making silicon perforation structure 100 centers, but make outer conducting ring at second 102.Or, make outer conducting ring at first 101 earlier, but at second the 102 core electric conducting material 150 of making silicon perforation structure 100 centers.
In another execution mode of the present invention, core electric conducting material 150 is all right different with the time point that outer conducting ring is made.For example, it can be made before semiconductor element 120, it can be in semiconductor element 120 back but before the ground floor metal interconnecting, make.Or it can be made behind metal interconnecting ... or the like.
In the another execution mode of the present invention, core electric conducting material 150 or the conducting ring expanded range on first 101 also can be different.For example, core electric conducting material of before semiconductor element 120, producing 150 or conducting ring only are arranged in the semiconductor-based end 103.In semiconductor element 120 back but core electric conducting material 150 or the conducting ring before the ground floor metal interconnecting, produced can extend to contact plunger 126 with integrated mode from the semiconductor-based end 103.Core electric conducting material 150 or the conducting ring behind metal interconnecting, produced then can extend to the superiors of metal interconnecting with integrated mode from the semiconductor-based end 103.Therefore, when core electric conducting material 150 is when different time points is made with outer field conducting ring, both length is understood different.
Depending on the circumstances or the needs of the situation, please refer to Fig. 9, the internal connection-wire structure 125 in the semiconductor technology depending on the circumstances or the needs of the situation can also be a kind of multi-layer metal structure 160.Multi-layer metal structure 160 is positioned on first 101, and comprises first conductive structure 161, second conductive structure 162 and the 3rd conductive structure 163.First conductive structure 161 and the 3rd conductive structure 163 can be the parts of endless metal structure 110, or both do not link to each other in fact.In embodiments of the present invention, second conductive structure 162 and the 3rd conductive structure 163 can be jagged respectively.For example, please refer to Figure 10 A, the 3rd conductive structure 163 can be a ring jaggy, and allows second conductive structure 162 from breach, to pass.Or, please refer to Figure 10 B, second conductive structure 162 can be a circle jaggy, and allows first conductive structure 161 from breach, to pass.Thus, just can form required multi-layer metal structure 160.
In addition; Please refer to Fig. 9; First conducting ring 151 can also form first conducting ring, first extension 164 and first conducting ring the 3rd extension 166 with first conductive structure 161 and the 3rd conductive structure 163 respectively; Making conducting ring first extension 164 of winning is to be made up of 161 of first conductive structures, and first conducting ring the 3rd extension 166 then constitutes by the 3rd layer 166.In addition, second conductive structure 162 in the multi-layer metal structure 160 has constituted conductive layer second extension 165 again.Thus, first conducting ring, first extension 164 promptly can insert and put conductive layer second extension 165 wherein with first conducting ring the 3rd extension 166, with the reciprocation of 103 of screening conductive layer second extension 165 and wafers.
Figure 10 A, Figure 10 B, Figure 10 C illustrate the vertical view of different layers in the multi-layer metal structure 160.Figure 10 A illustrates the vertical view on A-A ' plane among Fig. 9, the vertical view that Figure 10 B illustrates B-B ' plane among Fig. 9, the vertical view that Figure 10 C illustrates C-C ' plane among Fig. 9.The shape of second conductive structure 162 and the 3rd conductive structure 163 is not limit, and is electrically connected and shield effectiveness as long as can produce effectively.
First conductive structure 161, second conductive structure 162 and the 3rd conductive structure 163 in the multi-layer metal structure 160 can comprise multilayer respectively.For example, can still be less than and the number of plies of the 3rd conductive structure again more than the number of plies of first conductive structure 161 during the number of plies of second conductive structure 162.Depending on the circumstances or the needs of the situation, please refer to Figure 10, conductive layer extension 165 can also have bending structure 167, makes conductive layer extension 165 be bound to extend to top layer and signal is picked out.
Through after the above method step, promptly can obtain silicon perforation structure 100 of the present invention, shown in Fig. 7-10.Wafer 103 includes substrate 103, first 101 and second 102, and piercing hole 115 promptly is arranged in wafer 103, and is communicated with first 101 and second 102.Silicon perforation structure 100 of the present invention is characterised in that, compound circulus 110 wherein.Compound circulus 110 comprise at least core electric conducting material 150, piercing hole dielectric collar 112, the first substrate ring 113 or first conducting ring 151, with first dielectric collar 114.First conducting ring 151 comprises first electric conducting material 151.
Depending on the circumstances or the needs of the situation, please refer to Fig. 8, concentric at least one group of conducting ring and dielectric collar can also be arranged in the periphery of first dielectric collar 114.For example, second conducting ring 152 and second dielectric collar 117.Second conducting ring 152 can be around also directly contacting first dielectric collar 114.117 of second dielectric collar can be centered on by wafer 113 again around also directly contacting second conducting ring 152.
On first 101 of wafer 103, semiconductor element 120 depending on the circumstances or the needs of the situation can be arranged, cover the interlayer dielectric layer 124 of semiconductor element 120, and be positioned on the interlayer dielectric layer 124 and the internal connection-wire structure 125 that is electrically connected with semiconductor element 120.Semiconductor element 120 generally includes grid 123 and source electrode that is positioned at grid 123 both sides 121 and drain electrode 122 etc.Internal connection-wire structure 125 is promptly via contact plunger 126, passes interlayer dielectric layer 124 and is electrically connected with the grid 123, source electrode 121 and the drain electrode 122 that are positioned on first 101 respectively.
Depending on the circumstances or the needs of the situation, please refer to Fig. 9, internal connection-wire structure 125 can be a kind of multi-layer metal structure 160.Multi-layer metal structure 160 is positioned on first 101 and comprises first conductive structure 161, second conductive structure 162 and the 3rd conductive structure 163.In embodiments of the present invention, second conductive structure 162 and the 3rd conductive structure 163 can be jagged respectively.For example, please refer to Figure 10 A, the 3rd conductive structure 163 can be a ring jaggy, and allows second conductive structure 162 from breach, to pass.Or, please refer to Figure 10 B, second conductive structure 162 can be a circle jaggy, and allows first conductive structure 161 from breach, to pass.Thus, just can form required multi-layer metal structure 160.
In addition; Please refer to Fig. 9; First conducting ring 151 can also form first conducting ring, first extension 164 and first conducting ring the 3rd extension 166 with first conductive structure 161 and the 3rd conductive structure 163 respectively; Conducting ring first extension 164 of winning is made up of 161 of first conductive structures, and first conducting ring the 3rd extension 166 constitute by the 3rd layer 166.In addition, second conductive structure 162 in the multi-layer metal structure 160 has constituted conductive layer second extension 165 again.Thus, first conducting ring, first extension 164 promptly can insert and put conductive layer second extension 165 wherein with first conducting ring the 3rd extension 166, with the reciprocation of 103 of screening conductive layer second extension 165 and wafers.
First conductive structure 161, second conductive structure 162 and the 3rd conductive structure 163 in the multi-layer metal structure 160 can comprise multilayer respectively.For example, when second conductive structure 162 comprises the 1st during to the m layer, first conductive structure 161 can comprise the 1st at most to the m-1 layer, will comprise the 1st to the m+1 layer and the 3rd conductive structure 163 is minimum.Depending on the circumstances or the needs of the situation, please refer to Fig. 9, conductive layer extension 165 can also have bending structure 167, extends to top layer simultaneously and signal is picked out.
Figure 10 A, Figure 10 B, Figure 10 C illustrate the vertical view of different layers in the multi-layer metal structure 160.Figure 10 A illustrates the vertical view on A-A ' plane among Fig. 9, the vertical view that Figure 10 B illustrates B-B ' plane among Fig. 9, the vertical view that Figure 10 C illustrates C-C ' plane among Fig. 9.The shape of second conductive structure 162 and the 3rd conductive structure 163 is not limit, and is electrically connected and shield effectiveness as long as can produce effectively.
Please refer to Figure 11; According to another embodiment of the present invention; Want to lower even when blocking the bad coupling effect of 103 of core electric conducting material 150 and substrates, core electric conducting material 150 can utilize intraconnections to be electrically connected to suitable voltage respectively with the first substrate ring 113 or first conducting ring 151.The first substrate ring 113 or first conducting ring 151 promptly are used to shield core electric conducting material 150 and 101 bad reciprocations of wafer.For example, core electric conducting material 150 is electrically connected to core voltage Vc, the first substrate ring 113 or first conducting ring 151 then is electrically connected to the first voltage Vf.Depending on the circumstances or the needs of the situation, the core voltage Vc and the first voltage Vf can be identical or approaching, or core voltage Vc can be different with the first voltage Vf.What for example, the first voltage Vf can be for core voltage Vc is half the.It is required and determine when the appropriate core voltage Vc and the first voltage Vf can implement according to the present invention.The internal connection-wire structure that the first substrate ring 113 or first conducting ring 151 is electrically connected to appropriate voltage can be around core electric conducting material 150 but the loop configuration that does not contact with its entity.
Please refer to Figure 12, it is electric conducting material that the newel of compound circulus 110 of the present invention is not limited to, can also be for having the dielectric material post 112 of insulating property (properties).Therefore; Dielectric material post 112 by the first substrate ring 113 or conducting ring institute around, the first substrate ring or conducting ring 113 by 114 of first dielectric collar around, first dielectric collar 114 by 152 of the second substrate ring or conducting rings around, the second substrate ring or conducting ring 152 again by 117 of second dielectric collar around; The second last dielectric collar 117 again by 103 at the semiconductor-based end around, make second conducting ring 115 via second dielectric collar 117 with the semiconductor-based ends 103 insulation.
The above is merely the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (21)
1. silicon perforation structure comprises:
Wafer comprises first and second;
Piercing hole is communicated with this first and this second;
Conductive layer fills up in this piercing hole;
The piercing hole dielectric collar directly contacts and around this conductive layer;
First conducting ring directly contacts and around this piercing hole dielectric collar; And
First dielectric collar directly contacts and around this first conducting ring, and is centered on by this wafer.
2. silicon perforation structure as claimed in claim 1, wherein this conductive layer is electrically connected to core voltage and this first conducting ring is electrically connected to first voltage, and wherein this core voltage is identical with this first voltage.
3. silicon perforation structure as claimed in claim 1, wherein this conductive layer is electrically connected to core voltage and this first conducting ring is electrically connected to first voltage, and wherein this core voltage is different with this first voltage.
4. silicon perforation structure as claimed in claim 1, wherein this first conducting ring is used to shield the reciprocation between this conductive layer and this wafer.
5. silicon perforation structure as claimed in claim 1, wherein this conductive layer has the core electric conducting material and this first conducting ring has first electric conducting material, and wherein this core electric conducting material is identical with this first electric conducting material.
6. silicon perforation structure as claimed in claim 1, wherein this conductive layer has the core electric conducting material and this first conducting ring has first electric conducting material, and wherein this core electric conducting material is different with this first electric conducting material.
7. silicon perforation structure as claimed in claim 1 also comprises:
Second conducting ring directly contacts and around this first dielectric collar; And
Second dielectric collar directly contacts and around this second conducting ring, and is centered on by this wafer.
8. silicon perforation structure as claimed in claim 1, wherein this conductive layer is to have the column construction that diameter is about the 5-20 micron.
9. silicon perforation structure as claimed in claim 1 also comprises:
Multi-layer metal structure is positioned at this first and goes up and comprise first conductive structure, second conductive structure and the 3rd conductive structure;
First conducting ring, first extension is made up of this first conductive structure;
First conducting ring the 3rd extension is made up of the 3rd conductive structure; And
Conductive layer second extension is made up of this second conductive structure, and wherein this first conducting ring, first extension inserts and puts this conductive layer second extension wherein with this first conducting ring the 3rd extension, to shield this conductive layer extension.
10. silicon perforation structure as claimed in claim 1, wherein this conductive layer second extension has bending structure.
11. a method that forms the silicon perforation structure comprises:
Wafer is provided, this wafer comprise substrate, first with second;
In this wafer, form compound circulus, this compound circulus comprises:
Core substrate post;
The piercing hole dielectric collar comprises dielectric material and direct contact and centers on this core substrate post;
The first substrate ring directly contacts and around this piercing hole dielectric collar; And
First dielectric collar directly contacts and around this first substrate ring, and is centered on by this wafer;
Expose this compound circulus via this second this wafer of thinning;
Form second dielectric layer, cover this second and this compound circulus of exposure;
Remove this substrate in this core substrate post fully, make this core substrate post become piercing hole, wherein this piercing hole is communicated with this first and this second; And
Use the core electric conducting material to fill up this piercing hole and obtain this silicon perforation structure.
12. the method like claim 11 formation silicon perforation structure wherein also comprises:
Obtaining carrying out semiconductor technology behind this silicon perforation structure.
13. the method like claim 11 formation silicon perforation structure wherein also comprises:
Before obtaining this silicon perforation structure, carry out semiconductor technology.
14. the method like claim 11 formation silicon perforation structure also comprises:
Remove this first substrate ring fully and become first cavity ring; And
And use first electric conducting material to fill up this first cavity ring.
15. like the method for claim 14 formation silicon perforation structure, wherein this core electric conducting material is identical with this first electric conducting material.
16. like the method for claim 14 formation silicon perforation structure, wherein this core electric conducting material is different with this first electric conducting material.
17. the method like claim 11 formation silicon perforation structure also comprises:
Form second conducting ring, directly contact and around this first dielectric collar; And
Form second dielectric collar, directly contact and around this second conducting ring, and centered on by this wafer.
18. like the method for claim 11 formation silicon perforation structure, wherein this conductive layer is to have the column construction that diameter is about the 5-20 micron.
19. the method like claim 11 formation silicon perforation structure also comprises:
Form multi-layer metal structure; Be positioned at this first and go up and comprise first conductive structure, second conductive structure and the 3rd conductive structure; First conducting ring, first extension is made up of this first conductive structure, and first conducting ring the 3rd extension is made up of the 3rd conductive structure; And conductive layer second extension is made up of this second conductive structure.
20. like the method for claim 19 formation silicon perforation structure, wherein this first conducting ring, first extension inserts and puts this conductive layer second extension wherein with this first conducting ring the 3rd extension, to shield this conductive layer second extension.
21. like the method for claim 20 formation silicon perforation structure, wherein this conductive layer second extension has bending structure.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017052471A1 (en) * | 2015-09-23 | 2017-03-30 | Nanyang Technological University | Semiconductor devices and methods of forming the same |
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| WO2017052471A1 (en) * | 2015-09-23 | 2017-03-30 | Nanyang Technological University | Semiconductor devices and methods of forming the same |
| CN108028245A (en) * | 2015-09-23 | 2018-05-11 | 南洋理工大学 | Semiconductor devices and the method for forming it |
| US10950689B2 (en) | 2015-09-23 | 2021-03-16 | Nanyang Technological University | Semiconductor device with a through-substrate via hole having therein a capacitor and a through-substrate via conductor |
| CN107293513A (en) * | 2016-04-11 | 2017-10-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method and electronic installation |
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| CN107301948B (en) * | 2016-04-15 | 2022-04-19 | 台湾积体电路制造股份有限公司 | Method for metal CMP integration process |
| CN111261606B (en) * | 2019-02-18 | 2020-11-17 | 长江存储科技有限责任公司 | Through silicon contact structure and forming method thereof |
| CN111261606A (en) * | 2019-02-18 | 2020-06-09 | 长江存储科技有限责任公司 | Through silicon contact structure and forming method thereof |
| US11069596B2 (en) | 2019-02-18 | 2021-07-20 | Yangtze Memory Technologies Co., Ltd. | Through silicon contact structure and method of forming the same |
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| US11710679B2 (en) | 2019-02-18 | 2023-07-25 | Yangtze Memory Technologies Co., Ltd. | Through silicon contact structure and method of forming the same |
| US11721609B2 (en) | 2019-02-18 | 2023-08-08 | Yangtze Memory Technologies Co., Ltd. | Through silicon contact structure and method of forming the same |
| CN110277348A (en) * | 2019-06-05 | 2019-09-24 | 浙江芯动科技有限公司 | A kind of method of manufacturing technology and semiconductor TSV structure of semiconductor TSV structure |
| CN110277348B (en) * | 2019-06-05 | 2021-09-28 | 浙江芯动科技有限公司 | Manufacturing process method of semiconductor TSV structure and semiconductor TSV structure |
| TWI708365B (en) * | 2019-07-24 | 2020-10-21 | 南亞科技股份有限公司 | Semiconductor structure |
| CN112310022A (en) * | 2019-07-24 | 2021-02-02 | 南亚科技股份有限公司 | Semiconductor structure |
| US11031348B2 (en) | 2019-07-24 | 2021-06-08 | Nanya Technology Corporation | Semiconductor structure |
| CN112310022B (en) * | 2019-07-24 | 2024-01-09 | 南亚科技股份有限公司 | Semiconductor structure |
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