CN103367307B - Wear silicon through hole and its formation method - Google Patents
Wear silicon through hole and its formation method Download PDFInfo
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- CN103367307B CN103367307B CN201210084616.2A CN201210084616A CN103367307B CN 103367307 B CN103367307 B CN 103367307B CN 201210084616 A CN201210084616 A CN 201210084616A CN 103367307 B CN103367307 B CN 103367307B
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Abstract
The invention discloses a kind of structure of wearing silicon through hole, it comprises a conductive electrode, an insulating barrier and a doped region.Wherein, conductive electrode is arranged in a substrate, and conductive electrode can run through a first surface and a second surface of substrate.Insulating barrier is arranged in substrate, and surrounds described conductive electrode.Doped region is arranged in substrate, and surrounds described insulating barrier.Silicon through hole of wearing of the present invention is enclosed in conductive electrode and insulating barrier owing to having doped region, therefore can solve leakage current in prior art and the too high defect of noise.The present invention still further provides a kind of formation method of wearing silicon through hole.
Description
Technical field
The present invention relates to a kind of structure and its formation method of wearing silicon through hole, special, relate to a kind of there is doped region wear silicon through hole and its formation method.
Background technology
In the information society in modern times, by integrated circuit (integratedcircuit, IC) microprocessing systems formed is already by the every aspect generally applying to live, the electrical home appliances, mobile communication equipment, personal computer etc. that such as automatically control, have the use of integrated circuit.And day by day progressing greatly along with science and technology, and human society is for the various imaginations of electronic product, makes integrated circuit also toward more polynary, more accurate, more small-sized future development.
General alleged integrated circuit, is crystal grain (die) by producing in existing semiconductor technology and is formed.Manufacture the process of crystal grain, by production one wafer (wafer): first, a wafer distinguishes multiple region, and on each zone, by various semiconductor technology as deposition, photoetching, etching or flatening process, to form various required circuit traces, then, again cutting is carried out to the regional on wafer and form each crystal grain, and be packaged into chip (chip), last again by chip electrical to circuit board, as a printed circuit board (PCB) (printedcircuitboard, PCB), after making pin (pin) electrically connect of chip and printed circuit board (PCB), just the various process stylized can be performed.
In order to improve chip functions and usefulness, increase integrated level more multiple semiconductor element can be held under the confined space, relevant manufactures develops the Stack Technology of many semiconductor wafers, include chip package (flip-chip) technology, multi-die package (multi-chippackage, MCP) technology, encapsulation stacks (packageonpackage, PoP) technology, encapsulate built-in packaging body (packageinpackage, PiP) technology etc., can by the stacking integrated level increasing semiconductor element in unit volume each other between wafer or packaging body.Develop again one in recent years and be called the technology of wearing silicon through hole (throughsiliconvia, TSV), the interior bonds (interconnect) of each chip chamber in packaging body can be promoted, stacking efficiency up to be promoted further.But, existingly wear the problem that silicon through hole also exists leakage current sometimes, and then have impact on the quality of element.Therefore, a kind of design is also needed good to wear silicon through hole, to solve foregoing problems.
Summary of the invention
The present invention in there is provided a kind of structure of wearing silicon through hole, to solve aforementioned electrical leakage stream and the too high problem of noise.
According to one of them object of the present invention, the invention provides one and wear silicon through hole.Wear silicon through hole and comprise a conductive electrode, an insulating barrier and a doped region.Conductive electrode is arranged in a substrate, and wherein conductive electrode can run through a first surface and a second surface of substrate.Insulating barrier is arranged in substrate, and surrounds described conductive electrode.Doped region is arranged in substrate, and surrounds described insulating barrier.
Object according to another preferred, present invention also offers a kind of formation method of wearing silicon through hole.First provide a substrate, it has a first surface and a second surface.Then a perforate is formed at the first surface of substrate.Then in the formation doped region, surface of perforate.The follow-up surface in doped region forms insulating barrier and conductive layer, to fill up perforate.Finally carry out thinning technique, to expose conductive layer from the second surface of substrate.
Provided by the present inventionly wear silicon through hole, be enclosed in the periphery of insulating barrier and conductive electrode owing to having doped region, the noise rejection ability that entirety wears silicon through hole can be increased, and obtain excellent performance.
Accompanying drawing explanation
Fig. 1 is to Figure 8 shows that the present invention wears the step schematic diagram of the manufacture method of silicon through hole.
Wherein, description of reference numerals is as follows:
300 substrate 312 insulating barriers
302 first surface 314 conductive layers
304 second surface 315 conductive electrodes
306 perforates 316 the 3rd surface
308 material layers 318 wear silicon through hole
310 doped region 320 contact pads
Embodiment
For making those skilled in the art can understand the present invention further, the following description has enumerated the several preferred implementation of the present invention, and coordinates accompanying drawing and explanation, with describe in detail content of the present invention and wish realize effect.
Please refer to Fig. 1 to Fig. 8, be depicted as the step schematic diagram that the present invention wears the manufacture method of silicon through hole.As shown in Figure 1, first one substrate 300 is provided, such as silicon base (siliconsubstrate), epitaxial silicon substrate (epitaxialsiliconsubstrate), silicon germanium semiconductor substrate (silicongermaniumsubstrate), silicon carbide substrate (siliconcarbidesubstrate) or silicon-coated insulated (silicon-on-insulator, SOI).Substrate 300 has first surface 302 and a second surface 304.In the preferred embodiment of the present invention, first surface 302 is such as the active face (activesurface) of substrate 300, and second surface 304 is such as the back side (backsurface) of substrate 300.Substrate 300 thickness is substantially 700 to 1000 microns (micrometer).Then, the first surface 302 of substrate 300 is formed a perforate 306, such as, forms perforate 306 in the mode of dry ecthing.About 5 to 10 microns, the aperture of perforate 306, and the degree of depth is about 50 to 100 microns, but the formation method of perforate 306 and execution mode are not limited thereto, and visible product does different adjustment.
As shown in Figure 2, the first surface 302 of substrate 300 forms a material layer 308 comprehensively, covers the surface of perforate 306.Preferably, material layer 308 can fill up perforate 306 completely.In an embodiment, material layer 308 is the material containing arsenic, such as, be arsenic silex glass (arseno-silicateglass, ASG).Form the step of material layer 308 such as by being chemical vapour deposition (CVD) (chemicalvapordeposition, CVD) technique or physical vapour deposition (PVD) (physicalvapordeposition, PVD) technique, to provide good filling effect.
As shown in Figure 3, then carry out an annealing (annealing) technique, make the dopant diffusion being arranged in material layer 308 to substrate 300, and form doped region (dopingarea) 310 on the surface in perforate 306, scrutable, arsenic admixture can be had in doped region 310.Then material layer 308 is removed.
It should be noted that in other embodiments, doped region 310 is formed by additive method, such as: ion implantation (ionimplant) technique or gas phase doping (gasphasedoping, GPD) technique.Gas phase doping technique, for example, first can provide an impurity gas to perforate 306, such as, be the gas containing arsenic, make the surface of perforate be exposed to adulterate in impurity gas, then optionally can also carry out an annealing process, to form doped region 310.
As shown in Figure 4, behind formation doped region 310, first on the first surface 302 of substrate 300, forming an insulating barrier 312, such as, is a silicon dioxide layer.Perforate 306 is not filled up on the surface that insulating barrier 312 can be formed in perforate 306.Then, at first surface 302 up one-tenth one conductive layer 314 of substrate 300, wherein conductive layer 314 can fill up perforate 306 completely.In an embodiment, conductive layer 314 is such as metallic copper, and the method formed is such as electroplating technology.
As shown in Figure 5, one flatening process is carried out to the first surface 302 of substrate 300, such as etch back process or chemico-mechanical polishing (chemicalmechanicalpolish, CMP) technique is to remove insulating barrier beyond perforate 306 312 and conductive layer 314, makes insulating barrier 312, conductive layer 314 flushes substantially with first surface 302.
As shown in Figure 6, a thinning technique is carried out to the second surface 304 of substrate 300, and be thinned to and expose conductive layer 314.Now, the second surface 304 after thinning becomes the 3rd surface 316.And the conductive layer 314 of position in perforate 306 also form conductive electrode 315.Thus, in substrate 300, namely define the structure of wearing silicon through hole 318, wherein wear silicon through hole 318 and include the conductive electrode 315 running through substrate 300, surround the insulating barrier 312 of conductive electrode 315 and the position doped region 310 in insulating barrier 312 periphery.
In a preferred embodiment of the present invention, as shown in Figure 7, the noise wearing silicon through hole 318 for entirety to increase doped region 310 suppresses effect, optionally can also carry out ion implantation technology to the 3rd surperficial 316 and/or first surface 302 of substrate 300, make doped region 310 extend to the 3rd surface 316 and/or first surface 302 of substrate 300.In the preferred embodiment of the present invention, owing to first surface 302 also may need form other semiconductor elements or interlayer dielectric layer (not showing in Fig. 7), therefore doped region 310 preferably can be formed in the 3rd surface 316 of substrate 300.In an embodiment, doped region 310 meeting ground connection (ground), therefore the noise rejection ability wearing silicon through hole 318 can be increased.The mode of doped region 310 ground connection is such as other circuit by the 3rd surface 316, or is reached by other circuit of first surface 302.
As shown in Figure 8, finally go back visible product demand, on the one or three surface 316 and/or first surface 302 of substrate 300, optionally form electrical connection system carry out conducting and wear conductive electrode 315 in silicon through hole 318, to carry out the I/O of signal.For example, can form a contact pad 320 to be electrically connected conductive electrode 315 on the 3rd surface 316 of substrate 300, subsequent touch pad 320 can be electrically connected with other chips or circuit board (not shown).In the preferred embodiment of the present invention, the earthed circuit in abovementioned dopant district 310 can be formed together with the outside electrical connection system of conductive electrode 315.Such as, first surface 302 is formed metal interconnecting system (metalinterconnectionsystem) (not shown), this metal interconnecting system can make doped region 310 ground connection simultaneously, and conductive electrode 315 is outwards electrically connected.
By the structure of Fig. 8, provided by the present inventionly wear silicon through hole 318, include first surface 302 and the 3rd surface 316 that conductive electrode 315 runs through substrate 300, insulating barrier 312 to be arranged in substrate 300 and to surround conductive electrode 315, and doped region 310 to be arranged in substrate 300 and to surround insulating barrier 312.In an embodiment, first surface 302 and the 3rd surface 316 of substrate 300 are run through in doped region 310, and preferably also can be distributed in the 3rd surface 316, the namely back side of substrate 300, wherein doped region 310 can include arsenic ion.In an embodiment, doped region 310 can by the Circuits System on first surface 302 or the 3rd surface 316 ground connection, to increase overall signal rejection ability.
Provided by the present inventionly wear silicon through hole, be enclosed in the periphery of insulating barrier and conductive electrode owing to having doped region, the noise rejection ability that entirety wears silicon through hole can be increased, and obtain excellent performance.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. wear a silicon through hole, it is characterized in that, comprising:
Conductive electrode is arranged in substrate, and wherein said conductive electrode runs through first surface and the second surface of described substrate;
Insulating barrier is arranged in described substrate, and surrounds described conductive electrode; And
Doped region is arranged in described substrate, and surrounds described insulating barrier, and the described second surface of described substrate is in addition coated with described doped region completely.
2. according to claim 1ly wear silicon through hole, it is characterized in that the described first surface of described substrate and described second surface are run through in described doped region.
3. according to claim 1ly wear silicon through hole, it is characterized in that described doped region comprises arsenic.
4. according to claim 1ly wear silicon through hole, it is characterized in that described doped region ground connection.
5. a method for silicon through hole is worn in formation, it is characterized in that, comprising:
There is provided substrate, it has first surface and second surface;
Described first surface in described substrate forms a perforate;
In the formation doped region, surface of described perforate;
Insulating barrier and conductive layer is formed, to fill up described perforate on the surface of described doped region;
Thinning technique is carried out, to expose described conductive layer from the described second surface of described substrate; And
Ion implantation technology is carried out to the second surface after described thinning, the second surface after making described doped region extend to described thinning.
6. the method for silicon through hole is worn in formation according to claim 5, it is characterized in that the step forming described doped region comprises:
At the deposited on silicon arsenic silica glass layer of described perforate; And
Carry out annealing process.
7. the method for silicon through hole is worn in formation according to claim 5, it is characterized in that the step forming described doped region comprises:
Carry out gas phase doping technique; And
Carry out annealing process.
8. the method for silicon through hole is worn in formation according to claim 7, it is characterized in that described gas phase doping technique comprises use arsenic.
9. the method for silicon through hole is worn in formation according to claim 5, it is characterized in that, after described thinning technique, also comprising described doped region ground connection.
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| CN201210084616.2A CN103367307B (en) | 2012-03-27 | 2012-03-27 | Wear silicon through hole and its formation method |
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| CN201210084616.2A CN103367307B (en) | 2012-03-27 | 2012-03-27 | Wear silicon through hole and its formation method |
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| CN103367307A CN103367307A (en) | 2013-10-23 |
| CN103367307B true CN103367307B (en) | 2016-03-23 |
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| US9847290B1 (en) * | 2016-12-12 | 2017-12-19 | Globalfoundries Inc. | Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variability |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214723A (en) * | 2011-06-01 | 2011-10-12 | 北京大学 | Semiconductor radiation sensing device and manufacturing method thereof |
| CN102272916A (en) * | 2009-01-22 | 2011-12-07 | 国际商业机器公司 | 3d chip-stack with fuse-type through silicon via |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20110241185A1 (en) * | 2010-04-05 | 2011-10-06 | International Business Machines Corporation | Signal shielding through-substrate vias for 3d integration |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102272916A (en) * | 2009-01-22 | 2011-12-07 | 国际商业机器公司 | 3d chip-stack with fuse-type through silicon via |
| CN102214723A (en) * | 2011-06-01 | 2011-10-12 | 北京大学 | Semiconductor radiation sensing device and manufacturing method thereof |
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